1285316 · (2) 玖、發明說明 (發明說明應敘明：發明所屬之技術領域、先前技術、內容、實施方式及圖式簡單說明) 發明所屬之技術領域 本發明係關於匯流排資料傳送。特別是，本發明係為減 少傳送匯流排資料的線路。 先前技術 圖1所示者即為用於傳送資料之匯流排其一範例。圖1 係一用於無線通訊系統之接收與傳送增益控制器（GC) 30 、32 ,及一 GC控制器38說明圖。一通訊台，像是基地台或 使用者設備，會傳送（TX)及接收（RX>信號。為控制這些信 號增益，落屬於其他接收/傳送元件的運作範園之間，GC 30 、32會調整RX及TX信號上的增益度。 為控制GC 30、32的增益參數，會利用一 GC控制器38。 即如圖1所示，該GC控制器38會利用一功率控制匯流排， 像是16條線路匯流排34、36來送出TX 36及RX 34信號的增 益值，像是各者為八條線路。功率控制匯流排線路34、36 雖可供允快速資料傳送，然這會要求該GC 30、32及該GC 控制器38上許多接腳，或是像一專用積髖電路（ASIC)之稹 髖電路（1C)上GC 30、32及GC控制器38間的許多連線。增加 接腳數會要求額外電路板空間與連線。增加1C連線會佔用 珍貴的1C空間。大量的接腳或連線或會依實作方式而定提 高匯流排成本。 從而，希望是可具有其他的資料傳送方式。 發明內容 1285316 (3) 發明說明鑕頁 一種混合平行/串列匯流排介面，此者具有一資料區塊 解多工裝置。該資料區塊解多工裝置具有一翰入，此者經 組態設定以接收一資料區塊，並將該資料區塊解多工成複 數個細塊。對於各個細塊，一平行轉串列轉換器可將該細 塊轉化成串列資料。一線路可傳送各個細塊的串列資料。 一串列轉平行轉換器可轉換各細塊的串列資料以復原該 細塊。資料區塊重建裝置可將各復原細塊合併成該資料區 塊。一使用者設備（或一基地台）具有一增益控制控制器。 該增益控制控制器會產生一具有代表一增益值之η位元的 0 資料區塊。一資料區塊解多工裝置具有一输入，此者經組 態設定以接收該資料區塊，並將該資料區塊解多工成複數 個細塊。各個細塊具有複數個位元。對於各個細塊，一平 行轉串列轉換器可將該細塊轉化成串列資料，一線路傳送 該細塊串列資料，而一串列轉平行轉換器可轉換該細塊串 列資料以復原該細塊。一資料區塊重建裝置可將該等經復 原細塊合併成該資料區塊。一增益控制器接收該資料區塊 ，並利用該資料區塊的增益值以調整其增益。 _ 實施方式 圖2所示者係一混合平行/串列匯流排介面區塊圖，而圖 3為一混合平行/串列匯流排介面資料傳送作業流程圖。一 資料區塊會被跨於該介面而從節點1 50傳送到節點2 52 (54) 。一資料區塊解多工裝置40接收該區塊，並將其解多工成 為i個細塊，以利於i條資料傳送線路44上傳送（56)。該數值 i係根據連線數目與傳送速度之間的取捨而定。一種決定i 發明說明鑛頁 1285316 (4) 值的方式是首先決定一傳送該資料區塊所得承允之最大 延遲。按照此最大延遲，可決定出傳送該區塊所需要的最 小線路數目。利用最小數量的線路，用以傳送資料的線路 會被選定為至少該最小值量。線路44可為接腳，以及其在 電路板上或於一 1C連接上的相關連線。一種解多工成細塊 的方式是將區塊切割成一最顯著到一最小顯著細塊。為如 圖4說明，於兩條線路上傳送一八位元區塊，該區塊會被 解多工成一四位元最顯著細塊及一四位元最小顯著細塊。 另一種方式則是將該區塊交錯跨於i個細塊。該區塊的 前i個位元會變成各i個細塊的第一位元。其次的i個位元會 變成各i個細塊的第二位元，如此下去一直到該最後i個位 元。為說明如圖5所示之在兩條連線上的一八位元區塊， 第一個位元會被映對到細塊1的第一位元。第二個位元會 被映對到細塊2的第一位元。第三個位元會被映對到細塊1 的第二位兀，如此繼績下去，一直到將最後一個位元映對 到細塊2的最後位元。 各個細塊會被送到i個平行轉串列（P/S)轉換器42之相對 應者（58),從平行位元轉換成串列位元，並於線路上串列 循序地傳送（60)。在各條線路的相對側會是一串列轉平行 (S/P)轉換器46。各個S/P轉換器46會將所傳串列資料轉換成 其原始細塊（62)〇第i個經復原細塊會被一資料區塊重建裝 置48處理，以重建該原始資料區塊（64)。 另一方面，雙向方式，會利用i條連線以按雙向方式傳 送資料，即如圖6。可按雙向傳送資訊資料，或是可按單 發明說明鑛頁 在此，一資 1285316 · (5) 一方向傳送資訊而朝另一方向送返確認信號。1285316 (2) 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明In particular, the present invention is to reduce the number of lines that carry bus data. Prior Art The one shown in Figure 1 is an example of a bus for transmitting data. 1 is an illustration of a receive and transmit gain controller (GC) 30, 32, and a GC controller 38 for a wireless communication system. A communication station, such as a base station or user equipment, transmits (TX) and receives (RX> signals. To control the gain of these signals, it belongs to the operation of other receiving/transmitting components, GC 30, 32 Adjusting the gain on the RX and TX signals. To control the gain parameters of the GC 30, 32, a GC controller 38 is utilized. As shown in Figure 1, the GC controller 38 utilizes a power control bus, such as The 16 line bus bars 34, 36 send the gain values of the TX 36 and RX 34 signals, such as eight lines for each. The power control bus lines 34, 36 are available for fast data transfer, which would require the GC. 30, 32 and a number of pins on the GC controller 38, or a number of connections between the GC 30, 32 and the GC controller 38 on a hip circuit (1C) of an exclusive hip circuit (ASIC). The number of pins will require additional board space and wiring. Adding a 1C connection will take up a precious 1C space. A large number of pins or connections may increase the cost of the busbar according to the implementation. Therefore, it is hoped that it can have other Information transmission method. SUMMARY OF THE INVENTION 1285316 (3) Description of the invention The page has a hybrid parallel/serial bus interface, which has a data block demultiplexing device. The data block demultiplexing device has a binary input, and the configuration is configured to receive a data block, and The data block is demultiplexed into a plurality of fine blocks. For each thin block, a parallel to serial converter can convert the thin block into serial data. A line can transmit serial data of each fine block. The serial to parallel converter can convert the serial data of each fine block to restore the fine block. The data block reconstruction device can merge the restored fine blocks into the data block. A user equipment (or a base station) has a gain control controller. The gain control controller generates a 0 data block having n bits representing a gain value. A data block demultiplexing device has an input configured to receive the The data block, and the data block is multiplexed into a plurality of fine blocks. Each of the fine blocks has a plurality of bits. For each of the fine blocks, a parallel-to-serial converter can convert the fine block into a serial data. , the line transmits the thin block Column data, and a series of parallel to parallel converters can convert the fine block serial data to restore the fine blocks. A data block reconstruction device can combine the restored fine blocks into the data block. The data block is received, and the gain value of the data block is used to adjust the gain. _ Embodiment FIG. 2 is a hybrid parallel/serial bus interface block diagram, and FIG. 3 is a hybrid parallel/ A serial bus interface data transfer operation flow chart. A data block is transmitted from the node 1 50 to the node 2 52 (54) across the interface. A data block demultiplexing device 40 receives the block, and It is multiplexed into i fine blocks to facilitate transmission on the i data transmission line 44 (56). This value i is based on the trade-off between the number of connections and the transmission speed. One way to determine the value of the mine page 1285316 (4) is to first determine the maximum delay for the transfer of the data block. Based on this maximum delay, the minimum number of lines required to transmit the block can be determined. With a minimum number of lines, the line used to transmit the data is selected to be at least the minimum amount. Line 44 can be a pin and its associated wiring on the board or on a 1C connection. One way to solve multiple work into thin blocks is to cut the block into a most significant to a least significant fine block. As illustrated in Figure 4, an eight-bit block is transmitted on two lines, and the block is multiplexed into a four-bit most significant thin block and a four-bit least significant fine block. Another way is to interleave the block across i fine blocks. The first i bits of the block will become the first bit of each i fine block. The next i bits will become the second bit of each i fine block, and so on until the last i bits. To illustrate an eight-bit block on two lines as shown in Figure 5, the first bit is mapped to the first bit of the thin block 1. The second bit will be mapped to the first bit of the thin block 2. The third bit will be mapped to the second bit of the thin block 1, and the success will continue until the last bit is mapped to the last bit of the thin block 2. Each of the thin blocks is sent to the corresponding (58) of the i parallel-to-serial train (P/S) converters 42, converted from parallel bits to serialized bits, and serially transmitted on the line ( 60). On the opposite side of each line will be a series of parallel to parallel (S/P) converters 46. Each S/P converter 46 converts the transmitted serial data into its original fine block (62). The i-th restored thin block is processed by a data block reconstruction device 48 to reconstruct the original data block ( 64). On the other hand, in the two-way mode, i lines are used to transfer data in a two-way manner, as shown in Figure 6. The information can be transmitted in both directions, or the mine page can be described in a single invention. Here, the capital 1285316 (5) transmits information in one direction and returns an acknowledgement signal in the other direction.
料區塊解多工及重建裝置66會接收從節點1 50傳送到節點 2 52的資料區塊。該解多工及重建裝置66會將該區塊解多 工成i個細塊。i個P/S轉換器68會將各個細塊轉換成串列資 料。一組多工器（MUX)/DEMUX 71將各個P/S轉換器68耦接到 i條線路44的相對應者。在節點2 52處，另一組的多工器 MUX/DEMUX 75將線路44連接到一組S/P轉換器72。該組S/P 轉換器72會將各細塊的所收串列資料轉換成為原始傳送 . _ - 『 的細塊。所收細塊會被一資料區塊解多工及重建裝置76 重建成原始資料區塊，並输出為所接收的資料區塊。 對於從節點2 52傳送到節點1 50的各區塊，該資料區塊 解多工及重建裝置76會接收一資料區塊。該區塊會被解多 工成為各細塊，並將各細塊傳送到一組P/S轉換器74。該 P/S轉換器74會將各細塊轉換成串列格式，以供跨於i條線 路44傳送。節點2組的MUX/DEMUX 75會將該等P/S轉換器74 耦接到i條線路44，而節點1組的MUX/DEMUX 71會將線路44 耦接到i個S/P轉換器70。該等S/P轉換器70將所傳資料轉換 成其原始細塊。該資料區塊解多工及重建裝置66從所收細 塊重建出資料區塊，以输出所接收的資料區塊。既然一次 只會在單一方向上傳送資料，這種實作可按半雙工方式運 作。 圖7係一雙向切換電路的實作簡圖。該節點1 P/S轉換器 68的串列输出會被输入到一三態式緩衝器78。該緩衝器78 具有另一输入，這會被耦接到一表示高狀態的電壓。該緩. -10- 1285316 -j (6) j發明說明鑛頁 衝器78的输出係串列資料，透過線路85被傳送到一節點2 三態式緩衝器84。電阻86會被耦接於線路85與接地之間。 該節點2緩衝器84傳通該串列資料給一節黠2S/P轉換器74 。類似地，來自該節點2 P/S轉換器74的串列输出會被输入 到一三態式緩衝器72。該緩衝器72也具有另一耦接於一高 電壓的输入。該緩衝器82的串列输出會透過線路85而傳送 到節點1三態式緩衝器80。該節點1緩衝器80會將該串列資 料傳通至一節點1 s/ρ轉換器70。 在另種實作裡，部分的i條線路44可在一方向上傳送資 料，而其他的i條線路44可在另一方向上傳送資料6在節 點1 50,會收到一資料區塊以供傳送到節黠2 52。根據該 區塊所需之資料產通速率以及另一方向上的話務需求而 定，在此會利用j條連線來傳送該區塊，其中該j值為1到i 之間。該區塊會被分成j個細塊，並利用i個P/S轉換器68中 的j個來轉換成j組串列資料。相對應的j個節點2 S/Ρ轉換器 72，與節點2資料區塊區別及重建裝置76會復原該資料區 塊。在相反方向上，會利用達i-j或k條線路以傳送該資料 區塊。 在一用於增益控制匯流排之雙向式匯流排較佳實作中 ，會在一方向上送出一增益控制值，並送返一確認信號。 或另者，在一方向上送出一增益控制值，而在另一方向上 送出一增益控制裝置狀態信號。 一種混合平行/串列介面實作係於一同步系統內，且可 參如圖8所說明者。在此，會利用一同步時脈以同步各式 1285316 ⑺ 發明說明績頁 元件的計時。為表述該資料區塊傳送作業的起點，會送出 一開始位元。即如圖8所示，各線路會在其正常零水準。 然後會送出一表示開始區塊傳送作業的開始位元。在本例 中，所有線路會送出一開始位元，然實僅需在一條線路上 送出開始位元。如在任一條線路上送出開始位元，像是一 1值，則接收節點會明瞭開始該區塊資料傳送作業。在此 ，會透過其相對應線路送出各個串列細塊。在傳送各細塊 後，線路會回返至彼等正常狀態，像是皆為低者。 在其他實作裡，也會利用開始位元做為待予執行之函數 · 的表示器。這種資作方式可如圖9說明。而如圖10所示者 ，如任一連線的第一位元為1值，該接收節點會瞭解待予 傳送區塊資料。即如圖11之GC控制器實作的表格所列，利 用三種開始位元組合：01、i〇及11。〇〇表示尚未送出開始 位元。各個組合代表一種函數。在本例中，〇1表示應執行 一相對減少函數，像是將該資料區塊值減少1值。10表示 應執行一相對增加函數，像是將該資料區塊值增加1值。 11表示應執行一絕對值函數，此時該區塊會維持相同數值 _ 。為增加可用函數的數目，可利用額外位元，例如，可將 每條線路2個開始位元映對到達七⑺項函數，或是將i條線 路的η個開始位元映對到達種函數。處理裝置86會依 闋始位元所述，對所收的資料匾塊執行函數。 在如圈12所示的另款實作裡，開始位元表示一目的地裝 置。即如圖13所示，此為兩個目的地裝置/兩條線路實作 ,開始位元的組合會關聯到對所傳資料區塊之目的地裝置 • 12 · 1285316 - ·- ⑻ I發明說明績頁 88-92。01表示裝置1 ; 1〇表示裝置2 ;而11表示裝置3。在收 到該資料區塊重建裝置48的開始位元後，所重建的區塊會 被送到相對應裝置88-92。為增加潛在目的地裝置的數目 ，可利用額外的開始位元。對於在各i條線路上的n個開始 位元，可選定達in+1-l個裝置。 即如圖14所示，可利用開始位元來表示函數及目的地裝 置兩者。圈14顯示一具有像是RX及TX GC兩個裝置的三條 連線系統。在各條線路上利用開始位元，圖中繪出兩個裝 置的三種函數。在本例中，線路1的開始位元代表該標的 裝置，「0」為裝置1,而「1」為裝置2。連線2及3的位元 代表所執行函數。「11」代表絕對值函數；「10」代表相對 增加函數；而「01」代表相對減少函數^所有三個開始位 元為零，意即「〇〇〇」，會是正常非資料傳送狀態，而在此 並未使用「001」。可利用額外的位元以增加更多的函數或 裝置。對於在各i條線路上的η個闋始位元，可選定達 個函數/裝置組合。 圖15係一實作表示函數及目的地裝置兩者之開始位元 的系統區塊圈。經復原的細塊會由該資料區塊重建裝置48 所接收。根據所收到的開始位元，該處理裝置86會執行所 述函數，而將所處理區塊送到所述之目的地裝置88-92。 即如圈16流程圖所示，會將表示該函數/目的地的開始 位元增入各個細塊內（94)。在此，會透過這i條線路送出這 些細塊（96)。利用開始位元，會在資料區塊上執行適當函 數，資料區塊會被送到適當目的地或兩者（98)。 1285316 -, (9) I發明說明鑛頁 為增加同步系統內的產通量，會利用時脈的正（雙）及負 (單）邊緣兩者來傳送區塊資料。其一實作可如圖17所示。 資料區塊解多工裝置1〇〇收到資料區塊，並將其解多工成 兩個（雙及單）組i個細塊。在此，會將i個細塊的各組資料 送到個別各組的i個P/S裝置102、104。即如圖17所示，一組 的單P/S裝置102會具有i個P/S裝置，這會擁有其經反置器 118所反置的時脈信號。因此，經反置的時脈信號會是經 相對於該系統時脈而延遲的半個時脈遇期。一組i個MUX 106會在該組雙P/S裝置104與該組單P/S裝置102之間，按兩 倍於該時脈速率而進行選定。在各連線上傳送的產獲資料 會是兩倍的時脈速率。在各連線的另一端是一相對應的 DEMUX 108。這些DEMUX 108會循序地按兩倍時脈速率， 將各條線路44耦接到一雙112與單110緩衝器。各個緩衝器 112、110接收一相對應的雙與單位元，並握持該數值一個 完整時脈週期。一雙116與單114組的S/P裝置會復原該等雙 與單細塊。一資料區塊重建裝置122會從各個所傳細塊重 建該資料區塊。 圖18說明利用該正及負時脈邊緣，在一系統線路上進行 的資料傳送作業。圖示者係待予於線路1上傳送的雙資料 與單資料。斜楔部分表示合併信號內的負時脈邊緣，而無 斜禊部分則表示正者。即如圖示，資料傳送速率會增加一 倍。 圖19係一用於一 GC控制器38及一 GC 124之間的混合平行 /串列介面較佳實作。一資料區塊，像是16位元的GC控制 1285316 · 發明說明續頁 38傳送給一 (10) 資料（8位元RX和8位元TX)，會被從該GC控制器 資料區塊解多工裝置40b該資料區塊會被解多工成為兩個 細塊，像是兩個8位元細塊。會對各個細塊增附一開始位 元，像是令為每個細塊9位元。在此，會利用兩個p/s轉換 器42於兩條線路上傳送這兩個細塊。當S/P轉換器46偵測到 開始位元時就會將所接收細塊轉換為平行格式。該資料區 塊重建裝置會重建原始16位元以控制GC 124的增益。如開 始位元表述出一函數，即如圖11所示，該AGC 124會在調 整增益之前，先對所收區塊執行該項函數。 圖20係於一混合平行/串列匯流排轉換器另一較佳實作 ，此係位於GC控制器38及一 RX GC 30與TX GC 32間，並利 用三（3)條線路。該GC控制器38會按適當RX及TX增益值與 開始位元，即如圈14所示，送出一資料區塊給該GC 30、 32。如確採用按圖14的開始位元，裝置1為RX GC 30而裝置 2為TX GC 32〇該資料區塊解多工裝置40會將該資料區塊解 多工成為三個細塊，以供透過這三條線路而傳送。利用三 個P/S轉換器42及三個S/P轉換46,各細塊會被串列地在各 線路上傳送，並轉換成原始細塊。該資料區塊重建裝置48 會重建原始資料區塊，並執行如開始位元所述之函數，像 是相對增加、相對減少及絕對值。所獲資料會被送到如開 始位元所述之RX或TX GC 30、32。 圖式簡單說明 圈1係RX與TX GC和GC控制器圖式說明。 圖2係一混合平行/串列匯流排介面區塊閫。 1285316 00 發明說明續頁 圖3係利用混合平行/串列匯流排介面之資料區塊傳送 作業流程圖。 圖4說明將一區塊轉成最顯著及最小顯著細塊之解多工 作業。 圖5說明利用資料交錯處理對一區塊進行解多工作業。 圖6係一雙向混合平行/串列匯流排介面之區塊圖。 圖7係一雙向線路實作圖式。 圖8係開始位元之計時圖。The block demultiplexing and reconstruction device 66 receives the data block transmitted from the node 150 to the node 2 52. The demultiplexing and reconstruction device 66 will demultiplex the block into i fine blocks. The i P/S converters 68 convert each of the thin blocks into a serial data. A set of multiplexers (MUX) / DEMUX 71 couples the respective P/S converters 68 to the corresponding ones of the i lines 44. At node 2 52, another set of multiplexer MUX/DEMUX 75 connects line 44 to a set of S/P converters 72. The set of S/P converters 72 converts the received serial data of each thin block into a thin block of the original transmission. _ - 『. The received fine block is reconstructed into a raw data block by a data block demultiplexing and reconstruction device 76 and output as a received data block. For each block transmitted from node 2 52 to node 150, the data block demultiplexing and reconstruction device 76 receives a data block. The block is demultiplexed into individual blocks and the blocks are transferred to a set of P/S converters 74. The P/S converter 74 converts the fine blocks into a serial format for transmission across the i lines 44. The MUX/DEMUX 75 of the Node 2 group couples the P/S converters 74 to the i lines 44, while the MUX/DEMUX 71 of the Node 1 group couples the lines 44 to the i S/P converters 70. . The S/P converters 70 convert the transmitted data into its original thin blocks. The data block demultiplexing and reconstruction device 66 reconstructs the data block from the received block to output the received data block. Since the data will only be transmitted in a single direction at a time, this implementation can be operated in a half-duplex manner. Figure 7 is a schematic diagram of the implementation of a bidirectional switching circuit. The serial output of the Node 1 P/S converter 68 is input to a tristate buffer 78. The buffer 78 has another input that is coupled to a voltage indicative of a high state. The delay. -10- 1285316 -j (6) The invention indicates that the output of the miner 78 is serially transmitted through line 85 to a node 2 tristate buffer 84. Resistor 86 is coupled between line 85 and ground. The node 2 buffer 84 passes the serial data to a 黠2S/P converter 74. Similarly, the serial output from the Node 2 P/S converter 74 is input to a tristate buffer 72. The buffer 72 also has another input coupled to a high voltage. The serial output of buffer 82 is transferred to node 1 tristate buffer 80 via line 85. The Node 1 buffer 80 will pass the serial data to a node 1 s/ρ converter 70. In another implementation, some of the i lines 44 can transmit data in one direction, while the other i lines 44 can transmit data 6 in the other direction at node 150, and receive a data block for transmission. To the festival 2 52. Depending on the data throughput rate required for the block and the traffic demand in the other direction, the j block is used to transfer the block, where the j value is between 1 and i. The block is divided into j thin blocks and converted into j sets of serial data using j of the i P/S converters 68. The corresponding j-node 2 S/Ρ converter 72, which is distinguished from the node 2 data block, and the reconstruction device 76 will restore the data block. In the opposite direction, i-j or k lines are used to transmit the data block. In a preferred implementation of a two-way bus for gain control bus, a gain control value is sent in one direction and an acknowledge signal is sent back. Alternatively, a gain control value is sent in one direction and a gain control device status signal is sent in the other direction. A hybrid parallel/serial interface implementation is incorporated into a synchronous system and can be referenced as illustrated in FIG. Here, a synchronization clock is used to synchronize the timing of the various components of the model 1285316 (7). In order to express the starting point of the data block transfer operation, a start bit is sent. That is, as shown in Figure 8, each line will be at its normal zero level. A start bit indicating the start of the block transfer job is then sent. In this example, all lines will send a start bit, but only the start bit will be sent on one line. If a start bit is sent on any line, such as a value of 1, the receiving node will know to start the block data transfer operation. Here, each of the tandem blocks is sent through its corresponding line. After transmitting the fine blocks, the lines will return to their normal state, as if they were all low. In other implementations, the start bit is also used as a representation of the function to be executed. This type of capitalization can be illustrated in Figure 9. As shown in FIG. 10, if the first bit of any connection is a value, the receiving node knows the data to be transmitted. That is, as shown in the table of the GC controller implementation shown in Figure 11, three combinations of start bits are used: 01, i〇, and 11. 〇〇 indicates that the start bit has not been sent. Each combination represents a function. In this example, 〇1 indicates that a relative reduction function should be performed, such as reducing the data block value by one. 10 indicates that a relative increase function should be performed, such as increasing the value of the data block by one. 11 indicates that an absolute value function should be executed, and the block will maintain the same value _ . In order to increase the number of available functions, additional bits can be utilized. For example, two start bits of each line can be mapped to the seven (7) term function, or the n start bits of i lines can be mapped to the seed function. . Processing device 86 executes the function on the received data block as described in the first bit. In the alternative implementation as shown in circle 12, the start bit represents a destination device. That is, as shown in Figure 13, this is the implementation of two destination devices/two lines, and the combination of the starting bits is associated with the destination device for the transmitted data block. • 12 · 1285316 - (-) Results page 88-92. 01 indicates device 1; 1 indicates device 2; and 11 indicates device 3. After receiving the start bit of the data block reconstruction device 48, the reconstructed block is sent to the corresponding device 88-92. To increase the number of potential destination devices, additional start bits can be utilized. For n start bits on each i line, up to 1 - 1 devices can be selected. That is, as shown in Fig. 14, both the function and the destination device can be represented by the start bit. Circle 14 shows a three-wire system with two devices like RX and TX GC. The start bit is used on each line, and the three functions of the two devices are drawn in the figure. In this example, the start bit of line 1 represents the target device, with "0" being device 1 and "1" being device 2. The bits of lines 2 and 3 represent the function being executed. "11" represents an absolute value function; "10" represents a relative increase function; and "01" represents a relative reduction function ^ all three start bits are zero, meaning "〇〇〇", which is a normal non-data transfer state, "001" is not used here. Additional bits can be utilized to add more functions or devices. For each of the n start bits on each of the i lines, a function/device combination can be selected. Figure 15 is a system block circle that implements the start bit of both the function and the destination device. The recovered thin blocks are received by the data block reconstruction device 48. Based on the received start bit, the processing device 86 executes the function and sends the processed block to the destination device 88-92. That is, as shown in the flowchart of circle 16, the start bit indicating the function/destination is added to each of the thin blocks (94). Here, these fine blocks (96) are sent through the i lines. With the start bit, the appropriate function is executed on the data block and the data block is sent to the appropriate destination or both (98). 1285316 -, (9) I invention description of the mine page In order to increase the throughput in the synchronous system, the block data is transmitted using both the positive (double) and negative (single) edges of the clock. One of the implementations can be as shown in FIG. The data block demultiplexing device receives the data block and demultiplexes it into two (double and single) groups of n fine blocks. Here, each group of i blocks of data is sent to the i P/S devices 102 and 104 of the respective groups. That is, as shown in Figure 17, a group of single P/S devices 102 will have i P/S devices, which will have their own clock signals inverted by the inverse device 118. Thus, the inverted clock signal will be a half-clock delay that is delayed relative to the system clock. A set of i MUXs 106 will be selected between the set of dual P/S devices 104 and the set of single P/S devices 102 by twice the clock rate. The data obtained on each connection will be twice the clock rate. At the other end of each connection is a corresponding DEMUX 108. These DEMUXs 108 sequentially couple each line 44 to a pair 112 and a single 110 buffer at twice the clock rate. Each of the buffers 112, 110 receives a corresponding double and unit cell and holds the value for a full clock cycle. A pair of 116 and a single 114 S/P unit will restore the double and single blocks. A data block reconstruction device 122 reconstructs the data block from each of the transmitted fine blocks. Figure 18 illustrates the data transfer operation performed on a system line using the positive and negative clock edges. The figure is the double data and single data to be transmitted on line 1. The wedge portion represents the negative clock edge within the combined signal, while the non-slash portion represents the positive. As shown, the data transfer rate will be doubled. Figure 19 is a preferred implementation of a hybrid parallel/serial interface between a GC controller 38 and a GC 124. A data block, such as a 16-bit GC control 1285316 · Description of the invention continuation 38 is transmitted to a (10) data (8-bit RX and 8-bit TX), which will be solved from the GC controller data block The multiplex device 40b will be multiplexed into two thin blocks, such as two 8-bit thin blocks. A starting bit is added to each of the thin blocks, such as 9 bits for each thin block. Here, two p/s converters 42 are used to transmit the two thin blocks on two lines. The received fine block is converted to a parallel format when the S/P converter 46 detects the start bit. The data block reconstruction device reconstructs the original 16 bits to control the gain of the GC 124. If the starting bit represents a function, as shown in Figure 11, the AGC 124 will perform the function on the received block before adjusting the gain. Figure 20 is another preferred embodiment of a hybrid parallel/serial bus converter located between the GC controller 38 and an RX GC 30 and TX GC 32 and utilizing three (3) lines. The GC controller 38 sends a data block to the GC 30, 32 at the appropriate RX and TX gain values and the start bit, as indicated by circle 14. If the starting bit according to Figure 14 is used, device 1 is RX GC 30 and device 2 is TX GC 32. The data block demultiplexing device 40 will demultiplex the data block into three fine blocks to For transmission through these three lines. With three P/S converters 42 and three S/P conversions 46, the fine blocks are transmitted in series on each line and converted into original thin blocks. The data block reconstruction unit 48 reconstructs the original data block and performs functions such as relative increase, relative decrease, and absolute value as described in the start bit. The information obtained will be sent to the RX or TX GC 30, 32 as described in the starting bit. A brief description of the pattern Circle 1 is a graphical representation of the RX and TX GC and GC controllers. Figure 2 is a hybrid parallel/serial bus interface block. 1285316 00 DETAILED DESCRIPTION OF THE INVENTION Figure 3 is a flow chart of a data block transfer operation using a hybrid parallel/serial bus interface. Figure 4 illustrates the multiplexed operation of converting a block into the most significant and least significant fine blocks. Figure 5 illustrates the use of data interleaving to solve a block of work. Figure 6 is a block diagram of a bidirectional hybrid parallel/serial bus interface. Figure 7 is a two-way line implementation diagram. Figure 8 is a timing diagram of the starting bit.
圖9係一函數可控制性之混合平行/串列匯流排介面的 區塊圖。 圖10係一函數可控制性之混合平行/串列匯流排介面的 開始位元計時圖。 圖11係表示各項函數之開始位元實作列表。 圖12係目的地控制混合平行/串列匯流排介面之區塊圖。 圖13係表示各項目的地之開始位元實作列表。 圖14係表示各項目的地/函數之開始位元實作列表。 圖15係目的地/函數控制混合平行/串列匯流排介面之區 塊圈。 圖16係表示各項目的地/函數之開始位元流程圖。 圖17係正及負時脈邊緣之混合平行/串列匯流排介面區 塊圖。 圖18係正及負時脈邊緣之混合平行/串列匯流排介面計 時圖。 圖19係一 2線式GC/GC控制器圈流排區塊圖。 16 1285316 (12) 發明說明績頁 圖20係一 3線式GC/GC控制器匯流排區塊圖 圖式代表符號說明 30 接收增益控制器 32 傳送增益控制器 34 線路匯流排 36 線路匯流排 38 GC控制器 40 資料區塊解多工裝置 42 平行轉串列（P/S)轉換器 44 資料傳送線路 46 串列轉平行（S/P)轉換器 48 資料區塊重建裝置 50 節點1 52 節點2 66 資料區塊解多工及重建裝置 68 平行轉串列（P/S)轉換器 70 串列轉平行（S/P)轉換器 72 串列轉平行（S/P)轉換器 74 平行轉串列（P/S)轉換器 76 資料區塊解多工及重建裝S 78 緩衝器 80 緩衝器 82 緩衝器 84 緩衝器 1285316 (13) 發明說明續頁 85 86 88 90 92 100 102 104 106 108 110 112 114 116 122 124 線路 鼋阻 目的地裝置 目的地裝置 目的地裝置 資料區塊解多工裝置 單P/S裝置 雙P/S裝置 多工器 解多工器 緩衝器 緩衝器 單P/S裝置 雙P/S裝置 資料區塊重建裝置 增益控制器Figure 9 is a block diagram of a hybrid parallel/serial bus interface of function controllability. Figure 10 is a start bit timing diagram of a hybrid parallel/serial bus interface of function controllability. Figure 11 is a diagram showing the starting bit implementation of each function. Figure 12 is a block diagram of the destination control hybrid parallel/serial bus interface. Figure 13 is a list of the starting bits of each destination. Figure 14 is a list of implementations of start bits for each destination/function. Figure 15 is a block diagram of the destination/function control hybrid parallel/serial bus interface. Figure 16 is a flow chart showing the start bit of each destination/function. Figure 17 is a block diagram of a hybrid parallel/serial bus interface interface for positive and negative clock edges. Figure 18 is a timing diagram of a hybrid parallel/serial bus interface interface for positive and negative clock edges. Figure 19 is a block diagram of a 2-wire GC/GC controller loop. 16 1285316 (12) Summary of the Invention Figure 20 is a 3-wire GC/GC controller bus block diagram diagram representation symbol description 30 receive gain controller 32 transmit gain controller 34 line bus 36 line bus 38 GC controller 40 data block demultiplexer 42 parallel to serial (P/S) converter 44 data transmission line 46 serial to parallel (S/P) converter 48 data block reconstruction device 50 node 1 52 nodes 2 66 Data block demultiplexing and reconstruction device 68 Parallel to serial (P/S) converter 70 Tandem to parallel (S/P) converter 72 Tandem to parallel (S/P) converter 74 Parallel Serial (P/S) Converter 76 Data Block Demultiplexing and Reconstruction S 78 Buffer 80 Buffer 82 Buffer 84 Buffer 1285316 (13) Summary of Invention Continuation 85 86 88 90 92 100 102 104 106 108 110 112 114 116 122 124 Line Resistance Destination Device Destination Device Destination Device Data Block Demultiplexer Single P/S Device Dual P/S Device Multiplexer Solution Multiplexer Buffer Buffer Single P/S Device dual P/S device data block reconstruction device gain controller
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