JPH05160819A - Data transfer equipment - Google Patents

Abstract

PURPOSE:To eliminate the need for simultaneous changeover of all serial interface circuits and for a fault detection means testing all the serial interface circuits at a desired period. CONSTITUTION:Test data are inputted from changeover circuits 1301-130n to parallel serial conversion circuits 1201-120n, the test data received by parallel serial conversion circuits 2201-220n are compared by a comparator circuit 230, a fault detection circuit 240 specifies a faulty serial interface circuit to inform it to a fault display circuit 270 as a fault detection means. Furthermore, the fault display circuit 270 informs the faulty serial interface circuit to a data division circuit 170 and a data edit circuit 280 to allow them to be closed. The data division circuit 170 re-distributes input data in the transmission unit able to be sent by the normal serial interface circuit and inputs the divided data to each serial interface circuit separately.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer device for carrying out data transfer using a plurality of serial interface circuits, and more particularly to fault handling of serial interface circuits.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram of a conventional example of a data transfer device, and FIG. 6 is a block diagram of a conventional example of a data transfer device provided with an alternative circuit.

As shown in FIG. 5, a conventional data transfer apparatus includes a transmission data generation circuit 100 and a data division circuit 11.
0, a transmission circuit 15 including a parallel-serial conversion circuit 120, a serial-parallel conversion circuit 220, a data editing circuit 210, and a receiving circuit 25 including a data receiving circuit 200.

In this data transfer device, the transmission data generated by the transmission data generation circuit 100 is the data line 100.
It is transferred to the data division circuit 110 through -1 and divided into data transmission units. The division unit is selected so that it can be easily handled on the serial interface circuit.
It was divided into units such as 8 bytes and 16 bytes.

The divided data is sent to the parallel-serial conversion circuit 120 by the data lines 110-1 to 110-n for each data, converted into serial data, and then passed through the serial interfaces 120-1 to 120-n. , Receiver circuit 2
5 is sent.

Serial interfaces 120-1 to 12
The data transferred on 0-n is received by the serial-parallel conversion circuit 220 of the receiving circuit 25, restored to parallel data by this circuit, and then passed through the data lines 220-1 to 220-n. It is sent to the editing circuit 210. The data editing circuit restores the data structure before division and sends it to the data receiving circuit 200.

That is, the transmitting / receiving circuit 15 to the receiving circuit 2
The data transfer to 5 was carried out via a plurality of serial interface circuits.

Further, when a failure occurs in the serial interface circuits, all the serial interface circuits can be switched all at once to the alternative circuit 410 shown in FIG.

[0009]

In the above-mentioned conventional data transfer device, when one of the serial interface circuits fails, data transfer from the transmission circuit 15 to the reception circuit 25 cannot be performed. Therefore, all the serial interface circuits are closed, and the switching circuit 400 and the alternative circuit 410 switch all the serial interface circuits to the alternative circuits to recover from the failure.

Therefore, even if some of the serial interface circuits fail, all of the serial interface circuits will be blocked, and waste will occur.

Further, in order to increase the speed, a general method is to increase the number of serial interface circuits for division transfer to improve the transfer capability, but it is extremely expensive to provide a failure detection circuit for each serial interface circuit. There are drawbacks.

Further, if all the circuits are blocked when the serial interface circuit fails, it becomes impossible to collect the fault information using the interface circuit, and a dedicated interface circuit is provided to collect the fault information. The need arises. This also increases the number of expensive serial interface circuits, which makes the device more expensive.

An object of the present invention is to provide a data transfer device which does not need to switch all the serial interface circuits to the spare serial interface circuits all at once in the event of a failure.

[0014]

A data transfer apparatus according to the present invention comprises a timing generating means for generating a predetermined test timing, a test data generating means for generating test data for testing each serial interface circuit, and a predetermined test. Test data sending means for sending the test data to a predetermined serial interface circuit at a timing; receiving means for receiving the test data from the serial interface circuit;
The data transfer apparatus according to the present invention has a predetermined number of serial interfaces that are provided for constant division transfer, having failure detection means including comparison means for comparing the contents of received test data with each other and detecting a failure. In addition to the circuit, a spare serial interface circuit provided, a fault circuit identifying unit that identifies the serial interface circuit in which a fault is detected, and a switching unit that switches the serial interface circuit in which the fault is detected to the spare serial interface circuit. And a fault circuit specifying means for specifying a serial interface circuit in which a fault is detected, a blocking means for blocking the serial interface circuit identified by the fault circuit specifying means, and a transfer by the blocked serial interface circuit Other normal data that was supposed to be It also includes a data transfer device having a redistribution means for allocating to operating serial interface circuits, and further includes means for collecting failure information, failure circuit identification means, and serial interface circuits excluding the serial interface circuit that has failed. Also included is a data transfer device having means for selecting one of the above and transmitting the failure information, and means for receiving the failure information.

[0015]

In the fault detection, the test data is sent to each serial interface circuit at a predetermined test timing, the received test data are compared with each other, and the quality thereof is detected, so that the occurrence of the fault can be immediately detected.

Further, when a failure is detected, the failure display circuit switches the failed serial interface circuit to a spare if there is a spare serial interface circuit,
When there is no spare, the redistribution means distributes and transmits the transmission data that was supposed to be sent to the failed serial interface circuit to other normally operating serial interface circuits. Transfers are continuous.

Further, since a failure is detected and the failure information of the serial interface circuit identified as the failure circuit is collected and received by the failure information receiving circuit via the normal serial circuit, it is possible to provide countermeasures against the failure.

[0018]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram of a first embodiment of a data transfer apparatus of the present invention.

The transmission circuit 10 includes a transmission data generation circuit 10
0, data division circuit 110, parallel-serial conversion circuit 120 ₁ ~
120 _n , switching circuits 130 _{1 to} 130 _n , test data generating circuit 140, and timing generating circuit 150.

The receiving circuit 20 is a data receiving circuit 200,
It is composed of a data editing circuit 210, a serial / parallel conversion circuit 220, a comparison circuit 230, and a failure detection circuit 240.

Transmission data generation circuit 100, data division
Circuit 110, parallel-serial conversion circuit 120 ₁ ~ 120_n , Day
Data receiving circuit 200, data editing circuit 210, serial-parallel conversion
Circuit 220₁ ~ 220_n Is the same as the conventional circuit. Off
Replacement circuit 130₁ ~ 130_nIs transfer data and test data
To switch and output. The test data generation circuit 140
This is a circuit that generates test data. Timing generation circuit 1
The switching circuit 130 generates a signal at a predetermined cycle.₁ 
~ 130_n The switching operation of is started. The comparison circuit 230 receives
The test data for each serial interface circuit
The results are compared and output. The fault detection circuit 240
Syria obstructed by the output of the comparison circuit 230
Interface circuit.

In normal data transfer, the data from the transmission data generating circuit 100 is transferred to the data dividing circuit 110 via the data line 100-1, and the data dividing circuit 1
The data divided by 10 is transferred to the switching circuit 130 via the data line 110-1. Switching circuit 130 ₁ ~
The data sent to 130 _n are data lines 130-1 to 130-1.
Parallel-serial conversion circuits 120 _{1 to} 120 _n via 30- _n
Sent to. The data sent to the parallel / serial conversion circuits 120 _{1 to} 120 _n is transferred to the serial / parallel conversion circuit 220 in the reception circuit 20.
Receiving circuit 2 via serial interfaces 120-1 to 120-n that connect 1 to 220 _n in a one-to- _one relationship
Transfer data to 0. Serial interface 120
_The data transferred over _{1 to} 120 _n is received by the receiving circuit 2.
The serial / parallel conversion circuits 220 _{1 to} 220 _n in 0 receive the
The data sent to the data editing circuit 210 via the data lines 220-1 to 220-n, and the data sent to the data editing circuit 210 has a shape of the data before being divided by the data dividing circuit 110 in the transmitting circuit 10. And is transferred to the data receiving circuit 200 via the data line 210-1.

When the patrol function for activating the test is operated, the switching circuits 130 _{1 to} 130 _n instructed to perform the patrol operation by the signal generation line 150-1 from the timing generation circuit 150 in the transmission circuit 10 switch the input data and execute the test. The test data from the data generating circuit 140 is transferred to the data line 140-
1 through 120. Parallel-serial conversion circuits 120 _{1 to} 120
transfer to _n . The data sent to the parallel / serial conversion circuits 120 _{1 to} 120 _n is transferred to the serial / parallel conversion circuit 22 in the reception circuit 20.
0 _{1 to} 220 _n are transferred to the receiving circuit 20 via the serial interface circuits 1 to _n which are connected to each other in a one-to- _one relationship. The data transferred on the serial interface circuits 1 to n is transferred to the serial / parallel conversion circuit 22 in the reception circuit 20.
0 _{1 to} 220 _n and data lines 220-1 to 22
The data is transferred to the data editing circuit 210 via 0-n and also to the comparison circuit 230.
30 are compared with each other, and the comparison result is the signal line 2
In step 30-1, it is transferred to the fault detection circuit 240. The occurrence of a failure is detected from the result transferred by the failure detection circuit 240.

FIG. 2 is a block diagram of the second embodiment of the data transfer apparatus of the present invention.

The transmission circuit 11 is a transmission data generation circuit 10
0, data division circuit 110, matrix switch circuit 1
60, parallel-serial conversion circuits 120 _{1 to} 120 _n .

The receiving circuit 21 is a data receiving circuit 200,
Data editing circuit 210, serial / parallel conversion circuits 220 _{1 to} 22
0 _n , matrix switch circuit 250, fault detection circuit 2
60 and a failure display circuit 270.

The matrix switch circuit 250 uses the data
Split line 110 and parallel-serial conversion circuit 120₁ ~ 120_n ,
In the middle of 120m, a switching circuit intervenes in the middle
When the serial interface circuit that became
Switch to the serial interface circuit. Matri
The x-switch circuit 250 includes a serial-parallel conversion circuit 220. ₁ 
~ 220_n , 220_m Between the data editing circuit 210 and
Interfering with the serial interface circuit
If specified, the spare serial interface circuit 220
_m Switch to. The fault detection circuit 260 fails
Found a failure if there was a serial interface circuit
And specify the circuit. Fault display circuit 270
Identifies the faulty serial interface circuit.
The matrix switch circuits 160 and 250,
Notify the real interface circuit and instruct switching.

FIG. 3 is a block diagram of a third embodiment of the data transfer apparatus of the present invention.

This data transfer device is shown in the first embodiment.
A component as a failure detection means is included. did
Therefore, the transmission circuit 12 is the transmission data generation circuit 100.
A data division circuit 170 and a switching circuit 130.₁ ~ 13
0_n And the parallel-serial conversion circuit 120 ₁ ~ 120_n And the test data
Data generation circuit 140 and timing generation circuit 150
is doing. The receiving circuit 22 includes a data receiving circuit 200,
Serial-parallel conversion circuit 220₁~ 220_n And the data editing circuit
280, a comparison circuit 230, a failure detection circuit 240,
It has a fault display circuit 270.

In addition to the function of the data division circuit 110, the data division circuit 170 closes the serial interface circuit when it receives a switching instruction designating the faulty serial interface circuit and divides the data normally. It has the function of redistributing and inputting into transmission units that can be transmitted by the circuit. In addition, the data editing circuit 2
In addition to the function of the data editing circuit 210, the reference numeral 80 is edited so that when a switching instruction designating a faulty serial interface circuit is received, the serial interface circuit is blocked and redistributed data is received. Have the function to When the fault display circuit 270 receives the fault notification designating the faulty serial interface circuit from the fault detection circuit 240, the fault display circuit 270 becomes a fault to the data division circuit 170 of the transmission circuit 12 and the data editing circuit 280 of the reception circuit 22. The switching instruction specifying the serial interface circuit is output.

Data from the transmission data generation circuit 100
Is the data division circuit 17 via the data line 100-1.
Data transferred to 0 and divided by the data division circuit 170.
Data through the data lines 110-1 to 110-n.
Serial conversion circuit 120₁ ~ 120 _n Transferred to. Average series
Conversion circuit 120₁ ~ 120_n Data transferred to the
Via the real interfaces 120-1 to 120-n
Serial-parallel conversion circuit 220 in the receiving circuit 22₁ ~ 220_n 
Transferred to. Serial-parallel conversion circuit 220₁ ~ 220 _n Received by
The received data passes through the data lines 220-1 to 220-n.
Therefore, the data is transferred to the data editing circuit 280 and the failure is detected.
It is transferred to the output circuit 260 and transferred to the failure detection circuit 260.
The failure is detected by the received test data. Fault detected
When issued, the fault display circuit 2 is routed through the signal line 260-1.
70 is notified. Fault display circuit 27 notified of a fault
0 through the signal line 270-2 to the transmission circuit 12
To notify the data editing circuit 280 at the same time
Even if a notification occurs via the signal line 270-1 and a failure occurs,
Separate the serial interface circuit and divide the data
Instruct the circuit 170 to use another serial that is operating normally.
In the interface circuit, the serial interface
Retransmission data including data to be transferred by the face circuit
Allocate and transfer.

FIG. 4 is a block diagram of a fourth embodiment of the data transfer apparatus of the present invention.

The transmission circuit 13 is the transmission data generation circuit 10
0, data division circuit 110, parallel-serial conversion circuit 120 ₁ ~
120 _n , switching circuits 130 _{1 to} 130 _n , fault information collection circuit 180, and path selection circuit 190.

The receiving circuit 23 is a data receiving circuit 200,
Data editing circuit 210, serial / parallel conversion circuits 220 _{1 to} 22
0 _n , a failure detection circuit 260, a failure display circuit 270, a switching circuit 290, and a failure information receiving circuit 300. The fault information collection circuit 180 investigates and outputs the fault type by receiving the fault notification. Path selection circuit 1
Upon receiving the fault notification, 90 designates a normal serial interface circuit, switches its switching start, and connects the output of the fault information collecting circuit 180. The switching circuit 290 selects and notifies only the failure information from the transmission circuit 13 according to the instruction from the failure display circuit 270. The fault information receiving circuit 300 is a circuit that edits and receives the fault information notified by the selection circuit 290.

The data from the transmission data generating circuit 100 is sent to the data dividing circuit 110 using the data line 100-1.
Data transferred to the parallel division conversion circuit 120 via the data lines 110-1 to 110-n and the switching circuits 130 _{1 to} 130 _{n.
1 to} 120 _n . Parallel-serial conversion circuit 120 ₁ ~
The data transferred to 120 _n is transferred to the serial-parallel conversion circuits 220 _{1 to} 220 _n in the receiving circuit 23 via the serial interfaces 120-1 to 120-n. The data received by the serial-parallel conversion circuits 220 _{1 to} 220 _n is transferred to the data editing circuit 210 via the data lines 220-1 to 220-n and also transferred to the failure detection circuit 260, and the failure detection circuit 260 is transferred. Detects a failure in the data transferred in. When a fault is detected, the signal line 260-
The failure display circuit 270 is notified via 1. The failure display circuit 270 notified of the failure notifies the transmission circuit 13 of the occurrence of the failure via the signal line 270-2 and notifies the data editing circuit 210 of the failure via the signal line 270-1. Is notified and the faulty serial interface circuit is disconnected. When the transmission circuit 13 collects the failure information in the failure information collection circuit 180 and receives the failure occurrence notification from the reception circuit 23 in the path selection circuit 190, the serial circuit operating normally via the signal line 190-1. The interface circuit is designated and the switching circuit 13
The input of 0 is switched, and the failure information collection circuit 180 transfers the failure information to the reception circuit 23 via the data line 180-1 via the serial interface circuit which operates normally. The reception circuit 23 to which the failure information has been transferred is switched to the switching circuit 29 by the signal line 270-1 from the failure display circuit 270.
0 is activated and the fault information receiving circuit 300 receives the fault information from the transmitting circuit 13.

[0037]

As described above, according to the present invention, since all serial interface circuits are tested at a desired timing, it is not necessary to provide an expensive fault detection circuit for each serial interface circuit, which is inexpensive and reliable. A high serial interface circuit can be configured, and a check mechanism that can check the normality of the serial interface circuit without affecting normal operation can be provided at low cost, and a standby serial interface circuit can be detected by fault detection. When it has, the failed circuit is switched to the spare, or the data that was supposed to be transferred by the failed circuit is redistributed to another normal serial interface circuit, so that some serial interface circuits Even if it fails, all serial interface Without closing the, there is an effect that it is possible to construct a serial interface circuit capable of continuing the operation of the circuit with minimal investment.

Further, even if the serial interface circuit fails, by limiting the failed serial interface circuit, it is possible to construct a serial interface circuit capable of collecting the failure information with a minimum required investment.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of a data transfer device of the present invention.

FIG. 2 is a block diagram of a second embodiment of a data transfer device of the present invention.

FIG. 3 is a block diagram of a third embodiment of a data transfer device of the present invention.

FIG. 4 is a block diagram of a fourth embodiment of the data transfer apparatus of the present invention.

FIG. 5 is a block diagram of a conventional example of a data transfer device.

FIG. 6 is a block diagram including an alternative circuit of a conventional data transfer device.

[Explanation of symbols]

1 to n Serial interface circuit 10, 11, 12, 13 Transmission circuit 100 Transmission data generation circuit 100-1 Data line 110 Data division circuit 110-1 Data line 120 _{1 to} 120 _n Parallel-serial conversion circuit 120-1 to 120-n Serial interface 130 _{1 to} 130 _n switching circuit 130-1 to 130-n data line 140 test data generation circuit 140-1 data line 150 timing generation circuit 150-1 signal line 160 matrix switch circuit 160-1 to 160-n 170 data Dividing circuit 170-1 to 170-n Data line 180 Fault information collecting circuit 180-1 Data line 190 Bus selection 190-1 Signal line 20, 21, 22, 23 Reception circuit 200 Data reception circuit 210, 280 Data editing circuit 210- 1,280-1 data line 20 ₁ to 220 _n serial-parallel conversion circuits 220-1 to 220-n the data line 230 comparator circuit 230-1 a signal line 240 the fault detection circuit 250 matrix switch circuits 250-1 to 250-n data lines 260 fault detection circuit 260-1 Signal line 270 Fault display circuit 270-1, 270-2 Signal line 290 Switching circuit 290-1 Data line 300 Fault information receiving circuit

Claims (4)

[Claims] 1. A transmission data generation circuit, a data division circuit,
A data transfer device having a transmission circuit including a parallel-serial conversion circuit and a reception circuit including a serial-parallel conversion circuit, a data editing circuit, a data receiving circuit, and a failure detection circuit, and dividing and transferring data by a plurality of serial interface circuits , A timing generation means for generating a predetermined test timing, a test data generation means for generating test data for testing each serial interface circuit, and a test data for sending the test data to each serial interface circuit at a predetermined test timing. Data having a failure detecting means including a sending means, a receiving means for receiving test data from each serial interface circuit, and a comparing means for comparing the contents of the received test data with each other to detect a failure. Transfer device. 2. A transmission data generation circuit, a data division circuit,
A data transfer device having a transmission circuit including a parallel-serial conversion circuit and a reception circuit including a serial-parallel conversion circuit, a data editing circuit, a data receiving circuit, and a failure detection circuit, and dividing and transferring data by a plurality of serial interface circuits , A spare serial interface circuit provided in addition to the predetermined number of serial interface circuits that are always used for division transfer, fault circuit identification means for identifying the serial interface circuit in which a fault has been detected, and a fault has been detected. A data transfer device comprising switching means for switching a serial interface circuit to a spare serial interface circuit. 3. A transmission data generation circuit, a data division circuit,
A data transfer device having a transmission circuit including a parallel-serial conversion circuit and a reception circuit including a serial-parallel conversion circuit, a data editing circuit, a data receiving circuit, and a failure detection circuit, and dividing and transferring data by a plurality of serial interface circuits In the above, the failure circuit identifying means for identifying the serial interface circuit in which the failure is detected, the blocking means for blocking the serial interface circuit identified by the failure circuit identifying means, and the blocked serial interface circuit are used for transfer. A data transfer device having redistribution means for allocating the existing data to another normally operating serial interface circuit. 4. A transmission data generation circuit, a data division circuit,
A data transfer device having a transmission circuit including a parallel-serial conversion circuit and a reception circuit including a serial-parallel conversion circuit, a data editing circuit, a data receiving circuit, and a failure detection circuit, and dividing and transferring data by a plurality of serial interface circuits , A failure circuit identifying means for identifying the serial interface circuit in which the failure is detected, and one of the serial interface circuits excluding the circuit when the failed serial interface circuit is identified. A data transfer device comprising: means for selecting one of the failure information and transmitting the failure information; and means for receiving the failure information.