CN100346327C - User equipment having a hybrid parallel/serial bus interface - Google Patents

Abstract

A hybrid serial/parallel bus interface for a user equipment (UE) has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter converts the nibble into serial data. A line transfers each nibble's serial data. A serial to parallel converter converts each nibble's serial data to recover that nibble. A data block reconstruction device combines the recovered nibbles into the data block.

Description

Subscriber equipment with hybrid parallel/serial bus interface

Technical field

The invention relates to bus data transmits.Particularly, the present invention is for reducing the circuit of transmission bus data.

Background technology

That shown in Figure 1 is the bus one example that is used to transmit data.Fig. 1 is a reception that is used for wireless communication system and transmit gain controller (GC) 30,32, and a GC controller 38 key diagrams.One called station similarly is base station or subscriber equipment, can transmit (TX) and receive (RX) signal.For controlling these signal gains, fall to belonging between the operational range of other reception/transfer assembly, GC 30,32 can adjust the degree of gain on RX and the TX signal.

For the gain parameter of control GC 30,32, can utilize a GC controller 38.Promptly as shown in Figure 1, this GC controller 38 can utilize a power control bus, similarly is the yield value that 16 bus wire 34,36 are sent TX 36 and RX 34 signals, is eight circuits such as wherein each.Though power control bus circuit 34,36 can transmit for fair rapid data, right this can require many pins on this GC 30,32 and this GC controller 38, or the integrated circuit (IC) of picture one special IC (ASIC) is gone up many connections of 38 of GC 30,32 and GC controllers.Increasing pin count can require additional circuit board space and be connected.Increase the IC connection and can take precious IC space.A large amount of pins or connection maybe can improve the bus cost surely according to implementation.

Thereby hope is the data mode that can have other.

Summary of the invention

According to a first aspect of the invention, a kind of hybrid parallel/serial bus interface is provided, this bus interface comprises: a block is separated multiplex machine, has an input, be configured setting to receive a block, and this block separated be multiplexed into two groups of thin pieces of i (nibble), each thin piece has a plurality of positions; An i even number and an odd number group and walk to serial convertor, thin piece of i of each group be sent to one not Zu and walk to the bit rate clock signal that serial convertor is synchronized with the second clock signal, and become serial datum to change each thin piece; One first group of i multiplexer, on i bar circuit, positive edge this even number set of serial transfer of this second clock signal and walk to serial convertor, and on i bar circuit, the negative edge of this second clock signal from this odd number group and walk to serial convertor serial transfer data; One second group of i demultiplexer receiving the serial data of even number and odd number, and is sent the even number serial data that is received to an even number impact damper, and the odd number serial data is sent to an odd number impact damper; Even number and odd number impact damper; An i even number and an odd number group be serial to parallel converters, this even number set be serial to parallel converters for to convert the even number serial data that is received to the even number parallel data, and export this even number parallel data by being synchronized with this second clock signal; And this i odd number group be serial to parallel converters, convert the odd number parallel data to the odd number serial data that will be received, and export this odd number parallel data by being synchronized with this second clock signal, and a data block reconstruction device, so that this even number and odd number parallel data are merged into this block.

According to a second aspect of the invention, provide a kind of base station that comprises the hybrid parallel/serial bus interface of above-mentioned first aspect.

According to a third aspect of the invention we, provide a kind of subscriber equipment that comprises the hybrid parallel/serial bus interface of above-mentioned first aspect.

Description of drawings

Fig. 1 is RX and TXGC and the graphic explanation of GC controller.

Fig. 2 is a hybrid parallel/serial bus interface block diagram.

Fig. 3 utilizes the block of hybrid parallel/serial bus interface to transmit operation process chart.

Fig. 4 explanation changes into a block the multiplexed operation of separating of the most remarkable and minimum significantly thin piece.

Fig. 5 explanation utilizes data interlace to handle a block is separated multiplexed operation.

Fig. 6 is the block diagram of a two-way hybrid parallel/serial bus interface.

Fig. 7 is that a two-way circuit is realized graphic.

Fig. 8 is the sequential chart of start bit.

Fig. 9 is the block diagram of the hybrid parallel/serial bus interface of a function controllability.

Figure 10 is the start bit sequential chart of the hybrid parallel/serial bus interface of a function controllability.

Figure 11 is that tabulation is realized in the start bit of expression various functions.

Figure 12 is the block diagram of destination control hybrid parallel/serial bus interface.

Figure 13 is that tabulation is realized in the start bit of the every destination of expression.

Figure 14 is that tabulation is realized in the start bit of the every destination/function of expression.

Figure 15 is the block diagram of destination/functions control hybrid parallel/serial bus interface.

Figure 16 is the start bit process flow diagram of the every destination/function of expression.

Figure 17 is the hybrid parallel/serial bus interface block diagram that is just reaching the negative clock signal edge.

Figure 18 is the hybrid parallel/serial bus interface sequential chart that is just reaching the negative clock signal edge.

Figure 19 is one 2 line formula GC/GC controller bus block diagrams.

Figure 20 is one 3 line formula GC/GC controller bus block diagrams.

Embodiment

That shown in Figure 2 is a hybrid parallel/serial bus interface block diagram, and Fig. 3 is a hybrid parallel/serial bus interface data transfer operations process flow diagram.One block can be sent to node 252 (54) from node 150 across this interface.One block is separated multiplex machine 40 and is received this block, and it is separated the multiplexed i of becoming a thin piece, is beneficial to transmit on the i bar data transmission lines 44 (56).This numerical value i decides according to the choice between linking number and the transfer rate.A kind of mode of the i of decision value is at first to determine one to transmit the maximum-delay that this block gained is agreed.According to this maximum-delay, can determine and transmit the needed minimum wire number of this block.Utilize the circuit of minimum number, can be chosen to be this minimum value amount at least in order to the circuit that transmits data.Circuit 44 can be pin, with and on the circuit board or the relevant connection in an IC connection.A kind of separate the mode that is multiplexed into thin piece be block is cut into one the most remarkable to a minimum significantly thin piece.For as Fig. 4 explanation, on two circuits, transmit one or eight blocks, this block can be separated is multiplexed into one or four thin pieces the most remarkable and one or four significantly thin pieces of minimum.

Another kind of mode then is that this block is staggered across i thin piece.I first of can become each i thin piece before this block.The i of next second of can become each i thin piece so goes down until this last i position.Be explanation one or eight blocks in two connections as shown in Figure 5, first meeting is mapped to first of thin piece 1.Second position can be mapped to first of thin piece 2.The 3rd position can be mapped to second of thin piece 1, so continues, until last is mapped to the last position of thin piece 2.

Each thin piece can be sent to i the parallel corresponding person (58) who changes serial (P/S) converter 42, convert serial bit to from parallel position, and serial transmits (60) sequentially on circuit.Opposite side at each bar circuit can be a transformation from serial to parallel (S/P) converter 46.Each S/P converter 46 can pass serial data with institute and convert its primary fine piece (62) to.I can be by a data block reconstruction device 48 processing, to rebuild this original data block (64) through restoring thin piece.

On the other hand, bidirectional mode can utilize the i bar to connect to transmit data by bidirectional mode, promptly as Fig. 6.Can be by two-way transfer information data, or can transmit information and give towards other direction by single direction and return confirmation signal.At this, a block is separated multiplexed and reconstructing device 66 can receive the block that is sent to node 2 52 from node 150.This separates multiplexed and reconstructing device 66 can be separated this block and is multiplexed into i thin piece.I P/S converter 68 can convert each thin piece to serial data.One group of multiplexer (MUX)/DEMUX 71 is couple to each P/S converter 68 the corresponding person of i bar circuit 44.At node 252 places, the multiplexer MUX/DEMUX 75 of another group is connected to one group of S/P converter 72 with circuit 44.This group S/P converter 72 can be converted into the serial data of receiving of each thin piece the thin piece of original transmission.The thin piece of receiving can be separated multiplexed by a block and reconstructing device 76 is reconstructed into original data block, and be output as the block that is received.

For each block that is sent to node 150 from node 252, this block is separated multiplexed and reconstructing device 76 can receive a block.This block can be separated multiplexed each thin piece that becomes, and with each thin block transfer to one group of P/S converter 74.This P/S converter 74 can convert each thin piece to serial form, for transmitting across i bar circuit 44.MUX/DEMUX that node is 2 groups 75 can be couple to i bar circuit 44 with described P/S converter 74, and the MUX/DEMUX 71 of 1 group of node can be couple to i S/P converter 70 with circuit 44.Described S/P converter 70 passes data-switching with institute and becomes its primary fine piece.This block is separated multiplexed and reconstructing device 66 reconstructs block from the thin piece of receive, to export the block that is received.Since once only can transmit data on single direction, this realization can operate by half-duplex mode.

Fig. 7 is the realization sketch of a two-way commutation circuit.The serial output of this node 1 P/S converter 68 can be imported into a ternary formula impact damper 78.This impact damper 78 has another input, and this can be coupled to the voltage of an expression high state.The output of this impact damper 78 is serial datas, sees through circuit 85 and is sent to a node 2 ternary formula impact dampers 84.Resistance 86 can be coupled between circuit 85 and the ground connection.These node 2 impact dampers 84 pass logical this serial data and give a node 2S/P converter 74.Similarly, the serial output from this node 2P/S converter 74 can be imported into a ternary formula impact damper 72.This impact damper 72 also has another and is coupled to a high-tension input.The serial output of this impact damper 82 can see through circuit 85 and be sent to node 1 ternary formula impact damper 80.This node 1 impact damper 80 can reportedly pass to a node 1S/P converter 70 with this serial number.

Plant in the realization at other, the i bar circuit 44 of part can transmit data on a direction, and other i bar circuit 44 can transmit data on other direction.At node 1 50, can receive that a block is for being sent to node 2 52.Decide according to required data throughput rate of this block and the traffic demand on the other direction, can utilize the j bar to connect at this and transmit this block, wherein this j value is between 1 to i.This block can be divided into j thin piece, and utilizes i the j in the P/S converter 68 to convert j group serial data to.Corresponding j node 2S/P converter 72 can restore this block with difference of node 2 block and reconstructing device 76.In the opposite direction, can utilize and reach i-j or k bar circuit to transmit this block.

In a preferable realization of reversible bus that is used for the gain control bus, can on a direction, send a gain control value, and send and return a confirmation signal.Or person in addition, on a direction, send a gain control value, and on other direction, send a gain control status signal.

It is in a synchronous system that a kind of hybrid parallel/serial line interface is realized, and can join the illustrated person as Fig. 8.At this, can utilize the timing of a synchronizing clock signals with synchronous various assembly.For explaining the starting point that this block transmits operation, can send position at the beginning.Promptly as shown in Figure 8, each circuit can be in its normal zero level.Can send the start bit of an expression beginning block transfer then.In this example, all circuits can be sent position at the beginning, and right real only the need sent the start bit on a circuit.As on arbitrary circuit, sending the start bit, similarly be one 1 values, then receiving node can understand that beginning this block data transmits operation.At this, can see through its corresponding circuit and send the thin piece of each serial.After transmitting each thin piece, the return normal condition to them of circuit meeting is such as being all low person.

In other is realized, also can utilize the announcer of start bit as the function of waiting to give execution.This implementation can illustrate as Fig. 9.And person as shown in figure 10 is 1 value as first of arbitrary connection, and this receiving node can be understood and waits to give the transmission block data.Promptly the form of realizing as the GC controller of Figure 11 is listed, utilizes three kinds of beginning bit combinations: 01,10 and 11.The start bit is not sent in 00 expression as yet.A kind of function of each combination representative.In this example, 01 expression should be carried out one and reduce function relatively, similarly is that this block value is reduced by 1 value.10 expressions should carry out one increases function relatively, similarly is that this block value is increased by 1 value.11 expressions should be carried out an ABS function, and this moment, this block can be kept identical numerical value.For increasing the number of available functions, can utilize extra bits, for example, 2 start bit mappings of every circuit can be arrived seven (7) functions, or n start bit mapping of i bar circuit arrived shape i ^N+1-a kind of function.Treating apparatus 86 can be described according to the start bit, and the block of being received is carried out function.

In the realization of money in addition as shown in figure 12, a destination device is represented in the start bit.Promptly as shown in figure 13, this is that two destination device/two circuit realizes that the combination of start bit can be associated with the destination device 88-92 to the biography block.01 indication device 1; 10 indication devices 2; And 11 indication devices 3.Behind the start bit of receiving this data block reconstruction device 48, the block of being rebuild can be sent to corresponding device 88-92.For increasing the number of potential destination device, can utilize extra start bit.For n start bit on each i bar circuit, can select and reach i ^N+1-1 device.

Promptly as shown in figure 14, can utilize the start bit come representative function and destination device both.Figure 14 shows one, and to have similarly be three connected systems of RX and two devices of TX GC.On each bar circuit, utilize the start bit, draw three kinds of functions of two devices among the figure.In this example, this target device is represented in the start bit of circuit 1, and " 0 " is device 1, and " 1 " is device 2.Connect 2 and 3 the performed function of position representative." 11 " represent ABS function; " 10 " representative increases function relatively; And " 01 " representative reduces function relatively.All three start bits are zero, and meaning i.e. " 000 ", can be normal non-data transfer state, and not use " 001 " at this.Can utilize extra position to increase more function or device.For n start bit on each i bar circuit, can select and reach i ^N+1-1 function/device combinations.

Figure 15 is the system chart of a realization representative function and both start bits of destination device.Thin piece through restoring can be received by this data block reconstruction device 48.According to the start bit of being received, this treating apparatus 86 can be carried out described function, delivers to described destination device 88-92 and institute is handled block.

Promptly shown in Figure 16 process flow diagram, the start bit of this function/destination of expression can be increased in each thin piece (94).At this, can see through this i bar circuit and send these thin pieces (96).Utilize the start bit, can carry out suitable function on block, block can be sent to suitable destination or both (98).

Be to increase the handling capacity in the synchro system, both transmit block data can to utilize just (two) of clock signal and negative (list) edge.One is realized can be as shown in figure 17.Block is separated multiplex machine 100 and is received block, and it is separated is multiplexed into the thin piece of two (two and single) group i.At this, the data of respectively organizing of i thin piece can be delivered to indivedual each i P/S device 102,104 of organizing.Promptly as shown in figure 17, single P/S device 102 of one group can have i P/S device, and this can have its clock signal signal that is inverted through the device 118 that is inverted.Therefore, the clock signal signal through being inverted can be half clock signal period that postpones through with respect to this clock signal of system.One group of i MUX 106 can organize between single P/S device 102 at the two P/S devices 104 of this group and this, selectes by doubling this bit rate clock signal.The product that transmits on each connects obtains the bit rate clock signal that data can be twices.The other end in each connection is a corresponding DEMUX 108.These DEMUX 108 can be couple to a pair of 112 and single 110 impact dampers with each bar circuit 44 sequentially by the twice bit rate clock signal.Each impact damper 112,110 receives a corresponding two and identical element, and grips complete clock signal period of this numerical value.A pair of 116 can restore described pair and slender with the S/P device of 114 groups of lists.One data block reconstruction device 122 can pass thin piece from each and rebuild this block.

Figure 18 illustrates utilization, and this is just reaching the negative clock signal edge, the data transfer operations of carrying out on a system line.The icon person waits to give Double Data and the forms data that transmits on circuit 1.Wedge is partly represented the negative clock signal edge in the combined signal, does not have the wedge part and then represents positive person.Promptly as icon, data transfer rate can double.

Figure 19 one is used for the preferable realization of hybrid parallel/serial line interface between a GC controller 38 and the GC 124.One block similarly is 16 a GC control data (8 RX and 8 TX), can be sent to a block from this GC controller 38 and separate multiplex machine 40.This block can be separated multiplexed two the thin pieces that become, and similarly is two 8 thin pieces.Can increase attached position at the beginning to each thin piece, similarly be that order is 9 of each thin pieces.At this, can utilize two P/S converters 42 on two circuits, to transmit these two thin pieces.When detecting the start bit, S/P converter 46 the thin piece of receive will be converted to parallel form.This data block reconstruction device can be rebuild original 16 gains with control GC 124.Explain out a function as the start bit, promptly as shown in figure 11, this AGC 124 can be before adjusting gain, earlier to this function of receipts onblock executing.

Figure 20 is in another preferable realization of a hybrid parallel/serial bus converter, and this is to be positioned at 32 of GC controller 38 and a RX GC 30 and TX GC, and utilizes three (3) bar circuits.This GC controller 38 can promptly as shown in figure 14, be sent a block and give this GC 30,32 by suitable RX and TX yield value and start bit.As the start bit that Figure 14 is pressed in true employing, device 1 is TX GC 32 for RX GC 30 installs 2.This block is separated multiplex machine 40 can separate multiplexed three the thin pieces that become with this block, transmits for seeing through this three-line.Utilize three P/S converters 42 and three S/P conversions 46, each thin piece can be transmitted on each circuit serially, and converts the primary fine piece to.This data block reconstruction device 48 can be rebuild original data block, and carries out as the described function in start bit, similarly is relative increase, minimizing and absolute value relatively.The data that obtain can be sent to as described RX in start bit or TX GC 30,32.

Claims (3)

1. interface that is used for the hybrid parallel/serial bus in the synchro system, this synchro system has relevant first clock signal, and this bus interface comprises:

Multiplex machine is separated in one data area, has an input receiving a block, and this block separated is multiplexed into two groups of i thin pieces, and each thin piece has a plurality of positions;

One even number set and an odd number group also walk to serial convertor, it respectively has i and walks to serial convertor, it is corresponding and walk to serial convertor that the thin piece of i of each group is sent to a group of the bit rate clock signal that is synchronized with a second clock signal, convert serial datum to i the thin piece that will be received, wherein this second clock signal is a delay clock signals of this first clock signal;

One first group of i multiplexer, on i bar circuit, in positive edge this even number set of serial transfer of this second clock signal and walk to serial convertor, and on i bar circuit, in the negative edge serial transfer of this second clock signal from this odd number group and walk to the data of serial convertor;

One second group of i demultiplexer receiving this even number and odd number serial data, and is sent the even number serial data that is received to an even number impact damper, and the odd number serial data is sent to an odd number impact damper;

One even number set and an odd number group are serial to parallel converters, it respectively has i and is serial to parallel converters, the i of this even number set is serial to parallel converters and converts the even number serial data that is received to the even number parallel data, and output is synchronized with this even number parallel data of this second clock signal; And

The i of this odd number group is serial to parallel converters and converts the odd number serial data that this received to the odd number parallel data, and output is synchronized with this odd number parallel data of this second clock signal, and

One data block reconstruction device is to merge into this block with this even number and odd number parallel data.

2. interface as claimed in claim 1 is characterized in that, each block has N position, and $1<i<\frac{N}{2}.$

3. interface as claimed in claim 1, it is characterized in that, this even number and odd number impact damper cushion this even number and odd number group serial converter respectively, so that this even number and odd number group serial converter receive even number and the odd number serial data that is received, wherein even number that is received and odd number serial data are synchronized with this second clock signal.

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