CN100346327C - User equipment having a hybrid parallel/serial bus interface - Google Patents

User equipment having a hybrid parallel/serial bus interface Download PDF

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Publication number
CN100346327C
CN100346327C CN 02823115 CN02823115A CN100346327C CN 100346327 C CN100346327 C CN 100346327C CN 02823115 CN02823115 CN 02823115 CN 02823115 A CN02823115 A CN 02823115A CN 100346327 C CN100346327 C CN 100346327C
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data
serial
odd
parallel
even
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CN 02823115
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CN1589437A (en
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约瑟·葛瑞丹
艾佛瑞·史达福利
堤摩西·A·亚瑟尼司
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美商内数位科技公司
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Priority to US09/990,060 priority Critical patent/US7069464B2/en
Priority to US10/080,899 priority patent/US6823469B2/en
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    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00Parallel/series conversion or vice versa
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; Arrangements for supplying electrical power along data transmission lines
    • H04L25/14Channel dividing arrangements in which a single bit stream is divided between several baseband channels and reassembled at the receiver

Abstract

一种用于一用户设备(UE)的混合并行/串行总线接口,包括一数据区块解多路复用装置,具有一输入,接收一数据区块并解多路复用成两组i细块;i偶数及一奇数组的并行至串行转换器,接收各组的i细块并转换各细块成一串行数据;一第一组i多路复用器;一第二组i解多路复用器,以接收偶数及奇数的串行数据并分别送出至一偶数缓冲器和一奇数缓冲器;i偶数组的串行至并行转换器,将所接收的偶数串行数据转换成偶数并行数据并输出该偶数并行数据;i奇数组的串行至并行转换器,将所接收的奇数串行数据转换成奇数并行数据并输出该奇数并行数据,一数据区块重建装置,将该偶数及奇数并行数据合并为该数据区块。 An apparatus for mixing a user equipment (UE), a parallel / serial bus interface, comprising a data block demultiplexing device having an input, a data block received and demultiplexed into two groups i nibble; i even and an odd parallel to serial converter to receive each group of i nibbles and converted into a respective nibble serial data; a first multiplexer group i; a second group i demultiplexer, the received serial data of even and odd and even number are sent to a buffer and an odd buffer; i even sets the serial-to-parallel converter, the received serial data even into even parallel data and outputting the even parallel data; i odd serial to parallel converter, converts the received serial data into odd odd odd parallel data and outputting the parallel data, a data block reconstruction device, the the even and odd parallel data for the combined data block.

Description

具有混合并行/串行总线接口的用户设备 The user equipment having a hybrid parallel / serial bus interface

技术领域 FIELD

本发明是关于总线数据传送。 The present invention relates to bus data transfers. 特别是,本发明是为减少传送总线数据的线路。 In particular, the present invention is to reduce the data transfer bus lines.

背景技术 Background technique

图1所示者即为用于传送数据的总线其一范例。 Are shown in Figure 1 is the one example of a bus for transferring data. 图1是一用于无线通信系统的接收与传送增益控制器(GC)30、32,及一GC控制器38说明图。 FIG 1 is a receive and transmit gain controller (GC) for a wireless communication system 30, 32 and a GC controller 38 described in FIG. 一通信台,像是基站或用户设备,会传送(TX)及接收(RX)信号。 A communication station, such as a base station or user equipment, may transmit (TX) and receive (RX) signal. 为控制这些信号增益,落属于其它接收/传送组件的运作范围之间,GC 30、32会调整RX及TX信号上的增益度。 To control the signal gain, between the falling part of the operating range of other reception / transmission components, GC 30,32 adjust the gain of the RX and TX signal.

为控制GC 30、32的增益参数,会利用一GC控制器38。 To control the gain parameters GC 30,32, a GC controller 38 will use. 即如图1所示,该GC控制器38会利用一功率控制总线,像是16条线路总线34、36来送出TX 36及RX 34信号的增益值,比如其中的每一个为八条线路。 That is, as shown in FIG. 1, the GC controller 38 will use a power control bus, such as bus lines 34, 16 to 34 sends the gain value and the RX signal TX 36, wherein each of such eight lines. 功率控制总线线路34、36虽可供允快速数据传送,然这会要求该GC 30、32及该GC控制器38上许多接脚,或是像一专用集成电路(ASIC)的集成电路(IC)上GC 30、32及GC控制器38间的许多连接。 Although the power control bus lines 34,36 allow for a fast data transfer, then it will require the GC 30,32 and the GC controller 38 on a number of pins, like an integrated circuit or a application specific integrated circuit (ASIC) to (IC 30,32 GC and GC controller 38 on the number of connection). 增加接脚数会要求额外电路板空间与连接。 Will increase the number of pins requires additional circuit board space and connections. 增加IC连接会占用珍贵的IC空间。 Increased IC IC connection will take up valuable space. 大量的接脚或连接或会依实现方式而定提高总线成本。 A large number of pins or connections or implementation will depend may be increase the cost of the bus.

从而,希望是可具有其它的数据传送方式。 Thus, desirably may have other data transfer methods.

发明内容 SUMMARY

根据本发明的第一方面,提供了一种混合并行/串行总线接口,该总线接口包含:一数据区块解多路复用装置,具有一输入,经配置设定以接收一数据区块,并将该数据区块解多路复用成两组i细块(nibble),各个细块具有多个位;i偶数及一奇数组的并行至串行转换器,各组的i细块被发送至一别组的并行至串行转换器同步于第二时钟信号的时钟信号速率,并以转换各细块成一串行数据;一第一组i多路复用器,于i条线路上,在该第二时钟信号的正边缘处串行传送该偶数组的并行至串行转换器,并且于i条线路上,在该第二时钟信号的负边缘处自该奇数组的并行至串行转换器串行传送数据;一第二组i解多路复用器,以接收偶数及奇数的串行数据,并将所接收的偶数串行数据送出至一偶数缓冲器,而将奇数串行数据送出至一奇数缓冲器;偶数及奇数缓冲器; According to a first aspect of the present invention, there is provided a hybrid parallel / serial bus interface, the bus interface comprising: a data block demultiplexing device having an input configured to receive a data block set and demultiplexing the data block into two groups i nibble (Nibble), each block having a plurality of fine bits; i even and an odd parallel to serial converter, each group of i nibbles It is sent to a respective set of parallel-to-serial converter in synchronization with the clock signal rate of the second clock signal, and to convert each nibble into a serial data; a first multiplexer group i, to i lines on the positive edge of the second clock signal the even sets parallel to serial converter serial transfer, and in the lines i, the negative edge of the second clock signal from the odd parallel to serial converter serial transmitting data; a second set of i demultiplexers for receiving the even and odd serial data, and sending the even received serial data to a buffer even number, and the odd sends serial data to an odd buffer; even and odd buffer; i偶数及一奇数组的串行至并行转换器,该偶数组的串行至并行转换器为将所接收的偶数串行数据转换成偶数并行数据,并按同步于该第二时钟信号而输出该偶数并行数据;以及该i奇数组的串行至并行转换器,以将所接收的奇数串行数据转换成奇数并行数据,并按同步于该第二时钟信号而输出该奇数并行数据,以及一数据区块重建装置,以将该偶数及奇数并行数据合并为该数据区块。 I even and an odd serial to parallel converter array, the even serial-to-parallel converter array to convert the received serial data into even the even parallel data, according to the second synchronization clock signal output the even parallel data; i and the odd serial to parallel converter, to convert the received serial data into odd odd parallel data, according to the synchronous clock signal and outputting the second odd parallel data, and a data block reconstruction device to the even and odd parallel data for the combined data block.

根据本发明的第二方面,提供了一种包括上述第一方面的混合并行/串行总线接口的基站。 According to a second aspect of the present invention, there is provided a method comprising mixing the above-described first aspect of the base station in parallel / serial bus interface.

根据本发明的第三方面,提供了一种包括上述第一方面的混合并行/串行总线接口的用户设备。 According to a third aspect of the present invention, there is provided a user equipment of the first aspect comprising mixing a parallel / serial bus interface.

附图说明 BRIEF DESCRIPTION

图1是RX与TXGC和GC控制器图式说明。 Figure 1 is the RX GC controller TXGC drawings and description.

图2是一混合并行/串行总线接口框图。 FIG 2 is a hybrid parallel / serial bus interface block diagram.

图3是利用混合并行/串行总线接口的数据区块传送作业流程图。 FIG 3 is the use of hybrid parallel / serial bus interface data block transfer flowchart.

图4说明将一区块转成最显著及最小显著细块的解多路复用作业。 4 illustrates a block transfer on the most significant and least significant nibble into multiplex operation.

图5说明利用数据交错处理对一区块进行解多路复用作业。 5 illustrates using a block of interleaved data demultiplex operation.

图6是一双向混合并行/串行总线接口的框图。 FIG 6 is a block diagram of a bi-directional hybrid parallel / serial bus interface.

图7是一双向线路实现图式。 FIG 7 is a bidirectional line to achieve the drawings.

图8是开始位的时序图。 FIG 8 is a timing diagram of the start bit.

图9是一函数可控制性的混合并行/串行总线接口的框图。 FIG. 9 is a function block diagram of controllability hybrid parallel / serial bus interface.

图10是一函数可控制性的混合并行/串行总线接口的开始位时序图。 FIG 10 is a function of the controllability of hybrid parallel / serial bus timing diagram of the start bit interface.

图11是表示各项函数的开始位实现列表。 11 is a start bit to realize the function list.

图12是目的地控制混合并行/串行总线接口的框图。 FIG 12 is a block diagram of a destination controlling hybrid parallel / serial bus interface.

图13是表示各项目的地的开始位实现列表。 13 is a start bit of the destination list to achieve.

图14是表示各项目的地/函数的开始位实现列表。 14 is a start bits indicating destinations / functions to achieve the list.

图15是目的地/函数控制混合并行/串行总线接口的框图。 FIG 15 is a destination / functions controlling hybrid parallel block diagram / serial bus interface.

图16是表示各项目的地/函数的开始位流程图。 FIG 16 is a flowchart illustrating start bits indicating destinations / functions.

图17是正及负时钟信号边缘的混合并行/串行总线接口框图。 FIG 17 is a positive and negative clock edge hybrid parallel / serial bus interface block diagram.

图18是正及负时钟信号边缘的混合并行/串行总线接口时序图。 FIG 18 is a positive and negative clock edge hybrid parallel / serial bus interface timing diagram.

图19是一2线式GC/GC控制器总线框图。 FIG 19 is a 2-line GC / GC controller bus block diagram.

图20是一3线式GC/GC控制器总线框图。 FIG 20 is a 3-line GC / GC controller bus block diagram.

具体实施方式 Detailed ways

图2所示者是一混合并行/串行总线接口框图,而图3为一混合并行/串行总线接口数据传送作业流程图。 As shown in FIG. 2 by a hybrid parallel / serial bus interface block diagram, and FIG. 3 is a mixing / serial bus interface data transfer flowchart parallel. 一数据区块会被跨于该接口而从节点150传送到节点252(54)。 Across a data block is transferred from the interface to the node 150 to node 252 (54). 一数据区块解多路复用装置40接收该区块,并将其解多路复用成为i个细块,以利于i条数据传送线路44上传送(56)。 A data block demultiplexing device 40 receives the block, and a demultiplexer becomes i nibbles, facilitate transport (56) 44 is the i th data transmission line. 该数值i是根据连接数目与传送速度之间的取舍而定。 The value i is a tradeoff between number of connections and transfer speed. 一种决定i值的方式是首先决定一传送该数据区块所得承允的最大延迟。 Method of determining the value of i is to first embodiment determines the maximum delay of the data block resulting in a transfer undertakes. 按照此最大延迟,可决定出传送该区块所需要的最小线路数目。 According to this maximum delay, the circuit may determine the minimum number of blocks required for the transfer. 利用最小数量的线路,用以传送数据的线路会被选定为至少该最小值量。 With a minimum number of lines for transmission of data lines will be selected to be at least the minimum amount. 线路44可为接脚,以及其在电路板上或于一IC连接上的相关连接。 Line 44 may be a pin, and the circuit board or associated connections in an IC on the connection. 一种解多路复用成细块的方式是将区块切割成一最显著到一最小显著细块。 A multiple mode into fine pieces solution is one of the most significant block is cut into a least significant nibble. 为如图4说明,于两条线路上传送一八位区块,该区块会被解多路复用成一四位最显著细块及一四位最小显著细块。 As described in FIG. 4, block transfer eighteen on two lines, the block is demultiplexed into fourteen most significant nibble and fourteen least significant nibble.

另一种方式则是将该区块交错跨于i个细块。 Another way sucked across the block interleaving in i nibbles. 该区块之前i个位会变成各i个细块的第一位。 Before i bits of the block become the first bit of each of the i nibbles. 其次的i个位会变成各i个细块的第二位,如此下去一直到该最后i个位。 Second i-i bits become the respective second bit nibbles, and so on until the last i bits. 为说明如图5所示的在两条连接上的一八位区块,第一个位会被映射到细块1的第一位。 To illustrate in FIG eighteen two connecting block shown in Figure 5, the first bit is mapped to the first bit of nibble 1. 第二个位会被映射到细块2的第一位。 The second bit is mapped to the first bit of nibble two. 第三个位会被映射到细块1的第二位,如此继续下去,一直到将最后一个位映射到细块2的最后位。 The third bit is mapped to a second bit of nibble one and so continue until the last bit is mapped to the last bit of nibble 2.

各个细块会被送到i个并行转串行(P/S)转换器42的相对应者(58),从并行位转换成串行位,并于线路上串行循序地传送(60)。 Each of i nibbles is sent to parallel to serial (P / S) converter should be, relative to (58) 42, converted from parallel bits to serial bits, and to sequentially serially transmitted on the line (60) . 在各条线路的相对侧会是一串行转并行(S/P)转换器46。 On the opposite side of each line is a serial to parallel would be (S / P) converter 46. 各个S/P转换器46会将所传串行数据转换成其原始细块(62)。 Each S / P converter 46 will convert the transmitted serial data into its original nibble (62). 第i个经复原细块会被一数据区块重建装置48处理,以重建该原始数据区块(64)。 The i-th small block is restored by a data block reconstruction device 48, so as to reconstruct the original data block (64).

另一方面,双向方式,会利用i条连接以按双向方式传送数据,即如图6。 On the other hand, in a bidirectional manner, i of connection will use to transmit data bi-directional manner, i.e., in Fig. 可按双向传送信息数据,或是可按单一方向传送信息而朝另一方向送返确认信号。 Transmitting information data can be bidirectional, single direction, or may be sent back an acknowledgment signal conveying information in the other direction. 在此,一数据区块解多路复用及重建装置66会接收从节点150传送到节点2 52的数据区块。 Here, a data block demultiplexing and reconstruction device 66 receives the data block transmitted from node 150 to node 2 52. 该解多路复用及重建装置66会将该区块解多路复用成i个细块。 The demultiplexing and reconstruction device 66 will be multiplexed into the i nibbles block solution. i个P/S转换器68会将各个细块转换成串行数据。 the i P / S converter 68 will convert each nibble into serial data. 一组多路复用器(MUX)/DEMUX 71将各个P/S转换器68耦接到i条线路44的相对应者。 A set of multiplexers (MUX) / DEMUX 71 to the respective P / S converter 68 is coupled to a corresponding stripe i by line 44. 在节点252处,另一组的多路复用器MUX/DEMUX 75将线路44连接到一组S/P转换器72。 At node 252, another set of multiplexer MUX / DEMUX 75 to line 44 is connected to a set of S / P converter 72. 该组S/P转换器72会将各细块的所收串行数据转换成为原始传送的细块。 The set of the S / P converter 72 will yield for each nibble serial data into the originally transmitted nibbles. 所收细块会被一数据区块解多路复用及重建装置76重建成原始数据区块,并输出为所接收的数据区块。 The received nibbles are a data block demultiplexing and reconstruction device 76 to reconstruct the original data block and output as the received data block.

对于从节点252传送到节点150的各区块,该数据区块解多路复用及重建装置76会接收一数据区块。 For transmission from node 252 to node 150 in each block, the data block demultiplexing and reconstruction device 76 receives a data block. 该区块会被解多路复用成为各细块,并将各细块传送到一组P/S转换器74。 This block is demultiplexed become the nibbles, each nibble and transferred to a set of P / S converter 74. 该P/S转换器74会将各细块转换成串行格式,以供跨于i条线路44传送。 The P / S converter 74 will convert each nibble into serial format for transfer across the strip in line 44 i. 节点2组的MUX/DEMUX 75会将所述P/S转换器74耦接到i条线路44,而节点1组的MUX/DEMUX 71会将线路44耦接到i个S/P转换器70。 Node MUX / DEMUX 2 groups of 75 will be the P / S converter 74 is coupled to the i lines 44, and MUX 1 node group / DEMUX 71 is coupled to line 44 will be the i-th S / P converter 70 . 所述S/P转换器70将所传数据转换成其原始细块。 The S / P converter 70 converts the transmitted data into its original nibbles. 该数据区块解多路复用及重建装置66从所收细块重建出数据区块,以输出所接收的数据区块。 The data block demultiplexing and reconstruction device 66 reconstructs the data block from the received nibbles, data to output the received block. 既然一次只会在单一方向上传送数据,这种实现可按半双工方式运作。 Since data is only sent once in a single direction, this implementation may be half-duplex operation.

图7是一双向切换电路的实现简图。 FIG 7 is a schematic view of achieving a bidirectional switching circuit. 该节点1 P/S转换器68的串行输出会被输入到一三态式缓冲器78。 The node 1 P / S converter 68 serial output will be typed into a tri-state buffer 78 type. 该缓冲器78具有另一输入,这会被耦接到一表示高状态的电压。 The buffer 78 has another input which is coupled to a high state indicates a voltage. 该缓冲器78的输出是串行数据,透过线路85被传送到一节点2三态式缓冲器84。 The output buffer 78 is the serial data, transferred through line 85 to a Node 2 tri-state buffer 84 formula. 电阻86会被耦接于线路85与接地之间。 Resistor 86 is coupled between line 85 and ground. 该节点2缓冲器84传通该串行数据给一节点2S/P转换器74。 The Node 2 buffer 84 through the serial data transmission to a node 2S / P converter 74. 类似地,来自该节点2P/S转换器74的串行输出会被输入到一三态式缓冲器72。 Similarly, the serial output from the node 2P / S converter 74 will be typed into a tri-state buffer 72 type. 该缓冲器72也具有另一耦接于一高电压的输入。 The buffer 72 also having another coupled to a high voltage input. 该缓冲器82的串行输出会透过线路85而传送到节点1三态式缓冲器80。 The serial output buffer 82 will be sent through line 85 to a Node 1 tri-state buffer 80 formula. 该节点1缓冲器80会将该串行数据传通至一节点1S/P转换器70。 The Node 1 buffer 80 will pass through the serial data to a node 1S / P converter 70.

在另种实现里,部分的i条线路44可在一方向上传送数据,而其它的i条线路44可在另一方向上传送数据。 In another kind of realization where, i lines 44 may transfer data portion in one direction, while the other i lines 44 may transfer data in the other direction. 在节点1 50,会收到一数据区块以供传送到节点2 52。 In node 150, receives a data block for transmission to the node 252. 根据该区块所需的数据吞吐速率以及另一方向上的话务需求而定,在此会利用j条连接来传送该区块,其中该j值为1到i之间。 The required data throughput rate, and the block in the other direction of traffic needs, and j will use this connection to transmit the block bar, wherein the value of j from 1 to i. 该区块会被分成j个细块,并利用i个P/S转换器68中的j个来转换成j组串行数据。 The block is divided into j nibbles, and using the i P / S converter 68 is converted to the j-th to j sets of serial data. 相对应的j个节点2S/P转换器72,与节点2数据区块区别及重建装置76会复原该数据区块。 J corresponding nodes 2S / P converter 72, the difference between the node 2 and the data block reconstruction device 76 will recover the data block. 在相反方向上,会利用达ij或k条线路以传送该数据区块。 In the opposite direction, or it will use ij k of lines to transmit the data block.

在一用于增益控制总线的双向式总线较佳实现中,会在一方向上送出一增益控制值,并送返一确认信号。 In the preferred implementation of the bidirectional bus a formula for the gain control of the bus, in one direction will feed a gain control value, and sent back a confirmation signal. 或另者,在一方向上送出一增益控制值,而在另一方向上送出一增益控制装置状态信号。 Or another person, a gain control value is sent in one direction, and sends a status signal gain control device in the other direction.

一种混合并行/串行接口实现是于一同步系统内,且可参如图8所说明者。 A hybrid parallel / serial interface is in a synchronous system, and 8 may be described by reference FIG. 在此,会利用一同步时钟信号以同步各式组件的计时。 Here, we will use a synchronous clock signal to synchronize the timing of a variety of components. 为表述该数据区块传送作业的起点,会送出一开始位。 The starting point for the presentation of the data block transfer operations, will send a start bit. 即如图8所示,各线路会在其正常零水准。 That is, as shown in FIG. 8, each line will be in its normal zero level. 然后会送出一表示开始区块传送作业的开始位。 Then it will send a start bit indicating the start block transfer operations. 在本例中,所有线路会送出一开始位,然实仅需在一条线路上送出开始位。 In the present embodiment, all lines will send a start bit, and then sending only a solid start bit on one line. 如在任一条线路上送出开始位,像是一1值,则接收节点会明了开始该区块数据传送作业。 The start bit is sent out on either a line, such as a value of 1, the receiving node will be apparent to the start of the data block transfer operation. 在此,会透过其相对应线路送出各个串行细块。 Here, each of the serial nibble will send through its corresponding line. 在传送各细块后,线路会回返至它们的正常状态,比如皆为低者。 After the transfer of each fine block line will return to their normal state, such as those who are all low.

在其它实现里,也会利用开始位做为待予执行的函数的表示器。 In other implementations, and it would use the start bit is represented as a function to be performed. 这种实现方式可如图9说明。 9 illustrates such an implementation may be as shown in FIG. 而如图10所示者,如任一连接的第一位为1值,该接收节点会了解待予传送区块数据。 While those shown in FIG. 10, any one of a first value of a connection, the receiving node will know the data to be transmitted to the block. 即如图11的GC控制器实现的表格所列,利用三种开始字节合:01、10及11。00表示尚未送出开始位。 GC controller 11 that is listed in the table of FIG implemented, using three engagement start byte: 01, 10, 11.00 and represents a start bit was not sent. 各个组合代表一种函数。 It represents a combination of the respective functions. 在本例中,01表示应执行一相对减少函数,像是将该数据区块值减少1值。 In the present embodiment, 01 denotes a relative decrease function should be performed, such as the value decreases by one data block. 10表示应执行一相对增加函数,像是将该数据区块值增加1值。 10 represents a relative increase function should be performed, such as increasing the data block value of the value 1. 11表示应执行一绝对值函数,此时该区块会维持相同数值。 11 represents an absolute value function should be performed, then the block will maintain the same value. 为增加可用函数的数目,可利用额外位,例如,可将每条线路2个开始位映射到达七(7)项函数,或是将i条线路的n个开始位映射到达状in+1-1种函数。 To increase the number of available functions, additional bits can be used, for example, two start bits per line may be mapped items reach seven (7) functions or n starting bits to i lines reaches like mapping in + 1- one kind of function. 处理装置86会依开始位所述,对所收的数据区块执行函数。 Device 86 will start processing by the bit, performs the function of data block received.

在如图12所示的另款实现里,开始位表示一目的地装置。 In another implementation shown in section in FIG. 12, the start bits indicate a destination device. 即如图13所示,此为两个目的地装置/两条线路实现,开始位的组合会关联到对所传数据区块的目的地装置88-92。01表示装置1;10表示装置2;而11表示装置3。 That is, as shown in FIG. 13, this is a two destination device / two line implementation, the combination of the start bit of the destination device will be associated to the transmitted data block 88-92.01 representation apparatus 1; 10 represents means 2 ; and 11 denotes means 3. 在收到该数据区块重建装置48的开始位后,所重建的区块会被送到相对应装置88-92。 Upon receipt of the start bits of the data block reconstruction device 48, the reconstructed block is sent to the corresponding device 88-92. 为增加潜在目的地装置的数目,可利用额外的开始位。 To increase the number of potential destination devices, additional start bits may be utilized. 对于在各i条线路上的n个开始位,可选定达in+1-1个装置。 For n starting bits over each of i lines, up to in + 1-1 may be a device selected.

即如图14所示,可利用开始位来表示函数及目的地装置两者。 That is, as shown in FIG. 14, the start bits may be utilized to represent both function and destination device. 图14显示一具有像是RX及TX GC两个装置的三条连接系统。 Figure 14 shows a three connection system having two devices such as a RX and TX GC. 在各条线路上利用开始位,图中绘出两个装置的三种函数。 Using the start bit for each line, there is depicted three kinds of functions of two devices. 在本例中,线路1的开始位代表该标的装置,「0」为装置1,而「1」为装置2。 In this case, bit line 1 represents the beginning of the destination device, "0" for the device 1, and "1" for the device 2. 连接2及3的位代表所执行函数。 2 and 3 bits represent the connection of the function execution. 「11」代表绝对值函数;「10」代表相对增加函数;而「01」代表相对减少函数。 "11" represents the absolute value function; "10" represents a relative increase function; and "01" represents a relative reduction function. 所有三个开始位为零,意即「000」,会是正常非数据传送状态,而在此并未使用「001」。 All three start bits are zero, which means "000", will be the normal non-data transfer state, but this does not use "001." 可利用额外的位以增加更多的函数或装置。 Additional bits can be used to add more functions or devices. 对于在各i条线路上的n个开始位,可选定达in+1-1个函数/装置组合。 For n starting bits over each of i lines, up to in 1-1 functions / devices may be selected in combination +.

图15是一实现表示函数及目的地装置两者的开始位的系统框图。 FIG 15 is a system block diagram showing functions realized and the start position of both the destination device. 经复原的细块会由该数据区块重建装置48所接收。 Means 48 receives the nibbles will be restored by the data block reconstruction. 根据所收到的开始位,该处理装置86会执行所述函数,而将所处理区块送到所述的目的地装置88-92。 The start bit is received, the processing means 86 performs the function, and the processed block to the destination device 88-92.

即如图16流程图所示,会将表示该函数/目的地的开始位增入各个细块内(94)。 I.e. the flowchart shown in FIG. 16, the function will start bits / destination into the respective fine gain block (94). 在此,会透过这i条线路送出这些细块(96)。 Here, I will send the fine blocks (96) through which the i lines. 利用开始位,会在数据区块上执行适当函数,数据区块会被送到适当目的地或两者(98)。 Utilization start bit, performs the appropriate function on the data block, the data block is sent to the appropriate destination or both, (98).

为增加同步系统内的吞吐量,会利用时钟信号的正(双)及负(单)边缘两者来传送区块数据。 To increase the throughput in a synchronous system, will use the positive (even) and negative (odd) block of data to transmit both edges of the clock signal. 其一实现可如图17所示。 One shown in Figure 17 can be achieved. 数据区块解多路复用装置100收到数据区块,并将其解多路复用成两个(双及单)组i个细块。 A data block demultiplexing device 100 receives the data blocks, and demultiplexed into its two (single and double) the group i nibbles. 在此,会将i个细块的各组数据送到个别各组的i个P/S装置102、104。 Here, two sets of data will i nibbles is sent to the i-th individual groups of P / S devices 102,104. 即如图17所示,一组的单P/S装置102会具有i个P/S装置,这会拥有其经反置器118所反置的时钟信号信号。 That is, as shown in FIG. 17, a single set of P / S devices 102 may have the i P / S devices, which will have its clock signal 118 is inverted by inverted. 因此,经反置的时钟信号信号会是经相对于该系统时钟信号而延迟的半个时钟信号周期。 Thus, the inverted clock signal is half a clock signal period will be through the system clock signal with respect to the delay. 一组i个MUX 106会在该组双P/S装置104与该组单P/S装置102之间,按两倍于该时钟信号速率而进行选定。 A i-th group of MUX 106 will be between the set of two P / S device set 104 and the single P / S devices 102, to the clock signal to twice the rate selected for. 在各连接上传送的产获数据会是两倍的时钟信号速率。 Production eligible data is transmitted on each connection is twice the rate of the clock signal. 在各连接的另一端是一相对应的DEMUX 108。 At the other end of each connection is a corresponding DEMUX 108. 这些DEMUX 108会循序地按两倍时钟信号速率,将各条线路44耦接到一双112与单110缓冲器。 The DEMUX 108 may sequentially to twice the rate of the clock signal, each of the lines 44 is coupled to one pair of buffers 112 and 110 alone. 各个缓冲器112、110接收一相对应的双与单位元,并握持该数值一个完整时钟信号周期。 Receiving a respective buffers 112, 110 corresponding to the unit element and double, and holding the value of a complete clock signal period. 一双116与单114组的S/P装置会复原所述双与单细块。 116 and 114 one pair of single-S group / P apparatus will recover the single double nibbles. 一数据区块重建装置122会从各个所传细块重建该数据区块。 A data block reconstruction device 122 of the data block from each of the reconstructed transmitted nibbles.

图18说明利用该正及负时钟信号边缘,在一系统线路上进行的数据传送作业。 Figure 18 illustrates the use of the positive and negative clock edge, the data transfer operations performed on a line system. 图标者是待予于线路1上传送的双数据与单数据。 Icon to who is to be the data for the dual mono data on a transmission line. 斜楔部分表示合并信号内的负时钟信号边缘,而无斜楔部分则表示正者。 Wedge portion indicates the negative clock edge signal within the combined signal without said wedge portion are positive. 即如图标,数据传送速率会增加一倍。 That is such an icon, the data transfer rate can be doubled.

图19是一用于一GC控制器38及一GC 124之间的混合并行/串行接口较佳实现。 FIG 19 is a hybrid between a GC controller 38 and a GC 124 a parallel / serial interface is preferably implemented. 一数据区块,像是16位的GC控制数据(8位RX和8位TX),会被从该GC控制器38传送给一数据区块解多路复用装置40。 A data block, such as 16 of GC control data (8 bits RX and 8 the TX), is sent from the GC controller 38 to a data block demultiplexing device 40. 该数据区块会被解多路复用成为两个细块,像是两个8位细块。 The data block is demultiplexed into two nibbles, such as two 8-bit nibbles. 会对各个细块增附一开始位,像是令为每个细块9位。 Each nibble will be attached by a start bit, so that for each such 9 nibbles. 在此,会利用两个P/S转换器42于两条线路上传送这两个细块。 Here, we will use two P / S converter 42 transmits these two nibbles on two lines. 当S/P转换器46侦测到开始位时就会将所接收细块转换为并行格式。 When the S / P converter 46 to detect the start bit will be received nibbles to parallel format. 该数据区块重建装置会重建原始16位以控制GC 124的增益。 The data block reconstruction device reconstructs the original 16 to control the gain of the GC 124. 如开始位表述出一函数,即如图11所示,该AGC 124会在调整增益之前,先对所收区块执行该项函数。 The start bit is a function of the expression, i.e., as shown in FIG. 11, the AGC 124 adjusts the gain will be before, perform the function of the received blocks.

图20是于一混合并行/串行总线转换器另一较佳实现,此是位于GC控制器38及一RX GC 30与TX GC 32间,并利用三(3)条线路。 FIG. 20 is in a hybrid parallel / serial bus converter another preferred implementation, this is located in the GC controller 38 and a RX GC 30 and TX GC 32 rooms, using three (3) lines. 该GC控制器38会按适当RX及TX增益值与开始位,即如图14所示,送出一数据区块给该GC 30、32。 The GC controller 38 will be in proper RX and TX gain values ​​and start bits, as shown in Figure 14, sends a data block to the GC 30,32. 如确采用按图14的开始位,装置1为RX GC 30而装置2为TX GC 32。 The start bit is determined by using FIG. 14, the apparatus 1 RX GC 30 and TX GC 32 device 2 is. 该数据区块解多路复用装置40会将该数据区块解多路复用成为三个细块,以供透过这三条线路而传送。 The data block demultiplexing device 40 will demultiplex the data block into three nibbles, three lines for transmitted through this. 利用三个P/S转换器42及三个S/P转换46,各细块会被串行地在各线路上传送,并转换成原始细块。 Using three P / S converters 42 and three S / P converters 46, each of the nibbles are transferred serially on each line, and converted into the original nibbles. 该数据区块重建装置48会重建原始数据区块,并执行如开始位所述的函数,像是相对增加、相对减少及绝对值。 The data block reconstruction device 48 reconstructs the original data block and performs the function as the start bit, such as relative increase, relative decrease and absolute value. 所获数据会被送到如开始位所述的RX或TX GC 30、32。 The obtained data will be sent to the start bit of the RX or TX GC 30,32.

Claims (3)

1.一种用于同步系统内的混合并行/串行总线的接口,该同步系统具有一相关第一时钟信号,该总线接口包含:一数据区域解多路复用装置,具有一输入以接收一数据区块,并将该数据区块解多路复用成两组i个细块,各个细块具有多个位;一偶数组及一奇数组并行至串行转换器,其各具有i个并行至串行转换器,各组的i个细块被发送至同步于一第二时钟信号的时钟信号速率的一组相应的并行至串行转换器,以将所接收的i个细块转换成一串行数据,其中该第二时钟信号是该第一时钟信号的一延迟时钟信号;一第一组i个多路复用器,于i条线路上,在该第二时钟信号的正边缘处串行传送该偶数组并行至串行转换器,并且于i条线路上,在该第二时钟信号的负边缘处串行传送来自该奇数组并行至串行转换器的数据;一第二组i个解多路复用器,以接收该偶数 1. A hybrid synchronous parallel within the serial bus interface system / for the synchronous system having an associated first clock signal, the bus interface comprising: a data area demultiplexing means having an input to receive a a data block and demultiplexing the data block into two groups i nibbles, each nibble having a plurality of bits; an even and an odd array of parallel-to-serial converter, each having i serial to parallel converter, each group of i nibbles is synchronized to the clock signal corresponding parallel clock rate of a second set of signal-to-serial converter to send to the i-th received nibbles is converted into a serial data, wherein the second clock signal is a delayed clock signal of the first clock signal; a first set of the i-th multiplexer on lines i, n of the second clock signal at the edge of the even numbered serially transmitted parallel to serial converter, and on the i lines, serial negative edge of the second clock signal transmitted from the odd parallel to serial converter data; a first two groups i th demultiplexers for receiving the even 奇数串行数据,并将所接收的偶数串行数据送出至一偶数缓冲器,而将奇数串行数据送出至一奇数缓冲器;一偶数组及一奇数组串行至并行转换器,其各具有i个串行至并行转换器,该偶数组的i个串行至并行转换器将所接收的偶数串行数据转换成偶数并行数据,并输出同步于该第二时钟信号的该偶数并行数据;以及该奇数组的i个串行至并行转换器将该所接收的奇数串行数据转换成奇数并行数据,并输出同步于该第二时钟信号的该奇数并行数据,以及一数据区块重建装置,以将该偶数及奇数并行数据合并为该数据区块。 Odd serial data and the serial data received even an even sent to the buffer, and sends the odd serial data to an odd buffer; an even and an odd array of serial-to-parallel converter, each of i having the even serial-to-parallel converter, i even sets the serial to parallel converter converts the received serial data into even the even parallel data, and outputs the synchronization clock signal to the second parallel data ; i and the odd serial odd serial data to parallel converter converts the received parallel data into odd and odd outputs the second clock signal synchronized to the parallel data, and a data block reconstruction means in the even and odd parallel data for the combined data block.
2.如权利要求1所述的接口,其特征在于,各个数据区块具有N个位,且1<i<N2.]]> 2. The interface according to claim 1, wherein each data block has N bits and 1 & lt; i & lt;. N2]]>
3.如权利要求1所述的接口,其特征在于,该偶数及奇数缓冲器分别缓冲该偶数及奇数组串行/并行转换器,以使该偶数及奇数组串行/并行转换器接收所接收的偶数及奇数串行数据,其中所接收的偶数及奇数串行数据同步于该第二时钟信号。 / Parallel converter receives 3. The interface of claim 1, wherein each of the even and odd buffer buffers the even and odd serial / parallel converter, so that the even and odd serial even and odd received serial data, wherein the even and odd received serial data in synchronization with the second clock signal.
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