CN100435487C - Method of transferring data - Google Patents

Method of transferring data Download PDF

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Publication number
CN100435487C
CN100435487C CN 02823116 CN02823116A CN100435487C CN 100435487 C CN100435487 C CN 100435487C CN 02823116 CN02823116 CN 02823116 CN 02823116 A CN02823116 A CN 02823116A CN 100435487 C CN100435487 C CN 100435487C
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China
Prior art keywords
data
data block
block
method according
nibble
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CN 02823116
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Chinese (zh)
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CN1589531A (en
Inventor
提摩西·A·亚瑟尼司
约瑟·葛瑞丹
艾佛瑞·史达福利
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美商内数位科技公司
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Priority to US09/990,060 priority Critical patent/US7069464B2/en
Priority to US09/990,060 priority
Priority to US10/080,480 priority
Priority to US10/080,480 priority patent/US6823468B2/en
Application filed by 美商内数位科技公司 filed Critical 美商内数位科技公司
Publication of CN1589531A publication Critical patent/CN1589531A/en
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Publication of CN100435487C publication Critical patent/CN100435487C/en

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    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00Parallel/series conversion or vice versa
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; Arrangements for supplying electrical power along data transmission lines
    • H04L25/14Channel dividing arrangements in which a single bit stream is divided between several baseband channels and reassembled at the receiver

Abstract

一种用于用户设备(UE)的混合并行/串行总线接口,此者具有一数据区块解多路复用装置。 A user equipment for mixing (UE) in a parallel / serial bus interface, this person has a data block demultiplexing device. 该数据区块解多路复用装置具有一输入,此者经配置设定以接收一数据区块,并将该数据区块解多路复用成多个细块。 The data block demultiplexing device having an input, which are configured to receive a set of data blocks, and a plurality of demultiplexing the data block into small pieces. 对于各个细块,一并行转串行转换器可将该细块转化成串行数据。 For each nibble, a parallel to serial converter may convert the serial data into nibbles. 一线路可传送各个细块的串行数据。 It may transmit a serial data line of each fine block. 一串行转并行转换器可转换各细块的串行数据以复原该细块。 A serial to parallel converter may convert the serial data of each nibble to restore the nibbles. 数据区块重建装置可将各复原细块合并成该数据区块。 A data block reconstruction device may be recovered nibbles into the data block block merger.

Description

传送数据的方法 The method of transmitting data

技术领域 FIELD

本发明是关于总线数据传送。 The present invention relates to bus data transfers. 特别是,本发明是为减少传送总线数据的线路。 In particular, the present invention is to reduce the data transfer bus lines.

背景技术 Background technique

图i所示者即为用于传送数据的总线其一范例。 FIG example by one of i bus for transmitting data that is shown in FIG. 图l是一用于无线通信 Figure l is a for wireless communication

系统的接收与传送增益控制器(GC)30、 32,及一GC控制器38说明图.一通信台,像是基站或用户设备,会传送(TX)及接收(RX)信号,为控制这些信号增益,落属于其它接收/传送组件的运作范围之间,GC30、 32会调整RX及TX信号上的增益度。 System receive and transmit gain controller (GC) 30, 32, a GC controller 38 and an explanatory view A communication station, such as a base station or user equipment, may transmit (TX) and receive (RX) signal, these control signal gain, between the falling part of the operating range of other reception / transmission components, GC30, 32 will adjust the gain of the RX and TX signals.

为控制GC30、 32的增益参数,会利用一GC控制器38,即如图l所示,该GC控制器38会利用一功率控制总线,像是16条线路总线34、 36来送出TX 36及RX 34信号的增益值,比如其中的每一个为八条线路.功率控制总线线路34、 36虽可供允快速数据传送,然这会要求该GC30、 32及该GC控制器38上许多接脚,或是像一专用集成电路(ASIC)的集成电路(IC) 上GC30、 32及GC控制器38间的许多连接,增加接脚数会要求额外电路板空间与连接。 GC30 control, the gain parameter 32, a GC controller 38 will use, i.e. as shown in Figure L, the GC controller 38 will use a power control bus, such as bus 16 lines 34, 36 and 36 to feed the TX the gain value of the RX 34 signals, such as wherein each of eight lines. the power control bus lines 34, 36 although allowing for fast data transfer, then it will require the GC30, 32 and GC controller 38 on which a number of pins, as an integrated circuit or a application specific integrated circuit (ASIC) (IC) for the GC30, 32 and GC controller many connections, may increase the number of pins requires additional circuit board space and the connection 38. 增加IC连接会占用珍责的IC空间.大量的接脚或连接或会依实现方式而定提高总线成本。 Increased IC IC connection will occupy space Jane responsibility of the large number of pins or connections or implementation will depend may be increase the cost of the bus.

从而,希望是可具有其它的数据传送方式, Thus, desirably may have other data transmission mode,

发明内容 SUMMARY

一种混合并行/串行总线接口,此者具有一数据区块解多路复用装置. 该数据区块解多路复用装置具有一输入,此者经配置设定以接收一数据区块,并将该数据区块解多路复用成多个细块(nibble),对于各个细块,一并行转串行转换器可将该细块转化成串行数据。 A hybrid parallel / serial bus interface, this person has a data block demultiplexing device. The data block demultiplexing device having an input, which are configured to receive a data block settings and demultiplexing the data block into a plurality of small pieces (Nibble), for each small block, a parallel-serial converter can convert the serial data into nibbles. 一线路可传送各个细块的串行数据, 一串行转并行转换器可转换各细块的串行数据以复原该细块.数据区块重建装置可将各复原细块合并成该数据区块, 一基站(或用户设备)具有一增益控制控制器.该增益控制控制器会产生一具有代表一增益 A circuit may transmit serial data of each nibble, a serial to parallel converter may convert the serial data of each nibble nibbles to restore the data block reconstruction device may be incorporated into the recovered nibbles block data area block, a base station (or user equipment) having a gain controlled by the controller. the controller generates a gain control with a gain representative of

值的n位的数据区块。 n bit value of the data block. 一数据区块解多路复用装置具有一输入,此者经配置设定以接收该数据区块,并将该数据区块解多路复用成多个细块。 A data block demultiplexing device having an input, which are configured to receive the data block is set, and the block data multiplexing a plurality of solutions into small pieces. 各个细块具有多个位.对于各个细块, 一并行转串行转换器可将该细块转化成串行数据, 一线路传送该细块串行数据,而一串行转并行转换器可转换该细块串行数据以复原该细块, 一数据区块重建装置可将所述经复原细块合并成该数据区块。 Each nibble having a plurality of bits. For each nibble, a parallel to serial converter may convert the serial data into nibbles, a wire transfer of the nibbles serial data, and a serial to parallel converter may be converts the nibble serial data to recover the fine block, a data block reconstruction device may be merged into the data block of the restored via nibbles. 一增益控制器接收该数据区块,并利用该数据区块的增益值以调整其增益. A gain controller receiving the data block and the data block by the gain value to adjust its gain.

附图说明 BRIEF DESCRIPTION

图1是RX与TX GC和GC控制器图式说明。 FIG 1 is RX and the TX GC and GC controller described drawings. 图2是一混合并行/串行总线接口框图。 FIG 2 is a hybrid parallel / serial bus interface block diagram.

图3是利用混合并行/串行总线接口的数据区块传送作业流程图. FIG 3 is the use of hybrid parallel / serial bus interface data block transfer flowchart.

图4说明将一区块转成最显著及最小显著细块的解多路复用作业。 4 illustrates a block transfer on the most significant and least significant nibble into multiplex operation.

图5说明利用数据交错处理对一区块进行解多路复用作业。 5 illustrates using a block of interleaved data demultiplex operation.

图6是一双向混合并行/串行总线接口的框图。 FIG 6 is a block diagram of a bi-directional hybrid parallel / serial bus interface.

图7是一双向线路实现图式, FIG 7 is a bidirectional line to achieve the drawings,

图8是开始位的时序图. FIG 8 is a timing diagram of the start bit.

图9是一函数可控制性的混合并行/串行总线口的框图。 FIG. 9 is a function controllability hybrid parallel / serial bus port of a block diagram.

图10是一函数可控制性的混合并行/串行总线接口的开始位时序图, FIG 10 is a function of the controllability of hybrid parallel / serial bus timing diagram of the start bit interface,

图ll是表示各项函数的开始位实现列表, Figure ll is a start bits indicating the function of the realization of the list,

图12是目的地控制混合并行/串行总线接口的框图, FIG 12 is a block diagram of a destination controlling hybrid / serial bus interface in parallel,

图13是表示各项目的地的开始位实现列表。 13 is a start bit of the destination list to achieve.

图14是表示各项目的地/函数的开始位实现列表。 14 is a start bits indicating destinations / functions to achieve the list.

图15是目的地/函数控制混合并行/串行总线接口的框图。 FIG 15 is a destination / functions controlling hybrid parallel block diagram / serial bus interface.

图16是表示各项目的地/函数的开始位流程图。 FIG 16 is a flowchart illustrating start bits indicating destinations / functions.

图17是正及负时钟信号边缘的混合并行/串行总线接口框图. FIG 17 is a positive and negative clock edge hybrid parallel / serial bus interface block diagram.

图18是正及负时钟信号边缘的混合并行/串行总线接口时序图.图19是一2线式GC/GC控制器总线框图。 FIG 18 is a positive and negative clock edge hybrid parallel / serial bus interface timing diagram. FIG. 19 is a 2-line GC / GC controller bus block diagram. 图20是一3线式GC/GC控制器总线框图, FIG 20 is a 3-line GC / GC controller bus block diagram,

具体实施方式 Detailed ways

图2所示者是一混合并行/串行总线接口框图,而图3为一混合并行/串行总线接口数据传送作业流程图. 一数据区块会被跨于该接口而从节点1 50传送到节点2 52(54)。 As shown in FIG. 2 by a hybrid parallel / serial bus interface block diagram, and FIG. 3 is a mixing / serial bus interface data transfer flowchart parallel. A data block is transmitted across the interface to the node 150 from to node 252 (54). 一数据区块解多路复用装置40接收该区块,并将其解多路复用成为i个细块,以利于i条数据传送线路44上传送(56).该数值i是根据连接数目与传送速度之间的取舍而定。 A data block demultiplexing device 40 receives the block, and its solution become multiplex i nibbles, facilitate transport (56) on the i-th data transmission line 44. The value i is a connector trade-off between the number of transmission speed. 一种决定i值的方式是首先决定一传送该数据区块所得承允的最大延迟。 Method of determining the value of i is to first embodiment determines the maximum delay of the data block resulting in a transfer undertakes. 按照此最大延迟,可决定出传送该区块所需要的最小线路数目。 According to this maximum delay, the circuit may determine the minimum number of blocks required for the transfer. 利用最小数量的线路,用以传送数据的线路会被选定为至少该最小值量,线路44可为接脚,以及其在电路板上或于一IC连接上的相关连接。 With a minimum number of lines for transmitting data lines is selected to be at least the minimum amount, the line 44 may be a pin, and the circuit board or associated connections in an IC on the connection. 一种解多路复用成细块的方式是将区块切割成一最显著到一最小显著细块.为如图4说明,于两条线路上传送一八位区块,该区块会被解多路复用成一四位最显著细块及一四位最小显著细块。 One kind demultiplexed into nibbles way is to cut a block of the most significant to a least significant nibble. As illustrated in Figure 4, eighteen blocks transmitted on two lines, the block is demultiplexed into fourteen most significant nibble and fourteen least significant nibble.

另一种方式则是将该区块交错跨于i个细块。 Another way sucked across the block interleaving in i nibbles. 该区块之前i个位会变成各i个细块的第一位。 Before i bits of the block become the first bit of each of the i nibbles. 其次的i个位会变成各i个细块的第二位,如此下去一直到该最后i个位.为说明如图5所示的在两条连接上的一八位区块,第一个位会被映射到细块l的第一位.第二个位会被映射到细块2的第一位,第三个位会被映射到细块l的第二位,如此继续下去, 一直到将最后一个位映射到细块2的最后位。 Second i-i bits become the respective second bit nibbles, and so on until the last i bits. FIG eighteen block is described in the two connections shown in Figure 5, a first bits are mapped to a first bit nibbles l the second bit is mapped to the first bit of nibble two, the third bit is mapped to a second bit nibbles l, and so continue, until the last bit is mapped to the last bit of nibble 2.

各个细块会被送到i个并行转串行(P/S)转换器42的相对应者(58),从并行位转换成串行位,并于线路上串行循序地传送(60).在各条线路的相对侧会是一串行转并行(S/P)转换器46.各个S/P转换器46会将所传串行数据转换成其原始细块(62).第i个经复原细块会被一数据区块重建装置48处理,以重建该原始数据区块(64). Each of i nibbles is sent to parallel to serial (P / S) converter should be, relative to (58) 42, converted from parallel bits to serial bits, and to sequentially serially transmitted on the line (60) at the opposite side of each line is a serial to parallel would be (S / P) converter 46. the respective S / P converter 46 will convert the transmitted serial data into its original nibble (62). i- by restoring a small block is a data block reconstruction device 48, so as to reconstruct the original data block (64).

另一方面,双向方式,会利用i条连接以按双向方式传送数据,即如图6。 On the other hand, in a bidirectional manner, i of connection will use to transmit data bi-directional manner, i.e., in Fig. 可按双向传送信息数据,或是可按单一方向传送信息而朝另一方向送返确认信号。 Transmitting information data can be bidirectional, single direction, or may be sent back an acknowledgment signal conveying information in the other direction. 在此, 一数据区块解多路复用及重建装置66会接收从节点1 50传送到节点2 52的数据区块。 Here, a data block demultiplexing and reconstruction device 66 receives the data block transmitted from node 150 to node 2 52. 该解多路复用及重建装置66会将该区块解多路复用成i个细块。 The demultiplexing and reconstruction device 66 will be multiplexed into the i nibbles block solution. i个P/S转换器68会将各个细块转换成串行数据.一组多路复用器(MUX)/DEMUX 71将各个P/S转换器68耦接到i条线路44的相对应者。 the i P / S converter 68 will convert each nibble into serial data. a set of multiplexers (MUX) / DEMUX 71 to the respective P / S converter 68 is coupled to the corresponding lines i 44 By. 在节点2 52处,另一组的多路复用器MUX/DEMUX 75将线路44连接到一组S/P转换器72.该组S/P转换器72会将各细块的所收串行数据转换成为原始传送的细块。 At node 252, another set of multiplexer MUX / DEMUX 75 to line 44 is connected to a set of S / P converter 72. The group S / P converter 72 will yield for each nibble of the sequence line data into the originally transmitted nibbles. 所收细块会被一数据区块解多路复用及重建装置76重建成原始数据区块,并输出为所接收的数据区块。 The received nibbles are a data block demultiplexing and reconstruction device 76 to reconstruct the original data block and output as the received data block.

对于从节点2 52传送到节点1 50的各区块,该数据区块解多路复用及重建装置76会接收一数据区块。 For transmission from node 252 to node 150 in each block, the data block demultiplexing and reconstruction device 76 receives a data block. 该区块会被解多路复用成为各细块,并将各细块传送到一组P/S转换器74。 This block is demultiplexed become the nibbles, each nibble and transferred to a set of P / S converter 74. 该P/S转换器74会将各细块转换成串行格式,以供跨于i条线路44传送,节点2组的MUX/DEMUX75会将所述P/S转换器74耦接到i条线路44,而节点1组的MUX/DEMUX 71会将线路44耦接到i个S/P转换器70,所述S/P转换器70将所传数据转换成其原始细块.该数据区块解多路复用及重建装置66从所收细块重建出数据区块,以输出所接收的数据区块。 The P / S converter 74 will convert each nibble into serial format for straddle two groups i lines 44 transfer, the node MUX / DEMUX75 will the P / S converter 74 is coupled to the strip i line 44, and MUX 1 node group / DEMUX 71 is coupled to line 44 will be the i-th S / P converter 70, the S / P converter 70 converts the transmitted data into its original nibbles. the data region block demultiplexing and reconstruction device 66 reconstructs the data block from the received nibbles, data to output the received block. 既然一次只会在单一方向上传送数椐,这种实现可按半双工方式运作。 Since it is only sent once the number noted in a single direction, this implementation can be half-duplex operation.

图7是一双向切换电路的实现简图.该节点l P/S转换器68的串行输出会被输入到一三态式緩沖器78,该緩沖器78具有另一输入,这会被耦接到一表示高状态的电压.该緩冲器78的输出是串行数据,透过线路85被传送到一节点2三态式緩冲器84。 FIG 7 is a schematic view of achieving a bidirectional switching circuit. The node l P / S converter 68 serial output is input to a tri-state buffer 78 type, the buffer 78 has another input which is coupled to a high state represents the voltage output of the buffer 78 is the serial data, transmitted to a node 2 tri-state buffer 84 through line 85 formula. 电阻86会被耦接于线路85与接地之间,该节点2緩冲器84传通该串行数据给一节点2S/P转换器74。 Resistor 86 is coupled between line 85 and ground, the node 2 pass-through buffer 84 to the serial data to a Node 2S / P converter 74. 类似地,来自该节点2 P/S转换器74的串行输出会被输入到一三态式緩冲器72。 Similarly, the serial output from the Node 2 P / S converter 74 will be typed into a tri-state buffer 72 type. 该緩冲器72 也具有另一耦接于一高电压的输入。 The buffer 72 also having another coupled to a high voltage input. 该緩冲器82的串行输出会透过线路85 而传送到节点1三态式緩冲器80。 The serial output buffer 82 will be sent through line 85 to a Node 1 tri-state buffer 80 formula. 该节点1緩沖器80会将该串行数据传通至一节点l S/P转换器70。 The Node 1 buffer 80 will pass through the serial data to a node l S / P converter 70.

在另种实现里,部分的i条线路44可在一方向上传送数据,而其它的i 条线路44可在另一方向上传送数据。 In another kind of realization where, i lines 44 may transfer data portion in one direction, while the other i lines 44 may transfer data in the other direction. 在节点150,会收到一数据区块以供传送到节点2 52.根据该区块所需的数据吞吐速率以及另一方向上的话务需求而定,在此会利用j条连接来传送该区块,其中该j值为l到i之间.该 In node 150, receives a data block for transmission to Node 2 52. depends on the traffic demand required data throughput rate, and the block in the other direction, this will be transmitted using the connection bar j blocks, wherein the value of j between l and i. the

区块会被分成j个细块,并利用i个P/S转换器68中的j个来转换^j组串行数据。 Blocks are divided into j nibbles, and using the i P / S converter 68 converts the j ^ j set of serial data. 相对应的j个节点2S/P转换器72,与节点2数据区块区别及重建装置76 会复原该数据区块。 J corresponding nodes 2S / P converter 72, the difference between the node 2 and the data block reconstruction device 76 will recover the data block. 在相反方向上,会利用达ij或k条线路以传送该数据区块。 In the opposite direction, or it will use ij k of lines to transmit the data block.

在一用于增益控制总线的双向式总线较佳实现中,会在一方向上送出一增益控制值,并送返一确认信号。 In the preferred implementation of the bidirectional bus a formula for the gain control of the bus, in one direction will feed a gain control value, and sent back a confirmation signal. 或另者,在一方向上送出一增益控制值,而在另一方向上送出一增益控制装置状态信号, Or another person, in one direction out a gain control value, and gain control means sends a state signal in the other direction,

一种混合并行/串行接口实现是于一同步系统内,且可参如图8所说明者。 A hybrid parallel / serial interface is in a synchronous system, and 8 may be described by reference FIG. 在此,会利用一同步时钟信号以同步各式组件的计时。 Here, we will use a synchronous clock signal to synchronize the timing of a variety of components. 为表述该数据区块传送作业的起点,会送出一开始位。 The starting point for the presentation of the data block transfer operations, will send a start bit. 即如图8所示,各线路会在其正常零水准。 That is, as shown in FIG. 8, each line will be in its normal zero level. 然后会送出一表示开始区块传送作业的开始位,在本例中,所有线路会送出一开始位,然实仅需在一条线路上送出开始位.如在任一条线路上送出开始位,像是一1值,则接收节点会明了开始该区块数据传送作业。 Then will send a start bit indicates the start of a block transfer operation, in the present embodiment, all lines will send a start bit, and then sending only a solid start bit on a line. As feed start position on any one line, such as a value of 1, the receiving node will be apparent to the start of the data block transfer operation. 在此,会透过其相对应线路送出各个串行细块。 Here, each of the serial nibble will send through its corresponding line. 在传送各细块后, 线路会回返至它们的正常状态,比如皆为低者。 After the transfer of each fine block line will return to their normal state, such as those who are all low.

在其它实现里,也会利用开始位做为待予执行的函数的表示器.这种实现方式可如图9说明。 In other implementations, the start bit also use the indicator as a function to be performed. Such an implementation may be described in FIG. 9. 而如图10所示者,如任一连接的第一位为l值,该接收节点会了解待予传送区块数据。 While those shown in FIG. 10, as any one of a value of l is a connection, the receiving node will know the data to be transmitted to the block. 即如图11的GC控制器实现的表格所列,利用三种开始字节合:01、 lO及ll, OO表示尚未送出开始位.各个组合代表一种函数。 That is, as listed in Table 11 GC controller implementation, using three engagement start byte: 01, lO and ll, OO indicates a start bit was not sent each combination represents a function. 在本例中,Ol表示应执行一相对减少函数,像是将该数据区块值减少l值.IO表示应执行一相对增加函数,像是将该数据区块值增加1值。 In the present embodiment, Ol indicates a relative decrease function should be performed, such as reducing the value of the data block value .IO l represents a relative increase function should be performed, such as increasing the data block value 1 value. ll表示应执行一绝对值函数,此时该区块会维持相同数值.为增加可用函数的数目,可利用额外位,例如,可将每条线路2个开始位映射到达七(7)项函数,或是将i条线路的n个开始位映射到达i。 ll represents an absolute value function should be performed, then the block will maintain the same value. To increase the number of available functions, additional bits can be used, for example, two start bits per line may be mapped items arrive seven (7) functions or n starting bits the lines i reaches i mappings. +'-l种函数.处理装置86会依开始位所述,对所收的数据区块执行函数, + '-. L kind will function processing means 86 by the start bit, the execution of the function blocks of received data,

在如图12所示的另款实现里,开始位表示一目的地装置。 In another implementation shown in section in FIG. 12, the start bits indicate a destination device. 即如图13 所示,此为两个目的地装置/两条线路实现,开始位的组合会关联到对所传数据区块的目的地装置88-92。 That is, as shown in FIG. 13, this is a two destination device / two line implementation, the combination of the start bit will be associated with the destination device of the transmission data block 88-92. Ol表示装置l; 10表示装置2;而ll表示装置3。 Ol apparatus represents l; 10 represents means 2; ll represents the apparatus 3. 在收到该数据区块重建装置48的开始位后,所重建的区块会被送到相对应装置88-92。 Upon receipt of the start bits of the data block reconstruction device 48, the reconstructed block is sent to the corresponding device 88-92. 为增加潜在目的地装置的数目,可利用额外的开始位。 To increase the number of potential destination devices, additional start bits may be utilized. 对于在各i条线路上的n个开始位,可选定达in"-l个装置. For n starting bits over each of i lines, up to one in -l device "may be selected.

即如图14所示,可利用开始位来表示函数及目的地装置两者.图14 显示一具有像是RX及TX GC两个装置的三条连接系统.在各条线路上利用开始位,图中绘出两个装置的三种函数。 That is, as shown in FIG. 14, the start bits may be utilized to represent both function and destination device. FIG. 14 shows a three connection system having two devices such as a RX and TX GC. Utilization start position on the various lines, FIG. plotted in three kinds of functions of two devices. 在本例中,线路l的开始位代表该标的装置,「0J为装置1,而rn为装置2。连接2及3的位代表所执行函数。rilJ代表绝对值函数;「 10 J代表相对增加函数;而r 01J代表相对减少函数。所有三个开始位为零,意即r 000J ,会是正常非数据传送状态,而在此并未使用「oon ,可利用额外的位以增加更多的函数或装置。对于在各i条线路上的n个开始位,可选定达in"-l个函数/装置组合。 In the present embodiment, the start position of the line l representing the destination device, "1 0J to apparatus, and rn is connected to the device 2. The bits 2 and 3 representing the functions performed .rilJ representative of an absolute value function;" 10 J represents the relative increase function; and r 01J represents the relative decrease function of all three start bit is zero, which means r 000J, will be the normal non-data transfer state, but this does not use "oon, available extra bit to add more. device or function. for n starting bits over each of i lines, up can be selected in "-l functions / device combination.

图15是一实现表示函数及目的地装置两者的开始位的系统框图.经复原的细块会由该数据区块重建装置48所接收。 FIG 15 is a system block diagram showing functions realized and the start position of both the destination device via the fine pieces will be restored by the data block reconstruction device 48 receives. 根据所收到的开始位,该处理装置86会执行所述函数,而将所处理区块送到所述的目的地装置88-92 The destination device received start bits, the processing device 86 performs the function, and the processed block to the 88-92

即如图16流程图所示,会将表示该函数/目的地的开始位增入各个细块内(94)。 I.e. the flowchart shown in FIG. 16, the function will start bits / destination into the respective fine gain block (94). 在此,会透过这i条线路送出这些细块(96).利用开始位,会在数据区块上执行适当函数,数据区块会被送到适当目的地或两者(98). Here, I will send the fine blocks (96) through this line i. Utilization start bit, performs the appropriate function on the data block, the data block is sent to the appropriate destination or both, (98).

为增加同步系统内的吞吐量,会利用时钟信号的正(双)及负(单)边缘两者来传送区块数据.其一实现可如图17所示。 To increase the throughput in a synchronous system, the clock signal will use the positive (even) and negative (odd) edge of the two block data to transmit. One shown in Figure 17 may be implemented. 数椐区块解多路复用装置100收到数据区块,并将其解多路复用成两个(双及单)组i个细块.在此, 会将i个细块的各组数据送到个别各组的i个P/S装置102、 104。 Number noted in block demultiplexing device 100 receives the data blocks, and demultiplexed into its two (single and double) the group i nibbles. Each Here, the i-th small blocks will individual groups of data to each group number i P / S devices 102, 104. 即如图17 所示, 一组的单P/S装置102会具有i个P/S装置,这会拥有其经反置器118 所反置的时钟信号信号,因此,经反置的时钟信号信号会是经相对于该系统时钟信号而延迟的半个时钟信号周期. 一组i个MUX 106会在该组双P/S 装置104与该组单P/S装置102之间,按两倍于该时钟信号速率而进行选定。 That is, a single set of P / S unit 102 in FIG. 17 i may have a P / S devices, which will have its clock signal inverted is inverted by 118, and therefore, the inverted clock signal signal would be via the system clock signal with respect to the delayed half a clock signal period. i-th set of MUX 106 will be between the set of two P / S device set 104 and the single P / S devices 102, to twice to the clock signal for the selected rate. 在各连接上传送的产获数据会是两倍的时钟信号速率。 Production eligible data is transmitted on each connection is twice the rate of the clock signal. 在各连接的另一端是一相对应的DEMUX 108.这些DEMUX 108会循序地按两倍时钟信号速率,将各条线路44耦接到一双112与单110緩冲器。 At the other end of each connection is a corresponding DEMUX 108. The DEMUX 108 may sequentially to twice the rate of the clock signal, each of the lines 44 is coupled to one pair of buffers 112 and 110 alone. 各个緩冲器112、 110 接收一相对应的双与单位元,并握持该数值一个完整时钟信号周期。 Each buffer 112, 110 receives a corresponding unit cell with double and holding the value of a complete clock signal period. 一双U6与单114组的S/P装置会复原所述双与单细块。 One pair of single S U6 group 114 / P apparatus will recover the single double nibbles. 一数据区块重建装置122 会从各个所传细块重建该数据区块。 A data block reconstruction device 122 of the data block from each of the reconstructed transmitted nibbles.

图18说明利用该正及负时钟信号边缘,在一系统线路上进行的数据传送作业。 Figure 18 illustrates the use of the positive and negative clock edge, the data transfer operations performed on a line system. 图标者是待予于线路l上传送的双数据与单数据.斜楔部分表示合并信号内的负时钟信号边缘,而无斜楔部分则表示正者。 To be icons by a single double-data on the data transfer line l. Wedge portion indicates the negative clock edge signal within the combined signal without said wedge portion are positive. 即如图标,数据传送速率会增加一倍。 That is such an icon, the data transfer rate can be doubled.

图19是一用于一GC控制器38及一GC 124之间的混合并行/串行接口较佳实现。 FIG 19 is a hybrid between a GC controller 38 and a GC 124 a parallel / serial interface is preferably implemented. 一数据区块,像是16位的GC控制数据(8位RX和8位TX),会被从该GC控制器38传送给一数据区块解多路复用装置40,该数据区块会被解多路复用成为两个细块,像是两个8位细块.会对各个细块增附一开始位,像是令为每个细块9位.在此,会利用两个P/S转换器42于两条线路上传送这两个细块.当S/P转换器46侦测到开始位时就会将所接收细块转换为并行格式。 A data block, such as 16 of GC control data (8 bits RX and 8 the TX), is sent from the GC controller 38 to a data block demultiplexing device 40, the data block will Solutions are multiplexed into two nibbles, such as two eight bit nibbles. be attached to the respective small pieces by a start bit, so that for each such nibble 9. here, will use two P / S converter 42 to the two transmission lines two nibbles. nibbles when S / P converter 46 to detect the start bit will be received into a parallel format. 该数据区块重建装置会重建原始16位以控制GC 124的增益. 如开始位表述出一函数,即如图ll所示,该AGC 124会在调整增益之前, 先对所收区块执行该项函数. The data block reconstruction device reconstructs the original 16 to control the gain of the GC 124. As a function of the start bit representation, i.e. as shown in FIG ll, which will be the AGC 124 adjusts the gain before the first execution of the block of the received entry function.

图20是于一混合并行/串行总线转换器另一较佳实现,此是位于GC 控制器38及一RX GC 30与TX GC 32间,并利用三(3)条线路。 FIG. 20 is in a hybrid parallel / serial bus converter another preferred implementation, this is located in the GC controller 38 and a RX GC 30 and TX GC 32 rooms, using three (3) lines. 该GC控制器38会按适当RX及TX增益值与开始位,即如图14所示,送出一数据区块给该GC30、 32.如确采用按图14的开始位,装置1为RXGC30 而装置2为TX GC 32.该数据区块解多路复用装置40会将该数据区块解多路复用成为三个细块,以供透过这三条线路而传送.利用三个P/S转换器42及三个S/P转换46,各细块会被串行地在各线路上传送,并转换成原始细块。 The GC controller 38 will be in proper RX and TX gain values ​​and start bits, i.e. 14, sends a data block to the GC30, 32. The start bit is determined by using FIG. 14, the apparatus 1 is RXGC30 2 is a device TX GC 32. the data block demultiplexing device 40. the data block demultiplexing will be three small blocks, for which three lines transmitted through using three P / S converters 42 and three S / P converters 46, each of the nibbles are transferred serially on each line, and converted into the original nibbles. 该数据区块重建装置48会重建原始数据区块,并执行如开始位所述的函数,像是相对增加、相对减少及绝对值。 The data block reconstruction device 48 reconstructs the original data block and performs the function as the start bit, such as relative increase, relative decrease and absolute value. 所获数据会被送到如开始位所述的RX或TXGC30、 32。 The resulting data is sent to the RX or TXGC30 as the start bit, 32.

Claims (19)

1.一种由用户设备(UE)用以传送数据的方法,其中包含: 提供一数据区块; 将该数据区块解多路复用成多个细块,各个细块具有多个位; 对于各个细块: 将该细块转换成串行数据; 提供i个线路,并在该线路上传送该细块串行数据; 将该细块串行数据转换成并行数据,以复原该细块;及将各复原细块合并成该数据区块; 其中在数据区块内的位数目为N,线路数目为i,而1<i<N,当最大化一个要求的延迟时,i及N被选择来最小化线路的数量。 1. A method for transmitting data by a user equipment (the UE), which comprises: providing a data block; demultiplexing the data block into a plurality of nibbles, each nibble having a plurality of bits; for each nibble: the nibble into serial data; providing i th line, and transmitting the nibble serial data over the line; converts the nibble serial data into parallel data to recover that nibble ; and combined blocks recovered nibbles into the data block; wherein the number of bits in a data block is N, the number of lines is i, and 1 <i <N, maximized when a required delay, i and N It is selected to minimize the number of lines.
2. 如权利要求l所述的方法,其特征在于,在一细块内的位数目为四, 线路数目为二。 L The method according to claim 2, wherein the number of bits in a nibble is four, the number of lines is two.
3. —种由用户设备(UE)用以透过连接一第一节点至一第二节点的接口来传送数据区块的方法,其中该方法包含:将该数据区块解多路复用成m組,每一组具有n个位; 对这些m组增附一开始位,这些m个开始位中的每一个是每一组的第一位,而可共集地代表一特定数学函数或目的地;在个别线路上,从该第一节点传送这些m组中的每一个; 在该第二节点处接收所传的这m组;及根据这些m个开始位来利用所收m组。 3. The - method to transmit data blocks through the interface connected to a first node a second node by a user equipment (UE) is used, wherein the method comprises: demultiplexing the data block into m groups each having n bits; these m groups attached by a start bit, the start bit m of each of the first one of each group, but may represent a particular set of common mathematical functions or destination; on individual lines, is transmitted from the first node each of the m groups; receiving transmitted at the m sets of the second node; and these m bits beginning m using the received group.
4. 如权利要求3所述的方法,其特征在于,这些m个开始位至少其一会为1状态,且当该接口并未传送数据时,所有的个别线路会为0状态。 4. The method according to claim 3, wherein the at least one of the m start bits to be state 1, and if the interface is not transmitting data, all of the individual lines will be 0 state.
5. 如权利要求3所述的方法,其特征在于,这些m个开始位代表开始一数据传送作业。 5. The method according to claim 3, wherein the m start bits represent the beginning of a data transfer operation.
6. 如权利要求3所述的方法,其特征在于,这些m个开始位共集地代表一特定数学函数而非一目的地。 6. The method according to claim 3, wherein the m start bit represents a particular set of common mathematical function rather than a destination.
7. 如权利要求3所述的方法,其特征在于,这些m个开始位共集地代表一包括一相对增加、 一相对减少及一绝对值函数。 7. The method according to claim 3, wherein the m start bit represents a common set comprises a relative increase, a relative decrease and an absolute value function.
8. 如权利要求3所述的方法,其特征在于,这些m个开始位共集地代表一特定目的地而非一数学函数。 8. The method according to claim 3, wherein the m start bit represents a common set of a particular destination and not a mathematical function.
9. 如权利要求8所述的方法,其特征在于,这些m个开始位共集地代表包括一RX及TX增益控制器。 9. The method according to claim 8, wherein the set of the m start bits represent comprising a total of RX and TX gain controller.
10. 如权利要求3所述的方法,其特征在于,这些m个开始位共集地代表一特定数学函数及一特定目的地。 10. The method according to claim 3, wherein the m start bit represents a particular set of common mathematical function and a particular destination.
11 .一种由用户设备(UE)用以决定于一总线上传送区块数据而所需的i 条总线连接数目的方法,所述区块数据的各区块具有N个位,该方法包含:决定为传送所述数据区块而可承允的最大延迟; 决定依该最大要求延迟,为传送所述数据区块而所需的连接最大数目•,及决定i值,而i是至少为该所需连接的最小数目的数值。 Article number i is one kind of bus 11 for connecting method by a user equipment (UE) determines transmission data block on a bus desired, each block in the block data having N bits, the method comprising: It determines the maximum delay of the data block transfer and can undertake; a decision by the maximum delay requirements for transmission of the data block and the maximum number of connections required •, and determines the value of i, and i is the least for the minimum number of connections required value.
12. 如权利要求11所述的方法,其特征在于,该i条总线连接会对应于一芯片上的i个接脚。 12. The method according to claim 11, wherein the bus bar connections i corresponding to the i-th pins on a chip.
13. 如权利要求12所述的方法,其特征在于,该l<i<N。 13. The method according to claim 12, characterized in that the l <i <N.
14. 一种由用户设备用以传送数据的方法,其中包含: 通过一增益控制(GC)控制器产生一数据区块,该数据区块具有n个表示一增益值的位;经i条线路,将该数据区块从该GC控制器传送到一GC,在此l<i<n; 于该GC处接收该数据区块;及利用该数据区块的增益值来调整该GC增益。 14. A method for transmitting data by a user equipment, which comprises: generating a data block by a gain control (GC) controller, the data block having n bits represents a number of gain values; i via lines , the data block is transmitted from the GC controller to a GC, this l <i <n; receiving the data block to the GC at; and the data block by the gain value to adjust the gain of the GC.
15. 如权利要求14所述的方法,其中进一步包含: 在传送该数据之前,先将该数据区块解多路复用成多个细块,各细块是为于该i条线路的不同线路上传送;及在接收该数据区块之后,将各细块合并成该数据区块。 15. The method according to claim 14, wherein further comprising: prior to transmitting the data, the first data block demultiplexing into a plurality of nibbles, each nibble is different to the i lines in a transmission line; and after receiving the data block, and the combined data of each nibble into the block.
16. 如权利要求15所述的方法,其特征在于,被增附至各细块者是一开始位。 16. The method according to claim 15, characterized in that, by being attached to each nibble is a start bit by.
17. 如权利要求16所述的方法,其特征在于,该开始位可表述一待予执行的数学函数。 17. The method according to claim 16, characterized in that the start bit can be expressed in a mathematical function to be performed.
18. 如权利要求17所述的方法,其特征在于,由该开始位所表述的数学函数包括一相对增加、 一相对减少及一绝对值函数。 18. The method according to claim 17, wherein the start position expressed by the mathematical function comprises a relative increase, a relative decrease and an absolute value function.
19. 如权利要求14所迷的方法,其特征在于,该GC包括一RXGC及一TX GC,而所述开始位说明需将该区块送到RX GC或TX GC。 19. The method of claim 14 fans claim, wherein the GC includes a RXGC the TX GC and a, and the start bit for an explanation to the RX GC or block the TX GC.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2254192Y (en) * 1995-10-27 1997-05-14 姜波 Multifunctional high-grade KWH meter
CN2276694Y (en) * 1996-04-27 1998-03-18 厦门科华俐发展有限公司 Scrambling and descrambling device for wired TV.

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5327126A (en) * 1992-06-26 1994-07-05 Hewlett-Packard Company Apparatus for and method of parallel justifying and dejustifying data in accordance with a predetermined mapping
JPH06334537A (en) * 1993-05-21 1994-12-02 Fujitsu Ltd Serial/parallel converting circuit with indeterminacy removing function
US5926120A (en) * 1996-03-28 1999-07-20 National Semiconductor Corporation Multi-channel parallel to serial and serial to parallel conversion using a RAM array
US6040792A (en) * 1997-11-19 2000-03-21 In-System Design, Inc. Universal serial bus to parallel bus signal converter and method of conversion

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2254192Y (en) * 1995-10-27 1997-05-14 姜波 Multifunctional high-grade KWH meter
CN2276694Y (en) * 1996-04-27 1998-03-18 厦门科华俐发展有限公司 Scrambling and descrambling device for wired TV.

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JP4027894B2 (en) 2007-12-26
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