CN1332328C - Base station having a hybrid parallel/serial bus interface - Google Patents
Base station having a hybrid parallel/serial bus interface Download PDFInfo
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- CN1332328C CN1332328C CNB02823118XA CN02823118A CN1332328C CN 1332328 C CN1332328 C CN 1332328C CN B02823118X A CNB02823118X A CN B02823118XA CN 02823118 A CN02823118 A CN 02823118A CN 1332328 C CN1332328 C CN 1332328C
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4009—Coupling between buses with data restructuring
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Abstract
A hybrid serial/parallel bus interface for a base station has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter converts the nibble into serial data. A line transfers each nibble's serial data. A serial to parallel converter converts each nibble's serial data to recover that nibble. A data block reconstruction device combines the recovered nibbles into the data block.
Description
Technical field
The invention relates to bus data transmits.Particularly, the present invention is for reducing the circuit of transmission bus data.
Background technology
That shown in Figure 1 is the bus one example that is used to transmit data.Fig. 1 is a reception that is used for wireless communication system and transmit gain controller (GC) 30,32, and a GC controller 38 key diagrams.One called station similarly is base station or subscriber equipment, can transmit (TX) and receive (RX) signal.For controlling these signal gains, fall to belonging between the operational range of other reception/transfer assembly GC30,32 degree of gain that can adjust on RX and the TX signal.
For control GC30,32 gain parameter, can utilize a GC controller 38.Promptly as shown in Figure 1, this GC controller 38 can utilize a power control bus, similarly is the yield value that 16 bus wire 34,36 are sent TX36 and RX34 signal, similarly is that each is eight circuits.Though power control bus circuit 34,36 can transmit for fair rapid data, right this can require this GC30,32 and this GC controller 38 on many pins, or the integrated circuit (IC) of picture one special IC (ASIC) is gone up GC30,32 and many connections (connection) of 38 of GC controllers.Increasing pin count can require additional circuit board space and be connected.Increase the IC connection and can take precious IC space.A large amount of pins or connection maybe can improve the bus cost surely according to implementation.
Thereby hope is the data mode that can have other.
Summary of the invention
A kind of hybrid parallel/serial bus interface, this person has a block and separates multiplex machine.This block is separated multiplex machine and is had an input, and this person is configured setting and determines to receive a data field, and this block separated is multiplexed into a plurality of thin pieces (nibble).For each thin piece, a parallel serial convertor that changes can change into serial data with this thin piece.One circuit can transmit the serial data of each thin piece.One serial is changeed the serial data of convertible each the thin piece of parallel converters to restore this thin piece.Data block reconstruction device can be restored each thin piece and is merged into this block.One subscriber equipment (or base station) has a gain control controller.This gain control controller can produce one and have the block of the n position of representing a yield value.One block is separated multiplex machine and is had an input, and these are configured setting receiving this block, and this block separated is multiplexed into a plurality of thin pieces.Each thin piece has a plurality of positions.For each thin piece, a parallel serial convertor that changes can change into serial data with this thin piece, and a circuit transmits this thin piece serial data, and a serial is changeed convertible this thin piece serial data of parallel converters to restore this thin piece.One data block reconstruction device can be merged into this block through restoring thin piece with described.One gain controller receives this block, and the yield value that utilizes this block is to adjust its gain.
Description of drawings
Fig. 1 is RX and TX GC and the graphic explanation of GC controller.
Fig. 2 is a hybrid parallel/serial bus interface block diagram.
Fig. 3 utilizes the block of hybrid parallel/serial bus interface to transmit operation process chart.
Fig. 4 explanation changes into a block the multiplexed operation of separating of the most remarkable and minimum significantly thin piece.
Fig. 5 explanation utilizes data interlace to handle a block is separated multiplexed operation.
Fig. 6 is the block diagram of a two-way hybrid parallel/serial bus interface.
Fig. 7 is that a two-way circuit is realized graphic.
Fig. 8 is the sequential chart of start bit.
Fig. 9 is the block diagram of the hybrid parallel/serial bus mouth of a function controllability.
Figure 10 is the start bit sequential chart of the hybrid parallel/serial bus interface of a function controllability.
Figure 11 is that tabulation is realized in the start bit of expression various functions.
Figure 12 is the block diagram of destination control hybrid parallel/serial bus interface.
Figure 13 is that tabulation is realized in the start bit of the every destination of expression.
Figure 14 is that tabulation is realized in the start bit of the every destination/function of expression.
Figure 15 is the block diagram of destination/functions control hybrid parallel/serial bus interface.
Figure 16 is the start bit process flow diagram of the every destination/function of expression.
Figure 17 is the hybrid parallel/serial bus interface block diagram that is just reaching the negative clock signal edge.
Figure 18 is the hybrid parallel/serial bus interface sequential chart that is just reaching the negative clock signal edge.
Figure 19 is one 2 line formula GC/GC controller bus block diagrams.
Figure 20 is one 3 line formula GC/GC controller bus block diagrams.
Embodiment
Shown in Figure 2 is a hybrid parallel/serial bus interface block diagram, and Fig. 3 is a hybrid parallel/serial bus interface data transfer operations process flow diagram.One block can be sent to node 252 (54) from node 150 across this interface.One block is separated multiplex machine 40 and is received this block, and it is separated the multiplexed i of becoming a thin piece, is beneficial to transmit on the i bar data transmission lines 44 (56).This numerical value i decides according to the choice between linking number and the transfer rate.A kind of mode of the i of decision value is at first to determine one to transmit the maximum-delay that this block gained is agreed.According to this maximum-delay, can determine and transmit the needed minimum wire number of this block.Utilize the circuit of minimum number, can be chosen to be this minimum value amount at least in order to the circuit that transmits data.Circuit 44 can be pin, with and on the circuit board or the relevant connection in an IC connection.A kind of separate the mode that is multiplexed into thin piece be block is cut into one the most remarkable to a minimum significantly thin piece.For as Fig. 4 explanation, on two circuits, transmit one or eight blocks, this block can be separated is multiplexed into one or four thin pieces the most remarkable and one or four significantly thin pieces of minimum.
Another kind of mode then is that this block is staggered across i thin piece.Preceding i position of this block can become first of each i thin piece.The i of next second of can become each i thin piece so goes down until this last i position.Be explanation one or eight blocks in two connections as shown in Figure 5, first meeting is mapped to first of thin piece 1.Second position can be mapped to first of thin piece 2.The 3rd position can be mapped to second of thin piece 1, so continues, until last is mapped to the last position of thin piece 2.
Each thin piece can be sent to i the parallel corresponding person (58) who changes serial (P/S) converter 42, convert serial bit to from parallel position, and serial transmits (60) sequentially on circuit.Opposite side at each bar circuit can be a transformation from serial to parallel (S/P) converter 46.Each S/P converter 46 can pass serial data with institute and convert its primary fine piece (62) to.I can be by a data block reconstruction device 48 processing, to rebuild this original data block (64) through restoring thin piece.
On the other hand, bidirectional mode can utilize the i bar to connect to transmit data by bidirectional mode, promptly as Fig. 6.Can be by two-way transfer information data, or can transmit information and give towards other direction by single direction and return confirmation signal.At this, a block is separated multiplexed and reconstructing device 66 can receive the block that is sent to node 252 from node 150.This separates multiplexed and reconstructing device 66 can be separated this block and is multiplexed into i thin piece.I P/S converter 68 can convert each thin piece to serial data.One group of multiplexer (MUX)/DEMUX 71 is couple to each P/S converter 68 the corresponding person of i bar circuit 44.At node 252 places, the multiplexer MUX/DEMUX 75 of another group is connected to one group of S/P converter 72 with circuit 44.This group S/P converter 72 can be converted into the serial data of receiving of each thin piece the thin piece of original transmission.The thin piece of receiving can be separated multiplexed by a block and reconstructing device 76 is reconstructed into original data block, and be output as the block that is received.
For each block that is sent to node 150 from node 252, this block is separated multiplexed and reconstructing device 76 can receive a block.This block can be separated multiplexed each thin piece that becomes, and with each thin block transfer to one group of P/S converter 74.This P/S converter 74 can convert each thin piece to serial form, for transmitting across i bar circuit 44.MUX/DEMUX that node is 2 groups 75 can be couple to i bar circuit 44 with described P/S converter 74, and the MUX/DEMUX 71 of 1 group of node can be couple to i S/P converter 70 with circuit 44.Described S/P converter 70 passes data-switching with institute and becomes its primary fine piece.This block is separated multiplexed and reconstructing device 66 reconstructs block from the thin piece of receive, to export the block that is received.Since once only can transmit data on single direction, this realization can operate by half-duplex mode.
Fig. 7 is the realization sketch of a two-way commutation circuit.The serial output of this node 1P/S converter 68 can be imported into a ternary formula impact damper 78.This impact damper 78 has another input, and this can be coupled to the voltage of an expression high state.The output of this impact damper 78 is serial datas, sees through circuit 85 and is sent to a node 2 ternary formula impact dampers 84.Resistance 86 can be coupled between circuit 85 and the ground connection.These node 2 impact dampers 84 pass logical this serial data and give a node 2S/P converter 74.Similarly, the serial output from this node 2P/S converter 74 can be imported into a ternary formula impact damper 72.This impact damper 72 also has another and is coupled to a high-tension input.The serial output of this impact damper 82 can see through circuit 85 and be sent to node 1 ternary formula impact damper 80.This node 1 impact damper 80 can reportedly pass to a node 1S/P converter 70 with this serial number.
Plant in the realization at other, the i bar circuit 44 of part can transmit data on a direction, and other i bar circuit 44 can transmit data on other direction.At node 150, can receive that a block is for being sent to node 252.Decide according to required data throughput rate of this block and the traffic demand on the other direction, can utilize the j bar to connect at this and transmit this block, wherein this j value is between 1 to i.This block can be divided into j thin piece, and utilizes i the j in the P/S converter 68 to convert j group serial data to.Corresponding j node 2S/P converter 72 can restore this block with difference of node 2 block and reconstructing device 76.In the opposite direction, can utilize and reach i-j or k bar circuit to transmit this block.
In a preferable realization of reversible bus that is used for the gain control bus, can on a direction, send a gain control value, and send and return a confirmation signal.Or person in addition, on a direction, send a gain control value, and on other direction, send a gain control status signal.
It is in a synchronous system that a kind of hybrid parallel/serial line interface is realized, and can join the illustrated person as Fig. 8.At this, can utilize the timing of a synchronizing clock signals with synchronous various assembly.For explaining the starting point that this block transmits operation, can send position at the beginning.Promptly as shown in Figure 8, each circuit can be in its normal zero level.Can send the start bit of an expression beginning block transfer then.In this example, all circuits can be sent position at the beginning, and right real only the need sent the start bit on a circuit.As on arbitrary circuit, sending the start bit, similarly be one 1 values, then receiving node can understand that beginning this block data transmits operation.At this, can see through its corresponding circuit and send the thin piece of each serial.After transmitting each thin piece, the return normal condition to them of circuit meeting is such as being all low person.
In other is realized, also can utilize the announcer of start bit as the function of waiting to give execution.This implementation can illustrate as Fig. 9.And person as shown in figure 10 is 1 value as first of arbitrary connection, and this receiving node can be understood and waits to give the transmission block data.Promptly the form of realizing as the GC controller of Figure 11 is listed, utilizes three kinds of beginning bit combinations: 01,10 and 11.The start bit is not sent in 00 expression as yet.A kind of function of each combination representative.In this example, 01 expression should be carried out one and reduce function relatively, similarly is that this block value is reduced by 1 value.10 expressions should carry out one increases function relatively, similarly is that this block value is increased by 1 value.11 expressions should be carried out an ABS function, and this moment, this block can be kept identical numerical value.For increasing the number of available functions, can utilize extra bits, for example, 2 start bit mappings of every circuit can be arrived seven (7) functions, or n start bit mapping of i bar circuit arrived i
N+1-a kind of function.Treating apparatus 86 can be described according to the start bit, and the block of being received is carried out function.
In another kind was as shown in figure 12 realized, a destination device was represented in the start bit.Promptly as shown in figure 13, this is that two destination device/two circuit realizes that the combination of start bit can be associated with the destination device 88-92 to the biography block.01 indication device 1; 10 indication devices 2; And 11 indication devices 3.Behind the start bit of receiving this data block reconstruction device 48, the block of being rebuild can be sent to corresponding device 88-92.For increasing the number of potential destination device, can utilize extra start bit.For n start bit on each i bar circuit, can select and reach i
N+1-1 device.
Promptly as shown in figure 14, can utilize the start bit come representative function and destination device both.Figure 14 shows one, and to have similarly be three connected systems of RX and two devices of TX GC.On each bar circuit, utilize the start bit, draw three kinds of functions of two devices among the figure.In this example, this target device is represented in the start bit of circuit 1, and " 0 " is device 1, and " 1 " is device 2.Connect 2 and 3 the performed function of position representative." 11 " represent ABS function; " 10 " representative increases function relatively; And " 01 " representative reduces function relatively.All three start bits are zero, and meaning i.e. " 000 ", can be normal non-data transfer state, and not use " 001 " at this.Can utilize extra position to increase more function or device.For n start bit on each i bar circuit, can select and reach i
N+1-1 function/device combinations.
Figure 15 is the system chart of a realization representative function and both start bits of destination device.Thin piece through restoring can be received by this data block reconstruction device 48.According to the start bit of being received, this treating apparatus 86 can be carried out described function, delivers to described destination device 88-92 and institute is handled block
Promptly shown in Figure 16 process flow diagram, the start bit of this function/destination of expression can be increased in each thin piece (94).At this, can see through this i bar circuit and send these thin pieces (96).Utilize the start bit, can carry out suitable function on block, block can be sent to suitable destination or both (98).
Be to increase the handling capacity in the synchro system, both transmit block data can to utilize just (even number) of clock signal and negative (odd number) edge.One is realized can be as shown in figure 17.Block is separated multiplex machine 100 and is received block, and it is separated is multiplexed into the thin piece of two (even number and odd number) group i.At this, the data of respectively organizing of i thin piece can be delivered to indivedual each i P/S device 102,104 of organizing.Promptly as shown in figure 17, one group odd number P/S device 102 can have i P/S device, and this can have its clock signal signal that is inverted through the device 118 that is inverted.Therefore, the clock signal signal through being inverted can be half clock signal period that postpones through with respect to this clock signal of system.One group of i MUX 106 can select by doubling this bit rate clock signal between this group even number P/S device 104 and this group odd number P/S device 102.Result (resulting) data that transmit on each connects can be the bit rate clock signals of twice.The other end in each connection is a corresponding DEMUX 108.These DEMUX108 can press the twice bit rate clock signal sequentially, and each bar circuit 44 is couple to an even number 112 and odd number 110 impact dampers.Each impact damper 112,110 receives a corresponding even number and odd number bit, and grips complete clock signal period of this numerical value.One even number 116 can restore described even number and the thin piece of odd number with the S/P device of 114 groups of odd numbers.One data block reconstruction device 122 can pass thin piece from each and rebuild this block.
Figure 18 illustrates utilization, and this is just reaching the negative clock signal edge, the data transfer operations of carrying out on a system line.The icon person waits to give even data and the odd data that transmits on circuit 1.Wedge (hatching) part is represented the negative clock signal edge in the combined signal, does not have the wedge part and then represents positive person.Promptly as icon, data transfer rate can double.
Figure 19 one is used for the preferable realization of hybrid parallel/serial line interface between a GC controller 38 and the GC124.One block similarly is 16 a GC control data (8 RX and 8 TX), can be sent to a block from this GC controller 38 and separate multiplex machine 40.This block can be separated multiplexed two the thin pieces that become, and similarly is two 8 thin pieces.Can increase attached position at the beginning to each thin piece, be 9 of each thin pieces such as order.At this, can utilize two P/S converters 42 on two circuits, to transmit these two thin pieces.When detecting the start bit, S/P converter 46 the thin piece of receive will be converted to parallel form.This data block reconstruction device can be rebuild original 16 gains with control GC124.Explain out a function as the start bit, promptly as shown in figure 11, this AGC124 can be before adjusting gain, earlier to this function of receipts onblock executing.
Figure 20 is in another preferable realization of a hybrid parallel/serial bus converter, and this is to be positioned between GC controller 38 and a RX GC30 and TX GC32, and utilizes three (3) bar circuits.This GC controller 38 can promptly as shown in figure 14, be sent a block and give this GC30,32 by suitable RX and TX yield value and start bit.As the start bit that Figure 14 is pressed in true employing, device 1 is TX GC32 for RX GC30 installs 2.This block is separated multiplex machine 40 can separate multiplexed three the thin pieces that become with this block, transmits for seeing through this three-line.Utilize three P/S converters 42 and three S/P conversions 46, each thin piece can be transmitted on each circuit serially, and converts the primary fine piece to.This data block reconstruction device 48 can be rebuild original data block, and carries out as the described function in start bit, similarly is relative increase, minimizing and absolute value relatively.The data that obtain can be sent to as described RX in start bit or TX GC30,32.
Claims (37)
1. hybrid parallel/serial bus interface that is used for the base station wherein comprises:
One block is separated multiplex machine, has once configuration settings receiving the input of a block, and this block can be separated and be multiplexed into a plurality of thin pieces, and each thin piece has a plurality of positions;
For each thin piece:
Walk to serial convertor in the lump, converting serial data to by thin piece;
One circuit can transmit this thin piece serial data; And
Parallel converters is changeed in one serial, to change this thin piece serial data to restore this thin piece; And
One data block reconstruction device is restored thin piece and is merged into this block each.
2. hybrid parallel/serial bus interface as claimed in claim 1 is characterized in that, the bits number in block is N, and number of lines is i, and 1＜i＜N.
3. hybrid parallel/serial bus interface as claimed in claim 1 is characterized in that, the bits number in a thin piece is four, and number of lines is two.
4. hybrid parallel/serial bus interface that is used for the base station wherein comprises:
One device has an input, is configured setting and is multiplexed into a plurality of thin pieces to receive a block so that this block is separated, and each thin piece has a plurality of positions;
For each thin piece:
Be used for will this thin piece converting to the device of serial data;
Be used to transmit the circuit of this thin piece serial data; And
Be used to change this thin piece serial data to restore the device of this thin piece; And
Be used for each is restored the device that thin piece is merged into this block.
5. hybrid parallel/serial bus interface as claimed in claim 4 is characterized in that, the bits number in block is N, and number of lines is i, and 1＜i＜N.
6. hybrid parallel/serial bus interface as claimed in claim 4 is characterized in that, the bits number in a thin piece is four, and number of lines is two.
7. tool hybrid parallel/serial bus interface is used for data are sent to the base station of a Section Point from a first node, and wherein this interface comprises:
One block is separated multiplex machine, this block is separated common n the position that is multiplexed into the m group from this first node, and in these m group each increased attached position at the beginning, these m start bit can be represented a specific mathematical function or the destination that will carry out altogether with collecting;
To in these m group each, one is sent to the split circuit of this Section Point in order to this person with described m group from this first node;
One data block reconstruction device is used to receive described m group, is merged into this block so that described m is organized, and utilizes the described m group of receiving according to m start bit.
8. tool hybrid parallel/serial bus interface as claimed in claim 7, it is characterized in that, when transmitting data, this block separate multiplex machine can with these m start bit at least one be set at 1 state, and when this interface did not transmit data, can keep all split circuits was 0 state.
9. tool hybrid parallel/serial bus interface as claimed in claim 7 is characterized in that these m start bit representative beginning one data transfer operations.
10. tool hybrid parallel/serial bus interface as claimed in claim 7 is characterized in that, these m start bit represents one to wait to give the specific mathematical function of execution but not a destination altogether with collecting.
11. tool hybrid parallel/serial bus interface as claimed in claim 7 is characterized in that, these m start bit represents one to comprise that an increase relatively, reduces and an ABS function relatively altogether with collecting.
12. tool hybrid parallel/serial bus interface as claimed in claim 7 is characterized in that, these m start bit is represented specific purpose ground altogether with collecting but not one is waited to give the mathematical function of execution.
13. tool hybrid parallel/serial bus interface as claimed in claim 12 is characterized in that, these m start bit is represented altogether with collecting and is comprised that one receives and transmit gain controller.
14. tool hybrid parallel/serial bus interface as claimed in claim 7 is characterized in that, these m start bit represent altogether with collecting one wait to give the specific mathematical function of execution and specific purpose ground both.
15. a tool hybrid parallel/serial bus interface is used for data are sent to the base station of a Section Point from a first node, wherein this interface comprises:
Be used for block is separated the device of common n the position that is multiplexed into the m group;
Be used for that these m are organized each person and increase the device that these m start bit, attached position at the beginning can be represented a specific mathematical function or destination altogether with collecting;
Be used for seeing through individual line, transmit each device the described m group from this first node;
Be used for receiving the m that passes of institute organizes the device of each at this Section Point place; And
Be used for utilizing the described device of receiving the m group according to m start bit.
16. tool hybrid parallel/serial bus interface as claimed in claim 15 is characterized in that, this increase attaching put can with m start bit at least one be set at 1 state, and when this interface did not transmit data, all individual line can be 0 state.
17. tool hybrid parallel/serial bus interface as claimed in claim 15 is characterized in that, these m start bit representative beginning one data transfer operations.
18. tool hybrid parallel/serial bus interface as claimed in claim 15 is characterized in that, these m start bit represents one to wait to give the specific mathematical function of execution but not a destination altogether with collecting.
19. tool hybrid parallel/serial bus interface as claimed in claim 15 is characterized in that, these m start bit represents one to comprise that an increase relatively, reduces and an ABS function relatively altogether with collecting.
20. tool hybrid parallel/serial bus interface as claimed in claim 15 is characterized in that, these m start bit is represented specific purpose ground altogether with collecting but not one is waited to give the mathematical function of execution.
21. tool hybrid parallel/serial bus interface as claimed in claim 20 is characterized in that, these m start bit is represented altogether with collecting and is comprised that one receives and transmit gain controller.
22. tool hybrid parallel/serial bus interface as claimed in claim 15 is characterized in that, these m start bit is represented a specific mathematical function and a specific purpose ground of waiting to give execution altogether with collecting.
23. tool hybrid parallel/serial bus interface as claimed in claim 15 more comprises a kind of gain control system that is used for this base station, wherein comprises:
One gain controller is represented the block of the n position of a yield value to produce a tool;
I bar circuit, this block is sent to a gain control from this gain controller, 1＜i＜n wherein; And
This gain control is used to receive this block, and utilizes the yield value of this block to adjust the yield value of this gain control.
24. tool hybrid parallel/serial bus interface as claimed in claim 23 wherein further comprises:
One block is separated multiplex machine, is multiplexed into a plurality of thin pieces so that this block is separated, and each thin piece is for transmitting on the different circuits of i bar circuit; And
One data block reconstruction device is to be merged into this block with each thin piece.
25. tool hybrid parallel/serial bus interface as claimed in claim 24 is characterized in that, additional position at the beginning is to each thin piece.
26. tool hybrid parallel/serial bus interface as claimed in claim 25 is characterized in that, a mathematical function of waiting to give execution can be explained in this start bit.
27. tool hybrid parallel/serial bus interface as claimed in claim 26 is characterized in that, the mathematical function of being explained by this start bit comprises that an increase relatively, reduces and an ABS function relatively.
28. tool hybrid parallel/serial bus interface as claimed in claim 25 is characterized in that, this gain control comprises that receiving gain control and one transmits gain control, and the explanation of described start bit needs this block is delivered to receiving gain control or transmitted gain control.
29. a base station hybrid parallel/serial bus interface that is used for synchro system, this synchro system have a relevant clock signal, this base station hybrid parallel/serial bus interface comprises:
One block is separated multiplex machine, has an input, is configured setting receiving a block, and this block separated is multiplexed into a plurality of thin pieces, and each thin piece has a plurality of positions;
An one even number even number and an odd number group and walk to serial convertor, each group and walk to each thin piece that serial convertor can receive the bit rate clock signal that is synchronized with this clock signal, and become serial datum to change each thin piece;
One first group of i multiplexer, with on i bar circuit, positive edge in this clock signal transmits even number and walks to serial convertor group serial data, and on i bar circuit, transmits odd number and walks to serial convertor group serial data in the negative edge of this clock signal;
One second group of i demultiplexer receiving the serial data that passed of even number even number and odd number, and is sent the even number serial data that is received to an even number impact damper, and the odd number serial data is sent to an odd number impact damper;
One even number and odd number group be serial to parallel converters, the parallel converters that is serial to of this even number set is for the even number serial data that will be received converts the even number parallel data to, and exports this even number parallel data by being synchronized with this clock signal;
This odd number group be serial to parallel converters, convert the odd number parallel data to the odd number serial data that will be received, and export this odd number parallel data by being synchronized with this clock signal, and
One data block reconstruction device is to merge into this block with this even number and odd number parallel data.
30. base station as claimed in claim 29 hybrid parallel/serial bus interface is characterized in that, each block has N position, and
31. base station as claimed in claim 29 hybrid parallel/serial bus interface, it is characterized in that, this even number and this even number of odd number impact damper available buffer and odd number group and walk to serial convertor input, receive and be synchronized with the even number of this clock signal and serial data that odd number is received with the parallel converters that is serial to that makes this even number and odd number group.
32. a reversible parallel/serial bus interface that is utilized by a base station wherein comprises:
Many circuits, to transmit block, described many number of lines are lower than the figure place of each block;
One first node, can on described many circuits, block be sent to a Section Point, this first node can be separated described block and be multiplexed into a plurality of first thin piece, and the number of a plurality of first thin piece can be identical with described many circuits, and each thin piece has a plurality of positions; And
This Section Point is sent second block to this first node on described many circuits, this Section Point can be separated described block and be multiplexed into a plurality of second thin piece, the number of the described a plurality of second thin piece can be identical with described many circuits, and each thin piece has a plurality of positions.
33. reversible parallel/serial bus interface as claimed in claim 32, it is characterized in that, this first node can be separated described block and be multiplexed into a plurality of the 3rd thin piece, the number j of the described the 3rd thin piece can be lower than the number N of many circuits, and transmits the described the 3rd thin piece on j bar circuit.
34. reversible parallel/serial bus interface as claimed in claim 33, it is characterized in that, this Section Point each the 4th block can be separated be multiplexed into K the position, in this K value smaller or equal to N-j bar number of lines, and on K bar circuit the transmission the 4th block.
35. reversible parallel/serial bus interface as claimed in claim 32 is characterized in that, this first node block comprises gain controlling information.
36. reversible parallel/serial bus interface as claimed in claim 35 is characterized in that, this Section Point block comprises a gain controlling information confirmation of receipt.
37. reversible parallel/serial bus interface as claimed in claim 35 is characterized in that, this Section Point block comprises a status information that is relevant to this Section Point.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/990,060 US7069464B2 (en) | 2001-11-21 | 2001-11-21 | Hybrid parallel/serial bus interface |
| US09/990,060 | 2001-11-21 | ||
| US10/081,466 | 2002-02-22 | ||
| US10/081,466 US6829718B2 (en) | 2001-11-21 | 2002-02-22 | Base station having a hybrid parallel/serial bus interface |
| PCT/US2002/037150 WO2003046391A2 (en) | 2001-11-21 | 2002-11-19 | Base station having a hybrid parallel/serial bus interface |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2007101423323A Division CN101106505A (en) | 2001-11-21 | 2002-11-19 | Base station having a hybrid parallel/serial bus interface |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1610891A CN1610891A (en) | 2005-04-27 |
| CN1332328C true CN1332328C (en) | 2007-08-15 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB02823118XA Expired - Fee Related CN1332328C (en) | 2001-11-21 | 2002-11-19 | Base station having a hybrid parallel/serial bus interface |
Country Status (13)
| Country | Link |
|---|---|
| EP (1) | EP1446584B1 (en) |
| JP (2) | JP4142584B2 (en) |
| CN (1) | CN1332328C (en) |
| AT (1) | ATE367681T1 (en) |
| AU (1) | AU2002352801A1 (en) |
| CA (1) | CA2467632A1 (en) |
| DE (1) | DE60221270T2 (en) |
| ES (1) | ES2287345T3 (en) |
| HK (1) | HK1073701A1 (en) |
| MX (1) | MXPA04004790A (en) |
| NO (1) | NO20042541L (en) |
| TW (1) | TWI267274B (en) |
| WO (1) | WO2003046391A2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4546416B2 (en) * | 2006-04-24 | 2010-09-15 | ザインエレクトロニクス株式会社 | Image signal receiver |
| CN105242591B (en) * | 2015-08-17 | 2017-12-12 | 合肥宝龙达信息技术有限公司 | A kind of input/output interface combination system |
| CN108736897B (en) * | 2018-04-26 | 2022-08-09 | 深圳市国微电子有限公司 | Parallel-serial conversion circuit and device applied to high-speed interface physical layer chip |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5602780A (en) * | 1993-10-20 | 1997-02-11 | Texas Instruments Incorporated | Serial to parallel and parallel to serial architecture for a RAM based FIFO memory |
| CN1158070A (en) * | 1995-12-08 | 1997-08-27 | 三星电子株式会社 | Apparatus for embodying combined time switching and conference calling functions |
| US6122683A (en) * | 1997-04-10 | 2000-09-19 | International Business Machines Corp. | Handshake minimizing serial-to-parallel interface with shift register coupled by parallel bus to address logic and control logic |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2822815B2 (en) * | 1992-09-30 | 1998-11-11 | 日本電気株式会社 | Signal transmission method between base stations |
| JP2001136156A (en) * | 1999-11-08 | 2001-05-18 | Toshiba Digital Media Engineering Corp | Data transmission speed conversion circuit |
-
2002
- 2002-11-19 CN CNB02823118XA patent/CN1332328C/en not_active Expired - Fee Related
- 2002-11-19 EP EP02789755A patent/EP1446584B1/en not_active Expired - Lifetime
- 2002-11-19 WO PCT/US2002/037150 patent/WO2003046391A2/en active IP Right Grant
- 2002-11-19 DE DE60221270T patent/DE60221270T2/en not_active Expired - Lifetime
- 2002-11-19 CA CA002467632A patent/CA2467632A1/en not_active Abandoned
- 2002-11-19 MX MXPA04004790A patent/MXPA04004790A/en active IP Right Grant
- 2002-11-19 ES ES02789755T patent/ES2287345T3/en not_active Expired - Lifetime
- 2002-11-19 AT AT02789755T patent/ATE367681T1/en not_active IP Right Cessation
- 2002-11-19 AU AU2002352801A patent/AU2002352801A1/en not_active Abandoned
- 2002-11-19 JP JP2003547802A patent/JP4142584B2/en not_active Expired - Fee Related
- 2002-11-21 TW TW091134139A patent/TWI267274B/en not_active IP Right Cessation
-
2004
- 2004-06-17 NO NO20042541A patent/NO20042541L/en not_active Application Discontinuation
-
2005
- 2005-06-17 HK HK05105071A patent/HK1073701A1/en not_active IP Right Cessation
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2007
- 2007-09-19 JP JP2007243104A patent/JP2008011577A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5602780A (en) * | 1993-10-20 | 1997-02-11 | Texas Instruments Incorporated | Serial to parallel and parallel to serial architecture for a RAM based FIFO memory |
| CN1158070A (en) * | 1995-12-08 | 1997-08-27 | 三星电子株式会社 | Apparatus for embodying combined time switching and conference calling functions |
| US6122683A (en) * | 1997-04-10 | 2000-09-19 | International Business Machines Corp. | Handshake minimizing serial-to-parallel interface with shift register coupled by parallel bus to address logic and control logic |
Also Published As
| Publication number | Publication date |
|---|---|
| EP1446584B1 (en) | 2007-07-18 |
| CN1610891A (en) | 2005-04-27 |
| EP1446584A4 (en) | 2005-05-11 |
| JP2008011577A (en) | 2008-01-17 |
| ES2287345T3 (en) | 2007-12-16 |
| TW200303673A (en) | 2003-09-01 |
| AU2002352801A8 (en) | 2003-06-10 |
| DE60221270T2 (en) | 2008-04-10 |
| MXPA04004790A (en) | 2004-08-11 |
| CA2467632A1 (en) | 2003-06-05 |
| WO2003046391A3 (en) | 2003-10-09 |
| NO20042541L (en) | 2004-07-26 |
| HK1073701A1 (en) | 2005-10-14 |
| JP2005510915A (en) | 2005-04-21 |
| EP1446584A2 (en) | 2004-08-18 |
| JP4142584B2 (en) | 2008-09-03 |
| TWI267274B (en) | 2006-11-21 |
| ATE367681T1 (en) | 2007-08-15 |
| DE60221270D1 (en) | 2007-08-30 |
| AU2002352801A1 (en) | 2003-06-10 |
| WO2003046391A2 (en) | 2003-06-05 |
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