TWI239742B - Method employed by a user equipment (UE) for transferring data and base station/user equipment having a hybrid parallel/serial bus interface - Google Patents

Abstract

A hybrid serial/parallel bus interface method for a user equipment (UE) has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter converts the nibble into serial data. A line transfers each nibble's serial data. A serial to parallel converter converts each nibble's serial data to recover that nibble. A data block reconstruction device combines the recovered nibbles into the data block.

Description

1239742 玖 玖, invention description (the description of the invention should state: the technical field to which the invention belongs, the prior art, the content, the embodiments, and the drawings are briefly explained) TECHNICAL FIELD The present invention relates to bus data transmission. In particular, the present invention is to reduce the number of lines for transmitting bus data. Prior art The one shown in Figure 1 is an example of a bus for transmitting data. Figure 1 shows a Receive and Transmit Gain Controller (GC) for a wireless communication system 30

, 32, and a GC controller 38 are illustrated. A communication station, such as a base station or user equipment, transmits (TX) and receives (RX) signals. In order to control the gain of these signals, falling within the operating range of other receiving / transmitting components, the GC 30 and 32 will adjust the gain on the RX and TX signals.

To control the gain parameters of the GCs 30, 32, a GC controller 38 is used. That is, as shown in FIG. 1, the GC controller 38 uses a power control bus, such as 16 line buses 34 and 36 to send out the gain values of the TX 36 and RX 34 signals, as if each is eight lines. . Although the power control bus lines 34 and 36 can be used to allow fast data transmission, this will require many pins on the GC 30, 32 and the GC controller 38, or an integrated circuit like a dedicated integrated circuit (ASIC) (1C) Many connections between GC 30, 32 and GC controller 38. Increasing the number of pins will require additional board space and wiring. Adding 1C connections will take up precious 1C space. A large number of pins or connections may increase the cost of the bus depending on the implementation. Therefore, it is desirable to have other data transmission methods. SUMMARY OF THE INVENTION 1239742 (2) Description of the Invention Continued A hybrid bucket / serial bus interface has a data block demultiplexing device. The data block demultiplexing device has an input, which is configured to receive a data block, and demultiplexes the data block into a plurality of fine blocks. For each block, a parallel-to-serial converter converts the block into serial data. A line can transmit each column of data. A serial-to-parallel converter can convert the rate data of each block to recover the block. The data block reconstruction device can merge the restored fine blocks into the data block. A base station (or user equipment) has a gain control controller. The gain control controller generates a block of data having n bits representing a gain value. A data block demultiplexing device has an input, which is configured to receive the data block and demultiplex the data block into a plurality of fine blocks. Each fine block has a plurality of bits. For each fine block, a parallel-to-serial converter can convert the fine-block to serial data, a line transmits the fine-block serial data 'and a serial-to-parallel converter can convert the fine-block serial data to Restore the thin piece. A data block reconstruction device may merge the restored fine blocks into the data block. A gain controller receives the data block and uses the gain value of the data block to adjust its gain. The embodiment shown in FIG. 2 is a block diagram of a hybrid parallel / serial bus interface, and FIG. 3 is a flowchart of data transmission operation of the hybrid parallel / serial bus interface. A block of material is transmitted across the interface from node 1 50 to node 2 52 (54). A data block demultiplexing device 40 receives the block and demultiplexes it into one "field block" to facilitate transmission on i data transmission lines 44 (56). The value i is based on the number of connections It depends on the trade-off between transmission speed. — A decision i 1239742 Invention description Continue to buy 1_ Discuss__1__ Follow 1 Lai ___ 1 Brewing I Accept the maximum (3) value is to first determine a data area The block delay. According to this maximum delay, the minimum number of lines required to transmit the block can be determined. Using the minimum number of lines, the line used to transmit data will be selected to at least the minimum amount. Line 44 can be Pins and their related connections on a circuit board or on a 1C connection. A method of demultiplexing into fine blocks. Blocks are cut into one of the most significant to the least significant. This is illustrated in Figure 4 ' An eight-bit block is transmitted on the two lines, and the block will be resolved into the most significant four-bit block and the smallest four-bit block. Another way is to cross the block by mistake. i pieces. The W 1 bit of this block will become the first place of each i pieces The next i bits will be written into the second bit of each small piece, and so on until the last i bit is the eighth bit on the rain bar line as shown in Figure 5 Metablock, the first bit will be mapped to the first bit of block 1. The second bit will be mapped to the _ bit of block 2. The third bit will be mapped 7L 'to the second bit of the fine block j is continued until the last bit is mapped to the last bit of the fine block 2. Each fine block will be sent to the solid parallel transposed string (p / s Correspondence of converter 42 (5 8) 'converts from parallel bits to serial bits and transmits them in series on the line in sequence (60). On the opposite side of each line there will be a series of transfers Parallel (S / P) converter M. Each S / P converter 46 converts the transmitted event data into its original block (62). The i-th restored block is reconstructed by a data block 48 Processing to reconstruct the original data block (64). | On the other hand, two-way and ten-way, will use 丨 connection to send data in two-way way, as shown in Figure 6. You can send information data in two-way, or Caibu 1239742 (4) The description of the township f sends information in one direction and returns a confirmation signal in the other direction. Here, a data block demultiplexing and reconstruction device 66 will receive a transmission from node 5 to node 2 52 data blocks. The demultiplexing and reconstruction device "demultiplexes this block into i fine blocks. The i P / s converters 68 convert each of the fine blocks into the listed data, and the MUX / DEMUX 71 couples each P / S converter 68 to a corresponding one of the i lines 44. At node 2 52, another group of multiplexers MUX / DEMUX 75 connects line 44 to a group of S / P converters 72. The set of s / p converters 72 converts the received and listed data of each block into the original transmitted block. The received fine blocks will be demultiplexed and reconstructed by a data block to reconstruct the original data block and output it as the received data block. For each block transmitted from node 2 52 to node 50, the data block demultiplexing and reconstruction device 76 receives a data block. The block is demultiplexed into fine blocks and each fine block is transmitted to a set of p / s converters 74. The P / S converter 74 converts the various blocks into a serial format for transmission across the line 44. Μυχ / Ε > ΕΜυχ in node 2 group will connect these p / s converters to one line 44, and mux / DE in node 1 group] VIuX 71 will couple line 44 to i S / P Converter 70. The s / p converters 70 transform the transmitted data into its original fines. The data block demultiplexing and reconstruction device 66 reconstructs a data block from the received fine blocks to output the received data blocks. Since the data is transmitted in one direction at a time, this implementation can operate in half-duplex mode. FIG. 7 is a simplified implementation diagram of a bidirectional switching circuit. The serial output of the node 1 p / s converter 68 is input to a tri-state buffer 78. The buffer has another input, which is coupled to a voltage indicating a high state. The 1239742 invention description page will be sent (6)

Timing of components. Bits used to represent the beginning of the data block transfer operation. That is, as shown in Figure 8, each line will be at its normal zero level. A start bit is sent to indicate the start of the block transfer operation. In this example, all lines will send the start bit, but it is only necessary to send the start bit on one line. If the start bit is sent on any line, such as a value of 1, the receiving node will clearly start the block data transmission operation. Here, each _column block will be sent through its corresponding line. After transmitting each block, the line returns to their normal state, as if they were all low.

In other implementations, the start bit is also used as the indicator of the function to be executed. This implementation can be illustrated in Figure 9. As shown in FIG. 10, if the first bit of any connection is 1, the receiving node will know the block data to be transmitted. That is, as shown in the table implemented by the GC controller in FIG. 11, three start bit combinations are used: 01, 10, and 11.00 to indicate that no start bit has been sent. Each combination represents a function. In this example, 01 indicates that a relative reduction function should be performed, such as reducing the data block value by one. 10 indicates that a relative increase function should be performed, such as increasing the value of the data block by 1. 11 means that an absolute value function should be executed, and the block will maintain the same value at this time. To increase the number of available functions, additional bits can be used, for example, two start bit maps per line can be reached to seven (7) term functions, or n start bit maps of i lines can be reached in + 1-l functions. The processing device 86 executes a function on the received data block as described in the start bit. In another implementation shown in Fig. 12, the start bit indicates a destination device. That is, as shown in FIG. 13, this is an implementation of two destination devices / two lines. The combination of the start bit will be associated with the destination device for the transmitted data block-11-1239742 _ (7) IInvention Continued 8 8-92. 01 means device 1; 10 means device 2; and 11 means device 3. After receiving the start bit of the data block reconstruction device 48, the reconstructed block will be sent to the corresponding devices 88-92. To increase the number of potential destination devices, additional start bits can be utilized. For n start bits on each of the i lines, up to in + 1-1 devices can be selected.

That is, as shown in FIG. 14, the start bit can be used to represent both the function and the destination device. Figure 14 shows a three-wire system with two devices like RX and TX GC. Using the start bit on each line, three functions of the two devices are plotted in the figure. In this example, the start bit of line 1 represents the target device, "0" is device 1, and "1" is device 2. Bits 2 and 3 represent the function being executed. "11" represents an absolute value function; "10" represents a relative increase function; and "01" represents a relative decrease function. All three start bits are zero, meaning "000", which will be a normal non-data transfer state, and "001" is not used here. Additional bits can be utilized to add more functions or devices. For n starting bits on each i line, up to in + function / device combinations can be selected. Fig. 15 is a system block diagram showing the start bits of both the function and the destination device. The restored fine blocks are received by the data block reconstruction device 48. Based on the received start bit, the processing device 86 executes the function and sends the processed block to the destination devices 88-92. That is, as shown in the flowchart of Fig. 16, the start bit indicating the function / destination is added to each of the fine blocks (94). Here, these fine pieces will be sent out through this i line (96). With the start bit, the appropriate function is performed on the data block, and the data block is sent to the appropriate destination or both (98). -12- 1239742 ”Invention 讹 Continued page To increase the throughput in the synchronization system, it will use both the positive (double) and negative (single) edges of the clock to transfer block data. One implementation can be shown in Figure 17 '. The data block demultiplexing device 100 receives the data block and demultiplexes it into two (double and single) groups i fine blocks. Here, each group of the lake fine block will be demultiplexed. The data is sent to i P / S devices 102 and 104 of each group. As shown in FIG. 17, a single P / S device 10 of a group will have i P / s devices, which will have its own The inverted clock signal of the inverter 118. Therefore, the inverted clock signal will be a half clock period delayed with respect to the clock of the system. A group of Μυχ 1〇6 will be at The group of dual P / S devices 104 and the group of single p / s devices 102 are selected at twice the clock rate. The yield data transmitted on each connection will be twice as high. Pulse rate. At the other end of each connection is a corresponding DEMUX 108. These DEMUX 108 will sequentially couple each line 44 to a pair of 112 and single 11 buffers at twice the clock rate. Each Buffer 11 2. 110 receives a corresponding double and single element, and holds the value for a complete clock cycle. A double 116 and single 114 S / P device will restore the double and single fine blocks. A data block The reconstruction device 122 reconstructs the data block from each transmitted fine block. Figure 18 illustrates the data transfer operation performed on a system line using the positive and negative clock edges. The icon is to be transmitted on line 1. Dual data and single data. The oblique wedge part indicates the negative clock edge in the merged signal and the non- oblique wedge part indicates the positive one. That is, as shown in the figure, the data transfer rate will double. A hybrid parallel / serial interface between the GC controller 38 and a GC 124 is better implemented. A block of data, such as a 16-bit GC support-13- (9) 1239742 Invention Description Continued < 3 8 to a piece of data (8-bit RX and 8-bit TX), will be demultiplexed from the Gc controller material block 40. The data block will be demultiplexed into two fine blocks, like Are two 8-bit tiles. A starting bit is added to each tile, such as 9 bits for each tile. Here, we will The two p / s converters 42 are used to transmit the two fine blocks on two lines. When the s / p converter 46 detects the start bit, the received fine blocks are converted into a parallel format. This data area The block reconstruction device reconstructs the original 16 bits to control the gain of the GC 124. If a function is expressed at the beginning, as shown in Figure u, the AGC 124 will 'execute this item on the received block before adjusting the gain. Figure 20 is another preferred implementation of a hybrid parallel / serial bus converter. 'This system is located between the GC controller 38 and an rx GC 30 and TX GC 32, and uses three (3) lines. The GC controller 38 sends a data block to the Gc 30, 32 according to the appropriate RX and TX gain values and start bits, as shown in FIG. If the start bit according to Fig. 14 is indeed used, device 1 is KK gc 30 and device 2 is TX GC 32. The data block demultiplexing device 40 demultiplexes the data block into three fine blocks for transmission through the three lines. With three P / S converters 42 and three S / P converters 46, each fine block is transmitted in series on each line and converted into the original fine block. The data block reconstruction device 48 reconstructs the original data block 'and performs functions as described in the start bit, such as relative increase, relative decrease, and absolute value. The obtained data will be sent to RX or TX GC 30, 32 as described in the start bit. Schematic description Figure 1 is a schematic illustration of the RX and TX GC and GC controllers. Figure 2 is a block diagram of a hybrid parallel / serial bus interface. -14- 1239742 (10) Description page of the invention Figure 3 is a flow chart of the data block transfer operation using the hybrid parallel / serial bus interface. Figure 4 illustrates a demultiplexing operation that converts a block into the most significant and smallest significant fine blocks. FIG. 5 illustrates the demultiplexing operation of a block using data interleaving. Figure 6 is a block diagram of a bidirectional hybrid parallel / serial bus interface. FIG. 7 is a schematic diagram of a bidirectional line implementation.

FIG. 8 is a timing chart of a start bit. Figure 9 is a block diagram of a hybrid parallel / serial bus interface with function controllability. Figure 10 is a timing diagram of the start bit of a hybrid parallel / serial bus interface with function controllability. FIG. 11 shows a list of implementations of the start bits of each function. Figure 12 is a block diagram of the destination control hybrid parallel / serial bus interface. FIG. 13 shows a start bit implementation list of each destination.

FIG. 14 shows a start bit implementation list of each destination / function. Figure 15 is a block diagram of the destination / function control hybrid parallel / serial bus interface. FIG. 16 is a flowchart showing the start bit of each destination / function. Figure 17 is a block diagram of a mixed parallel / serial bus interface area with positive and negative clock edges. Fig. 18 Timing chart of mixed parallel / serial bus interface with positive and negative clock edges. Figure 19 is a block diagram of a 2-wire GC / GC controller bus. -15-1239742 Figure 30 32 34 36 38 40 42 44 46 48 50 52 66 68 70 72 74 76 78 80 82 84 (11) 20 series 3-wire GC / GC controller bus block diagram diagram representative symbol Description Receive Gain Controller Transmit Gain Controller Line Bus Line Bus GC Controller Data Block Demultiplexing Device Parallel to Serial (P / S) Converter Data Transmission Line Serial to Parallel (S / P) Converter Data Block Reconstruction Device Node 1 Node 2 Data Block Demultiplexing and Reconstruction Device Parallel to Serial (P / S) Converter Serial to Parallel (S / P) Converter Serial to Parallel (S / P) Conversion Device parallel to serial (p / s) converter data block demultiplexing and reconstruction device buffer buffer buffer buffer invention description Continued -16-1239742 (12) 85 line 86 resistance 88 destination device 90 purpose Local device 92 Destination device 100 Data block demultiplexing device 102 Single P / S device 104 Double P / S device 106 Multiplexer 108 Demultiplexer 110 Buffer 112 Buffer 114 Single P / S device 116 Dual P / S device 122 Data block reconstruction device 124 Gain controller Invented: Achievements page

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Claims (1)

1239742 Pick up and apply for patent scope 1. A method for transmitting data by a user equipment (UE), including: providing a data block; demultiplexing the data block into a plurality of fine blocks, each fine block having a plurality of bits; for each fine block Piece: Convert the fine block into _row data; provide a line 'and transmit the fine block serial data on the line; convert the fine block serial data into parallel data, and restore the fine block, and restore each fine block The blocks are merged into this data block. 2. The method according to item 1 of the patent application range, wherein the number of bits in the data block is N, the number of lines is i, and l < i < N. - 3. For the method of applying for item 1 of the patent scope, wherein the number of bits in a fine block is four and the number of lines is two. 4. A method for transmitting data blocks by a user equipment (UE) through an interface connecting a first node to a second node, wherein the method includes: demultiplexing the data blocks into m groups η Add a start bit to these m groups, these m start bits can collectively represent a specific mathematical function or destination; on individual lines, each of these m groups is transmitted from the first node Receive the transmitted m groups at the second node; and 1239742 request Qin Kexing to use the received m groups based on these m start bits. 5. For example, in the method of applying for the fourth item of the patent scope, at least one of these m start bits will be in the 1 state, and when the interface does not transmit data, all individual lines will be in the 0 state. 6. For example, the method in the fourth scope of the patent application, wherein these m start bits represent the start of a data transfer operation. 7. For example, the method of claim 4 in which the m start bits collectively represent a specific mathematical function rather than a destination. 8. For example, the method of claim 4 in the patent application range, wherein the m start bits collectively represent a function including a relative increase, a relative decrease, and an absolute value function. 9. For example, the method of claim 4 in which the m start bits collectively represent a specific destination rather than a mathematical function. 10. The method of claim 9 in which the m starting bits collectively represent a RX and TX gain controller. 11. The method according to item 4 of the scope of patent application, wherein the m start bits collectively represent a specific mathematical function and a specific destination. 12. — A method used by a user equipment (UE) to determine the number of i bus connections required to transmit block data on a bus, each block of such block data has N bits The method includes: determining the maximum delay that can be tolerated for transmitting the data blocks; determining the maximum number of connections required to transmit the data blocks according to the maximum delay; and determining the value of i, and i is at least the minimum number of required connections. Apply for the special page to read the page where the i bus line 1239742 13, if the method of applying for the scope of the patent No. 12 will correspond to 丨 pins on a chip. Mβ is the same as 1 < 1 < N 15 in the method 9 of item 13 of the patent application scope. A method used by a user device, which includes: * betting * a data block 'the data area is controlled by a gain control (GC) to generate "the village block has n bits representing a gain value' via i lines To control the data block from the GC to transport to Shen, where l < i <n; receive the data block at the GC; and use the gain value of the data block to adjust the GC gain. 16 The method according to item I5 of the scope of patent application, further comprising: before transmitting the data, demultiplexing the data block into a plurality of fine blocks, each fine block being on a different line of the i line Transmit; and after receiving the data block, combine the small blocks into the data block. K is the method of the 16th scope of the patent application, in which the first block is added to each small block. 18. For example, the method of claim 17 of the patent scope, wherein the start bit can represent a mathematical function to be executed. 19. The method of claim 18 of the patent application park, wherein the mathematical function expressed by the start bit includes A relative increase, a relative decrease And an absolute value function. 20. The method according to Claim 15 patentable scope of which the one comprises the RX GC and a GC TxGC, and such start bit block to the instructions for an RXGC or TX GC 0