EP1446722A4 - Equipement utilisateur (ue) comprenant une interface de bus parallele/serie hybride - Google Patents

Equipement utilisateur (ue) comprenant une interface de bus parallele/serie hybride

Info

Publication number
EP1446722A4
EP1446722A4 EP02789726A EP02789726A EP1446722A4 EP 1446722 A4 EP1446722 A4 EP 1446722A4 EP 02789726 A EP02789726 A EP 02789726A EP 02789726 A EP02789726 A EP 02789726A EP 1446722 A4 EP1446722 A4 EP 1446722A4
Authority
EP
European Patent Office
Prior art keywords
serial
data block
nibble
user equipment
bus interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP02789726A
Other languages
German (de)
English (en)
Other versions
EP1446722A1 (fr
Inventor
Joseph Gredone
Alfred Stufflet
Timothy A Axness
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
InterDigital Technology Corp
Original Assignee
InterDigital Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/990,060 external-priority patent/US7069464B2/en
Application filed by InterDigital Technology Corp filed Critical InterDigital Technology Corp
Priority to EP05104800A priority Critical patent/EP1575173B1/fr
Priority to EP05104801A priority patent/EP1575174B1/fr
Publication of EP1446722A1 publication Critical patent/EP1446722A1/fr
Publication of EP1446722A4 publication Critical patent/EP1446722A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Dc Digital Transmission (AREA)
EP02789726A 2001-11-21 2002-11-18 Equipement utilisateur (ue) comprenant une interface de bus parallele/serie hybride Withdrawn EP1446722A4 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP05104800A EP1575173B1 (fr) 2001-11-21 2002-11-18 Equipement utilisateur (UE) comprenant une interface de bus parallèle/serie hybride
EP05104801A EP1575174B1 (fr) 2001-11-21 2002-11-18 Equipement utilisateur (UE) comprenant une interface de bus parallele/serie hybride

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US990060 2001-11-21
US09/990,060 US7069464B2 (en) 2001-11-21 2001-11-21 Hybrid parallel/serial bus interface
US10/080,899 US6823469B2 (en) 2001-11-21 2002-02-22 User equipment (UE) having a hybrid parallel/serial bus interface
US80899 2002-02-22
PCT/US2002/036954 WO2003046737A1 (fr) 2001-11-21 2002-11-18 Equipement utilisateur (ue) comprenant une interface de bus parallele/serie hybride

Related Child Applications (2)

Application Number Title Priority Date Filing Date
EP05104801A Division EP1575174B1 (fr) 2001-11-21 2002-11-18 Equipement utilisateur (UE) comprenant une interface de bus parallele/serie hybride
EP05104800A Division EP1575173B1 (fr) 2001-11-21 2002-11-18 Equipement utilisateur (UE) comprenant une interface de bus parallèle/serie hybride

Publications (2)

Publication Number Publication Date
EP1446722A1 EP1446722A1 (fr) 2004-08-18
EP1446722A4 true EP1446722A4 (fr) 2005-04-20

Family

ID=26764107

Family Applications (1)

Application Number Title Priority Date Filing Date
EP02789726A Withdrawn EP1446722A4 (fr) 2001-11-21 2002-11-18 Equipement utilisateur (ue) comprenant une interface de bus parallele/serie hybride

Country Status (12)

Country Link
EP (1) EP1446722A4 (fr)
JP (1) JP2005510800A (fr)
CN (1) CN100346327C (fr)
AT (2) ATE397323T1 (fr)
AU (1) AU2002352773A1 (fr)
CA (1) CA2467841C (fr)
DE (1) DE60226910D1 (fr)
HK (1) HK1069905A1 (fr)
MX (1) MXPA04004742A (fr)
NO (1) NO20042522L (fr)
TW (2) TWI260172B (fr)
WO (1) WO2003046737A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1321382C (zh) * 2004-01-20 2007-06-13 宏达国际电子股份有限公司 串行/并行数据转换模块及相关计算机系统
CN1329850C (zh) * 2004-01-20 2007-08-01 凌阳科技股份有限公司 多重路径总线资料传输方法及系统

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH056335A (ja) * 1991-06-27 1993-01-14 Nec Eng Ltd 装置間インタフエース方式
JPH05160819A (ja) * 1991-12-03 1993-06-25 Nec Eng Ltd データ転送装置
JPH05250316A (ja) * 1992-03-05 1993-09-28 Nec Eng Ltd 装置間インタフェース方式
US5602780A (en) * 1993-10-20 1997-02-11 Texas Instruments Incorporated Serial to parallel and parallel to serial architecture for a RAM based FIFO memory
US5768529A (en) * 1995-05-05 1998-06-16 Silicon Graphics, Inc. System and method for the synchronous transmission of data in a communication network utilizing a source clock signal to latch serial data into first registers and a handshake signal to latch parallel data into second registers
US5812881A (en) * 1997-04-10 1998-09-22 International Business Machines Corporation Handshake minimizing serial to parallel bus interface in a data processing system
US7069464B2 (en) * 2001-11-21 2006-06-27 Interdigital Technology Corporation Hybrid parallel/serial bus interface

Non-Patent Citations (7)

* Cited by examiner, † Cited by third party
Title
"3606 - Digitally Controlled Programmable Gain Instrumentation Amplifier", October 1983, BURR-BROWN CORPORATION, TUCSON, ARIZONA, USA, XP002317899 *
"DS90CR211/DS90CR212 21-Bit Channel Link", July 1997, NATIONAL SEMICONDUCTOR, SANTA CLARA, CALIFORNIA, USA, XP002306540 *
HUQ S B ET AL: "An Overview of LVDS Technology", July 1998, NATIONAL SEMICONDUCTOR, SANTA CLARA, CALIFORNIA, USA, XP002317898 *
KITANOWSKA S ET AL: "Bus LVDS with Virtex-E Devices", 26 July 2000, XILINX INC, SAN JOSE, CALIFORNIA, USA, XP002307032 *
MAC GETTIGAN E: "Eight Channel, One Clock, One Frame LVDS Transmitter/Receiver", 15 March 2001, XILINX INC, SAN JOSE, CALIFORNIA, USA, XP002317897 *
NOVAK T ET AL: "Channel Link - Moving and Shaping Information In Point-toPoint Applications", May 1996, NATIONAL SEMICONDUCTOR, SANTA CLARA, CALIFORNIA, USA, XP002306541 *
VON HERZEN B ET AL: "Multi-Channel 622 Mb/s LVDS Data Transfer for Virtex-E Devices", 6 January 2001, XILINX INC., SAN JOSE, CALIFORNIA, USA, XP002306542 *

Also Published As

Publication number Publication date
AU2002352773A1 (en) 2003-06-10
TWI285316B (en) 2007-08-11
CA2467841A1 (fr) 2003-06-05
DE60226910D1 (de) 2008-07-10
HK1069905A1 (en) 2005-06-03
MXPA04004742A (es) 2004-08-02
TWI260172B (en) 2006-08-11
CN100346327C (zh) 2007-10-31
CA2467841C (fr) 2008-05-13
ATE388525T1 (de) 2008-03-15
TW200419359A (en) 2004-10-01
JP2005510800A (ja) 2005-04-21
TW200402240A (en) 2004-02-01
EP1446722A1 (fr) 2004-08-18
CN1589437A (zh) 2005-03-02
WO2003046737A1 (fr) 2003-06-05
NO20042522L (no) 2004-06-16
ATE397323T1 (de) 2008-06-15

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