AU2002352773A1 - User equipment (ue) having a hybrid parallel/serial bus interface - Google Patents

User equipment (ue) having a hybrid parallel/serial bus interface

Info

Publication number
AU2002352773A1
AU2002352773A1 AU2002352773A AU2002352773A AU2002352773A1 AU 2002352773 A1 AU2002352773 A1 AU 2002352773A1 AU 2002352773 A AU2002352773 A AU 2002352773A AU 2002352773 A AU2002352773 A AU 2002352773A AU 2002352773 A1 AU2002352773 A1 AU 2002352773A1
Authority
AU
Australia
Prior art keywords
serial
data block
nibble
user equipment
bus interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002352773A
Other languages
English (en)
Inventor
Timothy A. Axness
Joseph Gredone
Alfred Stufflet
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
InterDigital Technology Corp
Original Assignee
InterDigital Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/990,060 external-priority patent/US7069464B2/en
Application filed by InterDigital Technology Corp filed Critical InterDigital Technology Corp
Publication of AU2002352773A1 publication Critical patent/AU2002352773A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Dc Digital Transmission (AREA)
AU2002352773A 2001-11-21 2002-11-18 User equipment (ue) having a hybrid parallel/serial bus interface Abandoned AU2002352773A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US09/990,060 2001-11-21
US09/990,060 US7069464B2 (en) 2001-11-21 2001-11-21 Hybrid parallel/serial bus interface
US10/080,899 2002-02-22
US10/080,899 US6823469B2 (en) 2001-11-21 2002-02-22 User equipment (UE) having a hybrid parallel/serial bus interface
PCT/US2002/036954 WO2003046737A1 (fr) 2001-11-21 2002-11-18 Equipement utilisateur (ue) comprenant une interface de bus parallele/serie hybride

Publications (1)

Publication Number Publication Date
AU2002352773A1 true AU2002352773A1 (en) 2003-06-10

Family

ID=26764107

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002352773A Abandoned AU2002352773A1 (en) 2001-11-21 2002-11-18 User equipment (ue) having a hybrid parallel/serial bus interface

Country Status (12)

Country Link
EP (1) EP1446722A4 (fr)
JP (1) JP2005510800A (fr)
CN (1) CN100346327C (fr)
AT (2) ATE397323T1 (fr)
AU (1) AU2002352773A1 (fr)
CA (1) CA2467841C (fr)
DE (1) DE60226910D1 (fr)
HK (1) HK1069905A1 (fr)
MX (1) MXPA04004742A (fr)
NO (1) NO20042522L (fr)
TW (2) TWI260172B (fr)
WO (1) WO2003046737A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1329850C (zh) * 2004-01-20 2007-08-01 凌阳科技股份有限公司 多重路径总线资料传输方法及系统
CN1321382C (zh) * 2004-01-20 2007-06-13 宏达国际电子股份有限公司 串行/并行数据转换模块及相关计算机系统

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH056335A (ja) * 1991-06-27 1993-01-14 Nec Eng Ltd 装置間インタフエース方式
JPH05160819A (ja) * 1991-12-03 1993-06-25 Nec Eng Ltd データ転送装置
JPH05250316A (ja) * 1992-03-05 1993-09-28 Nec Eng Ltd 装置間インタフェース方式
US5602780A (en) * 1993-10-20 1997-02-11 Texas Instruments Incorporated Serial to parallel and parallel to serial architecture for a RAM based FIFO memory
US5768529A (en) * 1995-05-05 1998-06-16 Silicon Graphics, Inc. System and method for the synchronous transmission of data in a communication network utilizing a source clock signal to latch serial data into first registers and a handshake signal to latch parallel data into second registers
US5812881A (en) * 1997-04-10 1998-09-22 International Business Machines Corporation Handshake minimizing serial to parallel bus interface in a data processing system
US7069464B2 (en) * 2001-11-21 2006-06-27 Interdigital Technology Corporation Hybrid parallel/serial bus interface

Also Published As

Publication number Publication date
ATE397323T1 (de) 2008-06-15
DE60226910D1 (de) 2008-07-10
ATE388525T1 (de) 2008-03-15
MXPA04004742A (es) 2004-08-02
CA2467841A1 (fr) 2003-06-05
HK1069905A1 (en) 2005-06-03
EP1446722A4 (fr) 2005-04-20
JP2005510800A (ja) 2005-04-21
TW200419359A (en) 2004-10-01
TW200402240A (en) 2004-02-01
TWI285316B (en) 2007-08-11
CA2467841C (fr) 2008-05-13
NO20042522L (no) 2004-06-16
EP1446722A1 (fr) 2004-08-18
CN1589437A (zh) 2005-03-02
CN100346327C (zh) 2007-10-31
TWI260172B (en) 2006-08-11
WO2003046737A1 (fr) 2003-06-05

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase