CA2467841C - Equipement utilisateur (ue) comprenant une interface de bus parallele/serie hybride - Google Patents
Equipement utilisateur (ue) comprenant une interface de bus parallele/serie hybride Download PDFInfo
- Publication number
- CA2467841C CA2467841C CA002467841A CA2467841A CA2467841C CA 2467841 C CA2467841 C CA 2467841C CA 002467841 A CA002467841 A CA 002467841A CA 2467841 A CA2467841 A CA 2467841A CA 2467841 C CA2467841 C CA 2467841C
- Authority
- CA
- Canada
- Prior art keywords
- odd
- data
- serial
- converters
- data block
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M9/00—Parallel/series conversion or vice versa
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
Abstract
L'invention concerne une interface de bus série/parallèle hybride destinée à un équipement utilisateur (UE). Cette interface comprend un dispositif de démultiplexage de blocs de données (40) qui comporte une entrée conçue pour recevoir un bloc de données, ce dispositif démultiplexant ce bloc de données en une pluralité de quartets. Pour chaque quartet, un convertisseur parallèle-série (42) convertit le quartet en données série. Une ligne (44) transfère les données série de chaque quartet et un convertisseur série-parallèle (46) convertit ces données pour rétablir le quartet. Un dispositif de reconstruction de blocs de données (48) combine ensuite les quartets rétablis pour obtenir le bloc de données.
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/990,060 US7069464B2 (en) | 2001-11-21 | 2001-11-21 | Hybrid parallel/serial bus interface |
US09/990,060 | 2001-11-21 | ||
US10/080,899 | 2002-02-22 | ||
US10/080,899 US6823469B2 (en) | 2001-11-21 | 2002-02-22 | User equipment (UE) having a hybrid parallel/serial bus interface |
PCT/US2002/036954 WO2003046737A1 (fr) | 2001-11-21 | 2002-11-18 | Equipement utilisateur (ue) comprenant une interface de bus parallele/serie hybride |
Publications (2)
Publication Number | Publication Date |
---|---|
CA2467841A1 CA2467841A1 (fr) | 2003-06-05 |
CA2467841C true CA2467841C (fr) | 2008-05-13 |
Family
ID=26764107
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA002467841A Expired - Fee Related CA2467841C (fr) | 2001-11-21 | 2002-11-18 | Equipement utilisateur (ue) comprenant une interface de bus parallele/serie hybride |
Country Status (12)
Country | Link |
---|---|
EP (1) | EP1446722A4 (fr) |
JP (1) | JP2005510800A (fr) |
CN (1) | CN100346327C (fr) |
AT (2) | ATE397323T1 (fr) |
AU (1) | AU2002352773A1 (fr) |
CA (1) | CA2467841C (fr) |
DE (1) | DE60226910D1 (fr) |
HK (1) | HK1069905A1 (fr) |
MX (1) | MXPA04004742A (fr) |
NO (1) | NO20042522L (fr) |
TW (2) | TWI260172B (fr) |
WO (1) | WO2003046737A1 (fr) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1321382C (zh) * | 2004-01-20 | 2007-06-13 | 宏达国际电子股份有限公司 | 串行/并行数据转换模块及相关计算机系统 |
CN1329850C (zh) * | 2004-01-20 | 2007-08-01 | 凌阳科技股份有限公司 | 多重路径总线资料传输方法及系统 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH056335A (ja) * | 1991-06-27 | 1993-01-14 | Nec Eng Ltd | 装置間インタフエース方式 |
JPH05160819A (ja) * | 1991-12-03 | 1993-06-25 | Nec Eng Ltd | データ転送装置 |
JPH05250316A (ja) * | 1992-03-05 | 1993-09-28 | Nec Eng Ltd | 装置間インタフェース方式 |
US5602780A (en) * | 1993-10-20 | 1997-02-11 | Texas Instruments Incorporated | Serial to parallel and parallel to serial architecture for a RAM based FIFO memory |
US5768529A (en) * | 1995-05-05 | 1998-06-16 | Silicon Graphics, Inc. | System and method for the synchronous transmission of data in a communication network utilizing a source clock signal to latch serial data into first registers and a handshake signal to latch parallel data into second registers |
US5812881A (en) * | 1997-04-10 | 1998-09-22 | International Business Machines Corporation | Handshake minimizing serial to parallel bus interface in a data processing system |
US7069464B2 (en) * | 2001-11-21 | 2006-06-27 | Interdigital Technology Corporation | Hybrid parallel/serial bus interface |
-
2002
- 2002-11-18 DE DE60226910T patent/DE60226910D1/de not_active Expired - Lifetime
- 2002-11-18 CA CA002467841A patent/CA2467841C/fr not_active Expired - Fee Related
- 2002-11-18 AT AT05104801T patent/ATE397323T1/de not_active IP Right Cessation
- 2002-11-18 AT AT05104800T patent/ATE388525T1/de not_active IP Right Cessation
- 2002-11-18 JP JP2003548100A patent/JP2005510800A/ja active Pending
- 2002-11-18 EP EP02789726A patent/EP1446722A4/fr not_active Withdrawn
- 2002-11-18 MX MXPA04004742A patent/MXPA04004742A/es active IP Right Grant
- 2002-11-18 AU AU2002352773A patent/AU2002352773A1/en not_active Abandoned
- 2002-11-18 WO PCT/US2002/036954 patent/WO2003046737A1/fr active Application Filing
- 2002-11-18 CN CNB028231155A patent/CN100346327C/zh not_active Expired - Fee Related
- 2002-11-21 TW TW091134141A patent/TWI260172B/zh not_active IP Right Cessation
- 2002-11-21 TW TW092128229A patent/TWI285316B/zh not_active IP Right Cessation
-
2004
- 2004-06-16 NO NO20042522A patent/NO20042522L/no not_active Application Discontinuation
-
2005
- 2005-04-21 HK HK05103415A patent/HK1069905A1/xx not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
AU2002352773A1 (en) | 2003-06-10 |
TWI285316B (en) | 2007-08-11 |
MXPA04004742A (es) | 2004-08-02 |
ATE388525T1 (de) | 2008-03-15 |
CN1589437A (zh) | 2005-03-02 |
HK1069905A1 (en) | 2005-06-03 |
JP2005510800A (ja) | 2005-04-21 |
TW200419359A (en) | 2004-10-01 |
NO20042522L (no) | 2004-06-16 |
TW200402240A (en) | 2004-02-01 |
EP1446722A4 (fr) | 2005-04-20 |
WO2003046737A1 (fr) | 2003-06-05 |
DE60226910D1 (de) | 2008-07-10 |
EP1446722A1 (fr) | 2004-08-18 |
CA2467841A1 (fr) | 2003-06-05 |
CN100346327C (zh) | 2007-10-31 |
ATE397323T1 (de) | 2008-06-15 |
TWI260172B (en) | 2006-08-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6823469B2 (en) | User equipment (UE) having a hybrid parallel/serial bus interface | |
US7240233B2 (en) | Hybrid parallel/serial bus interface | |
CA2467841C (fr) | Equipement utilisateur (ue) comprenant une interface de bus parallele/serie hybride | |
EP1446584B1 (fr) | Station de base dotee d'une interface de bus hybride serielle/parallele | |
CA2467847A1 (fr) | Procede de transfert de donnees |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
EEER | Examination request | ||
MKLA | Lapsed |