CN100336183C - 用多官能碳硅烷制造介电层的方法 - Google Patents

用多官能碳硅烷制造介电层的方法 Download PDF

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CN100336183C
CN100336183C CNB028253167A CN02825316A CN100336183C CN 100336183 C CN100336183 C CN 100336183C CN B028253167 A CNB028253167 A CN B028253167A CN 02825316 A CN02825316 A CN 02825316A CN 100336183 C CN100336183 C CN 100336183C
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dielectric layer
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carbon silane
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S·柯希迈尔
D·盖泽尔
H·克劳斯
U·默克
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Abstract

本发明公开了一种对多官能碳硅烷溶胶-凝胶产物进行加热处理来制造低介电常数介电层之方法、所得的相应介电层及其在电子零部件生产中的应用。

Description

用多官能碳硅烷制造介电层的方法
本发明涉及一种用多官能碳硅烷(Carbosilane)生产制作介电层的方法、所得介电层及其应用。
高集成度微电子开关电路是由众多被有针对性地掺杂和结构化了的单晶硅制作的半导体元器件构成。这些单个的半导体元件通过由印导线(Leiterbahn)和绝缘所需的中间层构成的层状结构即所谓的相互连接连接成某一功能单元。
与时俱进的小型化发展对所用的材质提出了极高的要求。除了半导体晶体管之外，相互连接的性能也决定着这些高集成微电子开关电路的功能特征。越来越高的脉冲重复频率和为此所需的越来越短的信号传输时间决定了对材质提出的要求极高。
在此情况下，理想的是印制导线材料具有高导电性和绝缘材料具有小的介电常数。半导体元器件和相互连接的小型化对零部件性能的影响是负面的。印制导线横截面变小则增大了印制导线的电阻值。印制导线彼此间相互距离的缩小加之用绝缘材料的填充导致了不同的印制导线之间的电相互作用，因此也引起了不希望的信号延迟。印制导线之间的相互作用在很大程度上取决于绝缘材料的相对的介电常数ε(k值)。
针对这一技术难题人们试图应用比电导率更高的导电材料和介电常数更小的绝缘材料来解决它。这样，比电导率更高的铜就逐渐地取代了迄今为止被用作印制导线材料的铝。
直到现在二氧化硅用作为生产制作高集成开关电路中的绝缘材料不仅在其电学性能方面而且也在其加工性能(Prozess-Eigenschaften)方面经受住了考验。二氧化硅的介电常数约为4.0。对于现实的要求来说，这一数值然而还是太高。几代新的芯片所用的介电材料要求k值明显低于3.0，最好是低于2.5。
相对介电常数的值(k值)主要取决于测定此值时的温度。这里给出的值应被理解为在温度为22℃、压力为1巴时所测得的值。
除了介电常数(k值)之外，在替代二氧化硅时还应重视把一种新材料集成到半导体工艺中去时的一系列其他性能。比如说介电材料必须能够耐受住高达400℃的高工艺温度，这是在后续的喷镀金属步骤及回火步骤时将达到的温度。此外还必须要求可供使用的层材料及其前体要有足够的纯度，这是因为任何杂质尤其是金属会对层材料的电学性能产生负面影响。
介电材料加工起来应当能够尽可能地简便，并且在常用的工业方法中比如以旋涂的方法中应能作为薄层被涂覆上。
介电常数在3.0以下的电介质除了有机聚合物之外已公开的还有倍半硅氧烷(Silsesquioxane)和掺碳的二氧化硅(SiOC)。
用作介电常数小的电介质的有机聚合物在生产技术中已得到运用。然而这些聚合物的性能在整体工艺中导致显著的问题。它们的有限的化学和机械稳定性即限制了温度升高时的后续的加工步骤。比如说必要的抛光步骤在类似于二氧化硅的层状结构上能达到最佳的程度，然而在有机的聚合物层状结构上却经常达不到最佳效果。
倍半硅氧烷是硅有机聚合物，它在旋涂方法中以低聚物溶液的形式来涂覆，接着被热交联。国际专利WO 98/47944 A1传授了将有机倍半硅氧烷用于生产制作k值小于2.7的层状结构的技术。不过这种化合物只有通过昂贵的由三烷氧基硅烷的合成工艺才能得到。US-A-5,906,859教给人们涂敷低聚氢化倍半硅氧烷(Hydridosilsequioxanen)，该低聚氢化倍半硅氧烷经加热交联成聚合物。采用US-A-5906859中公开的化合物，介电常数可达到2.7至2.9。
掺杂碳的二氧化硅是用PE-CVD(等离子增强的化学气相沉积)方法以有机硅烷为原料，镀覆反应性氧等离子体而成。
掺杂碳的二氧化硅因其具有二氧化硅基质，故其工艺性能相似于二氧化硅，因此生产工艺中显然更容易集成。这种介电层的介电常数因含有碳而比二氧化硅小。US-A-6,054,206则公开了用气态有机硅烷来涂覆这种介电层。然而，高真空等离子化学气相沉积的工艺很费钱，因此它有成本高的缺点。使用掺碳的二氧化硅介电层的介电常数同样可达到2.7至2.9。
在国际专利申请WO99/55526A1中也公开了借助于CVD(化学气相沉积)工艺，最好是等离子化学气相沉积工艺生产制作介电层的技术。在有机硅前体的基础上得到的层状物具有由Si-O-Si化合键构成的主干结构，而有机的侧基团都结合到此结构上。优选进行化学气相沉积工艺的方式使得主干具有环形的结构。环形的有机硅氧烷特别适宜作母体。按照其实施例制作的介电层的介电常数在2.6至3.3之间。
国际专利申请WO 00/75975 A2公开了聚碳硅烷的应用技术，将聚碳硅烷以溶液的形式涂敷上，并通过加热处理使其在不连续的步骤中转换成k值小于2.5的聚有机硅层。所用的聚碳硅烷是指氢化聚碳硅烷，它至少包含一个连接到硅上的氢原子以及优选还包含烯丙基取代基。然而Si-H键对湿度很敏感，因此必须作适当处理。为了使Si-H键与不饱和的基团交联而采用的铂化合物却不受欢迎地成了金属杂质。为了得到小k值的层则热处理必须在精确控制的条件下进行，在此必须遵守不同的规定温度。
为进一步减小介电常数也就是减小电介质材料k值的普通做法是引进气孔。包含在气孔中的空气其k值几乎为1。如果人们把充满空气的气孔引入致密的材料之中，那么材料的平均k值就由致密材料的k值和空气的部分k值两部分构成。这样人们就能降低有效k值。纯净二氧化硅的k值于是可以从4.0一直降到2.0以下，不过为此则要求孔隙度＞90％(见1995年第267卷材料研究协会研讨会会议文集(Mat.Res.Soc.Symp.Proc.)第381页L.Hrubesch的文章)。如此高的孔隙度则又降低了机械稳定性并大大增加了这种层状物的加工难度。
这一原理可以普遍地应用到致密的介电层上。起始k值较小的介电层在孔隙度明显低的情况下k值就能达到2.0以下，这又有利于介电层的机械稳定性。
然而还是缺少适合于简便的热处理方法制作电介质层用的合适的简单就能得到的原始材料。
德国专利文献DE196 03 241C1中记叙了多官能有机硅氧烷的制备，该物质被用作为硅溶胶基无机涂料中的交联剂。这种材料在干燥之后形成柔软的膜，不太适合用作介电层材料，且其k值明显大于3。
目前令人感到意外地发现，用多官能碳硅烷比如说由DE19603241C1公开的化合物的溶胶-凝胶产物经过加热处理可以制作k值小的介电层。在此可以使用的特别是没有Si-H键的碳硅烷。这很惊人，特别是由于有国际专利申请WO00/75975 A2的技术背景，在该专利申请说明书第8页最后一段写道：只有具有至少一个连接到硅上的氢原子的聚碳硅烷才适合用来制作合宜的介电层。
经加热处理之后本发明的介电层在其构成方面与掺碳的二氧化硅相类似，并将低k值与简便的加热处理的优点综合到了一起。
因此，本发明的主题是要提供一种制作介电层的方法，该方法的特征是对多官能的碳硅烷的溶胶-凝胶产物进行加热处理。
此外本发明的主题还在于可用这种方法制作的介电层。
本发明的最后一个主题是此种介电层用作为生产制造微电子开关电路中的绝缘层，以及用于芯片封装、多芯片模块合成、层压印制电路板和显示器制造中的绝缘层的用途。
本发明方法中可以使用的溶胶-凝胶产物可以通过多官能碳硅烷在催化剂的存在下与水起反应而获得。
适合用作碳硅烷的多官能碳硅烷至少应含有2个硅原子，优选至少含有3个硅原子，每个硅原子各携带1至3个烷氧基或羟基，而这些硅原子各通过至少一个Si-C键结合到将各硅原子连接起来的结构单元上。
按照本发明的连接单元例如是直线的或支化的C1至C10亚烷基链，C5至C10亚环烷基基团，芳族基团，比如苯基、萘基或联苯基，或者也还包括芳香族基团和脂族基团的组合。脂族基和芳族基也可以含有杂原子如Si、N、O或F。
优选使用没有Si-H键的多官能碳硅烷。
适宜的多官能碳硅烷的实例为通式(I)所示化合物
            R1 4-iSi[(CH2)nSi(OR2)aR3 3-a]i           (I)
式中
R1＝烷基、芳基，优选为C1-C10烷基，C6-C10芳基，
i＝2至4，优选i＝4，
n＝1至10，优选是n＝2至4，尤其优选n＝2，
R2＝烷基、芳基，优选是C1-C10烷基，C6-C10芳基，尤其优选甲基、乙基、异丙基
a＝1至3
R3＝烷基、芳基，优选是C1-C10烷基，C6-C10芳基，尤其优选甲基。
对于a＝1的情况，R2也可为氢。
其他的实例为通式(II)所示的环状化合物
Figure C0282531600091
式中
m＝3至6，优选m＝3或4
n＝2至10，优选n＝2，
R4＝烷基、芳基，优选C1-C10烷基，C6-C10芳基，尤其优选甲基、乙基、异丙基；
对于b＝1的情况，R4也可为氢，
b＝1至3
R5＝烷基、芳基，优选C1-C10烷基，C6-C10芳基，尤其优选甲基，
R6＝C1-C6烷基或C6-C14芳基，优选为甲基、乙基，尤其优选甲基。
多官能碳硅烷的其他实例为通式(III)所示的化合物
             Si[OSiR7 2(CH2)pSi(OR8)dR9 3-d]4         (III)
其中
R7＝烷基、芳基，优选为C1-C10烷基，C6-C10芳基，尤其优选甲基，
p＝1至10，优选p＝2或4，尤其优选p＝2，
R8＝烷基、芳基，优选C1-C10烷基，C6-C10芳基，尤其优选甲基、乙基、异丙基；
对于d＝1的情况，R8也可为氢。
d＝1至3，
R9＝烷基、芳基，优选为C1-C10烷基，C6-C10芳基，尤其优选甲基。
也可将通式(I)至(III)所示化合物的低聚物或低聚物混合物用作多官能碳硅烷。
特别适合的化合物的例子是1，3，5，7-四甲基-1，3，5，7-四(2-(二乙氧基甲基甲硅烷基)亚乙基)环四硅氧烷，1，3，5，7-四甲基-1，3，5，7-四(2-(羟基二甲基甲硅烷基)亚乙基)环四硅氧烷或其低聚物。
为了制备溶胶-凝胶产物，例如可以向多官能碳硅烷掺加有机溶剂，随后视需要在催化剂存在下使之与水反应。这种溶胶-凝胶制备工艺，专业技术人员一般都熟知。因此，举例来说，EP743313A2、EP787734A1以及国际专利申请WO 98/52992 A1中记载了多官能有机硅烷和有机硅氧烷的合成以及制备相应的溶胶-凝胶-涂层溶液的方法。
适能的有机溶剂比如有酮、醇、二醇、醚及其混合物。添加溶剂是为了赋予溶液所要求的粘度。优选的溶剂有正丁醇、乙醇和异丙醇。
可能的稀释度为多官能碳硅烷在溶剂中占10％至90％(重量)，优选为20％至50％(重量)。
经添加水和视需要添加催化剂，引发水解反应和/或缩合反应。
可以添加那些能加速各官能团之间反应的化合物作为催化剂。适用的催化剂比如为有机酸和无机酸，例如具1至10个碳原子的脂族一元羧酸如甲酸或乙酸，具7至14个碳原子的芳族羧酸、比如苯甲酸，二元羧酸如乙二酸，脂族和芳族磺酸如对甲苯磺酸，无机挥发性的酸如盐酸或硝酸。尤其优选使用对甲苯磺酸。
催化剂可以水溶液或醇溶液的形式使用，浓度为0.05-5n，优选为0.1-1n。可向碳硅烷溶液添加比如1-50％(重量)、优选5-20％(重量)催化剂溶液。
尤其优选使用具有以下组成的多官能碳硅烷复配物：
20％至30％(重量)的碳硅烷，
0％至10％(重量)1n的缩合催化剂溶液和60％至80％(重量)溶剂。
上述复配物可在室温与所用溶剂沸点之间的温度下搅拌1至6小时。这个措施旨在促使多官能碳硅烷开始缩合过程。
为了制作介电层，通常将溶胶-凝胶产物涂到基体上。介电层的涂覆，原则上所有常用方法都可使用。这些方法例如是旋涂、浸涂、刷涂和喷涂。
多官能碳硅烷的溶胶-凝胶产物或其复配物在涂到基体上之后与以加热处理。加热处理比如说在100至800℃之间进行，优选在200至600℃之间，尤其优选在200至400℃之间进行。这种加热处理为的是使多官能碳硅烷完全交联并除去溶剂。此外，加热处理还用来产生气孔。加热处理可以以很简单的方式在一个工艺步骤里在规定的温度下进行。然而，也可以在多个工艺步骤里按照适当的温度时间曲线来进行。适用的温度时间曲线取决于多官能碳硅烷、所用催化剂及溶剂的比例，并且可以通过预先试验得知。
在加热处理之前，优选在100至150℃温度下使介电层交联5至120分钟。
微孔通过在高于某个温度的条件下进行加热处理而产生，在该温度下部分碳硅烷分解并以气态成分逸出。微孔形成的温度约在220℃以上，具体温度因所用多官能碳硅烷而异。
也可于涂覆前在溶胶-凝胶产物中添加微孔形成材料如高沸点溶剂或起泡剂。这些物质进行交联的过程中在介电层中保持不变，只是在后来的加热处理时才蒸发并/或分解成气态产物。
加热处理可用常用的烘炉、RTP(快速热处理)炉、电热板等来进行。但是也可以借助于微波、红外光、激光或其他高能电磁辐照来提供交联和形成微孔所需的能量。这种加热处理优选在烘炉中或电热板上进行。
加热处理可以在空气中或在其他气体中进行。优选在空气中或在氮气中进行加热处理。
在加热处理时，涂层中热不稳定成分受热分解，留下充满气体的微孔。
在本发明的另一种实施方式中，介电层在涂覆和加热处理后，还要再经受另一个加工步骤，它用来使微孔表面具有疏水性。硅有机材料的k值会由于Si-OH基团化学转化成Si-O-SiR3-基团而进一步减小。为此表面可用适当的化合物如三氯甲基硅烷或六亚甲基二硅氮烷来进行处理。上述方法的详细说明以及其他实施例比如在国际专利申请WO 99/36953 A1中已予记叙。
本发明的主题还在于按照本发明方法可制得的介电层。
本发明介电层的特点是k值小于2.8，优选小于2.5，尤其优选小于2.0，其中k值尤其取决于多官能碳硅烷的选择以及对溶胶-凝胶产物进行加热处理的条件。
本发明介电层的层厚优选为0.01至100μm。
本发明介电层能比如以介电绝缘层的形式用来生产微电子开关电路、封装芯片、合成多芯片模块以及制作层压印刷线路板和制作显示器。
可用来在其上涂覆本发明介电层的基体视应用场合而定。所有可以用前面提到的技术如旋涂、浸涂、刷涂和喷涂来涂覆的并又能耐受住加热处理时高温的基体均可采用，比如结构化的和非结构化的硅晶片、其他半导体如砷化镓或锗化硅的结构化的和非结构化的晶片、具有导电层的结构化的或非结构化的玻璃板，或适用的结构化和非结构化的耐热塑料基体。
实施例
各实施例中所列举的化合物均可以根据EP743313 A2、EP787734 A1或国际专利申请WO 98/52992 A1来制备。
所涂膜的层厚用表面形貌测量器(Surface Profiler，Alpha-Step 500，KLA-Tencor)来进行测量。
介电常数k通过测量模型平板电容器的电容C来确定。适用的表达式为：
C = k ω 0 A d - - - ( 1 )
式中，A是电容器极板的面积，d是极板间距离，且电场常数ε0＝8.8542*10-12As/Vm。对每个试样制作一个电容器。为此，实例中所述组合物的0.5至1μm厚的薄膜用旋涂的方法涂覆到一块25mm×25mm大小的导电ITO(铟-锡-氧化物)-玻璃片上，此间让一狭窄条纹脱胶，为的是以后可以触点接通。层状物上的反向触点接通则通过一个溅射镀覆的金电极(直径约5mm)来进行。
电容的测量则用阻抗波谱仪(EG&G 398)来进行。为此在没有偏压的情况下在10至100000Hz频谱范围内测定模型平板电容器的阻抗Z。模型电容器的电容C可按下式用阻抗Z算得：
Z = R 1 + ( ωRC ) 2 - - - ( 2 ) ,
式中ω是施加的交流电压的角频率(Kreisfvequeng)，R是与电容C并联的高欧姆数电阻值。
实施例1
将4.4g 1，3，5，7-四甲基-1，3，5，7-四(2-(二乙氧基甲基甲硅烷基)亚乙基)环四硅氧烷溶于12.2g异丙醇，并掺加1.0g 0.1n的对甲苯磺酸水溶液。混合液在室温下搅拌1小时。200μl的混合物用市售旋涂器在每分钟2000转的转速下喷丝到玻璃基体上并加热到130℃，历时两个小时。膜层厚度0.61μm，k值为2.7。
实施例2
将3.24克1，3，5，7-四甲基-1，3，5，7-四(2-羟基二甲基甲硅烷基)亚乙基)环四硅氧烷溶于8.7克异丙醇，并掺入1.0克0.1n的对甲苯磺酸水溶液。混合液在室温下搅拌1小时。200μ升的混合物在每分钟2000转的转速下喷丝到玻璃基体上，并加热到130℃一个小时，接着在200℃温度下于氮气中退火一个小时。退火的膜层厚度为1.44微米，k值为1.8。
实施例3
实施例2中的混合物200微升在每分钟2000转的转速下喷丝到玻璃基体上，加热到130℃，历时两个小时，之后在400℃温度下于氮气中退火一个小时。退火的薄膜层厚度为0.57微米，k值为2.5。

Claims (12)

1、制造介电层的方法，该方法包括：
(a)提供一种包含以下组分的组合物：
(i)至少一种多官能碳硅烷的溶胶-凝胶产物，所述多官能碳硅烷不具有Si-H键，并且为选自通式(I)所示的一种或多种化合物或其低聚物：
              R1 4-iSi[(CH2)nSi(OR2)aR3 3-a]i           (I)
式中
R1＝烷基或芳基，
i＝2至4，
n＝1至10，
R2＝烷基或芳基，
a＝1至3，和
R3＝烷基或芳基，
其中对于a＝1的情况，R2也可以是氢；和
(ii)微孔形成材料，其选自高沸点溶剂、起泡剂和受热不稳定的成分；
(b)将所述组合物涂覆到基体上；和
(c)在200-600℃下和在选自空气和氮气的气氛中热处理所述涂覆到基体上的组合物，从而形成所述的介电层，所述介电层具有多孔性；
其中所述介电层具有多孔性是通过在热处理步骤期间蒸发或分解所述微孔形成材料而形成，并且所述热处理步骤是通过选自工业上常用的烘炉、电热板、微波能量、红外光、激光或其它高能电磁射线辐照的方法来进行的。
2、根据权利要求1所述制造介电层的方法，其特征是，所述多官能碳硅烷还包含通式(II)所示的一种或多种化合物或它们的低聚物：
Figure C028253160003C1
式中
m＝3至6，
n＝2至10，
R4＝烷基或芳基，和
其中对于b＝1的情况，R4也可以是氢，
b＝1至3，
R5＝烷基或芳基，
R6＝C1-C6烷基或C6-C14芳基。
3、根据权利要求1所述制造介电层的方法，其特征是，所述多官能碳化硅烷还包含通式(III)所示的一种或多种化合物或它们的低聚物：
          Si[OSiR7 2(CH2)pSi(OR8)dR9 3-d]4        (III)
式中
R7＝烷基或芳基，
p＝1至10，
R8＝烷基或芳基，
其中对于d＝1的情况，R8也可以是氢，
d＝1至3，
R9＝烷基或芳基。
4、权利要求1所述制造介电层的方法，其特征是，所述介电层的介电常数小于2.8。
5、权利要求4所述制造介电层的方法，其特征是，所述介电层的介电常数小于2.5。
6、根据权利要求1所述制造介电层的方法，其特征是，在制备溶胶-凝胶产物时向多官能碳硅烷中添加酮、醇、二醇、醚或它们的混合物。
7、根据权利要求1所述制造介电层的方法，其特征是，在制备溶胶-凝胶产物时向多官能碳硅烷中添加挥发性有机酸或无机酸作催化剂。
8、根据权利要求1所述制造介电层的方法，其特征是，所述溶胶-凝胶产物以刷涂、旋涂、浸涂或喷涂方式涂覆到基体上。
9、权利要求1所述制造介电层的方法，其特征是，介电层在加热处理之后又经受进一步处理，在该处理中表面上的羟基数减少。
10、按权利要求1至9中任意一项的方法制造的介电层。
11、权利要求10所述的介电层，其特征是，该介电层的层厚为0.01至100μm。
12、权利要求10或11所述介电层作为绝缘层在高集成微电子开关电路生产中、芯片封装中、合成多芯片模块以及制作层压印刷线路板和制作显示器中的应用。
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US20040038048A1 (en) 2000-02-02 2004-02-26 Lg Chemical Ltd. Semiconductor interlayer dielectric material and a semiconductor device using the same
DE102004027857A1 (de) * 2004-06-08 2006-01-05 Siemens Ag Verfahren zum Herstellen eines keramischen Werkstoffs, keramischer Werkstoff und Keramikkörper mit dem keramischen Werkstoff
US7575979B2 (en) * 2004-06-22 2009-08-18 Hewlett-Packard Development Company, L.P. Method to form a film
US7892648B2 (en) * 2005-01-21 2011-02-22 International Business Machines Corporation SiCOH dielectric material with improved toughness and improved Si-C bonding
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JP4935111B2 (ja) 2006-02-22 2012-05-23 富士通株式会社 絶縁膜形成用組成物、半導体装置用絶縁膜、その製造方法および半導体装置
US20080012074A1 (en) * 2006-07-14 2008-01-17 Air Products And Chemicals, Inc. Low Temperature Sol-Gel Silicates As Dielectrics or Planarization Layers For Thin Film Transistors
WO2009150021A2 (en) * 2008-05-26 2009-12-17 Basf Se Method of making porous materials and porous materials prepared thereof
US10361137B2 (en) * 2017-07-31 2019-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5677410A (en) * 1995-05-16 1997-10-14 Bayer Ag Carbosilane-dendrimers, carbosilane-hybrid materials, methods for manufacturing them and a method for manufacturing coatings from the carbosilane-dendrimers
CN1161969A (zh) * 1996-01-30 1997-10-15 拜尔公司 多官能环状有机硅氧烷、其制备方法及其用途
CN1165161A (zh) * 1995-09-21 1997-11-19 旭硝子株式会社 低介电树脂组合物
US6225238B1 (en) * 1999-06-07 2001-05-01 Allied Signal Inc Low dielectric constant polyorganosilicon coatings generated from polycarbosilanes
EP1150346A2 (en) * 2000-04-28 2001-10-31 LG Chem Investment, Ltd A process for preparing insulating material having low dielectric constant

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6005131A (en) * 1996-01-30 1999-12-21 Bayer Aktiengesellschaft Multi-functional, cyclic organosiloxanes, process for the production thereof and use thereof
US6043330A (en) * 1997-04-21 2000-03-28 Alliedsignal Inc. Synthesis of siloxane resins
US6143855A (en) * 1997-04-21 2000-11-07 Alliedsignal Inc. Organohydridosiloxane resins with high organic content
CA2290455C (en) * 1997-05-23 2007-04-10 Bayer Aktiengesellschaft Organosilane oligomers
US6042994A (en) * 1998-01-20 2000-03-28 Alliedsignal Inc. Nanoporous silica dielectric films modified by electron beam exposure and having low dielectric constant and low water content
US6068884A (en) * 1998-04-28 2000-05-30 Silcon Valley Group Thermal Systems, Llc Method of making low κ dielectric inorganic/organic hybrid films
US6054206A (en) * 1998-06-22 2000-04-25 Novellus Systems, Inc. Chemical vapor deposition of low density silicon dioxide films
US5906859A (en) * 1998-07-10 1999-05-25 Dow Corning Corporation Method for producing low dielectric coatings from hydrogen silsequioxane resin
US6514091B2 (en) * 2000-11-28 2003-02-04 Sumitomo Wiring Systems, Ltd. Electrical junction box for a vehicle
EP1481284A4 (en) * 2002-03-04 2006-10-25 Tokyo Electron Ltd METHOD FOR PASSIVATING LOW DIELECTRIC MATERIALS IN WELDING PROCESSING
JP4139710B2 (ja) * 2003-03-10 2008-08-27 信越化学工業株式会社 多孔質膜形成用組成物、多孔質膜の製造方法、多孔質膜、層間絶縁膜、及び半導体装置
KR100507967B1 (ko) * 2003-07-01 2005-08-10 삼성전자주식회사 실록산계 수지 및 이를 이용한 반도체 층간 절연막

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5677410A (en) * 1995-05-16 1997-10-14 Bayer Ag Carbosilane-dendrimers, carbosilane-hybrid materials, methods for manufacturing them and a method for manufacturing coatings from the carbosilane-dendrimers
CN1165161A (zh) * 1995-09-21 1997-11-19 旭硝子株式会社 低介电树脂组合物
CN1161969A (zh) * 1996-01-30 1997-10-15 拜尔公司 多官能环状有机硅氧烷、其制备方法及其用途
US6225238B1 (en) * 1999-06-07 2001-05-01 Allied Signal Inc Low dielectric constant polyorganosilicon coatings generated from polycarbosilanes
EP1150346A2 (en) * 2000-04-28 2001-10-31 LG Chem Investment, Ltd A process for preparing insulating material having low dielectric constant

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DE10162443A1 (de) 2003-07-03
TW200305618A (en) 2003-11-01
JP2005513777A (ja) 2005-05-12
TWI265964B (en) 2006-11-11
US7090896B2 (en) 2006-08-15
WO2003052809A1 (de) 2003-06-26
EP1468446A1 (de) 2004-10-20
KR20040068274A (ko) 2004-07-30
US20030181537A1 (en) 2003-09-25
HK1076918A1 (en) 2006-01-27
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