CL2019003792A1 - Procesadores de alto rendimiento. - Google Patents

Procesadores de alto rendimiento.

Info

Publication number
CL2019003792A1
CL2019003792A1 CL2019003792A CL2019003792A CL2019003792A1 CL 2019003792 A1 CL2019003792 A1 CL 2019003792A1 CL 2019003792 A CL2019003792 A CL 2019003792A CL 2019003792 A CL2019003792 A CL 2019003792A CL 2019003792 A1 CL2019003792 A1 CL 2019003792A1
Authority
CL
Chile
Prior art keywords
processor
core
channeled
configuration
algorithmic
Prior art date
Application number
CL2019003792A
Other languages
English (en)
Inventor
Robert D Catiller
Daniel Roig
Gnanashanmugam Elumalai
Original Assignee
Icat Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Icat Llc filed Critical Icat Llc
Publication of CL2019003792A1 publication Critical patent/CL2019003792A1/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Software Systems (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Advance Control (AREA)
  • Logic Circuits (AREA)
  • Devices For Executing Special Programs (AREA)
  • Microcomputers (AREA)
  • Mathematical Physics (AREA)
  • Executing Machine-Instructions (AREA)
  • Organic Low-Molecular-Weight Compounds And Preparation Thereof (AREA)

Abstract

SE DESCRIBE UN COMPILADOR CANALIZADO DE COINCIDENCIA ALGORÍTMICA Y UN NÚCLEO CANALIZADO ALGORÍTMICO REUTILIZABLE QUE COMPRENDE UN SISTEMA PROCESADOR DE ALTO RENDIMIENTO. EL NÚCLEO CANALIZADO ALGORÍTMICO REUTILIZABLE ES UN NÚCLEO DE PROCESAMIENTO RECONFIGURABLE CON UNA ESTRUCTURA CANALIZADA QUE COMPRENDE UN PROCESADOR CON UNA INTERFAZ DE CONFIGURACIÓN PARA PROGRAMAR CUALQUIERA DE UNA PLURALIDAD DE OPERACIONES SEGÚN LO DETERMINADO POR LOS DATOS DE CONFIGURACIÓN, UN PROCESADOR DE DECISIÓN LÓGICA PARA PROGRAMAR UNA TABLA DE BÚSQUEDA, UN CONTADOR DE BUCLE Y UN REGISTRO CONSTANTE Y UN BLOQUE DE MEMORIA. ESTO SE PUEDE USAR PARA REALIZAR FUNCIONES. UN CIRCUITO PROGRAMABLE Y RECONFIGURABLE ENRUTA DATOS Y RESULTADOS DE UN NÚCLEO A OTRO NÚCLEO Y/O CONTROLADOR 10 Y/O GENERADOR DE INTERRUPCIÓN, SEGÚN SEA NECESARIO PARA COMPLETAR UN ALGORITMO SIN LA INTERVENCIÓN ADICIONAL DE UN PROCESADOR CENTRAL O PERIFÉRICO DURANTE EL PROCESAMIENTO DE UN ALGORITMO.
CL2019003792A 2017-06-22 2019-12-20 Procesadores de alto rendimiento. CL2019003792A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US201762523528P 2017-06-22 2017-06-22

Publications (1)

Publication Number Publication Date
CL2019003792A1 true CL2019003792A1 (es) 2020-07-10

Family

ID=64736139

Family Applications (1)

Application Number Title Priority Date Filing Date
CL2019003792A CL2019003792A1 (es) 2017-06-22 2019-12-20 Procesadores de alto rendimiento.

Country Status (17)

Country Link
US (1) US11436186B2 (es)
EP (1) EP3642706A4 (es)
JP (1) JP7183197B2 (es)
KR (1) KR20200031625A (es)
CN (1) CN110998513A (es)
AU (1) AU2018289605B2 (es)
BR (1) BR112019027531A2 (es)
CA (1) CA3067827A1 (es)
CL (1) CL2019003792A1 (es)
CO (1) CO2020000664A2 (es)
DO (1) DOP2019000311A (es)
IL (1) IL271746A (es)
PE (1) PE20200270A1 (es)
PH (1) PH12019502877A1 (es)
RU (1) RU2020102277A (es)
SG (1) SG11201912963SA (es)
WO (1) WO2018237361A1 (es)

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US20220121542A1 (en) * 2020-10-20 2022-04-21 Nvidia Corporation Techniques for testing semiconductor devices
US11182221B1 (en) * 2020-12-18 2021-11-23 SambaNova Systems, Inc. Inter-node buffer-based streaming for reconfigurable processor-as-a-service (RPaaS)
US11782760B2 (en) 2021-02-25 2023-10-10 SambaNova Systems, Inc. Time-multiplexed use of reconfigurable hardware
US11200096B1 (en) 2021-03-26 2021-12-14 SambaNova Systems, Inc. Resource allocation for reconfigurable processors
CN113360189B (zh) * 2021-06-04 2022-09-30 上海天旦网络科技发展有限公司 适用于流处理的异步优化方法、系统、装置和可读介质
TWI792546B (zh) * 2021-09-09 2023-02-11 瑞昱半導體股份有限公司 用於管線化控制的設備以及方法

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JPH07101410B2 (ja) * 1990-01-17 1995-11-01 インターナショナル、ビジネス、マシーンズ、コーポレーション データ処理ネットワークにおいて逐次化手段の試験のため命令流の実行を同期させる方法
US5684980A (en) 1992-07-29 1997-11-04 Virtual Computer Corporation FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in response to those instructions
US6347344B1 (en) * 1998-10-14 2002-02-12 Hitachi, Ltd. Integrated multimedia system with local processor, data transfer switch, processing modules, fixed functional unit, data streamer, interface unit and multiplexer, all integrated on multimedia processor
JP2002123563A (ja) * 2000-10-13 2002-04-26 Nec Corp コンパイル方法および合成装置ならびに記録媒体
GB0028079D0 (en) * 2000-11-17 2001-01-03 Imperial College System and method
JP3561506B2 (ja) * 2001-05-10 2004-09-02 東京エレクトロンデバイス株式会社 演算システム
WO2005086746A2 (en) * 2004-03-04 2005-09-22 Trustees Of Boston University Programmable-logic acceleraton of data processing applications
US7301368B2 (en) * 2005-03-15 2007-11-27 Tabula, Inc. Embedding memory within tile arrangement of a configurable IC
US7394288B1 (en) * 2004-12-13 2008-07-01 Massachusetts Institute Of Technology Transferring data in a parallel processing environment
US20060146864A1 (en) * 2004-12-30 2006-07-06 Rosenbluth Mark B Flexible use of compute allocation in a multi-threaded compute engines
WO2006114642A1 (en) 2005-04-28 2006-11-02 The University Court Of The University Of Edinburgh Reconfigurable instruction cell array
GB2466821A (en) * 2009-01-08 2010-07-14 Advanced Risc Mach Ltd An FPGA with an embedded bus and dedicated bus interface circuits
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US8607247B2 (en) * 2011-11-03 2013-12-10 Advanced Micro Devices, Inc. Method and system for workitem synchronization
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Also Published As

Publication number Publication date
KR20200031625A (ko) 2020-03-24
WO2018237361A1 (en) 2018-12-27
SG11201912963SA (en) 2020-01-30
JP7183197B2 (ja) 2022-12-05
BR112019027531A2 (pt) 2020-07-21
US20200142857A1 (en) 2020-05-07
PH12019502877A1 (en) 2020-12-07
EP3642706A4 (en) 2021-04-07
CO2020000664A2 (es) 2020-05-05
US11436186B2 (en) 2022-09-06
IL271746A (en) 2020-01-30
EP3642706A1 (en) 2020-04-29
CN110998513A (zh) 2020-04-10
DOP2019000311A (es) 2020-06-15
AU2018289605B2 (en) 2023-04-27
CA3067827A1 (en) 2018-12-27
AU2018289605A1 (en) 2020-02-13
RU2020102277A (ru) 2021-07-22
JP2020525907A (ja) 2020-08-27
PE20200270A1 (es) 2020-02-04

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