SG11201912963SA - High throughput processors - Google Patents

High throughput processors

Info

Publication number
SG11201912963SA
SG11201912963SA SG11201912963SA SG11201912963SA SG11201912963SA SG 11201912963S A SG11201912963S A SG 11201912963SA SG 11201912963S A SG11201912963S A SG 11201912963SA SG 11201912963S A SG11201912963S A SG 11201912963SA SG 11201912963S A SG11201912963S A SG 11201912963SA
Authority
SG
Singapore
Prior art keywords
high throughput
throughput processors
processors
throughput
Prior art date
Application number
SG11201912963SA
Inventor
Robert Catiller
Daniel Roig
Gnanashanmugam Elumalai
Original Assignee
Icat Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Icat Llc filed Critical Icat Llc
Publication of SG11201912963SA publication Critical patent/SG11201912963SA/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/78Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/80Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Software Systems (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Advance Control (AREA)
  • Logic Circuits (AREA)
  • Devices For Executing Special Programs (AREA)
  • Mathematical Physics (AREA)
  • Microcomputers (AREA)
  • Executing Machine-Instructions (AREA)
  • Organic Low-Molecular-Weight Compounds And Preparation Thereof (AREA)
SG11201912963SA 2017-06-22 2018-06-22 High throughput processors SG11201912963SA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201762523528P 2017-06-22 2017-06-22
PCT/US2018/039167 WO2018237361A1 (en) 2017-06-22 2018-06-22 High throughput processors

Publications (1)

Publication Number Publication Date
SG11201912963SA true SG11201912963SA (en) 2020-01-30

Family

ID=64736139

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201912963SA SG11201912963SA (en) 2017-06-22 2018-06-22 High throughput processors

Country Status (17)

Country Link
US (1) US11436186B2 (en)
EP (1) EP3642706A4 (en)
JP (1) JP7183197B2 (en)
KR (1) KR20200031625A (en)
CN (1) CN110998513A (en)
AU (1) AU2018289605B2 (en)
BR (1) BR112019027531A2 (en)
CA (1) CA3067827A1 (en)
CL (1) CL2019003792A1 (en)
CO (1) CO2020000664A2 (en)
DO (1) DOP2019000311A (en)
IL (1) IL271746A (en)
PE (1) PE20200270A1 (en)
PH (1) PH12019502877A1 (en)
RU (1) RU2020102277A (en)
SG (1) SG11201912963SA (en)
WO (1) WO2018237361A1 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220121542A1 (en) * 2020-10-20 2022-04-21 Nvidia Corporation Techniques for testing semiconductor devices
US11182221B1 (en) 2020-12-18 2021-11-23 SambaNova Systems, Inc. Inter-node buffer-based streaming for reconfigurable processor-as-a-service (RPaaS)
US11782760B2 (en) 2021-02-25 2023-10-10 SambaNova Systems, Inc. Time-multiplexed use of reconfigurable hardware
US11200096B1 (en) 2021-03-26 2021-12-14 SambaNova Systems, Inc. Resource allocation for reconfigurable processors
CN113360189B (en) * 2021-06-04 2022-09-30 上海天旦网络科技发展有限公司 Asynchronous optimization method, system, device and readable medium suitable for stream processing
TWI792546B (en) * 2021-09-09 2023-02-11 瑞昱半導體股份有限公司 Apparatus and method for pipeline control

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US4291372A (en) 1979-06-27 1981-09-22 Burroughs Corporation Microprocessor system with specialized instruction format
JPH07101410B2 (en) * 1990-01-17 1995-11-01 インターナショナル、ビジネス、マシーンズ、コーポレーション Method for synchronizing instruction stream execution for testing serialization means in a data processing network
US5684980A (en) 1992-07-29 1997-11-04 Virtual Computer Corporation FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in response to those instructions
US6347344B1 (en) * 1998-10-14 2002-02-12 Hitachi, Ltd. Integrated multimedia system with local processor, data transfer switch, processing modules, fixed functional unit, data streamer, interface unit and multiplexer, all integrated on multimedia processor
JP2002123563A (en) * 2000-10-13 2002-04-26 Nec Corp Compiling method, composing device, and recording medium
GB0028079D0 (en) * 2000-11-17 2001-01-03 Imperial College System and method
JP3561506B2 (en) * 2001-05-10 2004-09-02 東京エレクトロンデバイス株式会社 Arithmetic system
WO2005086746A2 (en) * 2004-03-04 2005-09-22 Trustees Of Boston University Programmable-logic acceleraton of data processing applications
US7301368B2 (en) * 2005-03-15 2007-11-27 Tabula, Inc. Embedding memory within tile arrangement of a configurable IC
US7804504B1 (en) 2004-12-13 2010-09-28 Massachusetts Institute Of Technology Managing yield for a parallel processing integrated circuit
US20060146864A1 (en) * 2004-12-30 2006-07-06 Rosenbluth Mark B Flexible use of compute allocation in a multi-threaded compute engines
US20100122105A1 (en) 2005-04-28 2010-05-13 The University Court Of The University Of Edinburgh Reconfigurable instruction cell array
GB2466821A (en) * 2009-01-08 2010-07-14 Advanced Risc Mach Ltd An FPGA with an embedded bus and dedicated bus interface circuits
GB201001621D0 (en) * 2010-02-01 2010-03-17 Univ Catholique Louvain A tile-based processor architecture model for high efficiency embedded homogenous multicore platforms
US8607247B2 (en) * 2011-11-03 2013-12-10 Advanced Micro Devices, Inc. Method and system for workitem synchronization
US20130157639A1 (en) * 2011-12-16 2013-06-20 SRC Computers, LLC Mobile electronic devices utilizing reconfigurable processing techniques to enable higher speed applications with lowered power consumption
US8959469B2 (en) * 2012-02-09 2015-02-17 Altera Corporation Configuring a programmable device using high-level language
US9535705B1 (en) * 2013-08-13 2017-01-03 Asher Hazanchuk Flexible hardware programmable scalable parallel processor
EP3014429B1 (en) * 2013-09-06 2020-03-04 Huawei Technologies Co., Ltd. Method and apparatus for asynchronous processor removal of meta-stability
US9645937B2 (en) * 2015-08-28 2017-05-09 International Business Machines Corporation Expedited servicing of store operations in a data processing system

Also Published As

Publication number Publication date
PH12019502877A1 (en) 2020-12-07
KR20200031625A (en) 2020-03-24
EP3642706A4 (en) 2021-04-07
AU2018289605B2 (en) 2023-04-27
IL271746A (en) 2020-01-30
WO2018237361A1 (en) 2018-12-27
PE20200270A1 (en) 2020-02-04
BR112019027531A2 (en) 2020-07-21
US20200142857A1 (en) 2020-05-07
CA3067827A1 (en) 2018-12-27
CO2020000664A2 (en) 2020-05-05
JP2020525907A (en) 2020-08-27
JP7183197B2 (en) 2022-12-05
CL2019003792A1 (en) 2020-07-10
DOP2019000311A (en) 2020-06-15
EP3642706A1 (en) 2020-04-29
CN110998513A (en) 2020-04-10
AU2018289605A1 (en) 2020-02-13
RU2020102277A (en) 2021-07-22
US11436186B2 (en) 2022-09-06

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