CO2020000664A2 - Procesadores de alto rendimiento - Google Patents

Procesadores de alto rendimiento

Info

Publication number
CO2020000664A2
CO2020000664A2 CONC2020/0000664A CO2020000664A CO2020000664A2 CO 2020000664 A2 CO2020000664 A2 CO 2020000664A2 CO 2020000664 A CO2020000664 A CO 2020000664A CO 2020000664 A2 CO2020000664 A2 CO 2020000664A2
Authority
CO
Colombia
Prior art keywords
core
processor
algorithmic
programming
algorithm
Prior art date
Application number
CONC2020/0000664A
Other languages
English (en)
Inventor
Robert D Catiller
Daniel Roig
Gnanashanmugam Elumalai
Original Assignee
Icat Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Icat Llc filed Critical Icat Llc
Publication of CO2020000664A2 publication Critical patent/CO2020000664A2/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Computing Systems (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Advance Control (AREA)
  • Logic Circuits (AREA)
  • Devices For Executing Special Programs (AREA)
  • Microcomputers (AREA)
  • Mathematical Physics (AREA)
  • Organic Low-Molecular-Weight Compounds And Preparation Thereof (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

Se describe un compilador canalizado de coincidencia algorítmica y un núcleo canalizado algorítmico reutilizable que comprende un sistema procesador de alto rendimiento. El núcleo canalizado algorítmico reutilizable es un núcleo de procesamiento reconfigurable con una estructura canalizada que comprende un procesador con una interfaz de configuración para programar cualquiera de una pluralidad de operaciones según lo determinado por los datos de configuración, un procesador de decisión lógica para programar una tabla de búsqueda, un contador de bucle y un registro constante y un bloque de memoria. Esto se puede usar para realizar funciones. Un circuito programable y reconfigurable enruta datos y resultados de un núcleo a otro núcleo y/o controlador 10 y/o generador de interrupción, según sea necesario para completar un algoritmo sin la intervención adicional de un procesador central o periférico durante el procesamiento de un algoritmo.
CONC2020/0000664A 2017-06-22 2020-01-22 Procesadores de alto rendimiento CO2020000664A2 (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201762523528P 2017-06-22 2017-06-22
PCT/US2018/039167 WO2018237361A1 (en) 2017-06-22 2018-06-22 HIGH SPEED PROCESSORS

Publications (1)

Publication Number Publication Date
CO2020000664A2 true CO2020000664A2 (es) 2020-05-05

Family

ID=64736139

Family Applications (1)

Application Number Title Priority Date Filing Date
CONC2020/0000664A CO2020000664A2 (es) 2017-06-22 2020-01-22 Procesadores de alto rendimiento

Country Status (17)

Country Link
US (1) US11436186B2 (es)
EP (1) EP3642706A4 (es)
JP (1) JP7183197B2 (es)
KR (1) KR20200031625A (es)
CN (1) CN110998513A (es)
AU (1) AU2018289605B2 (es)
BR (1) BR112019027531A2 (es)
CA (1) CA3067827A1 (es)
CL (1) CL2019003792A1 (es)
CO (1) CO2020000664A2 (es)
DO (1) DOP2019000311A (es)
IL (1) IL271746A (es)
PE (1) PE20200270A1 (es)
PH (1) PH12019502877A1 (es)
RU (1) RU2020102277A (es)
SG (1) SG11201912963SA (es)
WO (1) WO2018237361A1 (es)

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US12079097B2 (en) * 2020-10-20 2024-09-03 Nvidia Corporation Techniques for testing semiconductor devices
US11182221B1 (en) 2020-12-18 2021-11-23 SambaNova Systems, Inc. Inter-node buffer-based streaming for reconfigurable processor-as-a-service (RPaaS)
US11782760B2 (en) 2021-02-25 2023-10-10 SambaNova Systems, Inc. Time-multiplexed use of reconfigurable hardware
US11200096B1 (en) 2021-03-26 2021-12-14 SambaNova Systems, Inc. Resource allocation for reconfigurable processors
CN113360189B (zh) * 2021-06-04 2022-09-30 上海天旦网络科技发展有限公司 适用于流处理的异步优化方法、系统、装置和可读介质
TWI792546B (zh) * 2021-09-09 2023-02-11 瑞昱半導體股份有限公司 用於管線化控制的設備以及方法

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JP2002123563A (ja) * 2000-10-13 2002-04-26 Nec Corp コンパイル方法および合成装置ならびに記録媒体
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US7301368B2 (en) * 2005-03-15 2007-11-27 Tabula, Inc. Embedding memory within tile arrangement of a configurable IC
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US20060146864A1 (en) * 2004-12-30 2006-07-06 Rosenbluth Mark B Flexible use of compute allocation in a multi-threaded compute engines
EP1877927B1 (en) * 2005-04-28 2011-03-30 The University Court of the University of Edinburgh Reconfigurable instruction cell array
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Also Published As

Publication number Publication date
SG11201912963SA (en) 2020-01-30
US20200142857A1 (en) 2020-05-07
EP3642706A1 (en) 2020-04-29
BR112019027531A2 (pt) 2020-07-21
RU2020102277A (ru) 2021-07-22
JP2020525907A (ja) 2020-08-27
CN110998513A (zh) 2020-04-10
KR20200031625A (ko) 2020-03-24
EP3642706A4 (en) 2021-04-07
JP7183197B2 (ja) 2022-12-05
CL2019003792A1 (es) 2020-07-10
IL271746A (en) 2020-01-30
US11436186B2 (en) 2022-09-06
AU2018289605A1 (en) 2020-02-13
DOP2019000311A (es) 2020-06-15
CA3067827A1 (en) 2018-12-27
PE20200270A1 (es) 2020-02-04
AU2018289605B2 (en) 2023-04-27
WO2018237361A1 (en) 2018-12-27
PH12019502877A1 (en) 2020-12-07

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