PE20200270A1 - Procesadores de alto rendimiento - Google Patents

Procesadores de alto rendimiento

Info

Publication number
PE20200270A1
PE20200270A1 PE2019002611A PE2019002611A PE20200270A1 PE 20200270 A1 PE20200270 A1 PE 20200270A1 PE 2019002611 A PE2019002611 A PE 2019002611A PE 2019002611 A PE2019002611 A PE 2019002611A PE 20200270 A1 PE20200270 A1 PE 20200270A1
Authority
PE
Peru
Prior art keywords
core
processor
algorithmic
programming
high performance
Prior art date
Application number
PE2019002611A
Other languages
English (en)
Inventor
Robert D Catiller
Daniel Roig
Gnanashanmugam Elumalai
Original Assignee
Icat Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Icat Llc filed Critical Icat Llc
Publication of PE20200270A1 publication Critical patent/PE20200270A1/es

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/78Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/80Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Software Systems (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Advance Control (AREA)
  • Devices For Executing Special Programs (AREA)
  • Logic Circuits (AREA)
  • Mathematical Physics (AREA)
  • Microcomputers (AREA)
  • Organic Low-Molecular-Weight Compounds And Preparation Thereof (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

Se describe un compilador canalizado de coincidencia algoritmica y un nucleo canalizado algoritmico reutilizable que comprende un sistema procesador de alto rendimiento. El nucleo canalizado algoritmico reutilizable es un nucleo de procesamiento reconfigurable con. Una estructura canalizada que comprende un procesador con una interfaz de configuracion para programar cualquiera de una pluralidad de operaciones segun lo determinado por los datos de configuracion, un procesador de decision logica para programar una tabla de busqueda, un contador de bucle y un registro constante y un bloque de memoria. Esto se puede usar para realizar funciones. Un circuito programable y reconfigurable enruta datos y resultados de un nucleo a otro nucleo y/o controlador 10 y/o generador de interrupcion, segun sea necesario para completar un algoritmo sin la intervencion adicional de un procesador central o periferico durante el procesamiento de un algoritmo.
PE2019002611A 2017-06-22 2018-06-22 Procesadores de alto rendimiento PE20200270A1 (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201762523528P 2017-06-22 2017-06-22
PCT/US2018/039167 WO2018237361A1 (en) 2017-06-22 2018-06-22 HIGH SPEED PROCESSORS

Publications (1)

Publication Number Publication Date
PE20200270A1 true PE20200270A1 (es) 2020-02-04

Family

ID=64736139

Family Applications (1)

Application Number Title Priority Date Filing Date
PE2019002611A PE20200270A1 (es) 2017-06-22 2018-06-22 Procesadores de alto rendimiento

Country Status (17)

Country Link
US (1) US11436186B2 (es)
EP (1) EP3642706A4 (es)
JP (1) JP7183197B2 (es)
KR (1) KR20200031625A (es)
CN (1) CN110998513A (es)
AU (1) AU2018289605B2 (es)
BR (1) BR112019027531A2 (es)
CA (1) CA3067827A1 (es)
CL (1) CL2019003792A1 (es)
CO (1) CO2020000664A2 (es)
DO (1) DOP2019000311A (es)
IL (1) IL271746A (es)
PE (1) PE20200270A1 (es)
PH (1) PH12019502877A1 (es)
RU (1) RU2020102277A (es)
SG (1) SG11201912963SA (es)
WO (1) WO2018237361A1 (es)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12079097B2 (en) * 2020-10-20 2024-09-03 Nvidia Corporation Techniques for testing semiconductor devices
US11182221B1 (en) 2020-12-18 2021-11-23 SambaNova Systems, Inc. Inter-node buffer-based streaming for reconfigurable processor-as-a-service (RPaaS)
US11782760B2 (en) 2021-02-25 2023-10-10 SambaNova Systems, Inc. Time-multiplexed use of reconfigurable hardware
US11200096B1 (en) 2021-03-26 2021-12-14 SambaNova Systems, Inc. Resource allocation for reconfigurable processors
CN113360189B (zh) * 2021-06-04 2022-09-30 上海天旦网络科技发展有限公司 适用于流处理的异步优化方法、系统、装置和可读介质
TWI792546B (zh) * 2021-09-09 2023-02-11 瑞昱半導體股份有限公司 用於管線化控制的設備以及方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4291372A (en) 1979-06-27 1981-09-22 Burroughs Corporation Microprocessor system with specialized instruction format
JPH07101410B2 (ja) * 1990-01-17 1995-11-01 インターナショナル、ビジネス、マシーンズ、コーポレーション データ処理ネットワークにおいて逐次化手段の試験のため命令流の実行を同期させる方法
US5684980A (en) 1992-07-29 1997-11-04 Virtual Computer Corporation FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in response to those instructions
US6347344B1 (en) * 1998-10-14 2002-02-12 Hitachi, Ltd. Integrated multimedia system with local processor, data transfer switch, processing modules, fixed functional unit, data streamer, interface unit and multiplexer, all integrated on multimedia processor
JP2002123563A (ja) * 2000-10-13 2002-04-26 Nec Corp コンパイル方法および合成装置ならびに記録媒体
GB0028079D0 (en) * 2000-11-17 2001-01-03 Imperial College System and method
JP3561506B2 (ja) * 2001-05-10 2004-09-02 東京エレクトロンデバイス株式会社 演算システム
US20070277161A1 (en) * 2004-03-04 2007-11-29 Trustees Of Boston University System and Method for Programmable Logic Acceleration of Data Processing Applications and Compiler Therefore
US7301368B2 (en) * 2005-03-15 2007-11-27 Tabula, Inc. Embedding memory within tile arrangement of a configurable IC
US7673164B1 (en) 2004-12-13 2010-03-02 Massachusetts Institute Of Technology Managing power in a parallel processing environment
US20060146864A1 (en) * 2004-12-30 2006-07-06 Rosenbluth Mark B Flexible use of compute allocation in a multi-threaded compute engines
JP6059413B2 (ja) * 2005-04-28 2017-01-11 クアルコム,インコーポレイテッド 再構成可能命令セル・アレイ
GB2466821A (en) * 2009-01-08 2010-07-14 Advanced Risc Mach Ltd An FPGA with an embedded bus and dedicated bus interface circuits
GB201001621D0 (en) * 2010-02-01 2010-03-17 Univ Catholique Louvain A tile-based processor architecture model for high efficiency embedded homogenous multicore platforms
US8607247B2 (en) * 2011-11-03 2013-12-10 Advanced Micro Devices, Inc. Method and system for workitem synchronization
US20130157639A1 (en) * 2011-12-16 2013-06-20 SRC Computers, LLC Mobile electronic devices utilizing reconfigurable processing techniques to enable higher speed applications with lowered power consumption
US8959469B2 (en) * 2012-02-09 2015-02-17 Altera Corporation Configuring a programmable device using high-level language
US9535705B1 (en) * 2013-08-13 2017-01-03 Asher Hazanchuk Flexible hardware programmable scalable parallel processor
CN105431819A (zh) * 2013-09-06 2016-03-23 华为技术有限公司 异步处理器消除亚稳态的方法和装置
US9645937B2 (en) * 2015-08-28 2017-05-09 International Business Machines Corporation Expedited servicing of store operations in a data processing system

Also Published As

Publication number Publication date
CA3067827A1 (en) 2018-12-27
SG11201912963SA (en) 2020-01-30
CL2019003792A1 (es) 2020-07-10
IL271746A (en) 2020-01-30
US20200142857A1 (en) 2020-05-07
RU2020102277A (ru) 2021-07-22
EP3642706A4 (en) 2021-04-07
JP7183197B2 (ja) 2022-12-05
CO2020000664A2 (es) 2020-05-05
PH12019502877A1 (en) 2020-12-07
AU2018289605B2 (en) 2023-04-27
WO2018237361A1 (en) 2018-12-27
AU2018289605A1 (en) 2020-02-13
DOP2019000311A (es) 2020-06-15
US11436186B2 (en) 2022-09-06
JP2020525907A (ja) 2020-08-27
KR20200031625A (ko) 2020-03-24
CN110998513A (zh) 2020-04-10
BR112019027531A2 (pt) 2020-07-21
EP3642706A1 (en) 2020-04-29

Similar Documents

Publication Publication Date Title
CO2018008835A2 (es) Procesador con núcleo canalizado algoritmico reconfigurable y compilador canalizado de correlacion algoritmica
PE20200270A1 (es) Procesadores de alto rendimiento
US11645135B2 (en) Hardware apparatuses and methods for memory corruption detection
EP4354303A3 (en) Systems, methods, and apparatuses for matrix add, subtract, and multiply
JP2017157244A5 (es)
JP2019504403A5 (es)
KR101970597B1 (ko) Snow 3g 무선 보안 알고리즘을 가속화하기 위한 명령어
CL2017003263A1 (es) Arquitectura basada en bloques con ejecución paralela de bloques sucesivos.
US10255199B1 (en) Evicting clean secure pages without encryption
BR112017010075A2 (pt) processadores, métodos, sistemas e instruções de ajuste de coordenada de morton
JP2020511727A5 (es)
MX347759B (es) Comparar y reemplazar entrada de la tabla dat.
US9898300B2 (en) Instruction for fast ZUC algorithm processing
BR112015020272A2 (pt) método e dispositivo para atualização de firmware
BR112016021485A2 (pt) Pesquisa de encriptador com base em hash para cópia intrabloco
CN106663072B (zh) 用于配置中断的集合的装置和方法
GB2519813A (en) Pipelined configurable processor
BR112017010328A2 (pt) transferência de dados sem uso de fios com eficiência de energia
US10534611B2 (en) Branch prediction using multi-way pattern history table (PHT) and global path vector (GPV)
BR112017007876A2 (pt) aparelho de hardware de comutação de modo de smp/asmp rápida para um sistema de processador múltiplo de alta performance de potência baixa de custo baixo
US11238155B2 (en) Microarchitectural mechanisms for the prevention of side-channel attacks
CL2017002307A1 (es) Estilo controlado por condiciones
EP3547116A3 (en) Branch prediction based on coherence operations in processors
BR112018076270A8 (pt) Método e aparelho para realizar operações de coleta e cópia simd
MX2016011543A (es) Eficiencias de un sistema operativo/hipervisor para niveles de privilegios subdivididos.