MX347759B - Comparar y reemplazar entrada de la tabla dat. - Google Patents

Comparar y reemplazar entrada de la tabla dat.

Info

Publication number
MX347759B
MX347759B MX2014015347A MX2014015347A MX347759B MX 347759 B MX347759 B MX 347759B MX 2014015347 A MX2014015347 A MX 2014015347A MX 2014015347 A MX2014015347 A MX 2014015347A MX 347759 B MX347759 B MX 347759B
Authority
MX
Mexico
Prior art keywords
entry
operand
table entries
tlb
compare
Prior art date
Application number
MX2014015347A
Other languages
English (en)
Other versions
MX2014015347A (es
Inventor
Dan Greiner
Robert Rogers
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of MX2014015347A publication Critical patent/MX2014015347A/es
Publication of MX347759B publication Critical patent/MX347759B/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30047—Prefetch instructions; cache control instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G06F2212/683—Invalidation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Executing Machine-Instructions (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)

Abstract

Se compara un primer y segundo operandos. Si son iguales, el contenido del registro R1+1 se almacena en la ubicación del segundo operando, y la CUP o CPU especificadas en la configuración se despeja de todas las entradas de la tabla TLB del tipo designado, formadas a través del uso de la entrada reemplazando en el almacenamiento, y todas las entradas de la tabla TLB de nivel inferior formadas a través del uso de las entradas de la tabla TLB de nivel superior despejadas. Una estrada de la tabla DAT válida se emplaza con una nueva entrada, y la memoria intermedia de consulta de la traducción (TLB) se purga de cualquier copias de (al menos) la única entrada en todas las CPU en la configuración. Si el primer y segundo operandos son desiguales, el segundo operando se carga en la ubicación del primer operando. El resultado de la comparación se indica por el código de la condición. Se proporciona un método, un sistema y un producto de programa de computadora.
MX2014015347A 2012-06-15 2012-11-26 Comparar y reemplazar entrada de la tabla dat. MX347759B (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/524,468 US20130339656A1 (en) 2012-06-15 2012-06-15 Compare and Replace DAT Table Entry
PCT/IB2012/056736 WO2013186606A2 (en) 2012-06-15 2012-11-26 Compare and replace dat table entry

Publications (2)

Publication Number Publication Date
MX2014015347A MX2014015347A (es) 2015-07-06
MX347759B true MX347759B (es) 2017-05-10

Family

ID=49757047

Family Applications (1)

Application Number Title Priority Date Filing Date
MX2014015347A MX347759B (es) 2012-06-15 2012-11-26 Comparar y reemplazar entrada de la tabla dat.

Country Status (23)

Country Link
US (1) US20130339656A1 (es)
EP (1) EP2862089B1 (es)
JP (1) JP6202543B2 (es)
KR (1) KR101572409B1 (es)
CN (1) CN104903873B (es)
AU (1) AU2012382781B2 (es)
BR (1) BR112014031436B1 (es)
CA (1) CA2874186C (es)
DK (1) DK2862089T3 (es)
ES (1) ES2708331T3 (es)
HK (1) HK1210846A1 (es)
HR (1) HRP20190166T1 (es)
IL (1) IL236248A0 (es)
LT (1) LT2862089T (es)
MX (1) MX347759B (es)
PL (1) PL2862089T3 (es)
PT (1) PT2862089T (es)
RU (1) RU2550558C2 (es)
SG (1) SG11201407485RA (es)
SI (1) SI2862089T1 (es)
TW (1) TWI622880B (es)
WO (1) WO2013186606A2 (es)
ZA (1) ZA201408136B (es)

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WO2021085790A1 (ko) 2019-10-30 2021-05-06 박재범 다채널 사운드 시스템이 구비된 의자용 부재 및 이를 포함하는 의자
CA3156094C (en) 2019-10-30 2022-09-20 Tround Inc. Chair member provided with multi-channel sound system and chair comprising same
KR102333695B1 (ko) 2020-01-10 2021-12-02 박재범 다채널 사운드 시스템이 구비된 의자용 부재 및 이를 포함하는 의자
KR102359742B1 (ko) 2020-05-15 2022-02-08 박재범 다채널 사운드 시스템이 구비된 의자
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Also Published As

Publication number Publication date
DK2862089T3 (en) 2019-02-25
PL2862089T3 (pl) 2019-04-30
JP2015527632A (ja) 2015-09-17
US20130339656A1 (en) 2013-12-19
ES2708331T3 (es) 2019-04-09
AU2012382781B2 (en) 2016-06-02
KR101572409B1 (ko) 2015-12-04
TW201413454A (zh) 2014-04-01
EP2862089B1 (en) 2018-12-26
WO2013186606A2 (en) 2013-12-19
CN104903873B (zh) 2017-10-20
JP6202543B2 (ja) 2017-09-27
BR112014031436B1 (pt) 2021-08-10
WO2013186606A3 (en) 2015-06-11
MX2014015347A (es) 2015-07-06
TWI622880B (zh) 2018-05-01
KR20140138848A (ko) 2014-12-04
CA2874186C (en) 2020-09-22
SI2862089T1 (sl) 2019-03-29
EP2862089A4 (en) 2015-09-02
ZA201408136B (en) 2020-02-26
WO2013186606A8 (en) 2014-12-18
SG11201407485RA (en) 2014-12-30
PT2862089T (pt) 2019-02-04
EP2862089A2 (en) 2015-04-22
LT2862089T (lt) 2019-02-11
HK1210846A1 (en) 2016-05-06
BR112014031436A2 (pt) 2017-06-27
RU2550558C2 (ru) 2015-05-10
CN104903873A (zh) 2015-09-09
RU2012148399A (ru) 2014-05-20
HRP20190166T1 (hr) 2019-03-22
AU2012382781A1 (en) 2014-12-11
CA2874186A1 (en) 2013-12-19
IL236248A0 (en) 2015-01-29

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