BR112017011115A2 - método e aparelho para realizar uma coleta de bit de vetor - Google Patents
método e aparelho para realizar uma coleta de bit de vetorInfo
- Publication number
- BR112017011115A2 BR112017011115A2 BR112017011115A BR112017011115A BR112017011115A2 BR 112017011115 A2 BR112017011115 A2 BR 112017011115A2 BR 112017011115 A BR112017011115 A BR 112017011115A BR 112017011115 A BR112017011115 A BR 112017011115A BR 112017011115 A2 BR112017011115 A2 BR 112017011115A2
- Authority
- BR
- Brazil
- Prior art keywords
- bit
- vector
- source data
- data elements
- register
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30018—Bit or string instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Executing Machine-Instructions (AREA)
- Complex Calculations (AREA)
- Advance Control (AREA)
Abstract
?método e aparelho para realizar uma coleta de bit de vetor? trata-se de um aparelho e método para realizar uma coleta de bit de vetor. por exemplo, uma modalidade de um processador compreende: um primeiro registro de vetor para armazenar um ou mais elementos de dados de origem; um segundo registro de vetor para armazenar um ou mais elementos de controle, em que cada um dentre os elementos de controle compreende uma pluralidade de campos de bit, em que cada campo de bit deve ser associado a uma posição de bit correspondente em um registro de vetor de destino e para identificar um bit a partir de um ou mais elementos de dados de origem a serem copiados para cada uma dentre as posições de bit particulares; e lógica de coleta de bit de vetor para ler cada campo de bit do segundo registro de vetor para identificar um bit a partir de um ou mais elementos de dados de origem e para copiar de modo responsivo o bit de cada um dentre os um ou mais elementos de dados de origem para cada uma dentre as posições de bit correspondentes no registro de vetor de destino.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/583,639 US10296334B2 (en) | 2014-12-27 | 2014-12-27 | Method and apparatus for performing a vector bit gather |
| PCT/US2015/062565 WO2016105820A1 (en) | 2014-12-27 | 2015-11-25 | Method and apparatus for performing a vector bit gather |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| BR112017011115A2 true BR112017011115A2 (pt) | 2017-12-26 |
Family
ID=56151354
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| BR112017011115A BR112017011115A2 (pt) | 2014-12-27 | 2015-11-25 | método e aparelho para realizar uma coleta de bit de vetor |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US10296334B2 (pt) |
| EP (1) | EP3238036B1 (pt) |
| JP (1) | JP2018500666A (pt) |
| KR (1) | KR102528073B1 (pt) |
| CN (1) | CN107077333B (pt) |
| BR (1) | BR112017011115A2 (pt) |
| SG (1) | SG11201704324VA (pt) |
| TW (1) | TWI657372B (pt) |
| WO (1) | WO2016105820A1 (pt) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10296489B2 (en) * | 2014-12-27 | 2019-05-21 | Intel Corporation | Method and apparatus for performing a vector bit shuffle |
| WO2018158603A1 (en) * | 2017-02-28 | 2018-09-07 | Intel Corporation | Strideshift instruction for transposing bits inside vector register |
Family Cites Families (30)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB9513515D0 (en) * | 1995-07-03 | 1995-09-06 | Sgs Thomson Microelectronics | Expansion of data |
| US5838984A (en) * | 1996-08-19 | 1998-11-17 | Samsung Electronics Co., Ltd. | Single-instruction-multiple-data processing using multiple banks of vector registers |
| US6816961B2 (en) | 2000-03-08 | 2004-11-09 | Sun Microsystems, Inc. | Processing architecture having field swapping capability |
| JP2004507144A (ja) * | 2000-08-11 | 2004-03-04 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Σδ変調器を同期させる方法および装置 |
| US20020188830A1 (en) | 2001-06-01 | 2002-12-12 | Brian Boles | Bit replacement and extraction instructions |
| US20040054877A1 (en) * | 2001-10-29 | 2004-03-18 | Macy William W. | Method and apparatus for shuffling data |
| US6963341B1 (en) * | 2002-06-03 | 2005-11-08 | Tibet MIMAR | Fast and flexible scan conversion and matrix transpose in a SIMD processor |
| GB2409065B (en) * | 2003-12-09 | 2006-10-25 | Advanced Risc Mach Ltd | Multiplexing operations in SIMD processing |
| US7014122B2 (en) * | 2003-12-24 | 2006-03-21 | International Business Machines Corporation | Method and apparatus for performing bit-aligned permute |
| US8078836B2 (en) | 2007-12-30 | 2011-12-13 | Intel Corporation | Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a common set of per-lane control bits |
| US8447962B2 (en) * | 2009-12-22 | 2013-05-21 | Intel Corporation | Gathering and scattering multiple data elements |
| US20120239910A1 (en) * | 2008-08-15 | 2012-09-20 | Apple Inc. | Conditional extract instruction for processing vectors |
| US20110035568A1 (en) * | 2008-08-15 | 2011-02-10 | Apple Inc. | Select first and select last instructions for processing vectors |
| JP2012033032A (ja) * | 2010-07-30 | 2012-02-16 | Sony Corp | 情報処理装置および情報処理方法 |
| US20120060016A1 (en) * | 2010-09-07 | 2012-03-08 | International Business Machines Corporation | Vector Loads from Scattered Memory Locations |
| US8539206B2 (en) * | 2010-09-24 | 2013-09-17 | Intel Corporation | Method and apparatus for universal logical operations utilizing value indexing |
| WO2012131433A1 (en) | 2011-03-30 | 2012-10-04 | Freescale Semiconductor, Inc. | Integrated circuit device and methods of performing bit manipulation therefor |
| PL3422178T3 (pl) * | 2011-04-01 | 2023-06-26 | Intel Corporation | Przyjazny dla wektorów format instrukcji i jego wykonanie |
| US8688962B2 (en) * | 2011-04-01 | 2014-04-01 | Intel Corporation | Gather cache architecture |
| CN103827813B (zh) * | 2011-09-26 | 2016-09-21 | 英特尔公司 | 用于提供向量分散操作和聚集操作功能的指令和逻辑 |
| CN104011670B (zh) * | 2011-12-22 | 2016-12-28 | 英特尔公司 | 用于基于向量写掩码的内容而在通用寄存器中存储两个标量常数之一的指令 |
| US20140059322A1 (en) * | 2011-12-23 | 2014-02-27 | Elmoustapha Ould-Ahmed-Vall | Apparatus and method for broadcasting from a general purpose register to a vector register |
| CN107092465B (zh) * | 2011-12-23 | 2021-06-29 | 英特尔公司 | 用于提供向量混合和置换功能的指令和逻辑 |
| WO2013095603A1 (en) | 2011-12-23 | 2013-06-27 | Intel Corporation | Apparatus and method for down conversion of data types |
| CN114721721A (zh) * | 2011-12-23 | 2022-07-08 | 英特尔公司 | 用于混洗浮点或整数值的装置和方法 |
| WO2013101198A1 (en) * | 2011-12-30 | 2013-07-04 | Intel Corporation | Simd variable shift and rotate using control manipulation |
| US8972697B2 (en) * | 2012-06-02 | 2015-03-03 | Intel Corporation | Gather using index array and finite state machine |
| US9342479B2 (en) | 2012-08-23 | 2016-05-17 | Qualcomm Incorporated | Systems and methods of data extraction in a vector processor |
| CN105229599B (zh) | 2013-03-15 | 2017-12-12 | 甲骨文国际公司 | 用于单指令多数据处理器的高效硬件指令 |
| US10296489B2 (en) * | 2014-12-27 | 2019-05-21 | Intel Corporation | Method and apparatus for performing a vector bit shuffle |
-
2014
- 2014-12-27 US US14/583,639 patent/US10296334B2/en active Active
-
2015
- 2015-11-25 BR BR112017011115A patent/BR112017011115A2/pt not_active Application Discontinuation
- 2015-11-25 EP EP15874024.1A patent/EP3238036B1/en active Active
- 2015-11-25 JP JP2017528483A patent/JP2018500666A/ja active Pending
- 2015-11-25 CN CN201580064464.1A patent/CN107077333B/zh active Active
- 2015-11-25 SG SG11201704324VA patent/SG11201704324VA/en unknown
- 2015-11-25 WO PCT/US2015/062565 patent/WO2016105820A1/en active Application Filing
- 2015-11-25 KR KR1020177014407A patent/KR102528073B1/ko active IP Right Grant
- 2015-11-26 TW TW104139442A patent/TWI657372B/zh active
Also Published As
| Publication number | Publication date |
|---|---|
| KR102528073B1 (ko) | 2023-05-03 |
| JP2018500666A (ja) | 2018-01-11 |
| TWI657372B (zh) | 2019-04-21 |
| US10296334B2 (en) | 2019-05-21 |
| TW201640339A (zh) | 2016-11-16 |
| WO2016105820A1 (en) | 2016-06-30 |
| KR20170098806A (ko) | 2017-08-30 |
| CN107077333A (zh) | 2017-08-18 |
| SG11201704324VA (en) | 2017-07-28 |
| CN107077333B (zh) | 2021-06-08 |
| EP3238036A4 (en) | 2018-08-29 |
| EP3238036A1 (en) | 2017-11-01 |
| US20160188335A1 (en) | 2016-06-30 |
| EP3238036B1 (en) | 2020-10-14 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| B06U | Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette] | ||
| B11B | Dismissal acc. art. 36, par 1 of ipl - no reply within 90 days to fullfil the necessary requirements |