BR112015029810A2 - aparelho e método para reverter e permutar bits em um registro de máscara - Google Patents

aparelho e método para reverter e permutar bits em um registro de máscara

Info

Publication number
BR112015029810A2
BR112015029810A2 BR112015029810A BR112015029810A BR112015029810A2 BR 112015029810 A2 BR112015029810 A2 BR 112015029810A2 BR 112015029810 A BR112015029810 A BR 112015029810A BR 112015029810 A BR112015029810 A BR 112015029810A BR 112015029810 A2 BR112015029810 A2 BR 112015029810A2
Authority
BR
Brazil
Prior art keywords
mask
mask register
bit
bits
reversing
Prior art date
Application number
BR112015029810A
Other languages
English (en)
Other versions
BR112015029810A8 (pt
Inventor
Ould-Ahmed-Vall Elmoustapha
Valentine Robert
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of BR112015029810A2 publication Critical patent/BR112015029810A2/pt
Publication of BR112015029810A8 publication Critical patent/BR112015029810A8/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018—Bit or string instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Complex Calculations (AREA)
  • Image Processing (AREA)
  • Image Analysis (AREA)

Abstract

“aparelho e método para reverter e permutar bits em um registro de máscara” trata-se de um aparelho e método para realizar uma reversão de bit e permutação em valores de máscara. por exemplo, um processador é descrito para executar uma instrução a fim de realizar as operações de: ler uma pluralidade de bits de máscara armazenada em um registro de máscara de fonte, em que os bits de máscara são associados aos elementos de dados de vetor de um registro de vetor; e realizar uma operação de reversão de bit para copiar cada bit de máscara de um registro de máscara de fonte para um registro de máscara de destinação, em que a operação de reversão de bit faz com que os bits do registro de máscara de fonte sejam revertidos dentro do registro de máscara de destinação resultando em uma imagem espelhada simétrica da disposição de bit original.
BR112015029810A 2013-06-27 2014-06-17 conjugados medicamentosos de anticorpos, composição farmacêutica, kit, processo para a preparação e seu uso BR112015029810A8 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/929,563 US9645820B2 (en) 2013-06-27 2013-06-27 Apparatus and method to reserve and permute bits in a mask register
PCT/US2014/042789 WO2014209685A1 (en) 2013-06-27 2014-06-17 Apparatus and method to reverse and permute bits in a mask register

Publications (2)

Publication Number Publication Date
BR112015029810A2 true BR112015029810A2 (pt) 2017-07-25
BR112015029810A8 BR112015029810A8 (pt) 2019-12-24

Family

ID=52116842

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112015029810A BR112015029810A8 (pt) 2013-06-27 2014-06-17 conjugados medicamentosos de anticorpos, composição farmacêutica, kit, processo para a preparação e seu uso

Country Status (8)

Country Link
US (4) US9645820B2 (pt)
EP (1) EP3014417A4 (pt)
KR (2) KR101966713B1 (pt)
CN (2) CN105247474B (pt)
BR (1) BR112015029810A8 (pt)
RU (1) RU2636669C2 (pt)
TW (2) TWI575447B (pt)
WO (1) WO2014209685A1 (pt)

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Also Published As

Publication number Publication date
US10387148B2 (en) 2019-08-20
CN105247474A (zh) 2016-01-13
CN108052349B (zh) 2022-06-10
CN105247474B (zh) 2019-06-18
TWI575447B (zh) 2017-03-21
US10387149B2 (en) 2019-08-20
US20170220350A1 (en) 2017-08-03
TW201737063A (zh) 2017-10-16
KR20170027883A (ko) 2017-03-10
US20180039497A1 (en) 2018-02-08
US20150006847A1 (en) 2015-01-01
TWI641993B (zh) 2018-11-21
KR101966713B1 (ko) 2019-04-09
BR112015029810A8 (pt) 2019-12-24
TW201510862A (zh) 2015-03-16
US10209988B2 (en) 2019-02-19
EP3014417A4 (en) 2017-06-21
WO2014209685A1 (en) 2014-12-31
RU2015151187A (ru) 2017-06-01
US9645820B2 (en) 2017-05-09
RU2636669C2 (ru) 2017-11-27
US20180052686A1 (en) 2018-02-22
EP3014417A1 (en) 2016-05-04
KR101713841B1 (ko) 2017-03-09
KR20150138319A (ko) 2015-12-09
CN108052349A (zh) 2018-05-18

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Legal Events

Date Code Title Description
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B11B Dismissal acc. art. 36, par 1 of ipl - no reply within 90 days to fullfil the necessary requirements
B350 Update of information on the portal [chapter 15.35 patent gazette]