MX2017007060A - Método para acceder a los datos en una memoria en una dirección no alineada. - Google Patents

Método para acceder a los datos en una memoria en una dirección no alineada.

Info

Publication number
MX2017007060A
MX2017007060A MX2017007060A MX2017007060A MX2017007060A MX 2017007060 A MX2017007060 A MX 2017007060A MX 2017007060 A MX2017007060 A MX 2017007060A MX 2017007060 A MX2017007060 A MX 2017007060A MX 2017007060 A MX2017007060 A MX 2017007060A
Authority
MX
Mexico
Prior art keywords
memory
data
accessing
accessing data
address
Prior art date
Application number
MX2017007060A
Other languages
English (en)
Inventor
Jacobi Christian
David Bradbury Jonathan
Slegel Timothy
Karl Gschwind Michael
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of MX2017007060A publication Critical patent/MX2017007060A/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/04—Addressing variable-length words or parts of words
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30192—Instruction operation extension or modification according to data descriptor, e.g. dynamic data typing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1008—Correctness of operation, e.g. memory ordering
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1041—Resource optimization
    • G06F2212/1044—Space efficiency improvement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/25—Using a specific main memory architecture
    • G06F2212/251—Local memory within processor subsystem
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/656—Address space sharing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Executing Machine-Instructions (AREA)
  • Multi Processors (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

Un método para acceder a los datos en una memoria acoplada a un procesador, que comprende: recibir una instrucción de la referencia de la memoria para acceder a los datos de un primer tamaño en una dirección en la memoria; determinar un tamaño de la alineación de la dirección en la memoria; y acceder a los datos del primer tamaño en uno o más grupos de datos accediendo a cada bloque de grupo de datos de manera concurrente. Los grupos de datos tienen tamaños que son múltiplos del tamaño de la alineación.
MX2017007060A 2014-12-04 2015-10-30 Método para acceder a los datos en una memoria en una dirección no alineada. MX2017007060A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/560,486 US9582413B2 (en) 2014-12-04 2014-12-04 Alignment based block concurrency for accessing memory
PCT/EP2015/075231 WO2016087138A1 (en) 2014-12-04 2015-10-30 Method for accessing data in a memory at an unaligned address

Publications (1)

Publication Number Publication Date
MX2017007060A true MX2017007060A (es) 2017-11-08

Family

ID=54366218

Family Applications (1)

Application Number Title Priority Date Filing Date
MX2017007060A MX2017007060A (es) 2014-12-04 2015-10-30 Método para acceder a los datos en una memoria en una dirección no alineada.

Country Status (14)

Country Link
US (4) US9582413B2 (es)
EP (1) EP3227773B1 (es)
JP (1) JP6664105B2 (es)
KR (1) KR101976296B1 (es)
CN (1) CN107003957B (es)
AU (1) AU2015357677B2 (es)
BR (1) BR112017011910B1 (es)
CA (1) CA2961708C (es)
MX (1) MX2017007060A (es)
RU (1) RU2675509C1 (es)
SG (1) SG11201701609VA (es)
TW (1) TWI607307B (es)
WO (1) WO2016087138A1 (es)
ZA (1) ZA201704122B (es)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
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US9582413B2 (en) 2014-12-04 2017-02-28 International Business Machines Corporation Alignment based block concurrency for accessing memory
WO2019055738A1 (en) * 2017-09-15 2019-03-21 MIPS Tech, LLC MEMORY ACCESS NOT ALIGNED
WO2020037542A1 (zh) * 2018-08-22 2020-02-27 深圳市大疆创新科技有限公司 数据指令处理方法、存储芯片、存储系统和可移动平台
FR3093571B1 (fr) * 2019-03-08 2021-03-19 Commissariat Energie Atomique Procédé et dispositif de représentation en virgule flottante avec précision variable
US11036506B1 (en) * 2019-12-11 2021-06-15 Motorola Solutions, Inc. Memory systems and methods for handling vector data
CN111338997B (zh) * 2020-03-05 2021-07-20 苏州浪潮智能科技有限公司 一种arm服务器bios支持tcm通信的方法、装置、设备和介质

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Also Published As

Publication number Publication date
KR20170073688A (ko) 2017-06-28
US9582413B2 (en) 2017-02-28
EP3227773A1 (en) 2017-10-11
CN107003957B (zh) 2020-01-17
CA2961708A1 (en) 2016-06-09
US20160162400A1 (en) 2016-06-09
JP2018501554A (ja) 2018-01-18
KR101976296B1 (ko) 2019-05-07
RU2675509C1 (ru) 2018-12-20
BR112017011910A2 (pt) 2018-01-16
BR112017011910B1 (pt) 2023-04-04
WO2016087138A1 (en) 2016-06-09
US9904618B2 (en) 2018-02-27
US9910769B2 (en) 2018-03-06
CA2961708C (en) 2023-09-26
US10579514B2 (en) 2020-03-03
TW201621667A (zh) 2016-06-16
US20170123967A1 (en) 2017-05-04
JP6664105B2 (ja) 2020-03-13
TWI607307B (zh) 2017-12-01
SG11201701609VA (en) 2017-03-30
EP3227773B1 (en) 2020-05-20
AU2015357677A1 (en) 2017-03-09
US20180074950A1 (en) 2018-03-15
AU2015357677B2 (en) 2018-11-08
CN107003957A (zh) 2017-08-01
US20160162401A1 (en) 2016-06-09
ZA201704122B (en) 2018-11-28

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