WO2020037542A1 - 数据指令处理方法、存储芯片、存储系统和可移动平台 - Google Patents

数据指令处理方法、存储芯片、存储系统和可移动平台 Download PDF

Info

Publication number
WO2020037542A1
WO2020037542A1 PCT/CN2018/101718 CN2018101718W WO2020037542A1 WO 2020037542 A1 WO2020037542 A1 WO 2020037542A1 CN 2018101718 W CN2018101718 W CN 2018101718W WO 2020037542 A1 WO2020037542 A1 WO 2020037542A1
Authority
WO
WIPO (PCT)
Prior art keywords
instruction
memory
data
chip
memory chip
Prior art date
Application number
PCT/CN2018/101718
Other languages
English (en)
French (fr)
Inventor
庹伟
宋喆喆
张强
Original Assignee
深圳市大疆创新科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市大疆创新科技有限公司 filed Critical 深圳市大疆创新科技有限公司
Priority to PCT/CN2018/101718 priority Critical patent/WO2020037542A1/zh
Priority to CN201880039744.0A priority patent/CN110770699A/zh
Publication of WO2020037542A1 publication Critical patent/WO2020037542A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/445—Program loading or initiating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management

Definitions

  • Embodiments of the present invention relate to the field of storage technologies, and in particular, to a data instruction processing method, a storage chip, a storage system, and a removable platform.
  • DDR solid State Drive
  • SSD Solid State Drive
  • the existing DDR memory follows the Non-Volatile Memory Controller Interface Specification (NVME).
  • NVME Non-Volatile Memory Controller Interface Specification
  • the NVME driver runs on the DDR memory, so image data can be read or written from the DDR memory through NVME commands.
  • the CPU because the central processing unit (CPU) in cameras, camcorders and other products generally has limited performance, the CPU generates an NVME command, first stores the NVME command in a DDR memory, and notifies the SSD.
  • the SSD reads the NVME command from the DDR memory, and then executes the NVME command.
  • For each NVME command there is a process of entering and exiting the DDR memory, but because the DDR memory access delay is large, this will cause the execution time of each NVME command to be longer and the storage efficiency to be reduced.
  • Embodiments of the present invention provide a data instruction processing method, a storage chip, a storage system, and a movable platform, which are used to reduce the execution time of data instructions and improve storage efficiency.
  • an embodiment of the present invention provides a data instruction processing method, which is applied to a memory chip and includes:
  • the instruction information includes a storage address of the data instruction, so that the first memory obtains the data instruction from a storage unit in the storage chip according to the storage address.
  • an embodiment of the present invention provides a memory chip, including: a processor and a storage unit;
  • a processor configured to generate a data instruction and write the data instruction into a storage unit in the memory chip, and send instruction information to a first memory outside the memory chip;
  • the instruction information includes a storage address of the data instruction, so that the first memory is based on The storage address obtains a data instruction from a storage unit of the storage chip;
  • a storage unit for storing data instructions.
  • an embodiment of the present invention provides a memory system, including: a memory chip and a first memory external to the memory chip;
  • a memory chip configured to generate a data instruction and write the data instruction into a storage unit in the memory chip; and send instruction information to the first memory, where the instruction information includes a storage address of the data instruction;
  • the first memory is configured to obtain a data instruction from a storage unit in the storage chip according to the storage address.
  • an embodiment of the present invention provides a movable platform including a fuselage and a storage system according to the embodiment of the third aspect of the present invention.
  • the storage system is provided on the fuselage.
  • an embodiment of the present invention provides a computer-readable storage medium.
  • the computer-readable storage medium stores a computer program, where the computer program includes at least one piece of code, and the at least one piece of code can be executed by a computer to control all
  • the computer executes the data instruction processing method according to the embodiment of the present invention in the first aspect.
  • an embodiment of the present invention provides a computer program for implementing the data instruction processing method according to the first aspect of the present invention when the computer program is executed by a computer.
  • the data instruction processing method, storage chip, storage system and removable platform provided by the embodiments of the present invention generate data instructions by writing data instructions into a storage unit in the storage chip and send an instruction to a first memory outside the storage chip.
  • Information wherein the instruction information includes a storage address of the data instruction, and then the first memory obtains the data instruction from a storage unit in the storage chip according to the storage address.
  • the written data can be written into the memory cell in the memory chip to write data.
  • the instruction time is shorter, and the first memory obtains the data instruction directly from the storage unit in the memory chip.
  • the first instruction in the embodiment of the present invention The time for the memory to obtain the data instruction is shorter, thereby reducing the execution time of the data instruction and improving the storage efficiency.
  • FIG. 1 is a schematic architecture diagram of an unmanned flight system according to an embodiment of the present invention
  • FIG. 2 is a flowchart of a data instruction processing method according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a memory chip according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a storage system according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a movable platform according to an embodiment of the present invention.
  • a component when a component is called “fixed to” another component, it may be directly on another component or a centered component may exist. When a component is considered to be “connected” to another component, it can be directly connected to another component or a centered component may exist at the same time.
  • Embodiments of the present invention provide a data instruction processing method, a storage chip, a storage system, and a removable platform.
  • the movable platform may be, for example, a drone, an unmanned ship, an unmanned car, a robot, a handheld electronic device, or the like.
  • the drone may be a rotorcraft, for example, a multi-rotor aircraft propelled by multiple propulsion devices through air, and the embodiment of the present invention is not limited thereto.
  • FIG. 1 is a schematic architecture diagram of an unmanned flight system according to an embodiment of the present invention. This embodiment is described by taking a rotary wing drone as an example.
  • the unmanned aerial system 100 may include a drone 110, a display device 130, and a control terminal 140.
  • the UAV 110 may include a power system 150, a flight control system 160, a rack, and a gimbal 120 carried on the rack.
  • the drone 110 may perform wireless communication with the control terminal 140 and the display device 130.
  • the frame may include a fuselage and a tripod (also called a landing gear).
  • the fuselage may include a center frame and one or more arms connected to the center frame, and one or more arms extend radially from the center frame.
  • the tripod is connected to the fuselage, and is used to support the UAV 110 when landing.
  • the power system 150 may include one or more electronic governors (referred to as ESCs) 151, one or more propellers 153, and one or more electric motors 152 corresponding to the one or more propellers 153.
  • the electric motors 152 are connected to Between the electronic governor 151 and the propeller 153, the motor 152 and the propeller 153 are arranged on the arm of the drone 110; the electronic governor 151 is used to receive the driving signal generated by the flight control system 160 and provide driving according to the driving signal Current is supplied to the motor 152 to control the rotation speed of the motor 152.
  • the motor 152 is used to drive the propeller to rotate, so as to provide power for the flight of the drone 110, and the power enables the drone 110 to achieve one or more degrees of freedom.
  • the drone 110 may rotate about one or more rotation axes.
  • the rotation axis may include a roll axis (Roll), a yaw axis (Yaw), and a pitch axis (Pitch).
  • the motor 152 may be a DC motor or an AC motor.
  • the motor 152 may be a brushless motor or a brushed motor.
  • the flight control system 160 may include a flight controller 161 and a sensing system 162.
  • the sensing system 162 is used to measure the attitude information of the drone, that is, the position information and status information of the drone 110 in space, such as three-dimensional position, three-dimensional angle, three-dimensional velocity, three-dimensional acceleration, and three-dimensional angular velocity.
  • the sensing system 162 may include, for example, at least one of a gyroscope, an ultrasonic sensor, an electronic compass, an Inertial Measurement Unit (IMU), a vision sensor, a global navigation satellite system, and a barometer.
  • the global navigation satellite system may be a Global Positioning System (Global Positioning System, GPS).
  • the flight controller 161 is used to control the flight of the drone 110.
  • the flight controller 161 may control the flight of the drone 110 according to the attitude information measured by the sensing system 162. It should be understood that the flight controller 161 may control the drone 110 according to a pre-programmed program instruction, and may also control the drone 110 by responding to one or more control instructions from the control terminal 140.
  • the gimbal 120 may include a motor 122.
  • the gimbal is used to carry the photographing device 123.
  • the flight controller 161 may control the movement of the gimbal 120 through the motor 122.
  • the PTZ 120 may further include a controller for controlling the movement of the PTZ 120 by controlling the motor 122.
  • the gimbal 120 may be independent of the drone 110 or may be a part of the drone 110.
  • the motor 122 may be a DC motor or an AC motor.
  • the motor 122 may be a brushless motor or a brushed motor.
  • the gimbal can be located on the top of the drone or on the bottom of the drone.
  • the photographing device 123 may be, for example, a device for capturing an image, such as a camera or a video camera.
  • the photographing device 123 may communicate with the flight controller and perform shooting under the control of the flight controller.
  • the photographing device 123 of this embodiment includes at least a photosensitive element.
  • the photosensitive element is, for example, a complementary metal oxide semiconductor (CMOS) sensor or a charge-coupled device (CCD) sensor. It can be understood that the shooting device 123 can also be directly fixed on the drone 110, so that the PTZ 120 can be omitted.
  • CMOS complementary metal oxide semiconductor
  • CCD charge-coupled device
  • the display device 130 is located on the ground side of the unmanned flight system 100, can communicate with the drone 110 wirelessly, and can be used to display attitude information of the drone 110. In addition, an image captured by the imaging device may be displayed on the display device 130. It should be understood that the display device 130 may be an independent device, or may be integrated in the control terminal 140.
  • the control terminal 140 is located on the ground side of the unmanned flight system 100 and can communicate with the unmanned aerial vehicle 110 in a wireless manner for remotely controlling the unmanned aerial vehicle 110.
  • the drone 110 may further include a speaker (not shown) for playing audio files.
  • the speaker may be directly fixed on the drone 110 or may be mounted on the gimbal 120.
  • each component of the unmanned flight system is for identification purposes only, and should not be construed as limiting the embodiments of the present invention.
  • the memory chip described in the following embodiments may be deployed in the above-mentioned shooting device 123, for example.
  • FIG. 2 is a flowchart of a data instruction processing method according to an embodiment of the present invention. As shown in FIG. 2, the method in this embodiment may include:
  • the memory chip generates a data instruction.
  • the memory chip in this embodiment can generate a data instruction.
  • it may be a processor in a memory chip, such as a Central Processing Unit (CPU), which generates data instructions.
  • the data instruction may be, for example, an instruction for processing data, and processing the data may include reading data or writing data, and so on.
  • the data instruction may be, for example, an identification instruction.
  • the generated data instruction may be an instruction based on image data, for example, the above-mentioned processing of data includes processing of image data.
  • the data instruction may be a data instruction based on a non-volatile memory host controller interface specification (Non-Volatile Memory Express (NVME) protocol).
  • the data instructions based on the NVME protocol may include, for example, Input / Output (I / O) instructions and admin instructions.
  • the I / O instruction may include, for example, a data read instruction and a data write instruction.
  • the data instruction may also be a data instruction based on the Serial ATA Advanced Host Interface / Advanced Host Controller Interface (Serial ATA Advanced Host Controller Interface) protocol.
  • the storage chip writes a data instruction into a storage unit in the storage chip.
  • the storage chip in this embodiment may write the data instructions generated above into a storage unit of the storage chip.
  • the memory chip may be a Field-Programmable Gate Array (FPGA) chip.
  • the FPGA chip may be, for example, an FPGA chip with a system-on-chip (SOC).
  • the memory chip sends instruction information to a first memory external to the memory chip, where the instruction information includes a storage address of a data instruction.
  • the memory chip in this embodiment After the memory chip in this embodiment writes a data instruction to a memory unit in the memory chip, it sends instruction information to a first memory outside the memory chip.
  • the memory chip in this embodiment may also send instruction information to the first memory outside the memory chip after determining the storage address of the data instruction, and the instruction information includes the storage address of the data instruction.
  • the instruction information may include, for example, a start address of a data instruction in a storage unit inside the memory chip and a size of the data instruction.
  • the execution order of S202 and S203 can be adjusted according to needs in addition to the content described above.
  • the execution order of S202 and S203 is not limited herein.
  • the first memory may be a non-volatile memory, for example, a solid state drive (Solid State Drive, SSD).
  • Solid State Drive SSD
  • the memory chip is an FPGA chip
  • the FPGA chip and the SSD can communicate through a high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express (PCIE)).
  • PCIE Peripheral Component Interconnect Express
  • the first memory obtains a data instruction from a storage unit in the memory chip according to a storage address of the data instruction.
  • the first memory receives instruction information sent by the memory chip, and the instruction information includes a storage address of a data instruction.
  • the data instruction is obtained from a storage unit in the memory chip according to a storage address of the data instruction.
  • the data instruction processing method provided in this embodiment generates a data instruction, writes the data instruction into a storage unit in a memory chip, and sends instruction information to a first memory external to the memory chip, where the instruction information includes storage of the data instruction Address, and the first memory obtains a data instruction from a storage unit in the memory chip according to the storage address.
  • the write data instruction can be made by writing the generated data instruction to the memory unit in the memory chip
  • the time is shorter, and the first memory obtains data instructions directly from a memory unit in the memory chip.
  • the first memory obtains data instructions in this embodiment.
  • the time of the data instruction is shorter, thereby reducing the execution time of the data instruction and improving the storage efficiency.
  • the memory chip in this embodiment can selectively write the generated data instructions into a memory unit in the memory chip.
  • the memory chip before the memory chip writes the data instruction into the storage unit in the memory chip, it also determines the instruction type of the data instruction.
  • an implementation manner in which the memory chip writes the data instruction into the storage unit in the memory chip may be: if the instruction type of the data instruction belongs to the first instruction type, the memory chip writes the data instruction into the storage in the memory chip. Unit.
  • the memory chip writes the data instruction into a second memory external to the memory chip.
  • the first memory is a non-volatile memory
  • the second memory is a volatile memory.
  • the first memory is an SSD
  • the second memory is a DDR memory.
  • this embodiment guarantees that a data instruction belonging to the first instruction type is written into the storage unit of the memory chip as much as possible.
  • the memory chip may divide the generated data instruction into a first instruction type and a second instruction type according to a preset rule.
  • the preset rules can be flexibly set by the user according to the actual needs, so that the data instructions can be written into the storage unit inside the storage chip in a targeted manner.
  • the preset rule may include, for example, a mapping relationship between a data instruction and an associated instruction type.
  • the preset rules may specify that the A instruction, the B instruction, and the C instruction belong to the first instruction type, and the D instruction and the E instruction belong to the second instruction type, where the A instruction, the B instruction, the C instruction, the D instruction, and the E instruction represent different data. instruction.
  • the memory chip may divide the generated data instructions into two types (a first instruction type and a second instruction type) according to the acquisition frequency of the data instructions.
  • the first instruction type is an instruction whose acquisition frequency is greater than a preset frequency
  • the second instruction type is an instruction whose acquisition frequency is less than or equal to the preset frequency.
  • the acquisition frequency of the data instruction may be preset or statistically obtained, and updated at a preset period.
  • the memory chip may write a data instruction whose acquired frequency is greater than a preset frequency into a storage unit in the memory chip, and the memory chip may further write a data instruction whose acquired frequency is less than or equal to the preset frequency into the memory chip. External second storage.
  • writing data instructions with a high frequency of acquisition into a memory cell inside the memory chip it is possible to avoid data instructions with a low frequency of acquisition from occupying the memory resources inside the memory chip, and ensure that the memory cells inside the memory chip have sufficient
  • the storage resource is used to store data instructions that are fetched more frequently, and also improves the utilization efficiency of the internal storage unit of the memory chip, further improving the overall storage efficiency.
  • writing data instructions with a high frequency of acquisition into a memory unit inside the memory chip can reduce the time required to obtain this type of data instructions, thereby improving the efficiency of data instruction execution, especially when data instructions are frequently acquired , Can significantly improve the execution efficiency of data instructions.
  • the memory chip may divide the data read instruction and the data write instruction in the generated data instruction into the first instruction type according to the acquisition frequency of the data instruction or the preset rule, and divide the data instruction from the data instruction. Some instructions (such as the admin command) other than the instruction and the data write instruction are classified as the second instruction type. It should be noted that the data instruction of the first instruction type is not limited to including only a data read instruction and a data write instruction.
  • the data instruction generated by the memory chip may be a data read instruction, and the data read instruction is used to control writing data in the first memory to a second memory external to the memory chip.
  • the memory chip can write the data read instruction into a storage unit inside the memory chip and send instruction information to a first memory external to the memory chip, where the instruction information includes a storage address of the data read instruction .
  • the first memory may read the data read instruction from the storage unit inside the memory chip as required, and then write the data stored in the first memory to the second memory outside the memory chip according to the data read instruction. in.
  • the data instruction generated by the memory chip is a data write instruction
  • the data write instruction is used to control writing data in a second memory external to the memory chip to a third memory external to the memory chip.
  • the memory chip can write the data write instruction into a storage unit inside the memory chip and send instruction information to a first memory external to the memory chip, where the instruction information includes a storage address of the data write instruction .
  • the first memory reads the data write instruction from the storage unit inside the memory chip, and then reads the data stored in the second memory external to the memory chip according to the data write instruction, and writes the data In a third memory external to the memory chip.
  • the third memory may include a first memory, that is, the first memory may read data stored in a second memory external to the memory chip and write the data into the first memory according to a data write instruction.
  • the data stored in the second memory may include image data acquired by the image sensor, that is, the image sensor stores the acquired image data in the second memory in real time. Therefore, the data write instruction is stored in a storage unit inside the memory chip, and the first memory can quickly obtain the data write instruction, which improves the execution efficiency of the data write instruction. Therefore, the image data stored in the second memory can be written in time. In the first memory, the phenomenon of losing image data can be avoided, and especially when the image sensor collects video image data, the risk of video frame loss can be effectively avoided.
  • the first memory is a non-volatile memory
  • the second memory is a volatile memory
  • the third memory is a non-volatile memory.
  • the first memory is an SSD
  • the second memory is a DDR memory.
  • the storage unit in the storage chip may include on-chip memory (OCM) and / or cache memory (CACHE). That is, the memory chip writes the generated data instructions into the OCM. Alternatively, the memory chip writes the generated data instructions into CACHE. Alternatively, the memory chip may write some data instructions into the OCM and other data instructions into the CACHE.
  • OCM on-chip memory
  • CACHE cache memory
  • the OCM may be generated by a block memory on the FPGA chip, and the OCM may be packaged as an advanced eXtensible Interface (AXI) peripheral.
  • the OCM may be performed by the AXI bus and the processor of the memory chip. Communication.
  • the FPGA chip can be used to perform image signal processing ISP on the image data
  • the OCM and CACHE in the FPGA chip can be used for line buffer such as video.
  • OCM and CACHE have less read and write latency, and random access does not have the problem of address activation. Therefore, the time required for data instructions to be written into OCM or CACHE is shorter, and the time required for data instructions to be read from OCM or CACHE is shorter, thereby reducing the execution time of data instructions.
  • the first memory is an SSD
  • the storage chip is an FPGA chip
  • the generated data instructions are data instructions based on the NVME protocol
  • the generated data instructions are written into the OCM as an example.
  • the FPGA chip writes data instructions based on the NVME protocol into the DDR memory outside the FPGA chip
  • the SSD outside the FPGA chip obtains the above data instructions from the DDR memory through the FPGA chip, and each data instruction based on the NVME protocol
  • the FPGA chip writes the generated NVME protocol-based data instructions into the OCM inside the FPGA chip, and sends instruction information to the SSD outside the FPGA chip.
  • the instruction information includes the storage address of the data instruction, the SSD
  • the data instruction is obtained from the OCM according to the storage address. Because the OCM access delay is small and there is no address activation problem for random access, the read and write delays of data instructions based on the NVME protocol are small, which greatly improves the NVME protocol-based Data instruction execution efficiency.
  • the read and write latency of the data instructions is small, and there is no problem of address switching, which improves the storage efficiency, which can further improve the performance of the entire storage system.
  • the write bandwidth fluctuation of the SSD can be made smaller, which is conducive to improving the write SSD speed.
  • storing data instructions in the OCM can effectively reduce the risk of video frame loss.
  • the number of OCMs in the memory chip may be multiple.
  • the memory chip in this embodiment writes a data instruction into one OCM of the multiple OCMs according to a preset storage rule.
  • the preset storage rule instructs the data instruction to be written into the OCM with the largest free capacity. Accordingly, after the data chip generates the data instruction, it determines the OCM with the largest free capacity from multiple OCMs, and Write the generated data instruction to the OCM with the largest free capacity. Among them, the free capacity indicates the remaining available storage resources in the OCM. The larger the free capacity, the faster the OCM responds to the writing and reading of data instructions, further improving the storage efficiency.
  • the preset storage rule instructs the data instruction to be written into the OCM with the least number of accesses. Accordingly, after the data chip generates the data instruction, it determines the OCM with the least number of accesses from multiple OCMs And write the generated data instruction into the OCM with the least number of accesses. For example, the number of times each OCM is accessed can be counted periodically. The number of visits reflects to some extent the status of resources in the OCM being robbed by other instructions. Therefore, in this embodiment, the data instruction is written into the OCM with the least number of accesses, and the process of writing other instructions into the OCM can be avoided as much as possible.
  • the preset storage rule instructs data instructions to be written to an OCM that has the least number of accesses and the largest free capacity.
  • the memory chips are processed according to the number of accesses In order of arrangement, determine the M OCMs that are accessed later from multiple OCMs, where M is a positive integer not less than 1, and then write the data instruction into the OCM with the largest free capacity among the M OCMs. Therefore, the process of writing other instructions into the OCM is avoided as much as possible, and the faster the write and read responses to the data instructions, further improving the storage efficiency.
  • FIG. 3 is a schematic structural diagram of a memory chip according to an embodiment of the present invention.
  • the memory chip 300 provided by this embodiment may include a processor 301 and a storage unit 302.
  • the processor 301 and the storage unit 302 are connected through a bus communication, for example, they can be connected through an AXI bus.
  • the processor 301 may be a Central Processing Unit (CPU), and the processor 301 may also be another general-purpose processor.
  • a general-purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
  • the processor 301 is configured to generate a data instruction and write the data instruction into the storage unit 302 in the memory chip 300, and send instruction information to a first memory external to the memory chip 300; the instruction information includes a storage address of the data instruction, so that The first memory obtains a data instruction from the storage unit 302 of the storage chip 300 according to the storage address.
  • the storage unit 302 is configured to store a data instruction.
  • the data instruction is a data instruction based on the NVME protocol.
  • the memory chip 300 is an FPGA chip.
  • the storage unit 302 may include OCM and / or CACHE.
  • the processor 301 is specifically configured to write a data instruction into one of the OCMs according to a preset storage rule.
  • the processor 301 is specifically configured to write a data instruction into an OCM having the largest free capacity among the OCMs.
  • the data instruction is written into the OCM having the least number of accesses among the multiple OCMs.
  • the data instruction includes a data read instruction or a data write instruction.
  • the data read instruction is used to control writing data in the first memory to a second memory external to the memory chip 300.
  • the data write instruction is used to control writing data in a second memory external to the memory chip 300 to a third memory external to the memory chip 300.
  • the third memory includes a first memory.
  • the processor 301 is further configured to determine an instruction type of the data instruction before writing the data instruction into the storage unit 302 in the memory chip 300.
  • the processor 301 When the processor 301 writes a data instruction into the storage unit 302 in the storage chip 300, the processor 301 is specifically configured to: if the instruction type of the data instruction belongs to the first instruction type, write the data instruction to the storage unit 302 in the storage chip 300 in.
  • the processor 301 is further configured to: if the instruction type of the data instruction belongs to the second instruction type, write the data instruction into a second memory external to the memory chip 300.
  • the first instruction type is an instruction whose acquisition frequency is greater than a preset frequency
  • the second instruction type is an instruction whose acquisition frequency is less than or equal to the preset frequency
  • the first memory is a non-volatile memory
  • the second memory is a volatile memory
  • the second memory is a DDR memory.
  • the first memory is an SSD.
  • the data instruction is an instruction based on image data.
  • the memory chip provided in this embodiment may be used to implement the technical solutions of the memory chip in the foregoing method embodiments of the present invention.
  • the implementation principles and technical effects are similar, and details are not described herein again.
  • FIG. 4 is a schematic structural diagram of a storage system according to an embodiment of the present invention.
  • the storage system 400 provided by this embodiment may include a storage chip 401 and a first memory 402 external to the storage chip.
  • the memory chip 401 and the first memory 402 outside the memory chip are connected through a bus communication.
  • the storage system 400 provided in this embodiment may further include a second memory 403 external to the memory chip, and the second memory 403 may be communicatively connected to the foregoing device through a bus.
  • the storage system 400 provided in this embodiment may further include an image sensor 404, and the image sensor 404 may be communicatively connected with the foregoing device through a bus.
  • the storage chip 401 is configured to generate a data instruction and write the data instruction into a storage unit in the storage chip, and send instruction information to the first memory 402, where the instruction information includes a storage address of the data instruction.
  • the first memory 402 is configured to acquire a data instruction from a storage unit in a storage chip according to a storage address.
  • the data instruction is a data instruction based on the NVME protocol.
  • the memory chip is an FPGA chip.
  • the storage unit may include OCM and / or CACHE.
  • the storage chip 401 is specifically configured to write a data instruction into one of the OCMs according to a preset storage rule.
  • the memory chip 401 is specifically configured to write a data instruction into an OCM having the largest free capacity among a plurality of OCMs.
  • the data instruction is written into the OCM having the least number of accesses among the multiple OCMs.
  • the data instruction includes a data read instruction or a data write instruction.
  • the data read instruction is used to control writing data in the first memory 402 to the second memory 403 outside the memory chip.
  • the storage system 400 may further include a third memory (not shown in the figure) external to the memory chip.
  • the data instruction is a data write instruction
  • the data write instruction is used to control the second memory 403 outside the memory chip. The data in is written into a third memory outside the memory chip.
  • the third memory may include a first memory 402.
  • the memory chip 401 is further configured to determine an instruction type of the data instruction before writing the data instruction into a storage unit in the memory chip.
  • the memory chip 401 When the memory chip 401 writes a data instruction into a storage unit in the memory chip, it is specifically configured to: if the instruction type of the data instruction belongs to the first instruction type, write the data instruction into the storage unit in the memory chip.
  • the memory chip 401 is further configured to: if the instruction type of the data instruction belongs to the second instruction type, write the data instruction into the second memory 403.
  • the first instruction type is an instruction whose acquisition frequency is greater than a preset frequency
  • the second instruction type is an instruction whose acquisition frequency is less than or equal to the preset frequency
  • the first memory 402 is a non-volatile memory
  • the second memory 403 is a volatile memory
  • the second memory 403 is a DDR memory.
  • the first memory 402 is an SSD.
  • the storage system 400 may be an imaging system.
  • the image sensor 404 is configured to collect image data
  • the second memory 403 is configured to store image data collected by the image sensor.
  • the data instruction may be an instruction based on image data.
  • the memory chip 401 may adopt the structure of the embodiment shown in FIG. 3, and correspondingly, the technical solutions of the memory chip in the foregoing method embodiments may be implemented. The implementation principles and technical effects are similar, and are not described herein again.
  • the data stored in the second memory may include image data collected by the image sensor, that is, the image sensor stores the collected image data in the second memory in real time. Since the data write instruction is stored in a storage unit inside the memory chip, the first memory can quickly obtain the data write instruction, which improves the execution efficiency of the data write instruction. Therefore, the image data stored in the second memory can be written to the first memory in time. In a memory, the phenomenon of image data loss is avoided, especially when the image sensor collects video image data, which can effectively reduce the risk of video frame loss.
  • FIG. 5 is a schematic structural diagram of a movable platform according to an embodiment of the present invention.
  • the movable platform 500 provided in this embodiment may include a fuselage 501 and a storage system 502, and the storage system 502 is provided on the fuselage 501 on.
  • the storage system 502 may adopt the structure of the embodiment shown in FIG. 4, and correspondingly, the technical solutions in the foregoing method embodiments may be implemented. The implementation principles and technical effects are similar, and are not described herein again.
  • the movable platform 500 may be an aircraft.
  • the aircraft when the aircraft is used for aerial photography or to judge the environment of the aircraft by using the image data acquired by the aircraft, the image data acquired by the aircraft needs to be processed accordingly, and then the processed image data is transmitted to the control terminal on the ground.
  • the real-time display of image data can meet the user's aerial photography needs.
  • the aircraft as a remote control object can determine whether the environment of the aircraft is beneficial in real time through the real-time display of image data UAV flight, and judging results can better control the aircraft.
  • it will be detrimental to the control of the aircraft and to the improvement of aerial photography experience.
  • the present invention improves the execution efficiency of data instructions, so that the image data acquired by the aircraft can be transmitted to the control terminal in time, avoiding the phenomenon that the control terminal loses the picture taken by the drone, and is more conducive to controlling the flight of the drone , To ensure flight safety, but also help improve the real-time display of shooting screen.
  • the foregoing program may be stored in a computer-readable storage medium.
  • the program is executed, the program is executed.
  • the foregoing storage medium includes: a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc. The medium.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Memory System (AREA)

Abstract

一种数据指令处理方法、存储芯片、存储系统和可移动平台，此方法包括：生成数据指令；将数据指令写入存储芯片内的存储单元中，并向存储芯片外部的第一存储器发送指示信息；其中，指示信息包括数据指令的存储地址，以使第一存储器根据存储地址从存储芯片内的存储单元中获取数据指令。本实施例通过将生成的数据指令写入存储芯片内的存储单元，写入数据指令的时间更短，而且上述第一存储器是从存储芯片内的存储单元获取数据指令，第一存储器获取数据指令的时间更短，进而减少了数据指令的执行时间，提高了存储效率。

Description

数据指令处理方法、存储芯片、存储系统和可移动平台 技术领域
本发明实施例涉及存储技术领域，尤其涉及一种数据指令处理方法、存储芯片、存储系统和可移动平台。
背景技术
随着图像传感器的分辨率越来越高，像素的位深度越来越深，图像的数据量也越来越大，对数字图像采集系统存储性能的要求也越来越高。数字图像采集系统是相机、摄像机等产品中重要的一部分，一般图像传感器采集到的图像数据会实时存储在相机、摄像机等产品的双倍速率同步动态随机存储器(Double Data Rate Synchronous Dynamic Random Access Memory，DDR SDRAM)，又称为DDR存储器，并可以由DDR存储器转存至固态硬盘(Solid State Drive，SSD)中，当需要显示SSD中存储的图像数据时，又可以将图像数据由SSD写入DDR存储器中。
现有的DDR存储器遵循非易失性内存主机控制器接口规范(Non-Volatile Memory Express，NVME)，NVME驱动运行在DDR存储器上，因此可以通过NVME命令将图像数据从DDR存储器中读出或写入。其中，由于相机、摄像机等产品中的中央处理器(Central Processing Unit，CPU)一般性能有限，CPU生成NVME命令，先将该NVME命令存储于DDR存储器中，并通知给SSD。当需要执行该命令时，SSD从DDR存储器中读取该NVME命令，再执行该NVME命令。对于每条NVME命令来说，存在进DDR存储器和出DDR存储器的过程，但是由于DDR存储器的访问延时大，这会导致每条NVME命令的执行时间变长，存储效率降低。
发明内容
本发明实施例提供一种数据指令处理方法、存储芯片、存储系统和可移动平台，用于减少数据指令的执行时间，提高存储效率。
第一方面，本发明实施例提供一种数据指令处理方法，应用于存储芯片， 包括：
生成数据指令；
将数据指令写入存储芯片内的存储单元中，并向存储芯片外部的第一存储器发送指示信息；
其中，指示信息包括数据指令的存储地址，以使第一存储器根据存储地址从存储芯片内的存储单元中获取数据指令。
第二方面，本发明实施例提供一种存储芯片，包括：处理器和存储单元；
处理器，用于生成数据指令并将数据指令写入存储芯片内的存储单元中，并向存储芯片外部的第一存储器发送指示信息；指示信息包括数据指令的存储地址，以使第一存储器根据存储地址从存储芯片的存储单元中获取数据指令；
存储单元，用于存储数据指令。
第三方面，本发明实施例提供一种存储系统，包括：存储芯片和存储芯片外部的第一存储器；
存储芯片，用于生成数据指令并将数据指令写入存储芯片内的存储单元中；向第一存储器发送指示信息，指示信息包括数据指令的存储地址；
第一存储器，用于根据存储地址从存储芯片内的存储单元中获取数据指令。
第四方面，本发明实施例提供一种可移动平台，包括机身和如第三方面本发明实施例所述的存储系统，存储系统设于机身上。
第五方面，本发明实施例提供一种计算机可读存储介质，所述计算机可读存储介质存储有计算机程序，所述计算机程序包含至少一段代码，所述至少一段代码可由计算机执行，以控制所述计算机执行第一方面本发明实施例所述的数据指令处理方法。
第六方面，本发明实施例提供一种计算机程序，当所述计算机程序被计算机执行时，用于实现第一方面本发明实施例所述的数据指令处理方法。
本发明实施例提供的数据指令处理方法、存储芯片、存储系统和可移动平台，通过生成数据指令；将数据指令写入存储芯片内的存储单元中，并向存储芯片外部的第一存储器发送指示信息；其中，指示信息包括数据指令的存储地址，然后第一存储器根据存储地址从存储芯片内的存储单元中获取数 据指令。本发明实施例中，由于存储芯片内的存储单元访问延时相对较小且性能不受地址切换的影响，因此，通过将生成的数据指令写入存储芯片内的存储单元，可以使得写入数据指令的时间更短，而且上述第一存储器是直接从存储芯片内的存储单元获取数据指令，相较于经由存储芯片再至存储芯片外部的其他存储器中获取数据指令，本发明实施例中第一存储器获取数据指令的时间更短，进而减少了数据指令的执行时间，提高了存储效率。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是根据本发明的实施例的无人飞行系统的示意性架构图；
图2为本发明一实施例提供的数据指令处理方法的流程图；
图3为本发明一实施例提供的存储芯片的结构示意图；
图4为本发明一实施例提供的存储系统的结构示意图；
图5为本发明一实施例提供的可移动平台的结构示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
需要说明的是，当组件被称为“固定于”另一个组件，它可以直接在另一个组件上或者也可以存在居中的组件。当一个组件被认为是“连接”另一个组件，它可以是直接连接到另一个组件或者可能同时存在居中组件。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所 使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
下面结合附图，对本发明的一些实施方式作详细说明。在不冲突的情况下，下述的实施例及实施例中的特征可以相互组合。
本发明的实施例提供了数据指令处理方法、存储芯片、存储系统和可移动平台。该可移动平台例如可以是无人机、无人船、无人汽车、机器人、手持电子设备等。其中无人机例如可以是旋翼飞行器(rotorcraft)，例如，由多个推动装置通过空气推动的多旋翼飞行器，本发明的实施例并不限于此。
图1是根据本发明的实施例的无人飞行系统的示意性架构图。本实施例以旋翼无人机为例进行说明。
无人飞行系统100可以包括无人机110、显示设备130和控制终端140。其中，无人机110可以包括动力系统150、飞行控制系统160、机架和承载在机架上的云台120。无人机110可以与控制终端140和显示设备130进行无线通信。
机架可以包括机身和脚架(也称为起落架)。机身可以包括中心架以及与中心架连接的一个或多个机臂，一个或多个机臂呈辐射状从中心架延伸出。脚架与机身连接，用于在无人机110着陆时起支撑作用。
动力系统150可以包括一个或多个电子调速器(简称为电调)151、一个或多个螺旋桨153以及与一个或多个螺旋桨153相对应的一个或多个电机152，其中电机152连接在电子调速器151与螺旋桨153之间，电机152和螺旋桨153设置在无人机110的机臂上；电子调速器151用于接收飞行控制系统160产生的驱动信号，并根据驱动信号提供驱动电流给电机152，以控制电机152的转速。电机152用于驱动螺旋桨旋转，从而为无人机110的飞行提供动力，该动力使得无人机110能够实现一个或多个自由度的运动。在某些实施例中，无人机110可以围绕一个或多个旋转轴旋转。例如，上述旋转轴可以包括横滚轴(Roll)、偏航轴(Yaw)和俯仰轴(pitch)。应理解，电机152可以是直流电机，也可以交流电机。另外，电机152可以是无刷电机，也可以是有刷电机。
飞行控制系统160可以包括飞行控制器161和传感系统162。传感系统162用于测量无人机的姿态信息，即无人机110在空间的位置信息和状态信 息，例如，三维位置、三维角度、三维速度、三维加速度和三维角速度等。传感系统162例如可以包括陀螺仪、超声传感器、电子罗盘、惯性测量单元(Inertial Measurement Unit，IMU)、视觉传感器、全球导航卫星系统和气压计等传感器中的至少一种。例如，全球导航卫星系统可以是全球定位系统(Global Positioning System，GPS)。飞行控制器161用于控制无人机110的飞行，例如，可以根据传感系统162测量的姿态信息控制无人机110的飞行。应理解，飞行控制器161可以按照预先编好的程序指令对无人机110进行控制，也可以通过响应来自控制终端140的一个或多个控制指令对无人机110进行控制。
云台120可以包括电机122。云台用于携带拍摄装置123。飞行控制器161可以通过电机122控制云台120的运动。可选地，作为另一实施例，云台120还可以包括控制器，用于通过控制电机122来控制云台120的运动。应理解，云台120可以独立于无人机110，也可以为无人机110的一部分。应理解，电机122可以是直流电机，也可以是交流电机。另外，电机122可以是无刷电机，也可以是有刷电机。还应理解，云台可以位于无人机的顶部，也可以位于无人机的底部。
拍摄装置123例如可以是照相机或摄像机等用于捕获图像的设备，拍摄装置123可以与飞行控制器通信，并在飞行控制器的控制下进行拍摄。本实施例的拍摄装置123至少包括感光元件，该感光元件例如为互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，CMOS)传感器或电荷耦合元件(Charge-coupled Device，CCD)传感器。可以理解，拍摄装置123也可直接固定于无人机110上，从而云台120可以省略。
显示设备130位于无人飞行系统100的地面端，可以通过无线方式与无人机110进行通信，并且可以用于显示无人机110的姿态信息。另外，还可以在显示设备130上显示成像装置拍摄的图像。应理解，显示设备130可以是独立的设备，也可以集成在控制终端140中。
控制终端140位于无人飞行系统100的地面端，可以通过无线方式与无人机110进行通信，用于对无人机110进行远程操纵。
另外，无人机110还可以机载有扬声器(图中未示出)，该扬声器用于播放音频文件，扬声器可直接固定于无人机110上，也可搭载在云台120上。
应理解，上述对于无人飞行系统各组成部分的命名仅是出于标识的目的，并不应理解为对本发明的实施例的限制。下面实施例所述的存储芯片例如可以部署在上述的拍摄装置123中。
图2为本发明一实施例提供的数据指令处理方法的流程图，如图2所示，本实施例的方法可以包括：
S201、存储芯片生成数据指令。
本实施例的存储芯片可以生成数据指令。例如：可以是存储芯片中的处理器，例如中央处理单元(Central Processing Unit，CPU)，生成数据指令。该数据指令例如可以为对数据进行处理的指令，对数据进行处理可以包括读取数据或者写入数据等等。数据指令例如还可以为识别(Identify)指令。
可选的，生成的数据指令可以为基于图像数据的指令，例如上述对数据进行处理包括对图像数据进行处理。
可选的，数据指令可以为基于非易失性内存主机控制器接口规范(Non-Volatile Memory Express，NVME)协议的数据指令。基于NVME协议的数据指令例如可以包括输入/输出(Input/Output，I/O)指令和管理(admin)指令。其中，I/O指令例如可以包括数据读指令和数据写指令。当然，数据指令可以还可以为基于串行ATA高级主控接口/高级主机控制器接口(Serial ATA Advanced Host Controller Interface)协议的数据指令。
S202、存储芯片将数据指令写入存储芯片内的存储单元中。
本实施例中的存储芯片可以将上述生成的数据指令写入存储芯片的存储单元中。
可选的，存储芯片可以为现场可编程门阵列(Field-Programmable Gate Array，FPGA)芯片。FPGA芯片例如可以为带有片上系统(System on a Chip，SOC)的FPGA芯片。
S203、存储芯片向存储芯片外部的第一存储器发送指示信息，指示信息包括数据指令的存储地址。
本实施例中的存储芯片在将数据指令写入存储芯片内的存储单元之后，向存储芯片外部的第一存储器发送指示信息。
可选的，本实施例中的存储芯片也可以在确定数据指令的存储地址之后，向存储芯片外部的第一存储器发送指示信息，指示信息包括数据指令的存储 地址。指示信息例如可以包括数据指令在存储芯片内部的存储单元中的起始地址和数据指令的大小。
本实施例中，S202和S203的执行顺序除了上述说明的内容，还可以根据需要进行其它调整，对于S202和S203的执行顺序在此不做限定。
可选的，第一存储器可以为非易失性存储器，例如可以为固态硬盘(Solid State Drive，SSD)。若存储芯片为FPGA芯片，则FPGA芯片与SSD可以通过高速串行计算机扩展总线标准(Peripheral Component Interconnect Express，PCIE)进行通信。
S204、第一存储器根据数据指令的存储地址从存储芯片内的存储单元中获取数据指令。
本实施例中，第一存储器接收存储芯片发送的指示信息，该指示信息中包括数据指令的存储地址。当第一存储器需要获取该数据指令时，根据该数据指令的存储地址从存储芯片内的存储单元中获取数据指令。
本实施例提供的数据指令处理方法，通过生成数据指令，将数据指令写入存储芯片内的存储单元中，并向存储芯片外部的第一存储器发送指示信息，其中，指示信息包括数据指令的存储地址，然后第一存储器根据存储地址从存储芯片内的存储单元中获取数据指令。本实施例中，由于存储芯片内的存储单元访问延时相对较小且性能不受地址切换的影响，因此，通过将生成的数据指令写入存储芯片内的存储单元，可以使得写入数据指令的时间更短，而且上述第一存储器是直接从存储芯片内的存储单元获取数据指令，相较于经由存储芯片再至存储芯片外部的其他存储器中获取数据指令，本实施例中第一存储器获取数据指令的时间更短，进而减少了数据指令的执行时间，提高了存储效率。
在一些实施例中，由于存储芯片内部的存储资源非常宝贵，因此本实施例的存储芯片可以选择性地将生成的数据指令写入存储芯片内的存储单元中。
可选的，存储芯片在将数据指令写入存储芯片内的存储单元中之前，还确定数据指令的指令类型。相应地，存储芯片将数据指令写入存储芯片内的存储单元中的一种实现方式可以为：若数据指令的指令类型属于第一指令类型，则存储芯片将数据指令写入存储芯片内的存储单元中。
可选地，若数据指令的指令类型属于第二指令类型，则存储芯片将数据 指令写入存储芯片外部的第二存储器中。可选地，所述第一存储器为非易失性存储器，所述第二存储器为易失性存储器。例如：所述第一存储器为SSD，第二存储器为DDR存储器。
因此，本实施例尽可能保证属于第一指令类型的数据指令写入存储芯片的存储单元中。
在一些实施例中，存储芯片可以根据预设规则将生成的数据指令划分为第一指令类型和第二指令类型。预设规则可以由用户根据实际需要灵活设置，便于有针对性的将数据指令写入存储芯片内部的存储单元中。预设规则例如可以包括数据指令与所属指令类型之间的映射关系。如预设规则可以规定A指令、B指令和C指令属于第一指令类型，D指令和E指令属于第二指令类型，其中A指令、B指令、C指令、D指令和E指令表示不同的数据指令。
在一些实施例中，存储芯片可以根据数据指令的被获取频率将生成的数据指令划分为两类(第一指令类型和第二指令类型)。其中，第一指令类型为被获取频率大于预设频率的指令，第二指令类型为被获取频率小于等于预设频率的指令。可选的，数据指令的被获取频率可以是预先设定的，也可以是统计获得，以预设周期进行更新的。
在一些实施例中，存储芯片可以将被获取频率大于预设频率的数据指令写入存储芯片内的存储单元中，存储芯片还可以将被获取频率小于等于预设频率的数据指令写入存储芯片外部的第二存储器中。
因此，通过将被获取频率高的数据指令写入存储芯片内部的存储单元中，可以避免被获取频率低的数据指令占用存储芯片内部的存储资源，尽可能保证存储芯片内部的存储单元具有足够的存储资源用于存储被获取频率更高的数据指令，还提高了存储芯片内部存储单元的利用效率，进一步提高了整体的存储效率。同时，将被获取频率高的数据指令写入存储芯片内部的存储单元中，可以减少获取该类型的数据指令所需的时间，从而提高数据指令的执行效率，尤其是当数据指令被频繁获取时，可以显著提高数据指令的执行效率。
在一些实施例中，根据数据指令的被获取频率或者上述预设规则，存储芯片可以将生成的数据指令中的数据读指令和数据写指令划分为第一指令类型，将数据指令中除数据读指令和数据写指令之外的一些指令(例如admin  command)划分为第二指令类型。需要说明的是，第一指令类型的数据指令不局限于只包括数据读指令和数据写指令。
在一些实施例中，存储芯片生成的数据指令可以为数据读指令，数据读指令用于控制将第一存储器中的数据写入存储芯片外部的第二存储器。其中，存储芯片生成数据读指令后，存储芯片可以将数据读指令写入存储芯片内部的存储单元中，并向存储芯片外部的第一存储器发送指示信息，该指示信息包括数据读指令的存储地址。第一存储器接收到指示信息后，可以根据需要从存储芯片内部的存储单元中读取该数据读指令，然后根据数据读指令，将第一存储器中存储的数据写入存储芯片外部的第二存储器中。
在一些实施例中，存储芯片生成的数据指令为数据写指令，数据写指令用于控制将存储芯片外部的第二存储器中的数据写入存储芯片外部的第三存储器。其中，存储芯片生成数据写指令后，存储芯片可以将数据写指令写入存储芯片内部的存储单元中，并向存储芯片外部的第一存储器发送指示信息，该指示信息包括数据写指令的存储地址。第一存储器接收到指示信息后，从存储芯片内部的存储单元中读取该数据写指令，然后根据数据写指令，读取存储芯片外部的第二存储器中存储的数据，并将该数据写入存储芯片外部的第三存储器中。可选的，第三存储器可以包括第一存储器，也就是第一存储器根据数据写指令，可以读取存储芯片外部的第二存储器中存储的数据，并将该数据写入该第一存储器中。
可选地，第二存储器中存储的数据可以包括图像传感器采集到的图像数据，即图像传感器将采集的图像数据实时存储到第二存储器中。因此，数据写指令存储在存储芯片内部的存储单元中，第一存储器可以快速获取到该数据写指令，提高了数据写指令的执行效率，因此能够将第二存储器中存储的图像数据及时写入第一存储器中，避免出现图像数据丢失的现象，尤其是在图像传感器采集视频图像数据时，可以有效避免视频丢帧的风险。
可选地，所述第一存储器为非易失性存储器，所述第二存储器为易失性存储器，所述第三存储器为非易失性存储器。例如：所述第一存储器为SSD，第二存储器为DDR存储器。
在一些实施例中，上述存储芯片(即FPGA芯片)内的存储单元可以包括片上存储器(On Chip Memory，OCM)和/或高速缓存存储器(CACHE)。 也就是，存储芯片将生成的数据指令写入OCM。或者，存储芯片将生成的数据指令写入CACHE。或者，存储芯片可以一些数据指令写入OCM中，将另一些数据指令写入CACHE中。
可选的，OCM可以由FPGA芯片上的存储块(Block Memory)生成，该OCM可以封装成高级可扩展接口(Advanced eXtensible Interface，AXI)外设，OCM可以通过AXI总线与存储芯片的处理器进行通信。
其中，FPGA芯片可以用于对图像数据进行图像信号处理ISP，FPGA芯片内的OCM和CACHE可以用于诸如视频的行缓存。与DDR相比，OCM和CACHE具有读写延迟小，随机访问不存在地址激活的问题。因此，数据指令写入OCM或CACHE中所需时间较短，并且数据指令从OCM或CACHE中读出所需时间较短，从而减少了数据指令的执行时间。
以第一存储器为SSD，存储芯片为FPGA芯片、生成的数据指令为基于NVME协议的数据指令，且将生成的数据指令写入OCM，作为例子。现有技术中，FPGA芯片将基于NVME协议的数据指令写入FPGA芯片外部的DDR存储器中，FPGA芯片外的SSD再通过FPGA芯片从DDR存储器中获取上述数据指令，每条基于NVME协议的数据指令都存在进DDR存储器和出DDR存储器的过程，由于DDR存储器的访问延迟大，增大了数据指令的读写延迟，且若频繁地从DDR中取基于NVME协议的数据指令，会增加DDR的地址切换频率，降低DDR的带宽，影响整个存储系统的性能。而本发明实施例中，FPGA芯片将生成的基于NVME协议的数据指令写入FPGA芯片内部的OCM中，并向FPGA芯片外部的SSD发送指示信息，指示信息包括了该数据指令的存储地址，SSD根据该存储地址从OCM中获取该数据指令，由于OCM访问延迟小，且随机访问不存在地址激活的问题，使得基于NVME协议的数据指令的读写延迟都很小，大大提高了基于NVME协议的数据指令的执行效率。因此，数据指令的读写延迟小，且不存在地址切换的问题，提高了存储效率，进而可以提升整个存储系统的性能。特别地，可以使得SSD的写带宽波动更小，有利于提高写SSD速度，而相比DDR存储器的访问延迟不定而言，将数据指令存储于OCM中可以有效降低视频丢帧的风险。
在一些实施例中，存储芯片内部的OCM的数量可以为多个。
针对OCM的数量为多个时，本实施例中的存储芯片根据预设存储规则， 将数据指令写入多个OCM中的一个OCM中。
在一种可能的实现方式中，预设存储规则指示将数据指令写入空闲容量最大的OCM中，相应地，存储芯片在生成数据指令后，从多个OCM中确定空闲容量最大的OCM，并将生成的数据指令写入该空闲容量最大的OCM中。其中，空闲容量指示了OCM中的剩余可用存储资源，空闲容量越大的OCM对于数据指令的写入和读取响应越快，进一步提高了存储效率。
在一种可能的实现方式中，预设存储规则指示将数据指令写入被访问次数最小的OCM中，相应地，存储芯片在生成数据指令后，从多个OCM中确定被访问次数最小的OCM，并将生成的数据指令写入该被访问次数最小的OCM中。例如，可以周期性统计各个OCM的被访问次数。被访问次数在一定程度上反映了该OCM中资源被其它指令抢夺的状况。因此，本实施例将数据指令写入被访问次数最小的OCM中，可以尽可能避免影响其它指令写入OCM中的过程。
在一种可能的实现方式中，预设存储规则指示将数据指令写入被访问次数最小并且空闲容量最大的OCM中，相应地，存储芯片在生成数据指令后，按照被访问次数由高到低的排列顺序，从多个OCM中确定被访问次数靠后的M个OCM，M为不小于1的正整数，然后将数据指令写入M个OCM中空闲容量最大的OCM中。因此，尽可能避免影响其它指令写入OCM中的过程，并且对该数据指令的写入和读取响应越快，进一步提高了存储效率。
图3为本发明一实施例提供的存储芯片的结构示意图，如图3所示，本实施例提供的存储芯片300可以包括：处理器301和存储单元302。处理器301与存储单元302通过总线通信连接，例如可以通过AXI总线连接。处理器301可以是中央处理单元(Central Processing Unit，CPU)，该处理器301还可以是其他通用处理器。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
处理器301，用于生成数据指令并将数据指令写入存储芯片300内的存储单元302中，并向存储芯片300外部的第一存储器发送指示信息；指示信息包括数据指令的存储地址，以使第一存储器根据存储地址从存储芯片300的存储单元302中获取数据指令。
存储单元302，用于存储数据指令。
可选的，数据指令为基于NVME协议的数据指令。
可选的，存储芯片300为FPGA芯片。
可选的，存储单元302可以包括OCM和/或CACHE。
可选的，OCM的数量为多个。处理器301，具体用于：根据预设存储规则，将数据指令写入多个OCM中的一个OCM中。
可选的，处理器301，具体用于：将数据指令写入多个OCM中空闲容量最大的OCM中。或者，将数据指令写入多个OCM中被访问次数最小的OCM中。或者，按照被访问次数由高到低的排列顺序，从多个OCM中确定被访问次数靠后的M个OCM，M为不小于1的正整数，将数据指令写入M个OCM中空闲容量最大的OCM中。
可选的，数据指令包括数据读指令或者数据写指令。
可选的，数据指令为数据读指令时，数据读指令用于控制将第一存储器中的数据写入存储芯片300外部的第二存储器。或者，数据指令为数据写指令时，数据写指令用于控制将存储芯片300外部的第二存储器中的数据写入存储芯片300外部的第三存储器。
可选的，第三存储器包括第一存储器。
可选的，处理器301，在将数据指令写入存储芯片300内的存储单元302中之前，还用于确定数据指令的指令类型。
处理器301在将数据指令写入存储芯片300内的存储单元302中时，具体用于：若数据指令的指令类型属于第一指令类型，则将数据指令写入存储芯片300内的存储单元302中。
可选的，处理器301，还用于：若数据指令的指令类型属于第二指令类型，则将数据指令写入存储芯片300外部的第二存储器中。
可选的，第一指令类型为被获取频率大于预设频率的指令，第二指令类型为被获取频率小于等于预设频率的指令。
可选的，第一存储器为非易失性存储器，第二存储器为易失性存储器。
可选的，第二存储器为DDR存储器。
可选的，第一存储器为SSD。
可选的，数据指令为基于图像数据的指令。
本实施例提供的存储芯片，可以用于执行本发明上述各方法实施例中的 存储芯片的技术方案，其实现原理和技术效果类似，此处不再赘述。
图4为本发明一实施例提供的存储系统的结构示意图，如图4所示，本实施例提供的存储系统400可以包括存储芯片401和存储芯片外部的第一存储器402。存储芯片401和存储芯片外部的第一存储器402通过总线通信连接。可选的，本实施例提供的存储系统400还可以包括存储芯片外部的第二存储器403，第二存储器403可以通过总线与上述器件通信连接。可选的，本实施例提供的存储系统400还可以包括图像传感器404，图像传感器404可以通过总线与上述器件通信连接。
存储芯片401，用于生成数据指令并将数据指令写入存储芯片内的存储单元中，向第一存储器402发送指示信息，指示信息包括数据指令的存储地址。
第一存储器402，用于根据存储地址从存储芯片内的存储单元中获取数据指令。
可选的，数据指令为基于NVME协议的数据指令。
可选的，存储芯片为FPGA芯片。
可选的，存储单元可以包括OCM和/或CACHE。
可选的，OCM的数量为多个。存储芯片401，具体用于：根据预设存储规则，将数据指令写入多个OCM中的一个OCM中。
可选的，存储芯片401，具体用于：将数据指令写入多个OCM中空闲容量最大的OCM中。或者，将数据指令写入多个OCM中被访问次数最小的OCM中。或者，按照被访问次数由高到低的排列顺序，从多个OCM中确定被访问次数靠后的M个OCM，M为不小于1的正整数，将数据指令写入M个OCM中空闲容量最大的OCM中。
可选的，数据指令包括数据读指令或者数据写指令。
可选的，数据指令为数据读指令时，数据读指令用于控制将第一存储器402中的数据写入存储芯片外部的第二存储器403。或者，可选的，存储系统400还可以包括存储芯片外部的第三存储器(图中未示出)，数据指令为数据写指令时，数据写指令用于控制将存储芯片外部的第二存储器403中的数据写入存储芯片外部的第三存储器。
可选的，第三存储器可以包括第一存储器402。
可选的，存储芯片401，还用于将数据指令写入存储芯片内的存储单元中之前，确定数据指令的指令类型。
存储芯片401在将数据指令写入存储芯片内的存储单元中时，具体用于：若数据指令的指令类型属于第一指令类型，则将数据指令写入存储芯片内的存储单元中。
可选的，存储芯片401，还用于：若数据指令的指令类型属于第二指令类型，则将数据指令写入第二存储器403中。
可选的，第一指令类型为被获取频率大于预设频率的指令，第二指令类型为被获取频率小于等于预设频率的指令。
可选的，第一存储器402为非易失性存储器，第二存储器403为易失性存储器。
可选的，第二存储器403为DDR存储器。
可选的，第一存储器402为SSD。
可选的，存储系统400可以为成像系统。
可选的，图像传感器404，用于采集图像数据，第二存储器403，用于存储图像传感器采集到的图像数据。
可选的，数据指令可以为基于图像数据的指令。
其中，存储芯片401可以采用图3所示实施例的结构，其对应地，可以执行上述各方法实施例中存储芯片的技术方案，其实现原理和技术效果类似，此处不再赘述。
当本实施例提供的存储系统400为成像系统时，第二存储器中存储的数据可以包括图像传感器采集到的图像数据，即图像传感器将采集的图像数据实时存储到第二存储器中。由于数据写指令存储在存储芯片内部的存储单元中，第一存储器可以快速获取到该数据写指令，提高了数据写指令的执行效率，因此能够将第二存储器中存储的图像数据及时写入第一存储器中，避免出现图像数据丢失的现象，尤其是在图像传感器采集视频图像数据时，可以有效降低视频丢帧的风险。
图5为本发明一实施例提供的可移动平台的结构示意图，如图5所示，本实施例提供的可移动平台500可以包括：机身501和存储系统502，存储系统502设于机身501上。其中，存储系统502可以采用图4所示实施例的 结构，其对应地，可以执行上述各方法实施例中的技术方案，其实现原理和技术效果类似，此处不再赘述。
可选的，可移动平台500可以为飞行器。
具体的，当飞行器用于航拍或利用飞行器拍摄获取的图像数据对飞行器进行所在环境判断时，需要对飞行器拍摄获取的图像数据进行相应的处理，然后将处理后的图像数据传输给地面的控制端，以便控制端显示飞行器拍摄到的画面，从而通过图像数据的实时显示，可以满足用户的航拍需求，同时，飞行器作为远程控制物，通过图像数据的实时显示，可以实时判断飞行器的所在环境是否利于无人机的飞行，并通过判断结果可以较佳地控制飞行器。而在实际应用中，若飞行器至控制端的图像数据的传输存在延时或丢帧的情况，将不利于对飞行器的控制，也不利于航拍体验的提高。
本发明通过上述方案，通过提高数据指令的执行效率，使飞行器拍摄获取的图像数据能够及时传输给控制端，避免了控制端失去无人机拍摄画面的现象，更有利于控制无人机的飞行，保证飞行安全，还有利于提高拍摄画面显示的实时性。
本领域普通技术人员可以理解：实现上述方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成，前述的程序可以存储于一计算机可读取存储介质中，该程序在执行时，执行包括上述方法实施例的步骤；而前述的存储介质包括：只读内存(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (52)

  1. 一种数据指令处理方法，其特征在于，应用于存储芯片，包括：
    生成数据指令；
    将所述数据指令写入存储芯片内的存储单元中，并向所述存储芯片外部的第一存储器发送指示信息；
    其中，所述指示信息包括所述数据指令的存储地址，以使所述第一存储器根据所述存储地址从所述存储芯片内的存储单元中获取所述数据指令。
  2. 根据权利要求1所述的方法，其特征在于，所述数据指令为基于非易失性内存主机控制器接口规范NVME协议的数据指令。
  3. 根据权利要求1或2所述的方法，其特征在于，所述存储芯片为现场可编程门阵列FPGA芯片。
  4. 根据权利要求3所述的方法，其特征在于，所述存储单元包括片上存储器OCM和/或高速缓存存储器CACHE。
  5. 根据权利要求4所述的方法，其特征在于，所述OCM的数量为多个；
    所述将所述数据指令写入存储芯片内的存储单元中，包括：
    根据预设存储规则，将所述数据指令写入多个所述OCM中的一个所述OCM中。
  6. 根据权利要求5所述的方法，其特征在于，所述根据预设存储规则，将所述数据指令写入多个所述OCM中的一个所述OCM中，包括：
    将所述数据指令写入多个所述OCM中空闲容量最大的OCM中；或，
    将所述数据指令写入多个所述OCM中被访问次数最小的OCM中；或，
    按照被访问次数由高到低的排列顺序，从多个所述OCM中确定所述被访问次数靠后的M个所述OCM，所述M为不小于1的正整数；
    将所述数据指令写入M个所述OCM中空闲容量最大的OCM中。
  7. 根据权利要求3所述的方法，其特征在于，所述数据指令包括数据读指令或者数据写指令。
  8. 根据权利要求7所述的方法，其特征在于，所述数据指令为数据读指令时，所述数据读指令用于控制将所述第一存储器中的数据写入所述存储芯片外部的第二存储器；或者，
    所述数据指令为数据写指令时，所述数据写指令用于控制将所述存储芯 片外部的第二存储器中的数据写入所述存储芯片外部的第三存储器。
  9. 根据权利要求8所述的方法，其特征在于，所述第三存储器包括所述第一存储器。
  10. 根据权利要求3所述的方法，其特征在于，所述将所述数据指令写入存储芯片内的存储单元中之前，还包括：
    确定所述数据指令的指令类型；
    所述将所述数据指令写入存储芯片内的存储单元中，包括：
    若所述数据指令的指令类型属于第一指令类型，则将所述数据指令写入存储芯片内的存储单元中。
  11. 根据权利要求10所述的方法，其特征在于，还包括：
    若所述数据指令的指令类型属于第二指令类型，则将所述数据指令写入所述存储芯片外部的第二存储器中。
  12. 根据权利要求11所述的方法，其特征在于，所述第一指令类型为被获取频率大于预设频率的指令，所述第二指令类型为被获取频率小于等于所述预设频率的指令。
  13. 根据权利要求8或9或11或12所述的方法，其特征在于，所述第一存储器为非易失性存储器，所述第二存储器为易失性存储器。
  14. 根据权利要求13所述的方法，其特征在于，所述第二存储器为双倍速率DDR存储器。
  15. 根据权利要求13所述的方法，其特征在于，所述第一存储器为固态硬盘SSD。
  16. 根据权利要求1或2所述的方法，其特征在于，所述数据指令为基于图像数据的指令。
  17. 一种存储芯片，其特征在于，包括：处理器和存储单元；
    所述处理器，用于生成数据指令并将所述数据指令写入所述存储芯片内的所述存储单元中，并向所述存储芯片外部的第一存储器发送指示信息；所述指示信息包括所述数据指令的存储地址，以使所述第一存储器根据所述存储地址从所述存储芯片的存储单元中获取所述数据指令；
    所述存储单元，用于存储所述数据指令。
  18. 根据权利要求17所述的存储芯片，其特征在于，所述数据指令为基 于非易失性内存主机控制器接口规范NVME协议的数据指令。
  19. 根据权利要求17或18所述的存储芯片，其特征在于，所述存储芯片为现场可编程门阵列FPGA芯片。
  20. 根据权利要求19所述的存储芯片，其特征在于，所述存储单元包括片上存储器OCM和/或高速缓存存储器CACHE。
  21. 根据权利要求20所述的存储芯片，其特征在于，所述OCM的数量为多个；
    所述处理器，具体用于：根据预设存储规则，将所述数据指令写入多个所述OCM中的一个所述OCM中。
  22. 根据权利要求21所述的存储芯片，其特征在于，所述处理器，具体用于：
    将所述数据指令写入多个所述OCM中空闲容量最大的OCM中；或，
    将所述数据指令写入多个所述OCM中被访问次数最小的OCM中；或，
    按照被访问次数由高到低的排列顺序，从多个所述OCM中确定所述被访问次数靠后的M个所述OCM，所述M为不小于1的正整数；
    将所述数据指令写入M个所述OCM中空闲容量最大的OCM中。
  23. 根据权利要求17-22任一项所述的存储芯片，其特征在于，所述数据指令包括数据读指令或者数据写指令。
  24. 根据权利要求23所述的存储芯片，其特征在于，所述数据指令为数据读指令时，所述数据读指令用于控制将所述第一存储器中的数据写入所述存储芯片外部的第二存储器；或者，
    所述数据指令为数据写指令时，所述数据写指令用于控制将所述存储芯片外部的第二存储器中的数据写入所述存储芯片外部的第三存储器。
  25. 根据权利要求24所述的存储芯片，其特征在于，所述第三存储器包括所述第一存储器。
  26. 根据权利要求17-19任一项所述的存储芯片，其特征在于，所述处理器，在将所述数据指令写入所述存储芯片内的所述存储单元中之前，还用于确定所述数据指令的指令类型；
    所述处理器在将所述数据指令写入所述存储芯片内的所述存储单元中时，具体用于：若所述数据指令的指令类型属于第一指令类型，则将所述数据指 令写入所述存储芯片内的存储单元中。
  27. 根据权利要求26所述的存储芯片，其特征在于，所述处理器，还用于：若所述数据指令的指令类型属于第二指令类型，则将所述数据指令写入所述存储芯片外部的第二存储器中。
  28. 根据权利要求27所述的存储芯片，其特征在于，所述第一指令类型为被获取频率大于预设频率的指令，所述第二指令类型为被获取频率小于等于所述预设频率的指令。
  29. 根据权利要求24或25或27或28所述的存储芯片，其特征在于，所述第一存储器为非易失性存储器，所述第二存储器为易失性存储器。
  30. 根据权利要求29所述的存储芯片，其特征在于，所述第二存储器为双倍速率DDR存储器。
  31. 根据权利要求29所述的存储芯片，其特征在于，所述第一存储器为固态硬盘SSD。
  32. 根据权利要求17或18所述的存储芯片，其特征在于，所述数据指令为基于图像数据的指令。
  33. 一种存储系统，其特征在于，包括：存储芯片和所述存储芯片外部的第一存储器；
    所述存储芯片，用于生成数据指令并将所述数据指令写入所述存储芯片内的存储单元中；向所述第一存储器发送指示信息，所述指示信息包括所述数据指令的存储地址；
    所述第一存储器，用于根据所述存储地址从所述存储芯片内的存储单元中获取所述数据指令。
  34. 根据权利要求33所述的系统，其特征在于，所述数据指令为基于非易失性内存主机控制器接口规范NVME协议的数据指令。
  35. 根据权利要求33或34所述的系统，其特征在于，所述存储芯片为现场可编程门阵列FPGA芯片。
  36. 根据权利要求33-35任一项所述的系统，其特征在于，所述存储单元包括片上存储器OCM和/或高速缓存存储器CACHE。
  37. 根据权利要求36所述的系统，其特征在于，所述OCM的数量为多个；
    所述存储芯片，具体用于：根据预设存储规则，将所述数据指令写入多个所述OCM中的一个所述OCM中。
  38. 根据权利要求37所述的系统，其特征在于，所述存储芯片，具体用于：
    将所述数据指令写入多个所述OCM中空闲容量最大的OCM中；或，
    将所述数据指令写入多个所述OCM中被访问次数最小的OCM中；或，
    按照被访问次数由高到低的排列顺序，从多个所述OCM中确定所述被访问次数靠后的M个所述OCM，所述M为不小于1的正整数；
    将所述数据指令写入M个所述OCM中空闲容量最大的OCM中。
  39. 根据权利要求33-38任一项所述的系统，其特征在于，所述数据指令包括数据读指令或者数据写指令。
  40. 根据权利要求39所述的系统，其特征在于，所述系统还包括所述存储芯片外部的第二存储器，所述数据指令为数据读指令时，所述数据读指令用于控制将所述第一存储器中的数据写入所述存储芯片外部的所述第二存储器；或者，
    所述系统还包括所述存储芯片外部的第二存储器、第三存储器，所述数据指令为数据写指令时，所述数据写指令用于控制将所述存储芯片外部的所述第二存储器中的数据写入所述存储芯片外部的所述第三存储器。
  41. 根据权利要求40所述的系统，其特征在于，所述第三存储器包括所述第一存储器。
  42. 根据权利要求33-35任一项所述的系统，其特征在于，所述存储芯片，还用于将所述数据指令写入存储芯片内的存储单元中之前，确定所述数据指令的指令类型；
    所述存储芯片在将所述数据指令写入存储芯片内的存储单元中时，具体用于：若所述数据指令的指令类型属于第一指令类型，则将所述数据指令写入存储芯片内的存储单元中。
  43. 根据权利要求42所述的系统，其特征在于，所述系统还包括所述存储芯片外部的第二存储器；
    所述存储芯片，还用于：若所述数据指令的指令类型属于第二指令类型，则将所述数据指令写入所述第二存储器中。
  44. 根据权利要求43所述的系统，其特征在于，所述第一指令类型为被获取频率大于预设频率的指令，所述第二指令类型为被获取频率小于等于预设频率的指令。
  45. 根据权利要求40或41或43或44所述的系统，其特征在于，所述第一存储器为非易失性存储器，所述第二存储器为易失性存储器。
  46. 根据权利要求45所述的系统，其特征在于，所述第二存储器为双倍速率DDR存储器。
  47. 根据权利要求45所述的系统，其特征在于，所述第一存储器为固态硬盘SSD。
  48. 根据权利要求40或41或43或44所述的系统，其特征在于，所述存储系统为成像系统。
  49. 根据权利要求48所述的系统，其特征在于，所述系统还包括：图像传感器；
    所述图像传感器，用于采集图像数据；
    所述第二存储器，用于存储所述图像传感器采集到的图像数据。
  50. 根据权利要求33或34所述的系统，其特征在于，所述数据指令为基于图像数据的指令。
  51. 一种可移动平台，其特征在于，包括机身和如权利要求33-50任一项所述的存储系统，所述存储系统设于所述机身上。
  52. 根据权利要求51所述的可移动平台，其特征在于，所述可移动平台为飞行器。
PCT/CN2018/101718 2018-08-22 2018-08-22 数据指令处理方法、存储芯片、存储系统和可移动平台 WO2020037542A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2018/101718 WO2020037542A1 (zh) 2018-08-22 2018-08-22 数据指令处理方法、存储芯片、存储系统和可移动平台
CN201880039744.0A CN110770699A (zh) 2018-08-22 2018-08-22 数据指令处理方法、存储芯片、存储系统和可移动平台

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2018/101718 WO2020037542A1 (zh) 2018-08-22 2018-08-22 数据指令处理方法、存储芯片、存储系统和可移动平台

Publications (1)

Publication Number Publication Date
WO2020037542A1 true WO2020037542A1 (zh) 2020-02-27

Family

ID=69328592

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/101718 WO2020037542A1 (zh) 2018-08-22 2018-08-22 数据指令处理方法、存储芯片、存储系统和可移动平台

Country Status (2)

Country Link
CN (1) CN110770699A (zh)
WO (1) WO2020037542A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112631658B (zh) * 2021-01-13 2022-11-15 成都国科微电子有限公司 指令发送方法、芯片和电子设备
CN113254392B (zh) * 2021-07-12 2022-06-14 深圳比特微电子科技有限公司 用于片上系统的数据存储方法和基于片上系统的设备

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101162441A (zh) * 2007-11-09 2008-04-16 华为技术有限公司 数据的存取装置和方法
CN101398752A (zh) * 2007-09-29 2009-04-01 国际商业机器公司 重叠指令存取单元和重叠指令存取方法
CN103634659A (zh) * 2013-12-16 2014-03-12 乐视致新电子科技（天津）有限公司 智能电视的资源读取方法和装置
CN104486390A (zh) * 2014-12-04 2015-04-01 小米科技有限责任公司 数据共享的方法及装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103513957B (zh) * 2012-06-27 2017-07-11 上海芯豪微电子有限公司 高性能缓存方法
CN104346103B (zh) * 2013-08-09 2018-02-02 群联电子股份有限公司 指令执行方法、存储器控制器与存储器储存装置
US9582413B2 (en) * 2014-12-04 2017-02-28 International Business Machines Corporation Alignment based block concurrency for accessing memory
CN107430548B (zh) * 2015-03-06 2021-02-05 东芝存储器株式会社 存储装置的控制方法、及存储装置
US9720604B2 (en) * 2015-08-06 2017-08-01 Sandisk Technologies Llc Block storage protocol to RAM bypass

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101398752A (zh) * 2007-09-29 2009-04-01 国际商业机器公司 重叠指令存取单元和重叠指令存取方法
CN101162441A (zh) * 2007-11-09 2008-04-16 华为技术有限公司 数据的存取装置和方法
CN103634659A (zh) * 2013-12-16 2014-03-12 乐视致新电子科技（天津）有限公司 智能电视的资源读取方法和装置
CN104486390A (zh) * 2014-12-04 2015-04-01 小米科技有限责任公司 数据共享的方法及装置

Also Published As

Publication number Publication date
CN110770699A (zh) 2020-02-07

Similar Documents

Publication Publication Date Title
US11181809B2 (en) Focusing method, imaging device, and unmanned aerial vehicle
CN110733624B (zh) 无人驾驶飞行系统和用于无人驾驶飞行系统的控制系统
WO2021078270A1 (zh) 一种可拆换的云台相机、飞行器、系统及其云台拆换方法
WO2020019106A1 (zh) 云台和无人机控制方法、云台及无人机
CN108924520B (zh) 传输控制方法、装置、控制器、拍摄设备及飞行器
WO2019155335A1 (en) Unmanned aerial vehicle including an omnidirectional depth sensing and obstacle avoidance aerial system and method of operating same
WO2020019331A1 (zh) 气压计的高度测量补偿方法以及无人机
CN111345033A (zh) 参数同步方法、拍摄装置和可移动平台
US20210014427A1 (en) Control device, imaging device, mobile object, control method and program
WO2019113885A1 (zh) 核间通信方法、处理器和多处理器通信系统
WO2020037542A1 (zh) 数据指令处理方法、存储芯片、存储系统和可移动平台
EP3595286B1 (en) Information-processing device, information-processing method, and information-processing program
WO2019227287A1 (zh) 无人机的数据处理方法和设备
WO2020042159A1 (zh) 一种云台的转动控制方法、装置及控制设备、移动平台
US20210105411A1 (en) Determination device, photographing system, movable body, composite system, determination method, and program
WO2019241970A1 (zh) 无人机的扬声器控制方法和设备
WO2020199050A1 (zh) 视频编码方法、设备和可移动平台
JP2021097268A (ja) 制御装置、移動体および制御方法
WO2020062255A1 (zh) 拍摄控制方法和无人机
CN106060357B (zh) 成像设备、无人机及机器人
US11066182B2 (en) Control apparatus, camera apparatus, flying object, control method and program
WO2022027337A1 (zh) 可移动平台的控制系统、控制方法、设备及存储介质
WO2022205294A1 (zh) 无人机的控制方法、装置、无人机及存储介质
WO2020062054A1 (zh) 数据处理方法、设备以及无人机
WO2022227092A1 (zh) 可移动平台、芯片设计的验证装置、验证方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18930613

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18930613

Country of ref document: EP

Kind code of ref document: A1