BR112019005257A2 - predição de violação de memória - Google Patents

predição de violação de memória

Info

Publication number
BR112019005257A2
BR112019005257A2 BR112019005257A BR112019005257A BR112019005257A2 BR 112019005257 A2 BR112019005257 A2 BR 112019005257A2 BR 112019005257 A BR112019005257 A BR 112019005257A BR 112019005257 A BR112019005257 A BR 112019005257A BR 112019005257 A2 BR112019005257 A2 BR 112019005257A2
Authority
BR
Brazil
Prior art keywords
instructions
instruction block
processor
program
violation prediction
Prior art date
Application number
BR112019005257A
Other languages
English (en)
Inventor
krishna Anil
Michael Wright Gregory
Reddy Kothinti Naresh Vignyan
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112019005257A2 publication Critical patent/BR112019005257A2/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1021—Hit rate improvement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/45—Caching of specific data in cache memory
    • G06F2212/452—Instruction code
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6022—Using a prefetch buffer or dedicated prefetch cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6028—Prefetching based on hints or prefetch instructions

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Storage Device Security (AREA)

Abstract

são revelados métodos e equipamentos para impedir violações de memória. em um aspecto, uma unidade de busca acessa, a partir de um preditor de desvio de um processador, um indicador de desambiguação associado com um bloco de instruções de um programa a ser executado pelo processador, e busca, a partir de uma cache de instruções, o bloco de instruções. o processador executa instruções de carregamento e/ou instruções de armazenamento no bloco de instruções baseado no indicador de desambiguação indicando se as instruções de carregamento e/ou as instruções de armazenamento no bloco de instruções podem ou não desviar outras instruções do programa ou serem desviadas por outras instruções do programa.
BR112019005257A 2016-09-22 2017-09-01 predição de violação de memória BR112019005257A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/273,182 US20180081806A1 (en) 2016-09-22 2016-09-22 Memory violation prediction
PCT/US2017/049874 WO2018057274A1 (en) 2016-09-22 2017-09-01 Memory violation prediction

Publications (1)

Publication Number Publication Date
BR112019005257A2 true BR112019005257A2 (pt) 2019-06-04

Family

ID=59846743

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112019005257A BR112019005257A2 (pt) 2016-09-22 2017-09-01 predição de violação de memória

Country Status (7)

Country Link
US (1) US20180081806A1 (pt)
EP (1) EP3516508B1 (pt)
KR (1) KR20190049743A (pt)
CN (1) CN109690477A (pt)
AU (1) AU2017332597A1 (pt)
BR (1) BR112019005257A2 (pt)
WO (1) WO2018057274A1 (pt)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013100783A1 (en) 2011-12-29 2013-07-04 Intel Corporation Method and system for control signalling in a data path module
US10331583B2 (en) 2013-09-26 2019-06-25 Intel Corporation Executing distributed memory operations using processing elements connected by distributed channels
US10684859B2 (en) * 2016-09-19 2020-06-16 Qualcomm Incorporated Providing memory dependence prediction in block-atomic dataflow architectures
US10572376B2 (en) 2016-12-30 2020-02-25 Intel Corporation Memory ordering in acceleration hardware
US10416999B2 (en) 2016-12-30 2019-09-17 Intel Corporation Processors, methods, and systems with a configurable spatial accelerator
US10558575B2 (en) 2016-12-30 2020-02-11 Intel Corporation Processors, methods, and systems with a configurable spatial accelerator
US10474375B2 (en) * 2016-12-30 2019-11-12 Intel Corporation Runtime address disambiguation in acceleration hardware
US10515046B2 (en) 2017-07-01 2019-12-24 Intel Corporation Processors, methods, and systems with a configurable spatial accelerator
US10467183B2 (en) 2017-07-01 2019-11-05 Intel Corporation Processors and methods for pipelined runtime services in a spatial array
US10445234B2 (en) 2017-07-01 2019-10-15 Intel Corporation Processors, methods, and systems for a configurable spatial accelerator with transactional and replay features
US10445451B2 (en) 2017-07-01 2019-10-15 Intel Corporation Processors, methods, and systems for a configurable spatial accelerator with performance, correctness, and power reduction features
US10469397B2 (en) 2017-07-01 2019-11-05 Intel Corporation Processors and methods with configurable network-based dataflow operator circuits
US10515049B1 (en) 2017-07-01 2019-12-24 Intel Corporation Memory circuits and methods for distributed memory hazard detection and error recovery
US11086816B2 (en) 2017-09-28 2021-08-10 Intel Corporation Processors, methods, and systems for debugging a configurable spatial accelerator
US10496574B2 (en) 2017-09-28 2019-12-03 Intel Corporation Processors, methods, and systems for a memory fence in a configurable spatial accelerator
US10445098B2 (en) 2017-09-30 2019-10-15 Intel Corporation Processors and methods for privileged configuration in a spatial array
US10565134B2 (en) 2017-12-30 2020-02-18 Intel Corporation Apparatus, methods, and systems for multicast in a configurable spatial accelerator
US10417175B2 (en) 2017-12-30 2019-09-17 Intel Corporation Apparatus, methods, and systems for memory consistency in a configurable spatial accelerator
US10445250B2 (en) 2017-12-30 2019-10-15 Intel Corporation Apparatus, methods, and systems with a configurable spatial accelerator
US11307873B2 (en) 2018-04-03 2022-04-19 Intel Corporation Apparatus, methods, and systems for unstructured data flow in a configurable spatial accelerator with predicate propagation and merging
US10564980B2 (en) 2018-04-03 2020-02-18 Intel Corporation Apparatus, methods, and systems for conditional queues in a configurable spatial accelerator
US11200186B2 (en) 2018-06-30 2021-12-14 Intel Corporation Apparatuses, methods, and systems for operations in a configurable spatial accelerator
US10853073B2 (en) 2018-06-30 2020-12-01 Intel Corporation Apparatuses, methods, and systems for conditional operations in a configurable spatial accelerator
US10891240B2 (en) 2018-06-30 2021-01-12 Intel Corporation Apparatus, methods, and systems for low latency communication in a configurable spatial accelerator
US10459866B1 (en) 2018-06-30 2019-10-29 Intel Corporation Apparatuses, methods, and systems for integrated control and data processing in a configurable spatial accelerator
US10678724B1 (en) 2018-12-29 2020-06-09 Intel Corporation Apparatuses, methods, and systems for in-network storage in a configurable spatial accelerator
US10915471B2 (en) 2019-03-30 2021-02-09 Intel Corporation Apparatuses, methods, and systems for memory interface circuit allocation in a configurable spatial accelerator
US10965536B2 (en) 2019-03-30 2021-03-30 Intel Corporation Methods and apparatus to insert buffers in a dataflow graph
US10817291B2 (en) 2019-03-30 2020-10-27 Intel Corporation Apparatuses, methods, and systems for swizzle operations in a configurable spatial accelerator
US11029927B2 (en) 2019-03-30 2021-06-08 Intel Corporation Methods and apparatus to detect and annotate backedges in a dataflow graph
US11037050B2 (en) 2019-06-29 2021-06-15 Intel Corporation Apparatuses, methods, and systems for memory interface circuit arbitration in a configurable spatial accelerator
US11416254B2 (en) * 2019-12-05 2022-08-16 Apple Inc. Zero cycle load bypass in a decode group
US11907713B2 (en) 2019-12-28 2024-02-20 Intel Corporation Apparatuses, methods, and systems for fused operations using sign modification in a processing element of a configurable spatial accelerator
KR20210112557A (ko) * 2020-03-05 2021-09-15 에스케이하이닉스 주식회사 메모리 장치에서 연속으로 수행되는 다수의 커맨드 동작에 필요한 파워값을 정확하게 예측할 수 있는 메모리 시스템 및 메모리 시스템의 동작방법
CN111857831B (zh) * 2020-06-11 2021-07-20 成都海光微电子技术有限公司 一种存储体冲突优化方法、并行处理器及电子设备

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7062638B2 (en) * 2000-12-29 2006-06-13 Intel Corporation Prediction of issued silent store operations for allowing subsequently issued loads to bypass unexecuted silent stores and confirming the bypass upon execution of the stores
JP3843048B2 (ja) * 2002-06-28 2006-11-08 富士通株式会社 分岐予測機構を有する情報処理装置
US8170237B2 (en) * 2005-07-19 2012-05-01 Audioasics A/S Programmable microphone
US8127119B2 (en) * 2008-12-05 2012-02-28 The Board Of Regents Of The University Of Texas System Control-flow prediction using multiple independent predictors
CN101763291B (zh) * 2009-12-30 2012-01-18 中国人民解放军国防科学技术大学 一种程序控制流错误检测方法
US20110264528A1 (en) * 2010-04-26 2011-10-27 Whale Peter Contextual recommendations through proposed actions
US9128725B2 (en) * 2012-05-04 2015-09-08 Apple Inc. Load-store dependency predictor content management
US20130346727A1 (en) * 2012-06-25 2013-12-26 Qualcomm Incorporated Methods and Apparatus to Extend Software Branch Target Hints
US9367314B2 (en) * 2013-03-15 2016-06-14 Intel Corporation Converting conditional short forward branches to computationally equivalent predicated instructions
US9619750B2 (en) * 2013-06-29 2017-04-11 Intel Corporation Method and apparatus for store dependence prediction
US9442736B2 (en) * 2013-08-08 2016-09-13 Globalfoundries Inc Techniques for selecting a predicted indirect branch address from global and local caches
US10324727B2 (en) * 2016-08-17 2019-06-18 Arm Limited Memory dependence prediction

Also Published As

Publication number Publication date
US20180081806A1 (en) 2018-03-22
EP3516508A1 (en) 2019-07-31
EP3516508B1 (en) 2020-07-15
AU2017332597A1 (en) 2019-03-07
KR20190049743A (ko) 2019-05-09
CN109690477A (zh) 2019-04-26
WO2018057274A1 (en) 2018-03-29

Similar Documents

Publication Publication Date Title
BR112019005257A2 (pt) predição de violação de memória
BR112016023952A2 (pt) sistema e método para retardar o consumo de energia pelo pós-processamento de dados de sensor
BR112017009159A2 (pt) métodos e biomarcadores para predizer a eficácia e avaliação de um tratamento com agonista de ox40
GB2513266A (en) Providing logical partitions with hardware-thread specific information reflective of exclusive use of a processor core
BR112016012826A2 (pt) Implementação escalável para regiões de estimativa paralela de movimento
BR112015015990A2 (pt) rastreamento de conversão para instalação de aplicativos em dispositivos móveis
BR112017013687A2 (pt) impressão digital geométrica para localização de um dispositivo
MX346008B (es) Comparación de intervalos de series de vectores.
GB2513509A (en) Processor performance improvement for instruction sequences that include barrier instructions
BR112015022636A2 (pt) sistema de determinação de contexto de saúde
BR102012019557A2 (pt) Rastreamento com a consideração de mobilidade
BR112015017774A2 (pt) sistema, método e produto de programa de computador para projeto de sistema fotométrico e robustecimento ambiental
BR112013019563A2 (pt) métodos para prognóstico de ferida, para tratamento de ferida, para prognosticar se um paciente pode ser responsivo ao tratamento de uma ferida que exsuda um fluido de ferida, e para tratar uma ferida que exsuda um fluido de ferida, dispositivo para medir simultaneamente ou sequencialmente os níveis de hne e de pelo menos uma mmp em uma amostra de fluido de ferida, aparelho para diagnóstico, e, estojo.
BR112018077475A2 (pt) componente, programa de computador, sistema e kit para determinação para prescrição de óculos de grau
GB2571899A (en) Branch predictor search qualification using stream length prediction
RU2015125071A (ru) Способ и устройство для установки состояния прикладного приложения
BR112015018950A2 (pt) máscara de memória de alteração de fase
BR112017004249A2 (pt) sistema e método para segurança baseada em localização
BR112015018696A2 (pt) rotulagem de padrão
BR112014010634A8 (pt) Método implementado por computador, dispositivo de computação e meio de armazenamento legível por computador
BR112015032670A8 (pt) direcionamentos de sistema de posicionamento global tipo-humano
BR112018077404A2 (pt) sistema e método de marcação em grupo baseados na aprendizagem
BR112015018529A2 (pt) inferência de preferências da web a partir de dispositivo móvel
RU2013156495A (ru) Разрешение семантической неоднозначности при помощи семантического классификатора
BR112014013562A8 (pt) método, instruções de armazenamento por meio de armazenamento não transitório, e aparelho

Legal Events

Date Code Title Description
B11A Dismissal acc. art.33 of ipl - examination not requested within 36 months of filing
B11Y Definitive dismissal - extension of time limit for request of examination expired [chapter 11.1.1 patent gazette]