CL2019001579A1 - Bits de verificación por redundancia cíclica combinada para decodificación conjunta y verificación de información de control usando códigos polares. - Google Patents

Bits de verificación por redundancia cíclica combinada para decodificación conjunta y verificación de información de control usando códigos polares.

Info

Publication number
CL2019001579A1
CL2019001579A1 CL2019001579A CL2019001579A CL2019001579A1 CL 2019001579 A1 CL2019001579 A1 CL 2019001579A1 CL 2019001579 A CL2019001579 A CL 2019001579A CL 2019001579 A CL2019001579 A CL 2019001579A CL 2019001579 A1 CL2019001579 A1 CL 2019001579A1
Authority
CL
Chile
Prior art keywords
control information
cyclic redundancy
checking
redundancy check
check bits
Prior art date
Application number
CL2019001579A
Other languages
English (en)
Spanish (es)
Inventor
Joseph Binamira Soriaga
Changlong Xu
Jilei Hou
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CL2019001579A1 publication Critical patent/CL2019001579A1/es

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H04L43/0823—Errors, e.g. transmission errors
    • H04L43/0847—Transmission error
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
    • H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
    • H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
    • H04L69/324—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the data link layer [OSI layer 2], e.g. HDLC
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Environmental & Geological Engineering (AREA)
  • Computer Security & Cryptography (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
CL2019001579A 2016-12-15 2019-06-10 Bits de verificación por redundancia cíclica combinada para decodificación conjunta y verificación de información de control usando códigos polares. CL2019001579A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2016/110088 WO2018107430A1 (en) 2016-12-15 2016-12-15 Crc bits for joint decoding and verification of control information using polar codes

Publications (1)

Publication Number Publication Date
CL2019001579A1 true CL2019001579A1 (es) 2019-10-18

Family

ID=62557630

Family Applications (1)

Application Number Title Priority Date Filing Date
CL2019001579A CL2019001579A1 (es) 2016-12-15 2019-06-10 Bits de verificación por redundancia cíclica combinada para decodificación conjunta y verificación de información de control usando códigos polares.

Country Status (14)

Country Link
US (3) US11601217B2 (cg-RX-API-DMAC10.html)
EP (2) EP3556032A4 (cg-RX-API-DMAC10.html)
JP (1) JP7195255B2 (cg-RX-API-DMAC10.html)
KR (1) KR102418673B1 (cg-RX-API-DMAC10.html)
CN (2) CN114884619B (cg-RX-API-DMAC10.html)
AU (1) AU2017374543B2 (cg-RX-API-DMAC10.html)
BR (1) BR112019010982A2 (cg-RX-API-DMAC10.html)
CL (1) CL2019001579A1 (cg-RX-API-DMAC10.html)
CO (1) CO2019006091A2 (cg-RX-API-DMAC10.html)
IL (1) IL266267B (cg-RX-API-DMAC10.html)
MX (2) MX2019006210A (cg-RX-API-DMAC10.html)
PH (1) PH12019500964A1 (cg-RX-API-DMAC10.html)
RU (1) RU2733282C1 (cg-RX-API-DMAC10.html)
WO (2) WO2018107430A1 (cg-RX-API-DMAC10.html)

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KR20240078427A (ko) * 2021-10-08 2024-06-03 엘지전자 주식회사 무선통신 시스템에서 장치의 코드 블록 분할 방법 및 장치
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Also Published As

Publication number Publication date
US12113615B2 (en) 2024-10-08
JP7195255B2 (ja) 2022-12-23
CN110089057B (zh) 2022-05-24
WO2018107680A1 (en) 2018-06-21
US20230336270A1 (en) 2023-10-19
JP2020502910A (ja) 2020-01-23
US11601217B2 (en) 2023-03-07
KR102418673B1 (ko) 2022-07-07
EP3556032A4 (en) 2020-08-05
US20200235854A1 (en) 2020-07-23
EP4425806A3 (en) 2024-11-13
CA3042955A1 (en) 2018-06-21
MX2022014639A (es) 2023-01-18
US20200076535A1 (en) 2020-03-05
PH12019500964A1 (en) 2019-08-19
CO2019006091A2 (es) 2019-06-19
IL266267B (en) 2020-03-31
AU2017374543B2 (en) 2022-09-29
CN114884619B (zh) 2024-04-26
EP4425806A2 (en) 2024-09-04
US11711163B2 (en) 2023-07-25
MX2019006210A (es) 2019-11-11
EP3556032A1 (en) 2019-10-23
IL266267A (en) 2019-06-30
KR20190093582A (ko) 2019-08-09
US20230246739A9 (en) 2023-08-03
CN110089057A (zh) 2019-08-02
CN114884619A (zh) 2022-08-09
RU2733282C1 (ru) 2020-10-01
AU2017374543A1 (en) 2019-05-23
BR112019010982A2 (pt) 2019-10-15
WO2018107430A1 (en) 2018-06-21
NZ753016A (en) 2024-11-29

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