BR112018014387A2 - segmentação de blocos de códigos para codificação adaptativa de carga útil usando códigos turbo e códigos ldpc - Google Patents
segmentação de blocos de códigos para codificação adaptativa de carga útil usando códigos turbo e códigos ldpcInfo
- Publication number
- BR112018014387A2 BR112018014387A2 BR112018014387A BR112018014387A BR112018014387A2 BR 112018014387 A2 BR112018014387 A2 BR 112018014387A2 BR 112018014387 A BR112018014387 A BR 112018014387A BR 112018014387 A BR112018014387 A BR 112018014387A BR 112018014387 A2 BR112018014387 A2 BR 112018014387A2
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- payload
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- 230000003044 adaptive effect Effects 0.000 title 1
- 230000011218 segmentation Effects 0.000 title 1
- 238000000034 method Methods 0.000 abstract 3
- 125000004122 cyclic group Chemical group 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0075—Transmission of coding parameters to receiver
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
- H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
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- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
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- H—ELECTRICITY
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- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2957—Turbo codes and decoding
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- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/35—Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
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- H03M13/35—Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics
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- H03M13/35—Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
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- H03M13/63—Joint error correction and other techniques
- H03M13/6306—Error control coding in combination with Automatic Repeat reQuest [ARQ] and diversity transmission, e.g. coding schemes for the multiple transmission of the same information or the transmission of incremental redundancy
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
- H03M13/6513—Support of multiple code types, e.g. unified decoder for LDPC and turbo codes
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- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0006—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format
- H04L1/0007—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format by modifying the frame length
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- H—ELECTRICITY
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- H04L1/0041—Arrangements at the transmitter end
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- H—ELECTRICITY
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- H04L1/00—Arrangements for detecting or preventing errors in the information received
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- H—ELECTRICITY
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- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
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- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0064—Concatenated codes
- H04L1/0066—Parallel concatenated codes
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
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- H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
- H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
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- H04L1/1607—Details of the supervisory signal
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- H04L5/003—Arrangements for allocating sub-channels of the transmission path
- H04L5/0053—Allocation of signaling, i.e. of overhead other than pilot signals
- H04L5/0055—Physical resource allocation for ACK/NACK
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- H04W84/02—Hierarchically pre-organised networks, e.g. paging networks, cellular networks, WLAN [Wireless Local Area Network] or WLL [Wireless Local Loop]
- H04W84/04—Large scale networks; Deep hierarchical networks
- H04W84/042—Public Land Mobile systems, e.g. cellular systems
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- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Mobile Radio Communication Systems (AREA)
- Error Detection And Correction (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Abstract
são descritas técnicas para comunicação sem fio. um método pode incluir a seleção de um tipo de codificação para cada carga útil de uma pluralidade de cargas úteis. a seleção incluir selecionar um tipo de codificação de código de verificação de paridade de baixa densidade (ldpcc) para pelo menos uma primeira carga útil e selecionar um tipo de codificação de código turbo (tc) para pelo menos uma segunda carga útil. o método também inclui segmentar cada carga útil em uma pluralidade de blocos de código; gerar, para cada bloco de código, uma verificação cíclica de redundância (crc); codificar cada bloco de código e crc associada em uma ou mais palavras-código de uma pluralidade de palavras-código, em que a codificação se baseia, pelo menos em parte, no tipo de codificação selecionado para uma carga útil associada ao bloco de códigos; e transmitir as palavras-código.
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
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US201662278689P | 2016-01-14 | 2016-01-14 | |
US62/278,689 | 2016-01-14 | ||
US15/369,525 | 2016-12-05 | ||
US15/369,525 US10367530B2 (en) | 2016-01-14 | 2016-12-05 | Unified code block segmentation providing a cyclic redundancy check for low density parity check code codewords |
PCT/US2016/065145 WO2017123345A1 (en) | 2016-01-14 | 2016-12-06 | Code block segmentation for payload adaptive encoding using turbo codes and ldpc codes |
Publications (2)
Publication Number | Publication Date |
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BR112018014387A2 true BR112018014387A2 (pt) | 2018-12-11 |
BR112018014387B1 BR112018014387B1 (pt) | 2024-02-27 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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BR112018014387-1A BR112018014387B1 (pt) | 2016-01-14 | 2016-12-06 | Segmentação de blocos de códigos para codificação adaptativa de carga útil usando códigos turbo e códigos ldpc |
Country Status (7)
Country | Link |
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US (3) | US10367530B2 (pt) |
EP (1) | EP3403332A1 (pt) |
JP (2) | JP6957474B2 (pt) |
KR (2) | KR20240049653A (pt) |
CN (2) | CN114553374A (pt) |
BR (1) | BR112018014387B1 (pt) |
WO (1) | WO2017123345A1 (pt) |
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JP2022008887A (ja) | 2022-01-14 |
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CN108604905A (zh) | 2018-09-28 |
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WO2017123345A1 (en) | 2017-07-20 |
KR20240049653A (ko) | 2024-04-16 |
KR20180103889A (ko) | 2018-09-19 |
JP2019503146A (ja) | 2019-01-31 |
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