CH671653A5 - - Google Patents

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Publication number
CH671653A5
CH671653A5 CH433786A CH433786A CH671653A5 CH 671653 A5 CH671653 A5 CH 671653A5 CH 433786 A CH433786 A CH 433786A CH 433786 A CH433786 A CH 433786A CH 671653 A5 CH671653 A5 CH 671653A5
Authority
CH
Switzerland
Prior art keywords
metal
metal silicide
silicon body
bonding
sintering
Prior art date
Application number
CH433786A
Other languages
German (de)
English (en)
Inventor
Katalin Solt
Original Assignee
Landis & Gyr Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Landis & Gyr Ag filed Critical Landis & Gyr Ag
Priority to CH433786A priority Critical patent/CH671653A5/de
Priority to DE19873721929 priority patent/DE3721929A1/de
Publication of CH671653A5 publication Critical patent/CH671653A5/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Pressure Sensors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Ceramic Products (AREA)
CH433786A 1986-11-03 1986-11-03 CH671653A5 (pt)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CH433786A CH671653A5 (pt) 1986-11-03 1986-11-03
DE19873721929 DE3721929A1 (de) 1986-11-03 1987-07-02 Verfahren zur herstellung hermetisch dichter elektrischer leiterbahnen in halbleiterelementen

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CH433786A CH671653A5 (pt) 1986-11-03 1986-11-03

Publications (1)

Publication Number Publication Date
CH671653A5 true CH671653A5 (pt) 1989-09-15

Family

ID=4274212

Family Applications (1)

Application Number Title Priority Date Filing Date
CH433786A CH671653A5 (pt) 1986-11-03 1986-11-03

Country Status (2)

Country Link
CH (1) CH671653A5 (pt)
DE (1) DE3721929A1 (pt)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19741924C2 (de) * 1997-09-23 2000-03-02 Siemens Ag Verfahren zum elektrochemischen Verbinden und Verbundteil

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1138401A (en) * 1965-05-06 1969-01-01 Mallory & Co Inc P R Bonding

Also Published As

Publication number Publication date
DE3721929C2 (pt) 1990-02-08
DE3721929A1 (de) 1988-05-11

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Legal Events

Date Code Title Description
PL Patent ceased