CA3040604A1 - Receiving apparatus using low-density parity check code and bit deinterleaving and receiving method thereof - Google Patents

Abstract

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

Description

TRANSMITTING APPARATUS AND INTERLEAVING METHOD THEREOF
This application is a divisional of Canadian patent application No. 2940011 filed on February 23, 2015.
[Technical Field]
Apparatuses and methods consistent with exemplary embodiments relate to a transmitting apparatus and an interleaving method thereof, and more particularly, to a transmitting apparatus which processes and transmits data, and an interleaving method thereof.
[Background Art]
In the 21st century information-oriented society, broadcasting communication services are moving into the era of digitalization, multi-channel, wideband, and high quality. In particular, as high quality digital televisions, portable multimedia players and portable broadcasting equipment are increasingly used in recent years, there is an increasing demand for methods for supporting various receiving methods of digital broadcasting services.
In order to meet such demand, standard groups are establishing various standards and are providing a variety of services to satisfy users' needs. Therefore, there is a need for a method for providing improved services to users with high decoding and receiving performance.
[Disclosure]
[Technical Problem]
Exemplary embodiments of the inventive concept may overcome the above disadvantages and other disadvantages not described above. However, it is understood that the exemplary embodiment are not required to overcome the disadvantages described above, and may not overcome any of the problems described above.
The exemplary embodiments provide a transmitting apparatus which can map a bit included in a predetermined bit group from among a plurality of bit groups of a low density parity check (LDPC) codeword onto a predetermined bit of a modulation symbol, and transmit the bit, and an interleaving method thereof.
[Technical Solution]
According to an aspect of an exemplary embodiment, there is provided a transmitting apparatus incluidng: an encoder configured to generate an LDPC codeword by LDPC
encoding

2 based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.
Each of the plurality of bit groups may be formed of M number of bits. M may be a common divisor of Nkipo and Kldpo and may be determined to satisfy Qidpc=(Niapc-Kkipc)/M. In this case, Qldpc may be a cyclic shift parameter value regarding columns in a column group of an information word submatrix of the parity check matrix, Nkipc may be a length of the LDPC
codeword, and Kid may be a length of information word bits of the LDPC
codeword.
The interleaver may include: a parity interleaver configured to interleave parity bits of the LDPC codeword; a group interleaver configured to divide the parity-interleaved LDPC
codeword by the plurality of bit groups and rearrange an order of the plurality of bit groups in bit group wise; and a block interleaver configured to interleave the plurality of bit groups the order of which is rearranged.
The group interleaver may be configured to rearrange the order of the plurality of bit groups in bit group wise by using the following equation:
Yi =X1(0 j < N
group 3 where Xi is a jth bit group before the plurality of bit groups are interleaved, Yj is a jth bit group after the plurality of bit groups are interleaved, Ngroup is a total number of the plurality of bit groups, and n(j) is a parameter indicating an interleaving order.
Here, 7t(j) may be determined based on at least one of a length of the LDPC
codeword, a modulation method, and a code rate.
When the LDPC codeword has a length of 64800, the modulation method is 16-QAM, and the code rate is 6/15,7c(j) may be defined as in table 11.
When the LDPC codeword has a length of 64800, the modulation method is 16-QAM, and the code rate is 10/15, n(j) may be defined as in table 14.
When the LDPC codeword has a length of 64800, the modulation method is 16-QAM, and the code rate is 12/15, 7r(j) may be defined as in table 15.
When the LDPC codeword has a length of 64800, the modulation method is 64-QAM, and the code rate is 6/15, 7t(j) may be defined as in table 17.

3 When the LDPC codeword has a length of 64800, the modulation method is 64-QAM, and the code rate is 8/15,7[(j) may be defined as in table 18.
When the LDPC codeword has a length of 64800, the modulation method is 64-QAM, and the code rate is 12/15, 7r(j) may be defined as in table 21.
The block interle aver may be configured to interleave by writing the plurality of bit groups in each of a plurality of columns in bit group wise in a column direction, and reading each row of the plurality of columns in which the plurality of bit groups are written in bit group wise in a row direction.
The block interleaver may be configured to serially write, in the plurality of columns, at least some bit groups which are writable in the plurality of columns in bit group wise from among the plurality of bit groups, and then divide and write the other bit groups in an area which remains after the at least some bit groups are written in the plurality of columns in bit group wise.
According to an aspect of another exemplary embodiment, there is provided an interleaving method of a transmitting apparatus, including: generating an LDPC codeword by LDPC
encoding based on a parity check matrix; interleaving the LDPC codeword; and mapping the interleaved LDPC codeword onto a modulation symbol, wherein the mapping comprises mapping a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.
Each of the plurality of bit groups may be formed of M number of bits, and M
may be a common divisor of Nidp, and Kidp, and may be determined to satisfy Qidpc=(Nkipc-Kidpc)/M. In this case, ()kip, may be a cyclic shift parameter value regarding columns in a column group of an information word submatrix of the parity check matrix, Nidp, may be a length of the LDPC
codeword, and Kid may be a length of information word bits of the LDPC
codeword.
The interleaving may include: interleaving parity bits of the LDPC codeword;
dividing the parity-interleaved LDPC codeword by the plurality of bit groups and rearranging an order of the plurality of bit groups in bit group wise; and interleaving the plurality of bit groups the order of which is rearranged.
The rearranging in bit group wise may include rearranging the order of the plurality of bit groups in bit group wise by using the following equation:
Yj = X,r(j)(0 j < N ) group where N is a jth bit group before the plurality of bit groups are interleaved, Yj is a 1th bit group

4 after the plurality of bit groups are interleaved, Ngroup is a total number of the plurality of bit groups, and 7c(j) is a parameter indicating an interleaving order.
Here, 7r(j) may be determined based on at least one of a length of the LDPC
codeword, a modulation method, and a code rate.
When the LDPC codeword has a length of 64800, the modulation method is 16-QAM, and the code rate is 6/15, 7c(j) may be defined as in table 11.
When the LDPC codeword has a length of 64800, the modulation method is 16-QAM, and the code rate is 10/15, 7r(j) may be defined as in table 14.
When the LDPC codeword has a length of 64800, the modulation method is 16-QAM, and the code rate is 12/15, 7r(j) may be defined as in table 15.
When the LDPC codeword has a length of 64800, the modulation method is 64-QAM, and the code rate is 6/15, 71(j) may be defined as in table 17.
When the LDPC codeword has a length of 64800, the modulation method is 64-QAM, and the code rate is 8/15, 7r(j) may be defined as in table 18.
When the LDPC codeword has a length of 64800, the modulation method is 64-QAM, and the code rate is 12/15, 7r(j) may be defined as in table 21.
The interleaving the plurality of bit groups may include interleaving by writing the plurality of bit groups in each of a plurality of columns in bit group wise in a column direction, and reading each row of the plurality of columns in which the plurality of bit groups are written in bit group wise in a row direction.
The interleaving the plurality of bit groups may include serially writing, in the plurality of columns, at least some bit groups which are writable in the plurality of columns in bit group wise from among the plurality of bit groups, and then dividing and writing the other bit groups in an area which remains after the at least some bit groups are written in the plurality of columns in bit group wise.
According to an embodiment, there is provided a transmitting apparatus comprising: an encoder configured to encode input bits to generate parity bits based on a low density parity check (LDPC) code according to a code rate of 6/15 and a code length of 64800;
an interleaver configured to interleave the parity bits, split a codeword into a plurality of bit groups, and interleave the plurality of bit groups to provide an interleaved codeword, wherein the codeword comprising the input bits and the interleaved parity bits; and a mapper configured to map bits of the interleaved codeword onto constellation points for 16-quadrature amplitude 4a modulation(QAM), wherein the plurality of bit groups are interleaved based on a following equation: Yi = X"cm for (0 < Ngroup) , where Xj is a jth bit group among the plurality of bit groups, Yi is a ith bit group among the interleaved plurality of bit groups, Ngroup is a total number of the plurality of bit groups, and n(j) denotes a permutation order for the interleaving of the plurality of bit groups, and wherein the ir(j) is defined as follows:
Order of interleaving m(j) (0 j < 180) Code Rate 46 47 48 49 50 51 52 53 54 55 56 103 104 105 106 107 108 109 II() 111 112 113 6/15 it(j) In another embodiment there is a receiving apparatus comprising a receiver configured to receive a signal from a transmitting apparatus; a demodulator configured to demodulate the signal to generate values according to a 16-quadrature amplitude modulation(QAM); a deinterleaver configured to split the values into a plurality of groups, deinterleave the plurality of groups and deinterleave one or more values among the deinterleaved plurality of groups to provide deinterleaved values; and a decoder configured to decode the deinterleaved values based on a low density parity check (LDPC) code having a code rate being 6/15 and a code length being 64800 bits, wherein the plurality of groups are deinterleaved based on a following equation:

4b In(j) = Xj for (0 < Ngroup) where xi is a jth group among the plurality of groups, Yi is a jth group among the deinterleaved plurality of groups, Ngroup is a total number of the plurality of groups, and it(j) denotes a deinterleaving order for the deinterleaving, and wherein the n(j) is represented as follows:
Order of deinterleaving m(j) (0 j < 180) (ode Rate 6/15 3t(j) =
In another embodiment there is a receiving method comprising receiving a signal from a transmitting apparatus; demodulating the signal to generate values according to a 16-quadrature amplitude modulation(QAM); splitting the values into a plurality of groups;
deinterleaving the plurality of groups; deinterleaving one or more values among the deinterleaved plurality of groups to provide deinterleaved values; and decoding the deinterleaved values based on a low density parity check (LDPC) code having a code rate being 6/15 and a code length being 64800 bits, wherein the plurality of groups are deinterleaved based on a following equation:
Y7c(j) = Xj for (0 < Ngroup) 4c where N is a ith group among the plurality of groups, Yi is a ith group among the deinterleaved plurality of groups, Ngroup is a total number of the plurality of groups, and it(j) denotes a deinterleaving order for the deinterleaving, and wherein the n(j) is represented as follows:
Order of deinterleaving Ira) (0 j <180) Code Rate 46 47 48 49 50 51 52 53 54 55 56 6/15 no) [Advantageous Effects]
According to various exemplary embodiments, improved decoding and receiving performance can be provided.
[Description of Drawings]
The above and/or other aspects will be more apparent by describing in detail exemplary embodiments, with reference to the accompanying drawings, in which:

5 FIG. 1 is a block diagram to illustrate a configuration of a transmitting apparatus, according to an exemplary embodiment;
FIGs. 2 to 4 are views to illustrate a configuration of a parity check matrix, according to exemplary embodiments;
FIG. 5 is a block diagram to illustrate a configuration of an interleaver, according to an exemplary embodiment;
FIGs. 6 to 8 are views to illustrate an interleaving method, according to exemplary embodiments;
FIGs. 9 to 14 are views to illustrate an interleaving method of a block interleaver, according to exemplary embodiments;
FIG. 15 is a view to illustrate an operation of a demultiplexer, according to an exemplary embodiment;
FIGs. 16 and 17 are views to illustrate a method for designing an interleaving pattern, according to exemplary embodiments;
FIG. 18 is a block diagram to illustrate a configuration of a receiving apparatus according to an exemplary embodiment;
FIG. 19 is a block diagram to illustrate a configuration of a deinterleaver, according to an exemplary embodiment;
FIG. 20 is a view to illustrate a deinterleaving method of a block deinterleaver, according to an exemplary embodiment; and FIG. 21 is a flowchart to illustrate an interleaving method, according to an exemplary embodiment.
[Mode for Invention]
Hereinafter, various exemplary embodiments will be described in greater detail with reference to the accompanying drawings.
In the following description, same reference numerals are used for the same elements when they are depicted in different drawings. The matters defined in the description, such as detailed construction and elements, are provided to assist in a comprehensive understanding of the exemplary embodiments. Thus, it is apparent that the exemplary embodiments can be carried out without those specifically defined matters. Also, functions or elements known in the related art are not described in detail since they would obscure the exemplary embodiments with

6 unnecessary detail.
FIG. 1 is a block diagram to illustrate a configuration of a transmitting apparatus according to an exemplary embodiment. Referring to FIG. 1, the transmitting apparatus 100 includes an encoder 110, an interleaver 120, and a modulator 130 (or a constellation mapper).
The encoder 110 generates a low density parity check (LDPC) codeword by performing LDPC encoding based on a parity check matrix. To achieve this, the encoder 110 may include an LDPC encoder (not shown) to perform the LDPC encoding.
Specifically, the encoder 110 LDPC-encodes information word(or information) bits to generate the LDPC codeword which is formed of information word bits and parity bits (that is, LDPC parity bits). Here, bits input to the encoder 110 may be used as the information word bits.
Also, since an LDPC code is a systematic code, the information word bits may be included in the LDPC codeword as they are.
The LDPC codeword is formed of the information word bits and the parity bits.
For example, the LDPC codeword is formed of Nidpc number of bits, and includes Kid number of information word bits and Nparity.---Niapc-Kkipc number of parity bits.
In this case, the encoder 110 may generate the LDPC codeword by performing the LDPC
encoding based on the parity check matrix. That is, since the LDPC encoding is a process for generating an LDPC codeword to satisfy H=CT=0, the encoder 110 may use the parity check matrix when performing the LDPC encoding. Herein, H is a parity check matrix and C is an LDPC codeword.
For the LDPC encoding, the transmitting apparatus 100 may include a memory and may pre-store parity check matrices of various formats.
For example, the transmitting apparatus 100 may pre-store parity check matrices which are defined in Digital Video Broadcasting-Cable version 2 (DVB-C2), Digital Video Broadcasting-Satellite-Second Generation (DVB-S2), Digital Video Broadcasting-Second Generation Terrestrial (DVB-T2), etc., or may pre-store parity check matrices which are defined in the North America digital broadcasting standard system Advanced Television System Committee (ATSC) 3.0 standards, which are currently being established. However, this is merely an example and the transmitting apparatus 100 may pre-store parity check matrices of other formats in addition to these parity check matrices.
Hereinafter, a parity check matrix according to various exemplary embodiments will be

7 explained in detail with reference to the drawings. In the parity check matrix, elements other than elements having 1 have 0.
For example, the parity check matrix according to an exemplary embodiment may have a configuration of FIG. 2.
Referring to FIG. 2, a parity check matrix 200 is formed of an information word submatrix(or an information submatrix) 210 corresponding to information word bits, and a parity submatrix 220 corresponding to parity bits.
The information word submatrix 210 includes Kid number of columns and the parity submatrix 220 includes Npar1ty=N1dpc-K1dpc number of columns. The number of rows of the parity check matrix 200 is identical to the number of columns of the parity submatrix 220, Nparity=N1dpc-Kldpc=
In addition, in the parity check matrix 200, NI* is a length of an LDPC
codeword, Kidpc is a length of information word bits, and Nparity=N1dpc-Kidpc is a length of parity bits. The length of the LDPC codeword, the information word bits, and the parity bits mean the number of bits included in each of the LDPC codeword, the information word bits, and the parity bits.
Hereinafter, the configuration of the information word submatrix 210 and the parity submatrix 220 will be explained in detail.
The information word submatrix 210 includes Kid number of columns (that is, Oth column to (Kidpc-1)th column), and follows the following rules:
First, M number of columns from among Kid number of columns of the information word submatrix 210 belong to the same group, and Kid number of columns is divided into KidpdM
number of column groups. In each column group, a column is cyclic-shifted from an immediately previous column by Qmpe. That is, Qidpe may be a cyclic shift parameter value regarding columns in a column group of the information word submatrix 210 of the parity check matrix 200.
Herein, M is an interval at which a pattern of a column group, which includes a plurality of columns, is repeated in the information word submatrix 210 (e.g., M=360), and Oldpc is a size by which one column is cyclic-shifted from an immediately previous column in a same column group in the information word submatrix 210. Also, M is a common divisor of Nicip, and Kid and is determined to satisfy Qidp,=(Nidpc-Kidpc)/M. Here, M and Qidpc are integers and Kidpc/M is also an integer. M and Oidpc may have various values according to a length of the LDPC codeword

8 and a code rate (CR)(or, coding rate).
For example, when M=360 and the length of the LDPC codeword, Nidpc, is 64800, Qidpc may be defined as in table 1 presented below, and, when M=360 and the length Map, of the LDPC
codeword is 16200, Qidpc may be defined as in table 2 presented below.
[Table 1]
Code Rate NicIpc M Qldpc

9/15 64800 360 72

10/15 64800 360 60

11/15 64800 360 48

12/15 64800 360 36

13/15 64800: 360 24 [Table 2]
Code Rate Nldpc M Qldpc Second, when the degree of the O'h column of the ith column group (i=0, 1, ..., Kidpc/M-1) is Di (herein, the degree is the number of value 1 existing in each column and all columns belonging to the same column group have the same degree), and a position (or an index) of each row where 1 exists in the Oth column of the ith column group is RP0),R,T,- , an index Ri(ki)of a row where kth 1 is located in the jth column in the ith column group is determined by following Equation 1:
RJ = Cj_1) +Qmpe mod(Nidpc -Kidpc) ... (1), where k=0, 1,2, ...D1-1; i=0, 1, ..., Kidpc/M-1; and j=1, 2, ..., M-1.
Equation 1 can be expressed as following Equation 2:

RJ =
+ (j modM) x Qup,} mod(N ¨ Kidpc) ... (2), where k=0, 1,2, ...D1-1; i=0, 1, ..., Kidpe/M-1; and j=1, 2, ..., M-1. Since j=1, 2, = =, M-1, (j mod M) of Equation 2 may be regarded as j.
In the above equations, Ri(ki) is an index of a row where kth 1 is located in the jth column in the =th column group, Nidpe is a length of an LDPC codeword, Kid is a length of information word bits, Di is a degree of columns belonging to the ith column group, M is the number of columns belonging to a single column group, and Qldpc is a size by which each column in the column group is cyclic-shifted.
As a result, referring to these equations, when only R(ko) is known, the index Rrj) of the row where the kth 1 is located in the jth column in the ith column group can be known. Therefore, when the index value of the row where the kth 1 is located in the Oth column of each column group is stored, a position of column and row where 1 is located in the parity check matrix 200 having the configuration of FIG. 2 (that is, in the information word submatrix 210 of the parity check matrix 200) can be known.
According to the above-described rules, all of the columns belonging to the ith column group have the same degree Di. Accordingly, the LDPC codeword which stores information on the parity check matrix according to the above-described rules may be briefly expressed as follows.
For example, when NIdpc is 30, Kidpe is 15, and ()mix is 3, position information of the row where 1 is located in the Oth column of the three column groups may be expressed by a sequence of Equations 3 and may be referred to as "weight-1 position sequence".
R:1( =1,R:20) = 2, R:30) = 8,R:40) =10, le)õ, = 0,1e, = 9, R13, = 13, = 0,4; =14.
(3), where Ri(kj) is an index of a row where kth 1 is located in the jth column in the ith column group.
The weight-1 position sequence like Equation 3 which expresses an index of a row where 1 is located in the 0th column of each column group may be briefly expressed as in Table 3 presented below:
[Table 3]

=0 9 13 Table 3 shows positions of elements having value 1 in the parity check matrix, and the ith weight-1 position sequence is expressed by indexes of rows where 1 is located in the 0th column belonging to the ith column group.
The information word submatrix 210 of the parity check matrix according to an exemplary embodiment may be defined as in Tables 4 to 8 presented below, based on the above descriptions.
Specifically, Tables 4 to 8 show indexes of rows where 1 is located in the Oth column of the ith column group of the information word submatrix 210. That is, the information word submatrix 210 is formed of a plurality of column groups each including M number of columns, and positions of 1 in the 0th column of each of the plurality of column groups may be defined by Tables 4 to 8.
Herein, the indexes of the rows where 1 is located in the 0th column of the ith column group mean "addresses of parity bit accumulators". The "addresses of parity bit accumulators" have the same meaning as defined in the DVB-C2/S2/T2 standards or the ATSC 3.0 standards which are currently being established, and thus, a detailed explanation thereof is omitted.
For example, when the length Nicip, of the LDPC codeword is 64800, the code rate is 6/15, and M is 360, the indexes of the rows where 1 is located in the 0th column of the ith column group of the information word submatrix 210 are as shown in Table 4 presented below:
[Table 4]

CC of row where 1k locatecithe oth column of theith. column group.

35462 36153 36740 3708$ 37152 3746817658 , 28666303213271436390 37015 37162 3 .700 897 1708 6017 6490 7372 7825 9546 10398 16605,18561 18745 21625 .29687339383452034658 37056 maw 6 1264 4254.69369165 9416 9950 10861 11653 13697 13961 15164 13665 7. 111 1302 1628 2041 1524 5358 79881291 10322 1199512919 14127 15515 15711 17061. 19024 21195 22902 23727 24401 961 3035 7174 7948 13355 13607 14971 18189 18339 18665 iss75 19142 20615 21136 27583 30006 3111832106.36469 36583 37920 155 4313 .5145 6885 8123 9730 11840 12216 19194 20313 23056 24248 24830 25268 22395 22818 23261 23422 24064.26329 27723

14 1856 15100 19378 21848

15. 943 11191 2780629411 .9587 10626 11/347 25700 =

26 also 16627934 30021 39 4796 6230 25203 vssa 43 12246 12372 16'746 27452 In another example, when the length Nidpc of the LDPC codeword is 64800, the code rate is 8/15, and M is 360, the indexes of the rows where 1 is located in the Os"
column of the ith column group of the information word submatrix 210 are as shown in Table 5 presented below:
[Table 5]

Index of row where 1 is located in the 0th column of the ith column group 7 101$ 2002 5764 6777 9346 9629 11039 11/53 12690 13068 13990 16841 8 14$0 3084 3467 4401 4798 3187 7851 11368 12323 14325 14546 16360 12 10.17 1494 1718 4645 5030 6811 7868 $146 10611 15767 17682 18391

16 612 1528 2004 4244 45994926 1843 7684 10122 10443 12267 14363 13413

17 1361 2195 41466708 7118 7538 9138 9998 14862 15359 16076 18923 21401

18 52296235 7134 7655 9139 13527 15408 16038 16705 18320 19909 20901,22238 224372365425131 2755028247 29903

19 6972035 41387 5275 6909 9166 11805 15338 16381 18403 20425 20688 36 $927 18086 23525 1132 1290 $786 =

47 , 2185 3705 26834 49 12697134072217*

CA 3 0 4 0 6 0 4 2 0 1 9 ¨ 0 4 ¨ 1 7 78 10,861 119$0 14110 SO e74 17243 21989 $S = 30103 94 2895 8,930 15594 In another example, when the length Nidpc of the LDPC codeword is 64800, the code rate is th 10/15, and M is 360, the indexes of rows where 1 exists in the 0th column of the =column group of the information word submatrix 210 are defined as shown in Table 6 below.
[Table 6]

=
. index of row where us located in the 0th column of the itb column group - =
9791,43341964499 63418258447434 10348 14063445141705 t 17333 17653 2783917990' .1. 2559 4G256344 6510 9167972811312 1485517104 17721 18800 18791 1907919597 19540 =
2 3741 6894 79501.0539 12042 23233 23935 74752 2644926727 17025 18297 19413 1994S =
= 4 1354599 10201 1097511086 1129812713.1335415978 16395 275421815418451 1861220517 =
= 112,81999 5926 4059 555860856357 838610693 11450 154311 16223 1637017508.18654 7. 1993066 6446684939739536 10452 1285713675 15913 16717 1765419802 20115 21 a 3,1 23702,095 2585 5537 6196 475.77311 796613946 1938418576 20949 2242421587 =
. 9 955 2591 32453509 3706313476174 62767864 9033 23519 2557516446 10;4 913 37744083 5825 6288.72a 7333 985770/03 1405214240 031018228 2964420108 1= 1. 1793 2065 29441418 8143 8031 9055 977510678 1073211 31.2131:71.1792ii.04612.2.039 12 167 3262524 2325 26402668 60706597 7038 In09 9615, 11608 182.42.3.7012 38025.
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= 39' 1975 240712833 , 41 59552564716838.

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=
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t' 6111 907014930 95 = 177631479320816 ss ; 21831190717567 -9? 564014421 15175 til $7712035 240$1 100 S942 91A01X109 , _ '3,82 9849 11443 102 177E111345 Rie44 903, 7344 /U3934919 1134, '146131155,620959 105 7943 1049015207 ¨
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110. 113401730 17514 11/. 12644E414714 ul 16752 10B45 13050 114. 7043n1E7.53:
115.=3105413145MM
us_ 2.60119451i613 -117 14,112.1.672435792.
1/3 4201 F$47 1i1711- -1.191( 59.43,1907920721 In another example, when the length Nidp, of the LDPC codeword is 64800, the code rate is 10/15, and M is 360, the indexes of rows where 1 exists in the 0th column of the ith column group of the information word submatrix 210 are defined as shown in Table 7 below.
[Table 7]

Index of row where 1 is located in the 0th column of the ith column group 1 2341 2559.2643 2816 2865 5137 5331 7000 7523 8023 10439 10797 13208 15041 _ 3 349 573 910 2702 3654 6214 9246 9353 10638 11772 14447 14953 16620 _ 4 204 13902887 3835 6230 6533 7443 7876 9299 10291 10896 13960 18287 8 734 1001 1283 4959 10016 10176 10973 11578:12051 15550 15915 19022 19430 9 745 4057 5855 9885 10594 10989 13156 13219 .13351 13631 13685 14577 17713 13 1663 3247 5003 5760 7186 7360 10346 1421114717 147.92 15155 16128 17355 .21556 5009 5632 6531 9430 9886 10621 11765.13969 16178 16413 18110 18249 20616 20759 16 457 2686 3.318 4608 5620 5858 6480 7430 9602 12691 14664 18777 20152 _ 19 1042 1832 2545 2719 2947 3672 3700 6249 6398 6833 11114 14283 17694 20477 _ 22 1948991711 2408 27865391 7.108 8079 8716 11453 17303 19484 20989 21389 24 736 2424 4792.5600 6370 10061 16053 16775 18600 1254 8163 88769.1V 12141 14587 16545 1.7175 18191 33 14300 15765 16752 =

44 11150 15022. 20201 =48 1018 10231 17720 5781 11588 ,18888'

20 111 .. 4657 8714 21246 116 .. 8046 14636 17491 In another example, when the length Nidp, of the LDPC codeword is 64800, the code rate is 12/15, and M is 360, the indexes of rows where 1 exists in the 0th column of the lth column group of the information word submatrix 210 are defined as shown in Table 8 below.
[Table 8]

21 I Index of row where 1 is located in the 0th column of the ith column group 0 584 1472 1621.1867.3333 3563,3723 418551265889 7737 .8632 8940 9725.
-I 221.44.3 530 37793835 6939 7743 3280 8448 8491 9367 10042 1124212217 2 .46524837 49005029 6449 6637 5751 3684 9936 11681 12811 11886 12029.12909' 24123012 3647 4210 4473 7447.7.502 9490 10067 11092 11129 11256 12201 12383 4 2991. 2947 3348:3406.44174519 517666725493 8863 9201 11294 11372 12154 - 27/01 197 290 871-1727 3911. 5411 2676 8701 93501031.01079812439 6 1765 1897 2923.3584 3901 4048 6963 70547132 9165 20184 10824- 11278 12669 7 2183 3740 4808 52173860'6375 6787 8214 8466 9037 10353 10583 11118 12752.
8 73 1594. 2146 27153501 3572 3639 3725 6959.7287 840510120,10507 10691.
9 240 732 1215 .2183/788 2830 3499 3881 4197 4991.6423 7061 9758 10491 . 20 832.1568182834244319 4516 4E49 ons 9702 10203 1041711248 11518 12453 ii 2024 2470 3048 3638 38704132 3284 5772 5528.9426 9945 10873 1178711837' 2.2 1049.1.213 1651 2323 3493 4363 5750%6483 7623 8752 9732 4805 U7442.2.937 13 11.93.2060 2283 2964 3478. 4592 47956709 71628231. 8328 11140 11908'12243 =
2.4 971.2120 24393333 3350 4559 65675745.906 970210161 10542 10721 12639 2403 2918 3117.3247 am 5.593 s844 5931 7801 10132 /0225 11498 1216212941 16. 1781 22292276 2533 3532 3951 52.79 5774 7930 9324 10920 11035 12340 22440 17 289 384-1280 /230;3464 3273.3258 865589.42 9008 10179 11425.11745 /2533 18 _1553541.090 13302002.22363559 3705 4922 59556576 3564 9972 12763 19 303 876 2059 2142 5244 5330 6644 7576 8614 9598 /0410 1071811033. 12957 3449. 3617 4405 4602 47276182 3835'8928 9372 9644 10237 10747 11655 12747 21 .. 812.2585 28202677 8974 9632'11069'1/548 11839 12107 12411.12695 12812

22. 97241234943 6385 2449 7339 7477 8379 9177 9359 20074 11709 '1255212331 , 842.9791541 2262,2905 5276 6'75 87099 7894 8128 8325 8563 8875 10050-' 24 -.474791 968 3902 4924.4965-5085 5908 5109 6329 7931 9038 9401 18563 13974461.4658 5911 6037 7127,7318-8678 8924 9000 94739662 10446 12692 26 1394-7371 /2831 .
27 13934447 7972:
.28 035'2.5710S97 29 .4843 51.01 11040 .. 3234 8015. 10513 31 1108 10374 10546' 33 3398:76748569 ' 34 7719 9475 10503.:
. 35 29979418-2581.
36, 5777 652911229' , 37 19665214 9899. . . . ,30. 24083'5327 .483 7229 7548; . . _ 41. 7865 849 9804 43 _5180 7096 9481 .

44 1431.5786 8924 745'67578625 48 1915'2903 4005 ". -= 2594 939612742 $1 .159 210212579 52 ssa 3281 '3762 sa 57_01 5798 8413 .
54 .3582 6052 12047 55 , 4133 5773 9657 56' .2286874 11183 sa 7735 8073 12734 60 '3909 7103 12804 65 2423 4203 .9111 66 244 1555 4691.
rl '1106 2178 5371 63 3431.151710126 ea 25097.5910503 71 1742 8045 9529' 72 7861.8879,11AS1, 73, 4023 6108.6811 8621 10184 11555 _ 75-'672610861: 12348 76 312x 6101 7388 77 1 1137 5358 , ,381 2424 8537 80 .1980.2219 4569 $2 *2803'331412808 33 85781642 11533 .
84 B2,9 4585 7928- , 86 . 10675709 6867 88 .1092518 6756 89 '2105 10526 11i53 90 51921,059610749 91 .6260 7641 8233 92 = 2996 3094 11214 =

23 95 2734 107,53 12780 õ
96; 102117958 10025 90 392 3398 1141.7 100 1067 79i.9 8934 107 1.238 3548 10464 115 1.051 6188 10038 128 2295 awl 561.0 120 , 1766.363S 127549 In 5177 95862/243 126 2070171: 85613 128 512 10667 v1zc:4 _230 2880 886511:466 ma. 3903 5485 9992 143_ 446711913 ;1304 _ In the above-described examples, the length of the LDPC codeword is 64800 and the code rate is 6/15, 8/15, 10/15, and 12/15. However, this is merely an example and the position of 1 in

24 the information word submatrix 210 may be defined variously when the length of the LDPC
codeword is 16200 or the code rate has different values.
According to an exemplary embodiment, even when the order of numbers in a sequence corresponding to the ith column group of the parity check matrix 200 as shown in the above-described Tables 4 to 8 is changed, the changed parity check matrix is a parity check matrix used for the same code. Therefore, a case in which the order of numbers in the sequence corresponding to the ith column group in Tables 4 to 8 is changed is covered by the inventive concept.
= According to an exemplary embodiment, even when the arrangement order of sequences corresponding to each column group is changed in Tables 4 to 8, cycle characteristics on a graph of a code and algebraic characteristics such as degree distribution are not changed. Therefore, a case in which the arrangement order of the sequences shown in Tables 4 to 8 is changed is also covered by the inventive concept.
In addition, even when a multiple of Chdp, is equally added to all sequences corresponding to a certain column group in Tables 4 to 8, the cycle characteristics on the graph of the code or the algebraic characteristics such as degree distribution are not changed.
Therefore, a result of equally adding a multiple of Qapc to the sequences shown in Tables 4 to 8 is also covered by the inventive concept. However, it should be noted that, when the resulting value obtained by adding the multiple of Qidpc to a given sequence is greater than or equal to (Nwpc-Kidpc), a value obtained by applying a modulo operation for (Nidpc-Kkipc) to the resulting value should be applied instead.
Once positions of the rows where 1 exists in the 0th column of the ith column group of the information word submatrix 210 are defined as shown in Tables 4 to 8, positions of rows where 1 exists in another column of each column group may be defined since the positions of the rows where 1 exists in the 0th column are cyclic-shifted by Qwpc in the next column.
For example, in the case of Table 4, in the Oth column of the 0th column group of the information word submatrix 210, 1 exists in the 1606th row, 3402nd row, 4961st row.....
In this case, since Qtapc=(Nidpc-Kkipc)/M464800-25920)/360.108, the indexes of the rows where 1 is located in the 1st column of the 0th column group may be 1714(=1606+108), 3510(.3402+108), 5069(=4961+108),..., and the indexes of the rows where 1 is located in the 2nd column of the Oth column group may be 1822(.1714+108), 3618(.3510+108), 5177(=-5069+108),....

25 In the above-described method, the indexes of the rows where 1 is located in all rows of each column group may be defined.
The parity submatrix 220 of the parity check matrix 200 shown in FIG. 2 may be defined as follows:
The parity submatrix 220 includes Nidpc-Kidp, number of columns (that is, Kmpcth column to (IsTipdc-1)th column), and has a dual diagonal or staircase configuration.
Accordingly, the degree of columns except the last column (that is, (Nki1)th column) from among the columns included in the parity submatrix 220 is 2, and the degree of the last column is 1.
As a result, the information word submatrix 210 of the parity check matrix 200 may be defined by Tables 4 to 8, and the parity submatrix 220 of the parity check matrix 200 may have a dual diagonal configuration.
When the columns and rows of the parity check matrix 200 shown in FIG. 2 are permutated based on Equation 4 and Equation 5, the parity check matrix shown in FIG. 2 may be changed to a parity check matrix 300 shown in FIG. 3.
Qmpc=i+ 1 = j+i (0 <M,05. j <Q/dpc) (4) K Idpc Qldpc =k+11Cfripc+M=l+k (01c<M,05.1<Q1dpc)=== (5) The method for permutating based on Equation 4 and Equation 5 will be explained below.
Since row permutation and column permutation apply the same principle, the row permutation will be explained by the way of an example.
In the case of the row permutation, regarding the VII row, i and j satisfying X = Qupc x i+ fare calculated and the Xth row is permutated by assigning the calculated i and j to Mx j+i. For example, regarding the 7" row, i and j satisfying 7 = 2 x i + j are 3 and 1, respectively. Therefore, the 7th row is permutated to the 13th row (10 xl+ 3 =13 ).
When the row permutation and the column permutation are performed in the above-described method, the parity check matrix of FIG. 2 may be converted into the parity check matrix of FIG.
3.
Referring to FIG. 3, the parity check matrix 300 is divided into a plurality of partial blocks, and a quasi-cyclic matrix of M x M corresponds to each partial block.
Accordingly, the parity check matrix 300 having the configuration of FIG. 3 is formed of matrix units of M x M. That is, the submatrices of M x M are arranged in the plurality of partial

26 blocks, constituting the parity check matrix 300.
Since the parity check matrix 300 is formed of the quasi-cyclic matrices of MxM, M
number of columns may be referred to as a column block and M number of rows may be referred to as a row block. Accordingly, the parity check matrix 300 having the configuration of FIG. 3 is formed of Nqc_column=Nidpc/M number of column blocks and Nqc_row=Np.ity/M
number of row blocks.
Hereinafter, the submatrix of M X M will be explained.
First, the (Nqc column4) th column block of the 0th row block has a form shown in Equation 6 presented below:
0 0 ... 0 0 1 0 ... 0 0 A = 0 1 ... 00 = = = = =
0 0 ... 1 0 - ... (6) As described above, A 330 is an MxM matrix, values of the 0th row and the (M-1)th column are all "0", and, regarding (;,' i<(M-2), the (i+1)th row of the ith column is "1" and the other values are "0".
Second, regarding 0<i<Nidpc-Kidpc)/M-1 in the parity submatrix 320, the ith row block of the (Kidpc./M+i)th column block is configured by a unit matrix /,,,,õm 340. In addition, regarding 0<1<(Nkipc-Kidpc)/M-2, the (i+1)th row block of the (Kmpc/M+i)th column block is configured by a unit matrix /m., 340.
Third, a block 350 constituting the information word submatrix 310 may have a cyclic-shifted format of a cyclic matrix P, Pa" , or an added format of the cyclic-shifted matrix Pa of the cyclic matrix P (or an overlapping format).
For example, a format in which the cyclic matrix P is cyclic-shifted to the right by 1 may be expressed by Equation 7 presented below:

0 0 1 ¨= 0 P=
000...1 - === (7)

27 The cyclic matrix P is a square matrix having an M xM size and is a matrix in which a weight of each of M number of rows is 1 and a weight of each of M number of columns is 1.
When aki is 0, the cyclic matrix P, that is, P indicates a unit matrix / mxm and when aij is co, 13 is a zero matrix.
A submatrix existing where the ith row block and the jth column block intersect in the parity check matrix 300 of FIG. 3 may be Pa" . Accordingly, i and j indicate the number of row blocks and the number of column blocks in the partial blocks corresponding to the information word.
Accordingly, in the parity check matrix 300, the total number of columns is Nidpc=M x Nqc Columm and the total number of rows is Nparity=M X Nqc_row= That is, the parity check matrix 300 is formed of Nqc_coiumn number of "column blocks" and Nqc_row number of "row blocks".
Hereinafter, a method for performing LDPC encoding based on the parity check matrix 200 as shown in FIG. 2 will be explained. An LDPC encoding process when the parity check matrix 200 is defined as shown in Table 4 by way of an example will be explained for the convenience of explanation.
First, when information word bits having a length of Kkipc are [io, j1 2, = =
Kktp,_11, and parity bits having a length of Islidpc-Kkipc are [po, pi, P2). = = P A t 1], the LDPC encoding is performed by the following process.
Step 1) Parity bits are initialized as '0'. That is, po= pi= p2=====
Step 2) The Oth information word bit io is accumulated in a parity bit having the address of the parity bit defined in the first row (that is, the row of i=0) of table 4 as the index of the parity bit.
This may be expressed by Equation 8 presented below:

28 P15= P1606010 P24533= P24533 Oi 0 P3402 = P3402 ()JO P2537677 P25376 ei 0 P4961 = P4961 i 0 P25667= P256670 i 0 P6751 = P6751 0 i 0 P26836= P= 26836 0 i P7132 = P71320 i 0 P31799= P31799 0 i 0 P11516= P11516 Oi 0 P34173.= P34173 0 i P12300= P12300 0 o P35462= P35462 01 0 P12482 = P12482 0 i 0 P36153 7-- P= 361530 i P12592= P12592 ei 0 P36740 77 P= 36740 C) i 0 P13342= P13342 0 i 0 P37085= P370850 i 0 P13764 77 P13764 810 P37152= P37152 01 0 P14123= P14123010 P3746877 P37468 ei 0 P21576= P21576 ei 0 P37658 77 P37658 I0 P23946 77 P23946 e I0 ...(8) Herein, io is a 0th information word bit, p, is an ith parity bit, and ED is a binary operation.
According to the binary operation, le 1 equals 0, 1 ED 0 equals 1, 0 ED 1 equals 1, 08 0 equals 0.
Step 3) The other 359 information word bits in, (m=1, 2, ..., 359) are accumulated in the parity bit. The other information word bits may belong to the same column group as that of io. In this case, the address of the parity bit may be determined based on Equation 9 presented below:
(x + (m mod 360) x Qupc)M041S1 mpc ¨ K . . . (9) Herein, x is an address of a parity bit accumulator corresponding to the information word bit and Qmpn is a size by which each column is cyclic-shifted in the information word submatrix, and may be 108 in the case of table 4. In addition, since m=1, 2, ..., 359, (m mod 360) in Equation 9 may be regarded as m.
As a result, information word bits in, (m=1,2,..., 359) are accumulated in the parity bits having the address of the parity bit calculated based on Equation 9 as the index. For example, an operation as shown in Equation 10 presented below may be performed for the information word bit

29 P1714 = P17140 i 1 P24641 7-- P24641 0 i 1 P3510 = P35100 i 1 P25484= P25484 01 1 P5069 -7: P50690 i 1 P25775= P25775 1 P6859 = P6859ei 1 P26944= P26944 0 i 1 P7240 = P72400 i 1 P31907= P31907 C)il P11624= P11624 0i 1 P34281= P34281 0 i 1 P12408= P12408 0 i 1 P35570= P35570 0 i 1 P12590= P12590 0i 1 P36261= P36261 0 i 1 P12700= P12700 0 i 1 P36848= P36848 0 i 1 P13450= P13450 0 i 1 P37193= P37193 Oil P13872= P13872 0 i 1 P37260= P37260 0 i 1 P14231= P14231 011 P37576= P37576 0 i 1 P216847-- P21684 Ii P37766= P37766 0 i 1 P24054= P24054 0 i 1 ...(10) Herein, i1 is a 1st information word bit, pi is an ith parity bit, and ED is a binary operation.
According to the binary operation, 1ED 1 equals 0, le 0 equals 1, 0 1 equals 1, 0 ED 0 equals 0.
Step 4) The 360th information word bits i360 is accumulated in a parity bit having the address of the parity bit defined in the 2nd row (that is, the row of i=1) of table 4 as the index of the parity bit.
Step 5) The other 359 information word bits belonging to the same group as that of the information word bit i360 are accumulated in the parity bit. In this case, the address of the parity bit may be determined based on Equation 9. However, in this case, x is the address of the parity bit accumulator corresponding to the information word bit 1360.
Step 6) Steps 4 and 5 described above are repeated for all of the column groups of table 4.
Step 7) As a result, a parity bit pi is calculated based on Equation 11 presented below. In this case, i is initialized as 1.
pi= pi ED pi= 1,2,..., N K tdpc ¨1 . . . (11) In Equation 11, pi is an ith parity bit, IsTidpc is a length of an LDPC
codeword, Kid is a length of an information word of the LDPC codeword, and ED is a binary operation.
As a result, the encoder 110 may calculate the parity bits according to the above-described

30 method.
In another example, a parity check matrix according to an exemplary embodiment may have a configuration as shown in FIG. 4.
Referring to FIG. 4, the parity check matrix 400 may be formed of 5 matrices A, B, C, Z, and D. Hereinafter, the configuration of each matrix will be explained to explain the configuration of the parity check matrix 400.
First, 1µ41, M2, Qi, and Q2, which are parameter values related to the parity check matrix 400 as shown in FIG. 4, may be defined as shown in table 9 presented below according to the length and the code rate of the LDPC codeword.
[Table 9]
Sizes Rate Length Mi 16200 1080 11.880 3 33 41,4 16200, 720 10080 2 28 The matrix A is formed of K number of columns and g number of rows, and the matrix C is formed of K+g number of columns and N-K-g number of rows. Herein, K is a length of information word bits, and N is a length of the LDPC codeword.
Indexes of rows where 1 is located in the 0th column of the ith column group in the matrix A
and the matrix C may be defined based on table 10 according to the length and the code rate of the LDPC codeword. In this case, an interval at which a pattern of a column is repeated in each of the matrix A and the matrix C, that is, the number of columns belonging to the same group, may be 360.
For example, when the length N of the LDPC codeword is 64800 and the code rate is 6/15, the indexes of rows where 1 is located in the 0th column of the ith column group in the matrix A
and the matrix C are defined as shown in table 10 presented below:
[Table 10]

31 I Index of row where 1 is located in the 0th column of the ith column group :0 71276856 6867.1/964 17373 18159 26426 2846628477 2 233765 904 1366 38751.314515409 18620 2391030825.
'3 106224 405 127751386514787 16781 23886 24099 31419 .4 23496.891 2512 12589 14074 19392.20339.2765528684:
. 5 473 71/ 75912854374 389111255/13814 24242 32728 -;6' = 511567.81511823 17105-17400 19338 n31s, 24396 26448 = 7 = 45.733 836 1923.372717458 25745 33805-3599535557 = 9 727517731937.1732428512 3066630934 31016 31849 = .257343594'1404119141 2491426564 28809 3265534753 ii . 99 241 491 26509670 17.433 1778518988-22235 30742.
- 12 , 198299 655 6737851)410917 16092 19387 2075537690 13 351 916 926.181512170823216.30321 33578 34052 37949 14 54332 373,2010 3332 562316301 34337.36451 37861 139.25710651109020289 2959429732.32540.35133 36464' r 18 46282 2871625816383. 20258 27186 2749428429 38266 19 445486-1658 1.565997511294 26364 23695 3682635330 .. 20 .134 900 931'12518 1454417715.19623 2111133558 34570 = 23 332 675 .1033 183812004 15439 20765 31721 3422518863 = 24 527555332 35676318 831710883 13466 2427 25377 2.5 43178010211112 287 767513059 1779520570 2077:1 * 339 536 101.5 57256916 1084614487 21156 28123 32614 =.., 25 2.22535 989- 3593022 5362140118 2344.5 25127 29022.
. 37 39378530257758 11367 22276 22761'2823/36394 = _ 30 .234 257 1045 1367 2908 6337.26530 28142 3411935997:
.31 . 3546978991299781256717843 24194 34887 35206 = 32 3995-9967 502710647 1465718859 28075 2821436325:-33. 275477823 113751807328997:30521 31561 3194132116 .34 185_560, 966 -11733 12013-12760 13358 19372.32534 35504 35 7668911046 11150 20355 21638.29930 3101433050.34846 36; = 3.60389.1.057 5316 5938 14186 164043244534021 35722 I 37 = 306344 679.522466741.0305 13753 255833658536943'5 ,38 103 171 3.01587501174112144 1947026955 22495 27377 . 39 815832 8943883.1427914497 22595 281292871031246-40 . 2154117605886 25612 28556 3221332764 35961 36130' , 41 229489 106723858587 20565 234312810230147 32859 . 43 -89552 847 665698E9 23949 262262708031236 35823 144 .66142 443 33303613 7977 14944-1546(1918525983 = 46 346 423-806 5659 7668 8789 9928 19724 24039 27393 ; 47 '48460 10553512 7389 754029215 22180 .2822135437 18m5&-8241678450813588 19683 21750.3031113480..
15768 935' 2856.8137. 905121850 29941.3321734293 _ 50 349624 7161698,63956435897410649-15 932:17378

32 = 51 = 336..410 871' 3582.9830 1088513891 M2719203 36659' 51: 176. 8411Q7g 1/3019V9 2796428164 18720 32357 35495 5.3.. 23489010759431.9605 ppo 19113 11331 12679 24268.
54 . 516 638.731 6631 19871'22740 879139152 32639 35568' 55 253 S0'879 2086 16885 22952 237652538914656 37193 56' 954.99820033369 6870 732129856.31373 34888 57: :79 350933 4853 625111932 12058 21631 24552 24876 58 246647: .. 7784036 10391.10656 13194 3233532360 34179;
59 149 33 9 436 6971835&871511577, 22376 28684 31249 = ' 611 = 36 149 220 6936 18408 19192 19268 2306328411 35312' 61: 273 6831042 6327.10011 18041 z1.7p4 067 30791'31425 62' 46 138 722 2701 30164. 1300119939 26625 26458=28965;
63. . 121009 1040 1990 2930 5191 21215:.2262523011-29288 64. , 241'819 2245 3199 841521133 267E6 2722638838.
65' ,45 476 1075 -7391 15141'20414 31244 33336 35004 38391 66 .432578 667:1343 10466 11314 180723314 2772034465' 67. .248 291 556.1971 3989 699118000 19998 2393234652 68 :68 694 837 2246'7472787111078 12668 20937=3551 70: = 21 314 979 23112632410919527 21920 31411:34277 71 197 233804:1249438 1902114358 2p559270.99.30.525;
72 = 9802 16164 17499 22378 2240522704 26142 29906-73. . 9064 19904 12395 14057:1515.6.26000 32613 4.16.
= 74. 5178 6319102391934325628 30577 3.1110. 32291 In the above-described example, the length of the LDPC codeword is 64800 and the code rate 6/15. However, this is merely an example and the indexes of rows where 1 is located in the 0th column of the ith column group in the matrix A and the matrix C may be defined variously when the length of the LDPC codeword is 16200 or the code rate has different values.
Hereinafter, positions of rows where 1 exists in the matrix A and the matrix C
will be explained with reference to table 10 by way of an example.
Since the length N of the LDPC codeword is 64800 and the code rate is 6/15 in table 10, M1=1080, M2=37800,01=3, and Q2=105 in the parity check matrix 400 defined by table 10 with reference to table 9.
Herein, Q1 is a size by which columns of the same column group are cyclic-shifted in the matrix A, and 02 is a size by which columns of the same column group are cyclic-shifted in the matrix C.
In addition, 01=M1/L, 02=M2X, Mi=g, and M2=N-K-g, and L is an interval at which a pattern of a column is repeated in the matrix A and the matrix C, and for example, may be 360.
The index of the row where 1 is located in the matrix A and the matrix C may be determined based on the Mi value.
For example, since M1=1080 in the case of table 10, the positions of the rows where 1 exists

33 in the 0th column of the ith column group in the matrix A may be determined based on values smaller than 1080 from among the index values of table 10, and the positions of the rows where 1 exists in the 0th column of the ith column group in the matrix C may be determined based on values greater than or equal to 1080 from among the index values of table 10.
Specifically, in table 10, the sequence corresponding to the Oth column group is "71, 276, 856, 6867, 12964, 17373, 18159, 26420, 28460, 28477". Accordingly, in the case of the 0th column of the 0th column group of the matrix A, 1 may be located in the 71st row, 276th row, and 856th row, and, in the case of the 0th column of the 0th column group of the matrix C, 1 may be located in the 6867th row, 12964th row, 17373rd row, 18159th row, 26420th row, 28460th row, and 28477th row.
Once positions of 1 in the 0th column of each column group of the matrix A are defined, positions of rows where 1 exists in another column of each column group may be defined by cyclic-shifting from the previous column by Qi. Once positions of 1 in the 0th column of each column group of the matrix C are defined, position of rows where 1 exists in another column of each column group may be defined by cyclic-shifting from the previous column by Q2.
In the above-described example, in the case of the 0th column of the 0th column group of the matrix A, 1 exists in the 71st row, 276th row, and 856th row. In this case, since Q1=3, the indexes of rows where 1 exists in the 1st column of the Oth column group are 74(=71+3), 279(=276+3), and 859(=856+3), and the index of rows where 1 exists in the 2'd column of the 0th column group are 77(=74+3), 282 (=279+3), and 862(=859+3).
In the case of the Oth column of the 0th column group of the matrix C, 1 exists in the 6867th row, 12964th row, 17373"I row, 18159th row, 26420th row, 28460th row, and 28477th row. In this case, since Q2=105, the index of rows where 1 exists in the 1st column of the Oth column group are 6972(=6867+105), 13069(=12964+105), 17478(=17373+105), 18264(=18159+105), 26525(=26420+105), 28565(=28460+105), 28582(.28477+105), and the indexes of rows where 1 exists in the 2nd column of the 0th column group are 7077(=6972+105), 13174(=13069+105), 17583(.17478+105), 18369(=18264+105), 26630(=26525+105), 28670(=28565+105), 28687(=28582+105).
In this method, the positions of rows where 1 exists in all column groups of the matrix A and the matrix C are defined.
The matrix B may have a dual diagonal configuration, the matrix D may have a diagonal

34 configuration (that is, the matrix D is an identity matrix), and the matrix Z
may be a zero matrix.
As a result, the parity check matrix 400 shown in FIG. 4 may be defined by the matrices A, B, C, D, and Z having the above-described configurations.
Hereinafter, a method for performing LDPC encoding based on the parity check matrix 400 shown in FIG. 4 will be explained. An LDPC encoding process when the parity check matrix 400 is defined as shown in Table 10 by way of an example will be explained for the convenience of explanation.
For example, when an information word block S=(so, sl, Sic.i) is LDPC-encoded, an LDPC codeword A (.03..õ
= (so, ,..., po,pi,...,Pmi+m,_1) including a parity bit P = (po,p1,...,P,,1,m2_1) may be generated.
M1 and M2 indicate the size of the matrix B having the dual diagonal configuration and the size of the matrix C having the diagonal configuration, respectively, and Mi=g, M2=N-K-g.
A process of calculating a parity bit is as follows. In the following explanation, the parity check matrix 400 is defined as shown in table 10 by way of an example, for the convenience of explanation.
Step 1) k and p are initialized as ki=s; (i=0,1,..., K-1), pi=0 M1+M2-1).
Step 2) The 0th information word bit A0 is accumulated in the address of the parity bit defined in the first row (that is, the row of i=0) of table 10. This may be expressed by Equation 12 presented below:
P71=P71 X.0 P17373= P17373 0 X0 P276= P2760 X0 P18159= P18159 0 X 0 P856= P856 X(Y P28420 = P264200 0 P6867 = P 6067e X.0 P28460= P28460 e X 0 P12964= P12964 ?.0 P28477= P284770 X 0 ...(12) Step 3) Regarding the next L-1 number of information word bits Ain (m=1, 2, ..., L-1), kõ, is accumulated in the parity bit address calculated based on Equation 13 presented below:
+mx Qi)modMi (if <MO
M1 +{(x ¨MI +m x Q2)modM2} (if Afi )...(13) Herein, x is an address of a parity bit accumulator corresponding to the 0th information word bit Ao.

35 In addition, Q1=M1/L and Q2=M2/L. In addition, since the length N of the LDPC
codeword is 64800 and the code rate is 6/15 in table 10, M1=1080, M2=37800, Q1=3, Q2=105, and L=360 with reference to table 9.
Accordingly, an operation as shown in Equation 14 presented below may be performed for the 1st information word bit P74 = P74 A- 1 P17478 = P17478 0 A- 1 P279= P2790 A-1 P18264= P182640A-1 P859= P8590 A- 1 P26525= P265250 A-1 P6972 = P69720 X 1 P28565= P28565 0 A-1 P13069= P130690 A- 1 p28582= P28582 e ... (14) Step 4) Since the same address of the parity bit as in the second row (that is the row of i=1) of table 10 is given to the Lth information word bit XL, in a similar method to the above-described method, the address of the parity bit regarding the next L-1 number of information word bits X.
(m=L+1, L+2, 2L-1) is calculated based on Equation 13. In this case, x is the address of the parity bit accumulator corresponding to the information word bit XL, and may be obtained based on the second row of table 10.
Step 5) The above-described processes are repeated for L number of new information word bits of each group by considering new rows of table 10 as the address of the parity bit accumulator.
Step 6) After the above-described processes are repeated for the codeword bits X0 to 4-1, values regarding Equation 15 presented below are calculated in sequence from i=1:
Step 7) Parity bits AK to 2õ+õ1_1 corresponding to the matrix B having the dual diagonal configuration are calculated based on Equation 16 presented below:
2K+Lxt+s = PQ,xS+t (0 s <L;0 t <Q1) ...(16) Step 8) The address of the parity bit accumulator regarding L number of new codeword bits A.K to 2K+mi_1 of each group is calculated based on table 10 and Equation 13.
Step 9) After the codeword bits kic to A.K+mi_i are calculated, parity bits AK,..mi to 2lc+m1+m2-1 corresponding to the matrix C having the diagonal configuration are calculated based on

36 Equation 17 presented below:
27C+Mi+Lxt+s P Mil-Q2xS+1 (0 s <L,0 5_ t <Q2) ..(17) As a result, the parity bits may be calculated in the above-described method.
Referring back to FIG. 1, the encoder 110 may perform the LDPC encoding by using various code rates such as 3/15, 4/15, 5/15, 6/15, 7/15, 8/15, 9/15, 10/15, 11/15, 12/15, 13/15, etc. In addition, the encoder 110 may generate an LDPC codeword having various lengths such as 16200, 64800, etc., based on the length of the information word bits and the code rate.
In this case, the encoder 110 may perform the LDPC encoding by using the parity check matrix, and the parity check matrix is configured as shown in FIGS. 2 to 4.
In addition, the encoder 110 may perform Bose, Chaudhuri, Hocquenghem (BCH) encoding as well as LDPC encoding. To achieve this, the encoder 110 may further include a BCH encoder (not shown) to perform BCH encoding.
In this case, the encoder 110 may perform encoding in an order of BCH encoding and LDPC
encoding. Specifically, the encoder 110 may add BCH parity bits to input bits by performing BCH encoding and LDPC-encodes the information word bits including the input bits and the BCH parity bits, thereby generating the LDPC codeword.
The interleaver 120 interleaves the LDPC codeword. That is, the interleaver 120 receives the LDPC codeword from the encoder 110, and interleaves the LDPC codeword based on various interleaving rules.
In particular, the interleaver 120 may interleave the LDPC codeword such that a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC
codeword (that is, a plurality of groups or a plurality of blocks) is mapped onto a predetermined bit of a modulation symbol. Accordingly, the modulator 130 may map a bit included in a predetermined group from among the plurality of groups of the LDPC codeword onto a predetermined bit of the modulation symbol.
To achieve this, as shown in FIG. 5, the interleaver 120 may include a parity interleaver 121, a group interleaver (or a group-wise interleaver 122), a group twist interleaver 123 and a block interleaver 124.
The parity interleaver 121 interleaves the parity bits constituting the LDPC
codeword.
Specifically, when the LDPC codeword is generated based on the parity check matrix 200 having the configuration of FIG. 2, the parity interleaver 121 may interleave only the parity bits

37 of the LDPC codeword by using Equations 18 presented below:
ci for 0<i<Kidpc, and = cickoc.c2i.õ,, for 05_s<M, OS<Qmpc ... (18), where M is an interval at which a pattern of a column group is repeated in the information word submatrix 210, that is, the number of columns included in a column group (for example, M=360), and Oldpe is a size by which each column is cyclic-shifted in the information word submatrix 210. That is, the parity interleaver 121 performs parity interleaving with respect to the LDPC codeword c=(co, Csidx_i), and outputs Uquo, 111, .. UNi4,4).
The LDPC codeword parity-interleaved in the above-described method may be configured such that a predetermined number of continuous bits of the LDPC codeword have similar decoding characteristics (cycle distribution, a degree of a column, etc.).
For example, the LDPC codeword may have the same characteristics on the basis of M
number of continuous bits. Herein, M is an interval at which a pattern of a column group is repeated in the information word submatrix 210 and, for example, may be 360.
Specifically, a product of the LDPC codeword bits and the parity check matrix should be "0".
This means that a sum of products of the ith LDPC codeword bit, c(1=0, 1, ..., N1dpc-1) and the ith column of the parity check matrix should be a "0" vector. Accordingly, the ith LDPC codeword bit may be regarded as corresponding to the ith column of the parity check matrix.
In the case of the parity check matrix 200 of FIG. 2, M number of columns in the information word submatrix 210 belong to the same group and the information word submatrix 210 has the same characteristics on the basis of a column group (for example, the columns belonging to the same column group have the same degree distribution and the same cycle characteristic).
In this case, since M number of continuous bits in the information word bits correspond to the same column group of the information word submatrix 210, the information word bits may be formed of M number of continuous bits having the same codeword characteristics. When the parity bits of the LDPC codeword are interleaved by the parity interleaver 121, the parity bits of the LDPC codeword may be formed of M number of continuous bits having the same codeword characteristics.
However, regarding the LDPC codeword encoded based on the parity check matrix 300 of FIG. 3 and the parity check matrix 400 of FIG. 4, parity interleaving may not be performed. In this case, the parity interleaver 121 may be omitted.
The group interleaver 122 may divide the parity-interleaved LDPC codeword into a plurality

38 of bit groups and rearrange the order of the plurality of bit groups in bit group wise (or bit group unit). That is, the group interleaver 122 may interleave the plurality of bit groups in bit group wise.
To achieve this, the group interleaver 122 divides the parity-interleaved LDPC
codeword into a plurality of bit groups by using Equation 19 or Equation 20 presented below.
X J . ={, 1 j=[-1 c i3Ok<Nkilfor05j<Ngroup 360 pc ... (19) xi = luk 1360 x j k < 360 x (j +1),0 k < Nfripcifor0 5. j <Ngp... (20) where Ngroup _ is the total number of bit groups, X; is the jth bit group, and uk is the kth LDPC codeword bit input to the group interleaver 122. In addition, ¨k is the largest integer below k/360.
[

Since 360 in these equations indicates an example of the interval M at which the pattern of a column group is repeated in the information word submatrix, 360 in these equations can be changed to M.
The LDPC codeword which is divided into the plurality of bit groups may be as shown in FIG.
6.
Referring to FIG. 6, the LDPC codeword is divided into the plurality of bit groups and each bit group is formed of M number of continuous bits. When M is 360, each of the plurality of bit groups may be formed of 360 bits. Accordingly, the bit groups may be formed of bits corresponding to the column groups of the parity check matrix.
Specifically, since the LDPC codeword is divided by M number of continuous bits, Kkipc number of information word bits are divided into (Kidpc/M) number of bit groups and Islicipc-Kidpc number of parity bits are divided into (Nwpc-Kidpc)/M number of bit groups.
Accordingly, the LDPC codeword may be divided into (1=11dpe/M) number of bit groups in total.
For example, when M=360 and the length NIcipc of the LDPC codeword is 16200, the number of groups Ngroups constituting the LDPC codeword is 45(.16200/360), and, when M=360 and the length Nidpc of the LDPC codeword is 64800, the number of bit groups Ngroup constituting the LDPC codeword is 180(=64800/360).
As described above, the group interleaver 122 divides the LDPC codeword such that M
number of continuous bits are included in a same group since the LDPC codeword has the same codeword characteristics on the basis of M number of continuous bits.
Accordingly, when the

39 LDPC codeword is grouped by M number of continuous bits, the bits having the same codeword characteristics belong to the same group.
In the above-described example, the number of bits constituting each bit group is M. However, this is merely an example and the number of bits constituting each bit group is variable.
For example, the number of bits constituting each bit group may be an aliquot part of M. That is, the number of bits constituting each bit group may be an aliquot part of the number of columns constituting a column group of the information word submatrix of the parity check matrix. In this case, each bit group may be formed of aliquot part of M number of bits. For example, when the number of columns constituting a column group of the information word submatrix is 360, that is, M=360, the group interleaver 122 may divide the LDPC codeword into a plurality of bit groups such that the number of bits constituting each bit group is one of the aliquot parts of 360.
In the following explanation, the number of bits constituting a bit group is M
by way of an example, for the convenience of explanation.
Thereafter, the group interleaver 122 interleaves the LDPC codeword in bit group wise.
Specifically, the group interleaver 122 may group the LDPC codeword into the plurality of bit groups and rearrange the plurality of bit groups in bit group wise. That is, the group interleaver 122 changes positions of the plurality of bit groups constituting the LDPC
codeword and rearranges the order of the plurality of bit groups constituting the LDPC
codeword in bit group wise.
Herein, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise such that bit groups including bits mapped onto the same modulation symbol from among the plurality of bit groups are spaced apart from one another at predetermined intervals.
In this case, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by considering at least one of the number of rows and columns of the block interleaver 124, the number of bit groups of the LDPC codeword, and the number of bits included in each bit group, such that bit groups including bits mapped onto the same modulation symbol are spaced apart from one another at predetermined intervals.
To achieve this, the group interleaver 122 may rearrange the order of the plurality of groups in bit group wise by using Equation 21 presented below:
Yi = X,01)(0 j < N ) gTOup (21),

40 where N is the Jth bit group before group interleaving, and Yi is the jth bit group after group interleaving. In addition, 7t(j) is a parameter indicating an interleaving order and is determined by at least one of a length of an LDPC codeword, a modulation method, and a code rate. That is, n(j) denotes a permutation order for group wise interleaving.
Accordingly, X7,0) is a 7r(j)th bit group before group interleaving, and Equation 21 means that the pre-interleaving n(j)th bit group is interleaved into the Jt h bit group.
According to an exemplary embodiment, an example of 7t(j) may be defined as in Tables 11 to 22 presented below.
In this case, 'm(j) is defined according to a length of an LPDC codeword and a code rate, and a parity check matrix is also defined according to a length of an LDPC codeword and a code rate.
Accordingly, when LDPC encoding is performed based on a specific parity check matrix according to a length of an LDPC codeword and a code rate, the LDPC codeword may be interleaved in bit group wise based on n(j) satisfying the corresponding length of the LDPC
codeword and code rate.
For example, when the encoder 110 performs LDPC encoding at a code rate of 6/15 to generate an LDPC codeword of a length of 64800, the group interleaver 122 may perform interleaving by using 7t(j) which is defined according to the length of the LDPC codeword of 16200 and the code rate of 6/15 in tables 11 to 22 presented below.
For example, when the length of the LDPC codeword is 64800, the code rate is 6/15, and the modulation method(or modulation format) is 16-Quadrature Amplitude Modulation (QAM), 7t(j) may be defined as in table 11 presented below. In particular, table 11 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 4.
[Table 11]
Order of bit groups to be block interleaved rr(j) (0 j <180) j-th block of 1 2 3 4 5 6 7 8 9 group- 23 2 2 2 2 2 2 3 3 3 3 3 3 3 3 .. 3 .. 3 .. 4 .. 4 .. 4 .. 4 .. 4 .. 4 wise interleaver 46 7 8 9 0 1 2 3 4 5 6 7 8 9 0 I 2 3 4 5 6 7 8 output 69

41 716)-1h 3 5 14 4 6 4 1 4 2 3 2 3 2 block of 4 3 group- 8 8 3 2 9 1 0 6 1 wise 12 1 9 1 1 3 1 1 7 1 1 1 1 1 interleaver 1 1 1 1 8 1 7 1 1 7 1 1 8 input 71 42 78 54 5 07 5 2 51 7 17 09 0 06 34 8 In the case of Table 11, Equation 21 may be expressed as Yo=Xn(0)=X55) Y1=-X7c0)=X146, Y2=X7c(2)=X835 = = = Y178=X2(178)=X132, and Y179=Xx(179)=X135. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 55th bit group to the 0th bit group, the 146th bit group to the 1st bit group, the 83rd bit group to the 2nd bit group, ..., the 132nd bit group to the 178th bit group, and the 135th bit group to the 179th bit group.
In another example, when the length of the LDPC codeword is 64800, the code rate is 8/15, and the modulation method is 16-QAM, rc(j) may be defined as in table 12 presented below. In particular, table 12 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 5.
[Table 12]
j-th Order of bit groups to be block interleaved block of it(j) (0 Sj < 180) group- 1 2 3 4 5 6 7 8 9 1 1 1 1 wise interleaver 4 5 6 7 8 9 0 1 2 3 4 5 6 4 4 4 5 5 5 output 46 5 5 5 5 5 5 5

42 16 - 1 1 1 t 1 I 1 1 1 1 1 1 1 1 1 7t6)-th 92 1 6 6 2 2 2 2 6 5 7 5 4 block of group- 4 1 7 0 2 0 0 1 8 9 7 4 5 wise 1 1 3 1 1 1 1 1 1 1 1 1 interleaver input o 42 6 4 61 70 34 56 2 54 74 45 46 4 24 6 02 33 76 32 35 1 1 1= 1 1 In the case of Table 12, Equation 21 may be expressed as Y0=X70)=X58, Yi=X110)=X55, Y2=X*2)=Xiii, ===, Yrs=Xx(178)=X171, and Yr9=X7079)=X155. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 58th bit group to the 0th bit group, the 55th bit group to the 1st bit group, the 111th bit group to the 2"
bit group, ..., the 171st bit group to the 178th bit group, and the 155th bit group to the 179th bit group.
In another example, when the length of the LDPC codeword is 64800, the code rate is 10/15, and the modulation method is 16-QAM, ir(j) may be defined as in table 13 presented below. In particular, table 13 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 6.
[Table 13]
j-th Order of bit groups to be block interleaved block of it(j) (0 j < 180) Ip 1 1 1 1 1 1 1 1 group- 1 2 3 4 5 6 7 8 9

43 wise 2 2 2 2 2 2 3 3 3 3 3 3 3 interleaver -output 7 8 9 0 1 2 3 4 5 6 7 8 9 0 3 4 5 6 7 8 9 00 01 02 03 04 05 06 07 08 (19 10 11 12 13 14 1 1 1 1' 1 1 1 1 1 -2 3' 8 C 8 7 f 8' 5 1 4 4 4 3 4- 9 1 9 8 1 4 9 1 3 9 1 5 1 71(1)-1h 10 8 3 7 3 8 7 6 5 - 7' 1 4 1 block of group- 05 19 9 2 0 01 14 2 7 5 17 3 5 7 6 8 12 8 06 wise 16 7 1 5 2 6 1 7 1 6 2 2 1 9 interleaver input 7 1 61 62 23 38 73 77 00 2 7 37 32 69 58 16 1- 1 1 1 1 - I 1 I' 1 1 1 1 1 In the case of Table 13, Equation 21 may be expressed as Y0=Xx(0)=X74, Y1=X7c0)=X53, Y2=Xic(2)=X84, = = =5 Y178=XX(178)=X1595 and Yi79=X,1(l79)=X163. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 74th bit group to the 0th bit group, the 531 bit group to the 1st bit group, the 84th bit group to the 2116 bit group, ..., the 159th bit group to the 1781h bit group, and the 163rd bit group to the 179th bit group.
In another example, when the length of the LDPC codeword is 64800, the code rate is 10/15, and the modulation method is 16-QAM, n(j) may be defined as in table 14 presented below. In particular, table 14 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 7.
[Table 14]
j-th Order of bit groups to be block interleaved block of it(j) (0 j <180)

44 group- 1 2 3 4 5 6 7 8 9 1 1 1 1 wise interleaver 4 5 6 7 8 9 0 1 2 3 4 5 6 4 4 4 output 46 5 5 5 5 5 5 5 5 5 3 4 5 6 7 8 9 00 01 02 03 04 05 06 07 08 09 10 n 12 13 14 74D-1h 7 1 5 8 1 1 7 7 6 4 9 3 9 block of group- 4 4 4 11 5 0 4 5 0 0 7 01 wise 3 50 1 5 1 1 1 8 1 1 1 1 1 1 interleaver input 58 I

In the case of Table 14, Equation 21 may be expressed as Yo.--Y ..õ,(0)=X68, Y1=Xn(1)=X71, 112=Xn-(2)=X541 = = = 5 Y178=X1(l78)=-X135, and Y179=X7,079)=X24. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 68th bit group to the Oth bit group, the 71st bit group to the 1st bit group, the 54th bit group to the 2nd bit group, ..., the 1351h bit group to the 178th bit group, and the 24th bit group to the 179th bit group.
In another example, when the length of the LDPC codeword is 64800, the code rate is 12/15, and the modulation method is 16-QAM, Ir(j) may be defined as in table 15 presented below. In particular, table 15 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 8.
[Table 15]

45 Order of bit groups to be block interleaved n(j) (0 j < 180) j-th block of 4 4 4 5 5 5 5 5 5 5 5 5 5

46 group- 7 8 9 0 1 2 3 4 5 6 7 8 9 0 wise 69 interleaver 9 9 9 9 9 9 9 1 1 1 1 1 1 output it(j)-th 9 67 2 8 block of group- 85 04 24 2 0 18 4 wise 17 1 1 1 1 1 1 1 1 1 1 1 1 1 interleaver 16 1 1 1 1 1 1 7 1 1 1 1 1 1 1 .. 1 .. 1 .. 1 .. 1 .. 1 .. 4 .. 2 .. 1 input 3 52 46 77 03 60 47 6 72 44 50 32 76 68 67 62 70 38 51 61 0 6 30 In the case of Table 15, Equation 21 may be expressed as Y0=X70)=X12o, Yi=Xxo)=X32, Y2=Xx(2)=X38, = = =, Yi78=X1078)=Xiot, and Yi79=X2079)=X39. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 120th bit group to the 0th bit group, the 32nd bit group to the bit group, the 38th bit group to the 2nd bit group, ..., the 101st bit group to the 1781h bit group, and the 391h bit group to the 179th bit group.
In another example, when the length of the LDPC codeword is 64800, the code rate is 6/15, and the modulation method is 16-QAM, n(j) may be defined as in table 16 presented below. In particular, table 16 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 10.
[Table 16]
Order of bit groups to be block interleaved rc(j) (0 j < 180) j-th 23 block of group- 7 8 9 0 I 2 3 4 5 6 7 8 9 0 wise 69 interleaver 9 9 9 9 9 9 9 1 1 1 1 1 1 __ 1 1 1 1 1 1 1 I 1 output 11 1 1 1 I 1 1 1- 1 1 1 1 f 1 I-1 1. 1 1 I 7 1 1 9 n(j)-th 6 1 1 4 1 1 6 6 8 3 1 6 8 block of group- 33 7 9 6 8 55 1 6 6 9 8 2 54 3 1 wise 14 3 2 2 1 3 6 1 1 3 5 9 1 1 interleaver = 46 4 7 input 66 7 61 74 9 3 1 39 8 2 9 49 15 01 27 2 58 1 1 1 9 =

In the case of Table 16, Equation 21 may be expressed as Y0=X70)=X163, Yi=XN0)=Xi6o, Y2=X742)=X138, = = = Y178=X*178)=X148, and Yi79=X,079)=X98. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 163rd bit group to the 0th bit group, the 160th bit group to the 1st bit group, the 1381h bit group to the 2' bit group, ..., the 148th bit group to the 178th bit group, and the 981h bit group to the 179th bit group.
In another example, when the length of the LDPC codeword is 64800, the code rate is 6/15,

47 and the modulation method is 64-QAM, n(j) may be defined as in table 17 presented below. In particular, table 17 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 4.
[Table 17]
Order of bit groups to be block interleaved n(j) (0 j <180) -th j 23 block of group- 7 8 9 0 1 2 3 4 5 6 7 8 9 0 wise 69 interleaver 9 9 9 9 9 9 9 1 1 1 1 1 1 output _ 39 40 41 =42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 n(j)-th 16 1 5 6 5 6 5 1 7 5 1 6 3 block of _______________________________________________________________________ group- 3 8 8 229 37 0 3 66 5 7 42 74 5 49 8 45 2 69 0 33 63 19 wise 82 1 1 1 1 1 1 9 1 1 8 1 1 1 interleaver - -input o 18 27 4 9 08 26 31 3 11 1 25 62 57 58 09 40 23 54 50 0 1 In the case of Table 17, Equation 21 may be expressed as Y0=Xx(0)=X2.9, Yi=Xxo)=Xt7, Y2=X742)=X38, = = =, Y178=X/078)=X117) and Y179=Xx(179)=X155. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 291h bit group to the 0th bit group, the 17th bit group to the 1St bit group, the 38th bit group to the 2" bit =
group, ..., the 117th bit group to the 178t11 oft group, and the 155th bit group to the 179th bit group.

48 In another example, when the length of the LDPC codeword is 64800, the code rate is 8/15, and the modulation method is 64-QAM, Ir(j) may be defined as in table 18 presented below. In particular, table 18 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 5.
[Table 18]
Order of bit groups to be block interleaved IT(j) (0 j < 180) j-th 23 block of group-wise 69 interleaver 9 9 9 9 9 9 9 1 1 1 1 1 1 output 3 4 5 6 7 8 9 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 11 1 1 1 1 1 1' 1 1 1 - 1 1 1 1 1- 1 1 1 1 1 1 i-s 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 n(j)-th 9 6 5 8 7 1 8 7 6 8 7 1 1 block of 111123211 1121111 1' 3 1 3 ' 1 2 group- 21 08 39 42 4 4 0 57 59 38 43 9 40 63 50 75 14 1 2 5 45 8 wise 27 2 1 9 1 1 1 1 2 2 1 1 4 interleaver input 34 I 4 79 29 69 01 9 09 27 68 76 I 22 10 13 46 32 65 4 24 77 7 30 18 37 11 26 20 05 15 t In the case of Table 18, Equation 21 may be expressed as Yo x =...70)=X86, Yi=X7,0)=-X71, Y2=Xx(2)=X5i, ===, Y178=Xx(178)=-X174, and Y179=X7.(179)=X128. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 86th bit group to the 0th bit group, the 71st bit group to the 1st bit group, the 51st bit group to the rd bit

49 = =
group, ..., the 174th bit group to the 178th bit group, and the 128th bit group to the 179th DA group.
In another example, when the length of the LDPC codeword is 64800, the code rate is 10/15, and the modulation method is 64-QAM, 71(j) may be defined as in table 19 presented below. In particular, table 19 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 6.
[Table 19]
Order of bit groups to be block interleaved n(j) (0 j <180) j-th 23 block of - 4 4 4 5 5 5 5 5 5 5 5 5 group- 7 8 9 0 1 2 3 4 5 6 7 8 9 0 wise 69 interleaver 9 9 9 9 9 9 9 1 1 1 1 1 1 output _ 4 1 4 4 9 f 4 1 -ir(j)-th 8 5 6 7 1 8 1 6- 1 1 6 4 - 1 block of group- 7 7 8 1 5 3 17 7 10 2 4 2 18 7 8 wise 15 2 1 4 5 1 1 1 3 1 2 1 2 1 interleaver - -input 54 1 69 1 71 62 39 75 29 5 67 In the case of Table 19, Equation 21 may be expressed as Y0=X70)=X73, Yi=Xx0)=X36, Y2=Xx(2)=X21, = = = 9 11178=X14178)=X1497 and Yr9=X7079)=X135. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 73'd

50 bit group to the Oth bit group, the 361h bit group to the 181 bit group, the 21st bit group to the 2' bit group, ..., the 1491h bit group to the 178th bit group, and the 135th bit group to the 179th bit group.
In another example, when the length of the LDPC codeword is 64800, the code rate is 10/15, and the modulation method is 64-QAM, it(j) may be defined as in table 20 presented below. In particular, table 20 may be applied when LDPC encoding is performed 'based on the parity check matrix defined by table 7.
[Table 20]
Order of bit groups to be block interleaved rc(j) (0 5_ j <180) j-th 23 block of 4 4 4 5 5 5 5 5 5 5 5 5 5 group- 7 8 9 0 1 2 3 4 5 6 7 8 9 0 wise 69 interleaver 9 9 9 9 9 9 9 1 1 1 1 1 1 output 3 4 5 6 7 8 9 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 __ 1 __ 1 __ 1 __ 1 __ 1 __ 1 __ 1 __ 1 7L6)-1h 1 6 1 1 3 1 5 1 3 9 7 9 1 8 block of group- 29 7 7 4 9 3 00 4 1 73 69 3 49 04 0 1 02 10 24 0 9 8 wise 19 0 8 2 3 2 5 6 3 6 4 2 2 1 interleaver input 6 5 1 0 1 68 21 53 40 52 35 1 1 79 32 36 2 75 63 65 41 38 22 27 25 44 70 34 30 76 , In the case of Table 20, Equation 21 may be expressed as Y0=X0)=X113, YI=Xn0)=X115, Y2=X7r(2)=X47, ===, Y178=X74178)=X130, and Yr9=X21079)=X176. Accordingly, the group interleaver

51 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 113th bit group to the Oth bit group, the 115th bit group to the 1st bit group, the 47th bit group to the 2nd bit group, ..., the 130th bit group to the 178th bit group, and the 176th bit group to the 179th bit group.
In another example, when the length of the LDPC codeword is 64800, the code rate is 12/15, and the modulation method is 64-QAM, Ic(j) may be defined as in table 21 presented below. In particular, table 21 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 8.
[Table 21]
Order of bit groups to be block interleaved rt(j) (0 j <180) j-th 23 block of 4 4 4 5 5 5 5 5 5 5 5 5 5 group- 7 8 9 0 1 2 3 4 5 6 / 8 9 0 wise 69 interleaver 9 9 9 9 9 9 9 1 1 1 1 1 1 output =
it 1 1 1 1 1 1 1 1 1 1 1 1 1 74D-th 10 7 2 6 7 2 1 8 9 1 1 1 2 4 block of group-wise 29 interleaver input 6 23 14 0 07 78 45 73 6 44 30 76 71 75 25 9 62 59 0 64 15 69 72 5 61 51 19 22 52 57 37 =48 53 70 54 66 3 50 6 14 1 1 1 1 1 1" 1 6-- 2 1 1 1

52 In the case of Table 21, Equation 21 may be expressed as Yo.X70)=X83, Yi=Xmo)=X93, Y2=Xx(2)=X94, = = Y178=XR(178)=X2, and Yr9=X7079)=X14. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 831d bit group to the 0th bit group, the 93rd bit group to the 1' bit group, the 941h bit group to the 2nd bit group, ..., the 2nd bit group to the 178th bit group, and the 14th bit group to the 179th bit group.
In another example, when the length of the LDPC codeword is 64800, the code rate is 6/15, and the modulation method is 64-QAM, 7r(j) may be defined as in table 22 presented below. In particular, table 22 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 10.
[Table 22]
Order of bit groups to be block interleaved n(j) (0 j < 180) j-th 23 block of - 4 4 4 5 5 5 5 5 5 5 5 5 as group- 7 8 9 0 1 2 3 4 5 6 7 8 9 0 _ -wise 69 interleaver 9 9 9 9 9 9 9 1 1 1 1 1 1 output _ 1 1' 1 1- 1 I 1 1 f 1- 1 1 1 1 n(j)-th - 1 1 8 1 5 1 2 4 6 1 5 2 1 5 1 2 1 block of 64 55 1 02 3 1 1 7 1 26 7 6 group- 8 5 3 wise 7 1 7 1 4 3 3 2 1 4 6 4 1 interleaver 1 07 7 11 2 5 8 3 00 5 9 0 29 3 63 9 12 45 4 05 17 10 9 7 1 1 I 6 3 f 2 7 9 7 - 1 8 5-in 2 put 8 1 3 7 ,

53 lo 12 I 3' I 32 I 34 I 4 I 46 I 4 I 20 I 58 I 3' I " I 69 56 I 31 68 I 1 I 2 17-77 In the case of Table 22, Equation 21 may be expressed as Yo=X10)=-X175, Y1=X710)=X177, Y2=Xx(2)=X173, = = =, Yi78=X*178)=X31, and Yr9=X7r(179)=X72. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 175th bit group to the 0thbit group, the 177th bit group to the 1st bit group, the 173111 bit group to the 2nd bit group, ..., the 31st bit group to the 178th bit group, and the 72nd bit group to the 179th bit group.
In the above-described examples, the length of the LDPC codeword is 64800 and the code rate is 6/15, 8/15, 10/15, and 12/15. However, this is merely an example and the interleaving pattern may be defined variously when the length of the LDPC codeword is 16200 or the code rate has different values.
As described above, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by using Equation 21 and Tables 11 to 22.
"j-th block of Group-wise Interleaver output" in tables 11 to 22 indicates the j-th bit group output from the group interleaver 122 after interleaving, and "71(j-th block of Group-wise Interleaver input" indicates the n(j)-th bit group input to the group interleaver 122.
In addition, since the order of the bit groups constituting the LDPC codeword is rearranged by the group interleaver 122 in bit group wise, and then the bit groups are block-interleaved by the block interleaver 124, which will be described below, "Order of bit groups to be block interleaved" is set forth in Tables 11 to 22 in relation to n(j).
The LDPC codeword which is group-interleaved in the above-described method is illustrated in FIG. 7. Comparing the LDPC codeword of FIG. 7 and the LDPC codeword of FIG.
6 before group interleaving, it can be seen that the order of the plurality of bit groups constituting the LDPC codeword is rearranged.
That is, as shown in FIGs. 6 and 7, the groups of the LDPC codeword are arranged in order of bit group Xo, bit group X1, ..., bit group XNgroup_i before being group-interleaved, and are arranged in an order of bit group Yo, bit group Y1, ..., bit group Y
- Ngroup-1 after being group-interleaved. In this case, the order of arranging the bit groups by the group interleaving may be determined based on Tables 11 to 22.
The group twist interleaver 123 interleaves bits in a same group. That is, the group twist interleaver 123 may rearrange the order of the bits in the same bit group by changing the order of

54 the bits in the same bit group.
In this case, the group twist interleaver 123 may rearrange the order of the bits in the same bit group by cyclic-shifting a predetermined number of bits from among the bits in the same bit group.
For example, as shown in FIG. 8, the group twist interleaver 123 may cyclic-shift bits included in the bit group Y1 to the right by 1 bit. In this case, the bits located in the 0th position, the 1st position, the rd position, ..., the 358th position, and the 359th position in the bit group Y1 as shown in FIG. 8 are cyclic-shifted to the right by 1 bit. As a result, the bit located in the 359th position before being cyclic-shifted is located in the front of the bit group Y1 and the bits located in the Oth position, the 15' position, the 2nd position, ..., the 358th position before being cyclic-shifted are shifted to the right serially by 1 bit and located.
In addition, the group twist interleaver 123 may rearrange the order of bits in each bit group by cyclic-shifting a different number of bits in each bit group.
For example, the group twist interleaver 123 may cyclic-shift the bits included in the bit group Y1 to the right by 1 bit, and may cyclic-shift the bits included in the bit group Y2 to the right by 3 bits.
However, the above-described group twist interleaver 123 may be omitted according to circumstances.
In addition, the group twist interleaver 123 is placed after the group interleaver 122 in the above-described example. However, this is merely an example. That is, the group twist interleaver 123 changes only the order of bits in a certain bit group and does not change the order of the bit groups. Therefore, the group twist interleaver 123 may be placed before the group interleaver 122.
The block interleaver 124 interleaves the plurality of bit groups the order of which has been rearranged. Specifically, the block interleaver 124 may interleave the plurality of bit groups the order of which has been rearranged by the group interleaver 122 in bit group wise (or bits group unit). The block interleaver 124 is formed of a plurality of columns each including a plurality of rows and may interleave by dividing the plurality of rearranged bit groups based on a modulation order determined according to a modulation method.
In this case, the block interleaver 124 may interleave the plurality of bit groups the order of which has been rearranged by the group interleaver 122 in bit group wise.
Specifically, the block

55 interleaver 124 may interleave by dividing the plurality of rearranged bit groups according to a modulation order by using a first part and a second part.
Specifically, the block interleaver 124 interleaves by dividing each of the plurality of columns into a first part and a second part, writing the plurality of bit groups in the plurality of columns of the first part serially in bit group wise, dividing the bits of the other bit groups into groups (or sub bit groups) each including a predetermined number of bits based on the number of columns, and writing the sub bit groups in the plurality of columns of the second part serially.
Herein, the number of bit groups which are interleaved in bit group wise may be determined by at least one of the number of rows and columns constituting the block interleaver 124, the number of bit groups and the number of bits included in each bit group. In other words, the block interleaver 124 may determine the bit groups which are to be interleaved in bit group wise considering at least one of the number of rows and columns constituting the block interleaver 124, the number of bit groups and the number of bits included in each bit group, interleave the corresponding bit groups in bit group wise, and divide bits of the other bit groups into sub bit groups and interleave the sub bit groups. For example, the block interleaver 124 may interleave at least part of the plurality of bit groups in bit group wise using the first part, and divide bits of the other bit groups into sub bit groups and interleave the sub bit groups using the second part.
Meanwhile, interleaving bit groups in bit group wise means that the bits included in the same bit group are written in the same column. In other words, the block interleaver 124, in case of bit groups which are interleaved in bit group wise, may not divide the bits included in the same bit groups and write the bits in the same column, and in case of bit groups which are not interleaved in bit group wise, may divide the bits in the bit groups and write the bits in different columns.
Accordingly, the number of rows constituting the first part is a multiple of the number of bits included in one bit group (for example, 360), and the number of rows constituting the second part may be less than the number of bits included in one bit group.
In addition, in all bit groups interleaved by the first part, the bits included in the same bit group are written and interleaved in the same column of the first part, and in at least one group interleaved by the second part, the bits are divided and written in at least two columns of the second part.
The specific interleaving method will be described later.
Meanwhile, the group twist interleaver 123 changes only the order of bits in the bit group and

56 does not change the order of bit groups by interleaving. Accordingly, the order of the bit groups to be block-interleaved by the block interleaver 124, that is, the order of the bit groups to be input to the block interleaver 124, may be determined by the group interleaver 122. Specifically, the order of the bit groups to be block-interleaved by the block interleaver 124 may be determined by Ic(j) defined in Tables 11 to 22.
As described above, the block interleaver 124 may interleave the plurality of bit groups the order of which has been rearranged in bit group wise by using the plurality of columns each including the plurality of rows.
In this case, the block interleaver 124 may interleave the LDPC codeword by dividing the plurality of columns into at least two parts. For example, the block interleaver 124 may divide each of the plurality of columns into the first part and the second part and interleave the plurality of bit groups constituting the LDPC codeword.
In this case, the block interleaver 124 may divide each of the plurality of columns into N
number of parts (N is an integer greater than or equal to 2) according to whether the number of bit groups constituting the LDPC codeword is an integer multiple of the number of columns constituting the block interleaver 124, and may perform interleaving.
When the number of bit groups constituting the LDPC codeword is an integer multiple of the number of columns constituting the block interleaver 124, the block interleaver 124 may interleave the plurality of bit groups constituting the LDPC codeword in bit group wise without dividing each of the plurality of columns into parts.
Specifically, the block interleaver 124 may interleave by writing the plurality of bit groups of the LDPC codeword on each of the columns in bit group wise in a column direction, and reading each row of the plurality of columns in which the plurality of bit groups are written in bit group wise in a row direction.
In this case, the block interleaver 124 may interleave by writing bits included in a predetermined number of bit groups, which corresponds to a quotient obtained by dividing the number of bit groups of the LDPC codeword by the number of columns of the block interleaver 124, on each of the plurality of columns serially in a column direction, and reading each row of the plurality of columns in which the bits are written in a row direction.
Hereinafter, the group located in the jth position after being interleaved by the group interleaver 122 will be referred to as group Yi.

57 For example, it is assumed that the block interleaver 124 is formed of C
number of columns each including R1 number of rows. In addition, it is assumed that the LDPC
codeword is formed of Ngroup number of bit groups and the number of bit groups Ngroup is a multiple of C.
In this case, when the quotient obtained by dividing Ngroup number of bit groups constituting the LDPC codeword by C number of columns constituting the block interleaver 124 is A
(=Ngroup/C) (A is an integer greater than 0), the block interleaver 124 may interleave by writing A
(=Ngroup/C) number of bit groups on each column serially in a column direction and reading bits written on each column in a row direction.
For example, as shown in FIG. 9, the block interleaver 124 writes bits included in bit group Yo, bit group Y1,..., bit group YA-1 in the 1st column from the 1st row to the Rith row, writes bits included in bit group YA, bit group YA+1, = bit group Y2A-1 in the 2nd column from the 1st row to the RI!' row, ..., and writes bits included in bit group YcA-A, bit group YCA-A+1, bit group YcA4 in the column C from the 1st row to the Rith row. The block interleaver 124 may read the bits written in each row of the plurality of columns in a row direction.
Accordingly, the block interleaver 124 interleaves all bit groups constituting the LDPC
codeword in bit group wise.
However, when the number of bit groups of the LDPC codeword is not an integer multiple of the number of columns of the block interleaver 124, the block interleaver 124 may divide each column into 2 parts and interleave a part of the plurality of bit groups of the LDPC codeword in bit group wise, and divide bits of the other bit groups into sub bit groups and interleave the sub bit groups. In this case, the bits included in the other bit groups, that is, the bits included in the number of groups which correspond to the remainder when the number of bit groups constituting the LDPC codeword is divided by the number of columns are not interleaved in bit group wise, but interleaved by being divided according to the number of columns.
Specifically, the block interleaver 124 may interleave the LDPC codeword by dividing each of the plurality of columns into two parts.
In this case, the block interleaver 124 may divide the plurality of columns into the first part and the second part based on at least one of the number of columns of the block interleaver 124, the number of bit groups of the LDPC codeword, and the number of bits of bit groups.
Here, each of the plurality of bit groups may be formed of 360 bits. In addition, the number of bit groups of the LDPC codeword is determined based on the length of the LDPC
codeword and

58 the number of bits included in the bit group. For example, when an LDPC
codeword in the length of 16200 is divided such that each bit group has 360 bits, the LDPC
codeword is divided into 45 bit groups. Alternatively, when an LDPC codeword in the length of 64800 is divided such that each bit group has 360 bits, the LDPC codeword may be divided into 180 bit groups.
Further, the number of columns constituting the block interleaver 124 may be determined according to a modulation method. This will be explained in detail below.
Accordingly, the number of rows constituting each of the first part and the second part may be determined based on the number of columns constituting the block interleaver 124, the number of bit groups constituting the LDPC codeword, and the number of bits constituting each of the plurality of bit groups.
Specifically, in each of the plurality of columns, the first part may be formed of as many rows as the number of bits included in at least one bit group which can be written in each column in bit group wise from among the plurality of bit groups of the LDPC codeword, according to the number of columns constituting the block interleaver 124, the number of bit groups constituting the LDPC codeword, and the number of bits constituting each bit group.
In each of the plurality of columns, the second part may be formed of rows excluding as many rows as the number of bits included in at least some bit groups which can be written in each of the plurality of columns in bit group wise. Specifically, the number rows of the second part may be the same value as a quotient when the number of bits included in all bit groups excluding bit groups corresponding to the first part is divided by the number of columns constituting the block interleaver 124. In other words, the number of rows of the second part may be the same value as a quotient when the number of bits included in the remaining bit groups which are not written in the first part from among bit groups constituting the LDPC codeword is divided by the number of columns.
That is, the block interleaver 124 may divide each of the plurality of columns into the first part including as many rows as the number of bits included in bit groups which can be written in each column in bit group wise, and the second part including the other rows.
Accordingly, the first part may be formed of as many rows as the number of bits included in bit groups, that is, as many rows as an integer multiple of M. However, since the number of codeword bits constituting each bit group may be an aliquot part of M as described above, the first part may be formed of as many rows as an integer multiple of the number of bits

59 constituting each bit group.
In this case, the block interleaver 124 may interleave by writing and reading the LDPC
codeword in the first part and the second part in the same method.
Specifically, the block interleaver 124 may interleave by writing the LDPC
codeword in the plurality of columns constituting each of the first part and the second part in a column direction, and reading the plurality of columns constituting the first part and the second part in which the LDPC codeword is written in a row direction.
That is, the block interleaver 124 may interleave by writing the bits included in at least some bit groups which can be written in each of the plurality of columns in bit group wise in each of the plurality of columns of the first part serially, dividing the bits included in the other bit groups except the at least some bit groups and writing in each of the plurality of columns of the second part in a column direction, and reading the bits written in each of the plurality of columns constituting each of the first part and the second part in a row direction.
In this case, the block interleaver 124 may interleave by dividing the other bit groups except the at least some bit groups from among the plurality of bit groups based on the number of columns constituting the block interleaver 124.
Specifically, the block interleaver 124 may interleave by dividing the bits included in the other bit groups by the number of a plurality of columns, writing each of the divided bits in each of a plurality of columns constituting the second part in a column direction, and reading the plurality of columns constituting the second part, where the divided bits are written, in a row direction.
That is, the block interleaver 124 may divide the bits included in the other bit groups except the bit groups written in the first part from among the plurality of bit groups of the LDPC
codeword, that is, the bits in the number of bit groups which correspond to the remainder when the number of bit groups constituting the LDPC codeword is divided by the number of columns, by the number of columns, and may write the divided bits in each column of the second part serially in a column direction.
For example, it is assumed that the block interleaver 124 is formed of C
number of columns each including R1 number of rows. In addition, it is assumed that the LDPC
codeword is formed Of Ngroup number of bit groups, the number of bit groups Ngroup is not a multiple of C, and AxC +1= Nsroup (A is an integer greater than 0). In other words, it is assumed that when the

60 number of bit groups constituting the LDPC codeword is divided by the number of columns, the quotient is A and the remainder is 1.
In this case, as shown in FIGs 10 and 11, the block interleaver 124 may divide each column into a first part including R1 number of rows and a second part including R2 number of rows. In this case, R1 may correspond to the number of bits included in bit groups which can be written in each column in bit group wise, and R2 may be R1 subtracted from the number of rows of each column.
That is, in the above-described example, the number of bit groups which can be written in each column in bit group wise is A, and the first part of each column may be formed of as many rows as the number of bits included in A number of bit groups, that is, may be formed of as many rows as Ax M number.
In this case, the block interleaver 124 writes the bits included in the bit groups which can be written in each column in bit group wise, that is, A number of bit groups, in the first part of each column in the column direction.
That is, as shown in FIGs. 10 and 11, the block interleaver 124 writes the bits included in each of bit group Yo, bit group Yi, ..., group YA.1 in the l to Rith rows of the first part of the 1"
column, writes bits included in each of bit group YA, bit group YA4-1, = .., bit group Y2A4 in the 1st to Rid' rows of the first part of the 2nd column, ..., writes bits included in each of bit group YcA-A, bit group YCA-A+1, = = bit group YC,A4 in the 1" to Rig' rows of the first part of the column C.
As described above, the block interleaver 124 writes the bits included in the bit groups which can be written in each column in bit group wise in the first part of each column.
In other words, in the above exemplary embodiment, the bits included in each of bit group (Y0), bit group (Y1),..., bit group (YA.1) may not be divided and all of the bits may be written in the first column, the bits included in each of bit group (YA), bit group (YA+i),..., bit group (Y2A-1) may not be divided and all of the bits may be written in the second column,õ, and the bits included in each of bit group (YcA_A), bit group (YcA-A-F1),--- group (YcA.1) may not be divided and all of the bits may be written in the C column. As such, all bit groups interleaved by the first part are written in the same column of the first part.
Thereafter, the block interleaver 124 divides bits included in the other bit groups except the bit groups written in the first part of each column from among the plurality of bit groups, and writes the bits in the second part of each column in the column direction. In this case, the block

61 interleaver 124 divides the bits included in the other bit groups except the bit groups written in the first part of each column by the number of columns, so that the same number of bits are written in the second part of each column, and writes the divided bits in the second part of each column in the column direction.
In the above-described example, since Ax C +1=N grow, , when the bit groups constituting the LDPC codeword are written in the first part serially, the last bit group YNgroup_i of the LDPC
codeword is not written in the first part and remains. Accordingly, the block interleaver 124 divides the bits included in the bit group YNgroup-1 into C number of sub bit groups as shown in FIG. 10, and writes the divided bits (that is, the bits corresponding to the quotient when the bits included in the last group (YNgroup-i) are divided by C) in the second part of each column serially.
The bits divided based on the number of columns may be referred to as sub bit groups. In this case, each of the sub bit groups may be written in each column of the second part. That is, the bits included in the bit groups may be divided and may form the sub bit groups.
That is, the block interleaver 124 writes the bits in the 1st to R2til rows of the second part of the 1st column, writes the bits in the 1st to R2th rows of the second part of the 2"I column, ..., and writes the bits in the 1st to RP rows of the second part of the column C. In this case, the block interleaver 124 may write the bits in the second part of each column in the column direction as shown in FIG. 10.
That is, in the second part, the bits constituting the bit group may not be written in the same column and may be written in the plurality of columns. In other words, in the above example, the last bit group (YNgr0up-1) is formed of M number of bits and thus, the bits included in the last bit group (YNgroup-1) may be divided by M/C and written in each column. That is, the bits included in the last bit group (YNgroup-i) are divided by M/C, forming M/C number of sub bit groups, and each of the sub bit groups may be written in each column of the second part.
Accordingly, in at least one bit group which is interleaved by the second part, the bits included in the at least one bit group are divided and written in at least two columns constituting the second part.
In the above-described example, the block interleaver 124 writes the bits in the second part in the column direction. However, this is merely an example. That is, the block interleaver 124 may write the bits in the plurality of columns of the second part in the row direction. In this case, the block interleaver 124 may write the bits in the first part in the same method as described above.

62 Specifically, referring to FIG. 11, the block interleaver 124 writes the bits from the 1st row of the second part in the 1st column to the 1st row of the second part in the column C, writes the bits from the 211d row of the second part in the 1st column to the 2nd row of the second part in the column C, ..., etc., and writes the bits from the RP row of the second part in the 1st column to the RP row of the second part in the column C.
On the other hand, the block interleaver 124 reads the bits written in each row of each part serially in the row direction. That is, as shown in FIGs. 10 and 11, the block interleaver 124 reads the bits written in each row of the first part of the plurality of columns serially in the row direction, and reads the bits written in each row of the second part of the plurality of columns serially in the row direction.
Accordingly, the block interleaver 124 may interleave a part of the plurality of bit groups constituting the LDPC codeword in bit group wise, and divide and interleave some of the remaining bit groups. That is, the block interleaver 124 may interleave by writing the LDPC
codeword constituting a predetermined number of bit groups from among the plurality of bit groups in the plurality of columns of the first part in bit group wise, dividing the bits of the other bit groups and writing the bits in each of the columns of the second part, and reading the plurality of columns of the first and second parts in the row direction.
As described above, the block interleaver 124 may interleave the plurality of bit groups in the methods described above with reference to FIGs. 9 to 11.
In particular, in the case of FIG. 10, the bits included in the bit group which does not belong to the first part are written in the second part in the column direction and read in the row direction. In view of this, the order of the bits included in the bit group which does not belong to the first part is rearranged. Since the bits included in the bit group which does not belong to the first part are interleaved as described above, bit rrror rate (BER)/frame error rate (PER) performance can be improved in comparison with a case in which such bits are not interleaved.
However, the bit group which does not belong to the first part may not be interleaved as shown in FIG. 11. That is, since the block interleaver 124 writes and reads the bits included in the group which does not belong to the first part in and from the second part in the row direction, the order of the bits included in the group which does not belong to the first part is not changed and the bits are output to the modulator 130 serially. In this case, the bits included in the group which does not belong to the first part may be output serially and mapped onto a modulation

63 symbol.
In FIGs. 10 and 11, the last single bit group of the plurality of bit groups is written in the second part. However, this is merely an example. The number of bit groups written in the second part may vary according to the total number of bit groups of the LDPC
codeword, the number of columns and rows, the number of transmission antennas, etc.
The block interleaver 124 may have a configuration as shown in tables 23 and 24 presented below:
[Table 23]
Niciac= 64800 ()Pp. K 16 QAM 64 QAM 256'(*N11 1024 QAM 44)96 04M-Fit 32400 16200 10800 7920 6480 5400 _ .
[Table 24]
Rippe= 16200 (WV(' 16 QAM ; 64 QAM 256 QAM 1024 QAM 4096 QAM
C 2 4 i 6 8 10 12 R2 180. 90 180 225 180 270 Herein, C NO is the number of columns of the block interleaver 124, R1 is the number of rows constituting the first part in each column, and R2 is the number of rows constituting the second part in each column.
Referring to Tables 23 and 24, the number of columns has the same value as a modulation order according to a modulation method, and each of a plurality of columns is formed of rows corresponding to the number of bits constituting the LDPC codeword divided by the number of a plurality of columns.
For example, when the length Nkipc of the LDPC codeword is 64800 and the modulation method is 16-QAM, the block interleaver 124 is formed of 4 columns as the modulation order is 4 in the case of 16-QAM, and each column is formed of rows as many as R1+R2=16200(=64800/4). In another example, when the length Nidp, of the LDPC
codeword is 64800 and the modulation method is 64-QAM, the block interleaver 124 is formed of 6 columns as the modulation order is 6 in the case of 64-QAM, and each column is formed of rows as many as Ri+R2=10800(.64800/6).

64 Meanwhile, referring to Tables 23 and 24, when the number of bit groups constituting an LDPC codeword is an integer multiple of the number of columns, the block interleaver 124 interleaves without dividing each column. Therefore, R1 corresponds to the number of rows constituting each column, and R2 is 0. In addition, when the number of bit groups constituting an LDPC codeword is not an integer multiple of the number of columns, the block interleaver 124 interleaves the groups by dividing each column into the first part formed of R1 number of rows, and the second part formed of R2 number of rows.
When the number of columns of the block interleaver 124 is equal to the number of bits constituting a modulation symbol, bits included in a same bit group are mapped onto a single bit of each modulation symbol as shown in Tables 23 and 24.
For example, when N1tx=64800 and the modulation method is 16-QAM, the block interleaver 124 may be formed of four (4) columns each including 16200 rows. In this case, the bits included in each of the plurality of bit groups are written in the four (4) columns and the bits written in the same row in each column are output serially. In this case, since four (4) bits constitute a single modulation symbol in the modulation method of 16-QAM, bits included in the same bit group, that is, bits output from a single column, may be mapped onto a single bit of each modulation symbol. For example, bits included in a bit group written in the 1st column may be mapped onto the first bit of each modulation symbol.
In another example, when N1dpc=64800 and the modulation method is 64-QAM, the block interleaver 124 may be formed of six (6) columns each including 10800 rows. In this case, the bits included in each of the plurality of bit groups are written in the six (6) columns and the bits written in the same row in each column are output serially. In this case, since six (6) bits constitute a single modulation symbol in the modulation method of 64-QAM, bits included in the same bit group, that is, bits output from a single column, may be mapped onto a single bit of each modulation symbol. For example, bits included in a bit group written in the 1st column may be mapped onto the first bit of each modulation symbol.
Referring to Tables 23 and 24, the total number of rows of the block interleaver 124, that is, R1-FR2, is IsTkipc/C.
In addition, the number of rows of the first part, R1, is an integer multiple of the number of bits included in each group, M (e.g., M=360), and maybe expressed as LATgroup I C M, and the number of rows of the second part, R2, may be N1dp,JC-R1. Herein, [ATroup /C]
is the largest g

65 integer below Ngroup. -/C. Since R1 is an integer multiple of the number of bits included in each group, M, bits may be written in R1 in bit groups wise.
In addition, when the number of bit groups of the LDPC codeword is not a multiple of the number of columns, it can be seen from Tables 23 and 24 that the block interleaver 124 interleaves by dividing each column into two parts.
Specifically, the length of the LDPC codeword divided by the number of columns is the total number of rows included in the each column. In this case, when the number of bit groups of the LDPC codeword is a multiple of the number of columns, each column is not divided into two parts. However, when the number of bit groups of the LDPC codeword is not a multiple of the number of columns, each column is divided into two parts.
For example, it is assumed that the number of columns of the block interleaver 124 is identical to the number of bits constituting a modulation symbol, and an LDPC
codeword is formed of 64800 bits as shown in Table 28. In this case, each bit group of the LDPC codeword is formed of 360 bits, and the LDPC codeword is formed of 64800/360(.180) bit groups.
When the modulation method is 16-QAM, the block interleaver 124 may be formed of four (4) columns and each column may have 64800/4(.16200) rows.
In this case, since the number of bit groups of the LDPC codeword divided by the number of columns is 180/4(=45), bits can be written in each column in bit group wise without dividing each column into two parts. That is, bits included in 45 bit groups which is the quotient when the number of bit groups constituting the LDPC codeword is divided by the number of columns, that is, 45x360(=16200) bits can be written in each column.
However, when the modulation method is 256-QAM, the block interleaver 124 may be formed of eight (8) columns and each column may have 64800/8(.8100) rows.
In this case, since the number of bit groups of the LDPC codeword divided by the number of columns is 180/8=22.5, the number of bit groups constituting the LDPC codeword is not an integer multiple of the number of columns. Accordingly, the block interleaver 124 divides each of the eight (8) columns into two parts to perform interleaving in bit group wise.
In this case, since the bits should be written in the first part of each column in bit group wise, the number of bit groups which can be written in the first part of each column in bit group wise is 22, which is the quotient when the number of bit groups constituting the LDPC
codeword is divided by the number of columns, and accordingly, the first part of each column has

66 22x360(=7920) rows. Accordingly, 7920 bits included in 22 bit groups may be written in the first part of each column.
The second part of each column has rows which are the rows of the first part subtracted from the total rows of each column. Accordingly, the second part of each column includes 8100-7920(=180) rows.
In this case, the bits included in the other bit groups which have not been written in the first part are divided and written in the second part of each column.
Specifically, since 22x8(.176) bit groups are written in the first part, the number of bit groups to be written in the second part is 180-176 (=4) (for example, bit group Y1769 bit group Y177, bit group Y178, and bit group Y179 from among bit group Yo, bit group Y1, bit group Y2, = = =, bit group Y178, and bit group Y179 constituting the LDPC codeword).
Accordingly, the block interleaver 124 may write the four (4) bit groups which have not been written in the first part and remains from among the groups constituting the LDPC codeword in the second part of each column serially.
That is, the block interleaver 124 may write 180 bits of the 360 bits included in the bit group Y176 in the 1st row to the 180t1i row of the second part of the 1st column in the column direction, and may write the other 180 bits in the 1st row to the 180th row of the second part of the 2nd column in the column direction. In addition, the block interleaver 124 may write 180 bits of the 360 bits included in the bit group Y177 in the 1st row to the 180th row of the second part of the 31T1 column in the column direction, and may write the other 180 bits in the 1st row to the 180t1i row of the second part of the 4th column in the column direction. In addition, the block interleaver 124 may write 180 bits of the 360 bits included in the bit group Y178 in the 1st row to the 180th row of the second part of the 5th column in the column direction, and may write the other 180 bits in the 15t row to the 180th row of the second part of the 6'h column in the column direction. In addition, the block interleaver 124 may write 180 bits of the 360 bits included in the bit group Y179 in the 1st row to the 180th row of the second part of the 7th column in the column direction, and may write the other 180 bits in the 1st row to the 1801 row of the second part of the 8th column in the column direction.
Accordingly, the bits included in the bit group which has not been written in the first part and remains are not written in the same column in the second part and may be divided and written in the plurality of columns.

67 Hereinafter, the block interleaver 124 of FIG. 5 according to an exemplary embodiment will be explained in detail with reference to FIG. 12.
In a group-interleaved LDPC codeword (vo, v1, ..., Yi is continuously arranged like V={Yo, Yt, = = = 17Nr.p-1 The LDPC codeword after group interleaving may be interleaved by the block interleaver 124 as shown in FIG. 12. In this case, the block interleaver 124 divide a plurality of columns into the first part(Part 1) and the second part(Part 2) based on the number of columns of the block interleaver 124 and the number of bits of bit groups. In this case, in the first part, the bits constituting the bit groups may be written in the same column, and in the second part, the bits constituting the bit groups may be written in a plurality of columns(i.e. the bits constituting the bit groups may be written in at least two columns).
Specifically, input bits vi are written serially from the first part to the second part column wise, and then read out serially from the first part to the second part row wise. That is, the data bits vi are written serially into the block interleaver column-wise starting in the first aprt and continuing column-wise finishing in the second part, and then read out serially row-wise from the first part and then row-wise from the second part. Accordingly, the bit included in the same bit group in the first part may be mapped onto a single bit of each modulation symbol.
In this case, the number of columns and the number of rows of the first part and the second part of the block interleaver 124 vary according to a modulation format and a length of the LDPC codeword as in Table 25 presented below. That is, the first part and the second part block interleaving configurations for each modulation format and code length are specified in Table 25 presented below. Herein, the number of columns of the block interleaver 124 may be equal to the number of bits constituting a modulation symbol. In addition, a sum of the number of rows of the first part, I=Tri and the number of rows of the second part, Nr2, is equal to Nidpc/Nc (herein, Nc is Nov/Nei x 360 the number of columns). In addition, since Nri(= )is a multiple of 360, a multiple of bit groups may be written in the first part.
[Table 25]

68 Rows in Part 1 Ni Rows. in Part 2 Nr2 Modulation - Columns Nc Nidpc =64800= Nicipc =16200 Isildpe =64800 Nrdpc =16200 4096-QAM 5.400 1080 0 270 12 Hereinafter, an operation of the block interleaver 124 will be explained in detail.
Specifically, as shown in FIG. 12, the input bit vi (0 i <Nc x N ri) is written in ri row of q t column of the first part of the block interleaver 124. Herein, q [
and ri are ci --= -L-- and ri----(i Nri mod Nri), respectively.
In addition, the input bit vi (NcxNrii <Nkipc) is written in ri row of q column of the second part of the block interleaver 124. Herein, q and ri satisfy ci = [(i -Arc x Arri) I and Nr2 r, = Nri+{(i - Plc x N ri) mod N,2} , respectively.
An output bit qi(0j<I=T1dpc) is read from q column of ri row. Herein, ri and q satisfy i r . = [ -'!-- and ci=6 mod NO, respectively.
For example, when the length Islidp, of an LDPC codeword is 64800 and the modulation method is 256-QAM, the order of bits output from the block interleaver 124 may be 040,qi,q2,===,q63357,C163358)(163359)C1633600:163361)===5C164790=
(V00/7920,V15840,..=,V47519,V55439,V63359)V633603V63540)= = =,V64799). Herein, the indexes of the right side of the foregoing equation may be specifically expressed for the eight (8) columns as 0, 7920, 15840, 23760, 31680, 39600, 47520, 55440, 1, 7921, 15841, 23761, 31681, 39601, 47521, 55441, ... , 7919, 15839, 23759, 31679, 39599, 47519, 55439, 63359, 63360, 63540, 63720, 63900, 64080, 64260, 64440, 64620, ... , 63539, 63719, 63899, 64079, 64259, 64439, 64619, 64799.
Hereinafter, the interleaving operation of the block interleaver 124 will be explained in detail.
The block interleaver 124 may interleave by writing a plurality of bit groups in each column in bit group wise in a column direction, and reading each row of the plurality of columns in

69 which the plurality of bit groups are written in bit group wise in a row direction.
In this case, the number of columns constituting the block interleaver 124 may vary according to a modulation method, and the number of rows may be the length of the LDPC
codeword/the number of columns.
For example, when the modulation method is 16-QAM, the block interleaver 124 may be formed of 4 columns. In this case, when the length I\lidp, of the LDPC
codeword is 16200, the number of rows is 16200 (=64800/4). In another example, when the modulation method is 64-QAM, the block interleaver 124 may be formed of 6 columns. In this case, when the length 1=11dpc of the LDPC codeword is 64800, the number of rows is 10800 (.64800/6).
Hereinafter, the method for interleaving the plurality of bit groups in bit group wise by the block interleaver 124 will be explained in detail.
When the number of bit groups constituting the LDPC codeword is an integer multiple of the number of columns, the block interleaver 124 may interleave by writing the bit groups as many as the number of bit groups divided by the number of columns in each column serially in bit group wise.
For example, when the modulation method is 16-QAM and the length Nkipc of the LDPC
codeword is 64800, the block interleaver 124 may be formed of four (4) columns each including 16200 rows. In this case, since the LDPC codeword is divided into (64800/360=180) number of bit groups when the length Nidpc of the LDPC codeword is 64800, the number of bit groups (.180) of the LDPC codeword may be an integer multiple of the number of columns (.4) when the modulation method is 16-QAM. That is, no remainder is generated when the number of bit groups of the LDPC codeword is divided by the number of columns.
In this case, as shown in FIG. 13, the block interleaver 124 writes the bits included in each of the bit group 170, bit group Yli ...., bit group Y44 in the 1st row to 16200th row of the first column, writes the bits included in each of the bit group Y45, the bit group Y46,..., the bit group Y89 in the 1st row to 16200th row of the second column, writes the bits included in each of the bit group Y90, the bit group Y91,..., the bit group Y134 in the 1St row to 16200th row of the third column, and writes the bits included in each of the bit group Y135, the bit group Y136). =
the bit group Y179 in the 1st row to 16200th row of the fourth column. In addition, the block interleaver 124 may read the bits written in each row of the two columns serially in the row direction.
In another, when the modulation method is 64-QAM and the length IsTidpc of the LDPC

70 codeword is 64800, the block interleaver 124 may be formed of six (6) columns each including 10800 rows. In this case, since the LDPC codeword is divided into (64800/360=180) number of bit groups when the length Nidpc of the LDPC codeword is 64800, the number of bit groups (.180) of the LDPC codeword may be an integer multiple of the number of columns (=4) when the modulation method is 64-QAM. That is, no remainder is generated when the number of bit groups of the LDPC codeword is divided by the number of columns.
In this case, as shown in FIG. 14, the block interleaver 124 writes the bits included in each of the bit group Yo, bit group Y1....., bit group Y29 in the 1" row to 10800th row of the first column, writes the bits included in each of the bit group Y30, the bit group Y31,..., the bit group Y59 in the 1" row to 10800th row of the second column, writes the bits included in each of the bit group Y60, the bit group Y612. = , the bit group Y89 in the 1st row to 10800th row of the third column, writes the bits included in each of the bit group Y90, the bit group Y91,..., the bit group Y119 in the 1"
row to 10800th row of the fourth column, writes the bits included in each of the bit group Y1202 the bit group Y121,¨, the bit group Y149 in the 1" row to 10800th row of the fifth column, and writes the bits included in each of the bit group Y150, the bit group Y151,..., the bit group Y179 in the 1" row to 10800th row of the sixth column.. In addition, the block interleaver 124 may read the bits written in each row of the two columns serially in the row direction.
As described above, when the number of bit groups constituting the LDPC
codeword is an integer multiple of the number of columns of the block interleaver 124, the block interleaver 124 may interleave the plurality of bit groups in bit group wise, and accordingly, the bits belonging to the same bit group may be written in the same column.
As described above, the block interleaver 124 may interleave the plurality of bit groups of the LDPC codeword in the method described above with reference to FIGs. 13 and 14.
The modulator 130 maps the interleaved LDPC codeword onto a modulation symbol.

Specifically, the modulator 130 may demultiplex the interleaved LDPC codeword, modulate the demultiplexed LDPC codeword, and map the LDPC codeword onto a constellation.
In this case, the modulator 130 may generate a modulation symbol using the bits included in each of a plurality of bit groups.
In other words, as described above, the bits included in different bit groups are written in each column of the block interleaver 124, and the block interleaver 124 reads the bits written in each column in the row direction. In this case, the modulator 130 generates a modulation symbol by

71 mapping the bits read in each column onto each bit of the modulation symbol.
Accordingly, each bit of the modulation symbol belongs to a different bit group.
For example, it is assumed that the modulation symbol consists of C number of bits. In this case, the bits which are read from each row of C number of columns of the block interleaver 124 may be mapped onto each bit of the modulation symbol and thus, each bit of the modulation symbol consisting of C number of bits belong to C number of different bit groups.
Hereinbelow, the above feature will be described in greater detail.
First, the modulator 130 demultiplexes the interleaved LDPC codeword. To achieve this, the modulator 130 may include a demultiplexer (not shown) to demultiplex the interleaved LDPC
codeword.
The demultiplexer (not shown) demultiplexes the interleaved LDPC codeword.
Specifically, the demultiplexer (not shown) performs serial-to-parallel conversion with respect to the interleaved LDPC codeword, and demultiplexes the interleaved LDPC codeword into a cell having a predetermined number of bits (or a data cell).
For example, as shown in FIG. 15, the demultiplexer (not shown) receives the LDPC
codeword Q.(q0, qi, q2, ...) output from the interleaver 120, outputs the received LDPC
codeword bits to a plurality of substreams serially, converts the input LDPC
codeword bits into cells, and outputs the cells.
In this case, the bits having the same index in each of the plurality of substreams may constitute the same cell. Accordingly, the cells may be configured like (yo,o, Yi,o, Yieviou-1,0)--(qa, qi, ChMOD-1), (Y0,1) Y1,1) = = = ) YIMOD-1,1)4 %MOD, ChM0D+1) = = =
) C12)01MOD-1)) = = = = =
Herein, the number of substreams, Nsubstreams, may be equal to the number of bits constituting a modulation symbol, Timm. Accordingly, the number of bits constituting each cell may be equal to the number of bits constituting a modulation symbol (that is, a modulationorder).
For example, when the modulation method is 16-QAM, the number of bits constituting the modulation symbol, ilmou, is 4 and thus the number of substreams, Nsubstreams, is 4, and the cells may be configured like (yo,o, 371,0, 372,0, Y3,0)=(140, (lb q2, 113), (y0,1, yii, 372,1, q6,q7), (y0,2, yi,2, y2,2, y3,2)4418, q9, qw, qii), = = = =
In another example, when the modulation method is 64-QAM, the number of bits constituting the modulation symbol, Ilmou, is 6 and thus the number of substreams, Nsubstreams, is 6, and the cells may be configured like (yo,o, Y1,09 Y2,09 Y3,09 Y4,09 y5,0)--(q0, qi, q2, q3, q4, qs), (yo,i, yi,i, y2,1, 373,1,

72 Y4,1, Y5,1)=0:16,C17, C18,c19, (110,1410, (y0,2, y1,2, y2,2, Y3,25 Y4,2, Y5,2)=(C112, C113) (114/ C1157 C116, 4117), = = = =
The modulator 130 may map the demultiplexed LDPC codeword onto modulation symbols.
Specifically, the modulator 130 may modulate bits (that is, cells) output from the demultiplexer (not shown) in various modulation methods such as Quadrature Phase Shift Keying (QPSK), 16-QAM, 64-QAM, 256-QAM, 1024-QAM, 4096-QAM, etc. For example, when the modulation method is QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and QAM, the number of bits constituting the modulation symbol, Timm (that is, the modulation order), may be 2, 4, 6, 8, 10 and 12, respectively.
In this case, since each cell output from the demultiplexer (not shown) is formed of as many bits as the number of bits constituting the modulation symbol, the modulator 130 may generate the modulation symbol by mapping each cell output from the demultiplexer (not shown) onto a constellation point serially. Herein, the modulation symbol corresponds to a constellation point on the constellation.
However, the above-described demultiplexer (not shown) may be omitted according to circumstances. In this case, the modulator 130 may generate modulation symbols by grouping a predetermined number of bits from interleaved bits serially and mapping the predetermined number of bits onto constellation points. In this case, the modulator 130 may generate the modulation symbols by mapping rimoD number of bits onto the constellation points serially according to a modulation method.
The modulator 130 may modulate by mapping cells output from the demultiplexer (not shown) onto constellation points in a non-uniform constellation (NUC) method.
In the non-uniform constellation method, once a constellation point of the first quadrant is defined, constellation points in the other three quadrants may be determined as follows. For example, when a set of constellation points defined for the first quadrant is X, the set becomes ¨
conj(X) in the case of the second quadrant, becomes conj(X) in the case of the third quadrant, and becomes ¨(X) in the case of the fourth quadrant.
That is, once the first quadrant is defined, the other quadrants may be expressed as follows:
1 Quarter (first quadrant)=X
2 Quarter (second quadrant)=-conj(X) =
3 Quarter (third quadrant)=conj(X) 4 Quarter (fourth quadrant)=-X
Specifically, when the non-uniform M-QAM is used, M number of constellation points may

73 be defined as z={zo, zi, In this case, when the constellation points existing in the first quadrant are defined as Ixo, xi, x2, ..., xm/4.11, z may be defined as follows:
from zo to 2m/4.1=f101ri X0 to XM/4 from zmg to zum4.1.-conj(from x0 to xhipt) from Zamg to z3x14/4_1=conj(from x0 to xm/4) from Zumg to Z.4.mp4_1=-(f11)111 X0 to Xm/4) Accordingly, the modulator 130 may map the bits [yo, ym_i] output from the demultiplexer (not shown) onto constellation points in the non-uniform constellation method by mapping the output bits onto ZL having an index of L = E (y x 2m1). An example of the constellation i=0 =
defined according to the non-uniform constellation method may be expressed as in tables 26 to 30 presented below when the code rate is 5/15, 7/15, 9/15, 11/15, 13/15:
[Table 26]
Input data cell y Constellation point z.
(00) +10/,IT
(01) (1-10/T
(10) (-1 +1 i)brf (11) (-1 -1.0/.12-= [Table 27]
. .
=
= . , wittiati, on: , 610/3 3.0,013. 1110/13- 012/19' Ftl3f15 =
0.45301026231., 2.210341255261 =04111,14,25731 0420311.20571 12173+0.411194 (1332316.95471- 5:272510.22991 ; 0.1517+035111 -4 =
Ø266414ASIOV 0.301411,21031 132513441191 1,2110740.4909E 0.6521144.25711 0364740.23031 139340+0393BI -12.952414130611 1.2e9zfo.513.51. .048.41144:211241 1.2(43441311 '11.2676.630431, .2.4226434424 5.29214.92631 6.2299441.23461 (2.3667+0123261 23' i5115#1,2012i. 6.2524466271 049514.206111 61.2653424261 3.2021114.6591 11,7209+0.29271 O5*:44.5540i 01451.034571 [Table 28]
' Nishope maksen 9911,115 ,IM15 911$_9995 õ,,264.30/12 424.203 144_44 - .424j435 _ G.63421634231, a3332e.eblat: = L422?.C1.2SZOLo474e slur 1$491190&2197/1 01339744.69101 t1)16440S9991- 4.410,402,4734=
= 1.102.31111A3171. 0:117710.125611 L256310.14111 _0-15111411.68421..
1219310.31131 0.130644166241 11731540.46.131 :0-130314,633111 == . 641212141311 2.111114.26MI= '2421146.23216. 6.326114.22421' = .3.22524.21121: 63.2224464221,. 1.6444636421, 0:1999-0.0296 =
totta44.033E = 4:711044,39oSt- ,o:zisi=isszez. -tiligetoli est Itsessitusiot' '0,1013k11372P. '572434422041- '4223040.16461 24.
4.22115642301'; 1114211=11;332151' =429204611271 441214412301'. 0:24121.46561 -.0,56424.4.5141' .1.2613444141 '44/242446171.
4 . '6.22164131111 0.457940.20441, ittillen.23611: 0.71$240.1910,. Ø82141#1.217R:
:0:6?1,60.1415p. _Ø7119241014714' Ø14410.32661-=24 0.304960.1416 0.1021417111. 0.2172+1,0211/ µ4311611411.17961.
420694.141,92 examomoir 1.4261.4.11261. 0.69074615011.
27. 036134.154.1 426244322011, = 0320313,41221. =41.1771+033361- 46241/462213- 536244.1341 r.9990-1.1293k oaa.44.4.3.3ost =
-II:0,711.94.9.13191: 4.32164-11.119L71: _41.3010t:11,14731:: 8-1639411j91641- :11A1194,04,177 ..p.stiouoisscpr = 0aa,.924.A07)1 , 0.726=40.92091 r9:-042314432621: 02352+1.01901 0.30:1941101i. 0.193011.11277T, 11.39994.1251111.
.11.XL2601.22531 1143124-0.420.11 ..:1941.3441.54951 40, 0.750.9.26531 0945041.26191, A04Irrt0.11011: :0-819941.25.951 11.714.9910.15541 0.9934407111: '0:14.9i0.13351 C1965411733k.
an; =
61142443041: 4242+244944 44125432631 '4,11$5146411- .452344A21111' 11511224-41151; . 041654.12111== 0.251131/37234.
-4t. '0,21P5t0.3,1791.. 14525425111. ,;4142224205111, o1if.e=0,00610 0,110:004Per. 0.009,4505t. 4.10.44,147i = Ø42e,*(1,51,10i.
6.211124.2675r. ,131157.062351/. .14691=6302$1 2321112=521111 '0.131/2442222- 0376543901. ..0A11710.72461:. -=32121424.5.251-0,211042zeil I30 4011010-Ø187180e4e51 1-.123624034361_ -0.132620.14001, 1.22394.67621=== =
5143241.61)61 =;,.Ø5176Ø17121 = 4S, 5316124.31121- 1=101291.2.24121; = .4.126140.61161 -.2.466343.22236 catroo.istoot -LItamiiazav ii.ai22oz.39ut . .3341240.1944 [Table 29]
=
=
=

74 4/Shape NUC_64 tits &ss,7J15 N88_6431/13 -118C..64 9/0 91U0._64_10/15 NUC 14 13/15 NUC 61-17/23 tax st 0.43874L0R31 , 0.335240.60281 . 1.48274029201 03547+0.61491 1438840.28781 03317+06970 1.085440-53944 08624 1.17151 xl 1.e0234.43871 0207740.65141 13594034111 0.15814040121 1.2150441.81,331 01385=088241 1735340A6231 L1184 + 0.84621' 1187534108822 017114030281 1.021140.21741 0i567Ø2749F 1.03864022191 013234044371 1.047440.16951 03113 + 138431 v3= ' 1.0118140.87531 015564430351 0.879844157021 0.1334.037001' 0.849440.61451 0.101.540.13721 07243+0.15041 03635 41177071 14 02202+0.92381 0.602840.33451 0.29204148271 0.317740.40301 _0.2931+146561 0.568240.4509 1.0693+094154i 1.1795Ø2661i 4 0.201940.78181 .
065774020841 , 0.84104125631 07262+017541 03230+1.22754 11673940.14351 0.71/9240.80131 18895 + 0.48821 x6 . 0.101840 84r441 0302140.17111 0.217441.02111 0356840.17561 0.206941.06491 0.3597+034011 1.426140.22161 .. 0.8101 + 0.1492i 47 02653+0.75401 _413028Ø15561 '03702Ø87954 03771.013361 0.5677+089711 0.366040.12042 0.610641.17831 0.7482 + 0.4477i 0.78184020191 0.55560089721 0.30404024751 0563940.88641' 0.41190011771 0.600140.89221 0139240.40781 0.1524+0.99431 0.9238422021 0.235241.01901 0.30284016911 0.190042.02771 0.399840.25161 0.21204122532 0.42624042851 0.1482 + 0.68771 180 ,0.734010.26531 418450=126191 0685540.18711 0.81994125151 0.74424025591 0.9594+10714 , 0.140744113361 04692 + 1_0053i 411 0.84544030491 0.29224148941, 0612640.35631 0285441.4691/ .0595440.43281 0382941.39951 0.426540.13881 04492Ø73532 x12 0.26754024791 029794055491 0.1475.03040' 0.865440.605111 0.1166+0.1670 0.84394036754 0.138840.78571 0.1578 + 013191 413 0147940.26751 1.019740.23591 026914030281 1.038240.21411 025824033251 037594019591 0.419740.72061 0.1458 40,40251 1114 02890+027011 116264054571 0.1137140.66551 113624014161 0.135540140131 1.22394447602 03682+1.03141 0A763+014071 .15 0.270140.28901 148944029221 0.3555+0.61261 1466340.29731 0.3227+0.62001 1.3653+023231 0.2287+139141 0.4411 + 0.42671 [Table 30]
=

75 ./59.1. 96/15 97/15 118/15 99/15 910/15 911/15 612/15 .0 0.69004.69261 1.2905+1.30991 1.01044.37881 ,1.3231.1.15061 1.60974015491 0.31054033111 1.1014.1.16701 0.35564.34971 ' xl 0.3911.1.36451 1.050440.95771 1.048740.9662f 0.9851.1.23111 1.55494046051 0.434240.33601 0.8557.1.24211 0.357940.49451 52 0.21914.75241 1131940.19351 1.646440.74281 1.143940.89741 1.322640.12901 0.314940.4829/ 1.2957Ø80391 0.504940.35711 .3 0.2274+1.42081 1.157740.11161 1.324540.94141 0.934340.92711 1.27724.311291 5.440040.48071 1.088140.89561 0.50564050631 5.116784.24171 1.7681Ø25091 0.71941.24271 1.539940.79621 1.2753+1.52421 018114.33751 037954.11101 0.2123Ø34971 85 0.7275.1.16671 1.42754.14001 0.81064.01401 0309240.55991 1.443440.75401 5.06334.34041_ 0.6637.1.42151 0.211640.49001 .6 0.8747+1.04701 1.47944.52011 03595+1.03171 1.222240.65741 1.0491Ø84761 0.18184.48511 0.6930+1.00821 0.07134.34891 .7 0.7930+1.04061 1.340140.43461 0.611840.97211 . 0.957940.63731 1.1861Ø62531 0.06334.48151 0,884940.96471 0.0690Ø49601 69 0.209840.97681 5.7837+0.58671 1.676840.20021 0.7748.1.58671 0.932640.09701 0.308440.19711 1.206340.51151 0.35279010861 x9 0.2241.1.04541 0.825040.64551 9.999740.68441 0.6676+1.241191 0196240.28041 0.43564019931 1.005940.49521 0.3497Ø07131 .10 0183840.98781 0.823640.66011 1.421240.47691 0.5992Ø91081 1.104440.11021 0.309840.06761 1.417110.59011 0.496040.21231 all 0.1901.1,06591 0.877740.61101 1.147940.63121 0.679640.97431 1.064840.33671 0.434240.06911 1.04640.69351 0.49744.06981 812 0.554740.83121 1.006040.18431 0.607940.65661 0.5836.038791 0.732540.60711 0.177540.19851 0.66394.61861 0.208640.20791 .13 5.347940.86511 1.075940.17211 0.7284Ø69571 0.691540.57694 0.826040.45591 0.064040.19781 0.835340.56511 0.20944.06901 .14 0.607340.61821 1.00540.27581 0.57244.70311 0.3858+0.70581 0.874440.71531 0.17754,06761 0.687940.80221 0.067640.20791 1.15 0395540.84201 1.066240.2964 0.630240.72591 0.6868Ø67931 0.9882Ø53001 0.064740.06691 0.86344.76221 0.069810.06831 x16 1.407040.17901 0.8334+1.55541 0.1457+1.40101 1.611840.14971 0.16441.64071 0.7455Ø34111 0.1213+1.43661 0.356140.79591 .17 1.722740.29001 0.8165+1.10921 0.186641.73461 0.951140.11401 0.466741.57431 0.5811+0.33961 0.1077+1.20981 0.357140.63921 918 1.32464.25621 0.60924.27291 0.1174.1.10351 1.297040.12341 0.13634.35791 0.755640.46691 0.065144198011 0.5034Ø82711 x19 1.363640.36541 0.672841.14561 0.109641.01321 1.026640.11911 0.402341.30261 0.511624.47561 0.2009.1.01151 0.5063Ø66001 x20 1.3706+1.28341 0.306141.74691 04357.1.36361 1.583140.44961 1.0542+1.25841 0.955640.32901 0.3764.1.42641 0.21464.78621 .21 1.67014.114031 0.1327.1.40561 0.5853.1.68201 0.932840.35861 0.78754.44501 1.176740.30911 0.32374.21301 0.210940.63401 122 1.16144,79091 0.3522.1.34141 0.3439.1.06891 1.279640.31941 0.1697+304071 0.967340.47201 0.620540.98141 0.071340.80931 1423 1.124140.73671 0.2273+1.30811 0.323440.99621 1.01140.34471 0.65024.19511 1.2051Ø51351 0.3615+1.01631 0.069640.64671 014 0.976940.16631 0.5007.0,80981 0.10924.61741 0.5940+0.10591 5.098240.97451 0.736740.20151 0.571640.65961 0.2799+1.08621 .25 0.94524.20571 0.552840.83471 0.107440.63071 0.7215Ø11001 0.294240.93441 0.58114120151 0.21164.65971 0.2806,1.17551 026 1.010040.21821 0.48434.84961 0.11094019961 0.58634./1361 0.11424.14481 0.73140.06691 0.07294.81311 0.432140.99041 527 0.97954.24171 5.53044.87391 0.10764.73451 0.690940.11661 0.338541.09731 0.578140.06691 0.21584.82461 0.45614.18121 026 0.12414,49561 0.17154.91471 0.329140.02641 0.584340.36041 0.606240.74651 0.906240.19711 0.503640.64671 0.230940.94141 .29 0.823240.41371 5.1540Ø95101 0.31264.63731 0.697040.35921 0.460740.85381 1.282940.11851 0.353640.65721 0.10774.31911 x30 0.979940.53911 0,19644.94311 0.339240.69991 0.58084.31501 0.7263Ø17641 0.9156+0.07351 0.51154.80861 0.07714.98521 .31 0.979640.53561 0.171184.98321 0.320240.72121 0.6671140.32901 0.3430+1.00671 1.101140.07351 0.359340.82451 0.090141.17531 .32 0.137640.33421 0.375240.16671 0.965240.10661 0.140641.61621 0.265540.07461 0.3244Ø10441 1.254540.10101 0.330140.37271 x33 0138340.32921 0.3734Ø16671 0.907540.16661 0.12724.19841 0.266440.07591 0.456940.12181 1.06740.09561 0.825640.52561 *34 0.13634.3322/ 0.37584016611 0.972440.1171/ 0.1215*0.96441 0.45714.03521 0.320740.64151 L47324.1167/ 0.6593Ø3668/
a35 0.137040.32731 0.374640.16491 0.918640.17521 0.12204.03931 0.451640.10621 0.4509Ø63711 0.89814.08821 0.662344151811 836 0.1653Ø32651 0.40134.11301 0.634240.13721 0.11244011011 0.25594.17901 0.192040.81961 0.551840.06901 1.01864036451 .37 0.165640.32271 0.400140.12301 0.655040.14951 0.1177Ø60411 0.25864.17721 0.063340.81671 0.690340.05521 1.000140.52421 .38 0.16344.32461 0.4037+0.12301 0.629040.13931 0.1136Ø74551 0.359240.18111 0.18114.63711 0.57424.19971 1.166740.27251 .39 0.163640.31081 0401940.12181 0.6494Ø15041 0.118540.71601 0.372840.26541 0.064040.64151 0.737440.15641 1.3928Ø34081 z40 0.1779.Ø66411 0.60254.39111 1.3127.4112401 0.4324+1.56791 0.7706Ø09221 0.3331+1.06691 1.237840.30491 0.8011Ø12271 x41 0.182840.68451 0.5946Ø39281 0.957240.43441 0.3984.1.28251 0.740740.22601 0.4655+1.00871 1.05184030321 0.79614.07351 042 0.1745Ø68261 0.611640.31791 1.240340.26311 0.3766Ø95341 0.61804.09271 0.34334.21651 /.45844035111 0.6459+0.21981 413 0.179340.68291 0.60194.38371 1.02544.41301 0.3668+1.01511 0.601940.16581 0.500441.50621 0.910740.26031 0,6430Ø07131 144 0.354740.60091 0.737740.16181 0.600040.42141 0.3667443.59951 0.600740.49101 0.1971+1.00511 0.632140.47291 0.968140.22031 845 0.359340.60111 0.729840.15621 0.677340.42841 0.33284019601 0.667340.36281 0.0735+1.02951 0.7980Ø43921 0.961340.07351 046 0.3576Ø59901 0.7274Ø17521 0.5995Ø41021 0.3617Ø71941 0.478640.39351 0.1498+1.50181 0.6045Ø32741 1.3327Ø10391 .47 0.362440.59941 0.716540.17461 0.65314.41011 0.33734.69611 0317640.33911 0.016541.25531 0.7629419651 1.135910.08091 4413 0.269740.14431 0.150940.24251 0.1250+0.11531 0.106540.11461 0.0757Ø10031 0.7811Ø90801 0.059640.07391 0.638240.07091 3.49 0.27044014331 0.15034.24001 0.125240.11581 0.11454.11081 0.075343.10041 0.6167Ø81531 0.1767.007311 011145Ø69341 .50 0.264440.14421 0.151540.24371 0.124540.11521 0.105340./2741 0.077740.47681 0.7136Ø62551 0.061240.21981 0.6645414861 /451 0.265040.14321 0.1503Ø24251 0.12474011561 0.11340.12361 0.08674.47541 0.600040.63271 0.181940.21921 0.66004.67861 852 0.276340.16381 0.128540.23881 0376640.12441 0.111140.36211 0.102340.22431 0.96984.76601 0.42140.07151 1./6124.69491 x53 0.276840.16261 012794.24191 0.370740.12371 0.118640.3E4671 0.1010Ø22421 1.58554.14984 0.297840.07251 0.97054.69421 454 0.271510.16301 0.127940.24311 0.377940.12601 0.10804.34311 0.19504039191 0.94764.61751 0.43374.21151 1.3698+0.62591 14.55 0.27194.16115 0.127940.24061 0.371740.12521 0.117740.34191 0.1881Ø39691 1.46254040151 0.30574.21671 1.216340.48411 .56 0.648840.16961 0.33940.57641 0.116140.36931 0,3644Ø10801 0.0930.081221 0.337641.02251 0.066740.51241 0.7989+1.04981 .57 0.646240.17061 11.33644.57221 0.1157Ø36451 0.3263Ø11041 0.22154.78401 0.631341.03641 0.20084.50951 0.4395+1,42031 1.58 0.645640.17451 0.3328+0.57581 0.11764.34691 0.3691Ø11731 0.093740.65141 01015+1.28551 0.06234036531 0.611114.02461 s59 0.643140.17531 0.3303Ø56981 0.117140.34141 0.328940.11961 0.1540Ø63661 0.6342.9.27051 0.1399Ø36421 0.630341.24211 .60 0.585440.31661 0.149140.63161 03530+0.38991 0.3665Ø37591 0.481040.63051 1.0422+0.95931 0.48184.49461 1055040.89241 061 0.58624.31671 0.146140.62801 0.3422438061 0331040.37951 0.38564.70371 1174940.85381 0.338040.50501 0.8612+1.28001 062 0386440.32751 0.150940.62801 0.3614+0.37551 0.367240.33531 0.3527Ø52301 1.15564.16471 0.45714.34991 1.269640.89691 .63 0.5873Ø32541 0.14734.62051 0.350940.36561 0.3336Ø34021 03100435591 1.477140.67421 0.32164.35991 1.034241.11611 Table 26 indicates non-uniform QPSK, table 27 indicates non-uniform 16-QAM, Tables 28

76 and 29 indicate non-uniform 64-QAM, and table 30 indicates non-uniform 256-QAM.
Referring to these tables, the constellation point of the first quadrant may be defined with reference to tables 26 to 30, and the constellation points in the other three quadrants may be defined in the above-described method.
However, this is merely an example and the modulator 130 may map the output bits outputted from the demultiplexer (not shown) onto the constellation points in various methods.
The interleaving is performed in the above-described method for the following reasons.
Specifically, when the LDPC codeword bits are mapped onto the modulation symbol, the bits may have different reliability (that is, receiving performance or receiving probability) according to where the bits are mapped onto in the modulation symbol. The LDPC codeword bits may have different codeword characteristics according to the configuration of a parity check matrix. That is, the LDPC codeword bits may have different codeword characteristics according to the number of 1 existing in the column of the parity check matrix, that is, the column degree.
Accordingly, the interleaver 120 may interleave to map the LDPC codeword bits having a specific codeword characteristic onto specific bits in the modulation symbol by considering both the codeword characteristics of the LDPC codeword bits and the reliability of the bits constituting the modulation symbol.
For example, when the LDPC codeword formed of bit groups Xo to X179 is group-interleaved based on Equation 21 and Table 11, the group interleaver 122 may output the bit groups in the Order of X55, X146, X83, = = = X132, X135.
In this case, when the modulation method is 16-QAM, the number of columns of the block interleaver 124 is four (4) and each column may be formed of 16200 rows.
Accordingly, from among the 180 groups constituting the LDPC codeword, 45 bit groups (X55, X146, X83, X52, X62, X176, X160, X68, X53, X56, X81, X97, X79, X113, X163, X61, X58, X69, X133, X108, X66, X71, X$6, X144, X57, X67, X116, X59, X70, X156, X172, X65, X149, X155, X82, X138, X136, X141, X111, X96, X170, X90, X140, X64, X159) may be inputted to the first column of the block interleaver 124, 45 bit groups (X15, X14, X37, X54, )(44, X63, X43, X18, X47, X7, X25, X34, X29, X30, X25, X39, X16, X41, X45, X36, X0, X23, X32, X28> X27, X38, X48, X33, X22, X49, X51, X60, X46, X21, X4, X3, X20, X13, X50, X35, X24, X40, X171 X42, X6) may be inputted to the second column of the block interleaver 124, 45 bit groups (X112, X93, X
X101, X94, X115, X105, X31, X19, X177, X74, X10, X145, X162, X102, X120, X126, X95, X73, X152, X129, X174, X125, X72, X128, X78, X171, X8, X142, X178, X154,

77 X85, X107/ X75, X121 X9, X151, X771 X117, X109/ X80, X106, X134, X98, Xi) may be inputted to the third column of the block interleaver 124, and 45 bit groups (X122, X173, X161, X150, X110, X175, X166, X131, X119, X103, X139, X148, X157, X114, X147, X87, X158, X121, X164, X104, X89, X179, X123, X118, X99, (88, X11, X92, X165, X84, X168, X124, X169, X2, X130, X167, X153, X137, X143, X91, X100, X5, X76, X132, X135) may be inputted to the fourth column of the block interleaver 124.
In addition, the block interleaver 124 may output the bits inputted to the 1st row to the last row of each column serially, and the bits outputted from the block interleaver 124 may be inputted to the modulator 130 serially. In this case, the demultiplexer (not shown) may be omitted or the bits may be outputted serially without changing the order of bits inputted to the demultiplexer (not shown). Accordingly, the bits included in each of the bit groups X55, X15, X112, and X122 may constitute the modulation symbol.
When the modulation method is 64-QAM, the number of columns of the block interleaver 124 is six (6) and each column may be formed of 10800 rows.
Accordingly, from among the 180 groups constituting the LDPC codeword, 30 bit groups (X55, X146, X83, X52, X62, X176, X160, X68, X53, X56, X81, X97, X79, X113, X163, X61, X58, X69, X133, X108, X66, X71, X86, X144, X57, X67, X116, X59, X70, X156) may be inputted to the first column of the block interleaver 124, 30 bit groups (X172, X-65, X149, X155, X82, X138/ X136, X141, X111, X96, X170, X90, X140, X64, X159, X15, X14, X37, X54, X44, X63, X43, X18/ X47, X7, X25, X34, X29, X30, X26) may be inputted to the second column of the block interleaver 124, 30 bit groups (X39, X16, X41, X45, X36, X0, X23, X32, X28, X27, X38, X48, X33, X22, X49, X51, X60, X46, X21, X4, X3, X20, X13, X50, X35, X24, X40, X17, X42, X6) may be inputted to the third column of the block interleaver 124, 30 bit groups (X112, X93, X127, X101, X94, X115, X105, X31, X19, X177, X74, X10, X145, X162, X102, X120, X126, X95, X73, X152, X129, X174, X125, X72, X128, X78, X171, X8, X142, X178) may be inputted to the fourth column of the block interleaver 124, 30 bit groups (X154, X85, X107, X75, X12, X9, X151, X77, X117, X109, X80, X106, X134, X98, X1, X122, X173, X161, X150, X110, X175, X166, X131, X119, X103, X139, X148, X157, X114, X147) may be inputted to the fifth column of the block interleaver 124, and 30 bit groups (X8'7, X158, X121, X164, X104, X89, X179, X123, X118, X99, X88, X11, X92, X165, X84, X168, X124, X169, X2, X130, X167, X153, X137, X143, X91, X100, X5, X76, X132, X135) may be inputted to the sixth column of the block interleaver 124.
In addition, the block interleaver 124 may output the bits inputted to the 1st row to the last row of each column serially, and the bits outputted from the block interleaver 124 may be

78 inputted to the modulator 130 serially. In this case, the demultiplexer (not shown) may be omitted or the bits may be outputted serially without changing the order of bits inputted to the demultiplexer (not shown). Accordingly, the bits included in each of the bit groups X55, X172, X399 X112, X154 ,and X87 may constitute the modulation symbol.
As described above, since a specific bit is mapped onto a specific bit in a modulation symbol through interleaving, a receiver side can achieve high receiving performance and high decoding performance.
That is, when LDPC codeword bits of high decoding performance are mapped onto high reliability bits from among bits of each modulation symbol, the receiver side may show high decoding performance, but there is a problem that the LDPC codeword bits of the high decoding performance may not be received. In addition, when the LDPC codeword bits of high decoding performance are mapped onto low reliability bits from among the bits of the modulation symbol, initial receiving performance is excellent, and thus, overall performance is also excellent.
However, when many bits showing poor decoding performance are received, error propagation may occur.
Accordingly, when LDPC codeword bits are mapped onto modulation symbols, an LDPC
codeword bit having a specific codeword characteristic is mapped onto a specific bit of a modulation symbol by considering both codeword characteristics of the LDPC
codeword bits and reliability of the bits of the modulation symbol, and is transmitted to the receiver side.
Accordingly, the receiver side can achieve high receiving performance and decoding performance.
Hereinafter, a method for determining n(j), which is a parameter used for group interleaving, according to various exemplary embodiments, will be explained.
According to an exemplary embodiment, when the length of the LDPC codeword is 64800, the size of the bit group is determined to be 360 and thus 180 bit groups exist. In addition, there may be 180! possible interleaving patterns (Herein, factorial means A!=Ax(A-1) x ...x2x1) regarding an integer A.
In this case, since a reliability level between the bits constituting a modulation symbol may be the same according to a modulationorder, many number of interleaving patterns may be regarded as the same interleaving operation when theoretical performance is considered.
For example, when an MSB bit of the X-axis (or rear part-axis) and an MSB bit the Y-axis(or imaginary part-

79 axis) of a certain modulation symbol have the same theoretical reliability, the same theoretical performance can be achieved regardless of the way how specific bits are interleaved to be mapped onto the two MSB bits.
However, such a theoretical prediction may become incorrect as a real channel environment is established. For example, in the case of the QPSK modulation method, two bits of a symbol in a part of a symmetric channel like an additive white Gaussian noise (AWGN) channel theoretically have the same reliability. Therefore, there should be no difference in the performance theoretically when any interleaving method is used. However, in a real channel environment, the performance may be different depending on the interleaving method. In the case of a well-known Rayleigh channel which is not a real channel, the performance of QPSK greatly depends on the interleaving method and thus the performance can be predicted somewhat only by the reliability between bits of a symbol according to a modulation method. However, there should be a limit to predicting the performance.
In addition, since code performance by interleaving may be greatly changed according to a channel which evaluates performance, channels should be always considered to drive an interleaving pattern. For example, a good interleaving pattern in the AWGN
channel may be not good in the Rayleigh channel. If a channel environment where a given system is used is closer to the Rayleigh channel, an interleaving pattern which is better in the Rayleigh channel than in the AWGN channel may be selected.
As such, not only a specific channel environment but also various channel environments considered in a system should be considered in order to derive a good interleaving pattern. In addition, since there is a limit to predicting real performance only by theoretical performance prediction, the performance should be evaluated by directly conducting computation experiments and then the interleaving pattern should be finally determined.
However, since there are so many number of possible interleaving patterns to be applied (for example, 180!), reducing the number of interleaving patterns used to predict and test performance is an important factor in designing a high performance interleaver.
Therefore, the interleaver is designed through the following steps according to an exemplary embodiment.
1) Channels C1, C2, Ck to be considered by a system are determined.
2) A certain interleaver pattern is generated.

80 3) A theoretical performance value is predicted by applying the interleaver generated in step 2) to each of the channels determined in step 1). There are various methods for predicting a theoretical performance value, but a well-known noise threshold determining method like density evolution analysis is used according to an exemplary embodiment. The noise threshold recited herein refers to a value that can be expressed by a minimum necessary signal-to-noise ratio (SNR) capable of error-free transmission on the assumption that a cycle-free characteristic is satisfied when the length of a code is infinite and the code is expressed by the Tanner graph. The density evolution analysis may be implemented in various ways, but is not the subject matter of the inventive concept and thus a detailed description thereof is omitted.
4) When noise thresholds for the channels are expressed as THIN, TH2[i], THk[i] for the i-th generated interleaver, a final determination threshold value may be defined as follows:
TH[i]=WixTHi [i]+W2xTH2N+ +WkxTHk[i], where Wi +W2+ +Wk=1,Wi,W2, = = Wk> 0 Here, W1, W2, ..., Wk are adjusted according to importance of the channels.
That is, W1 W2) = = = Wk are adjusted to a larger value in a more important channel and W1, W2, = =, Wk are adjusted to a smaller value in a less important channel (for example, if the weight values of AWGN and Rayleigh channels are W1 and W2, respectively, Wi may be set to 0.25 and W2 may be set to 0.75 when one of the channels is determined to be more important.).
5) B number of interleaver patterns are selected in an ascending order of TH[i] values from among the tested interleaver patterns and are directly tested by conducting performance computation experiments. An FER level for the test is determined as 10^ ¨3 (for example, B=100).
6) D number of best interleaver patterns are selected from among the B number of interleaver patterns tested in step 5) (for example, D=5).
In general, an interleaver pattern which has a great SNR gain in the area of FER=10^ ¨3 may be selected as a good performance interleaver in step of 5). However, according to an exemplary embodiment, as shown in FIG. 16, performance of FER required in the system based on the result of real computation experiments for the area of FER=10^ ¨3 may be predicted through extrapolation, and then an interleaver pattern having good performance in comparison with the expected performance in the FER required in the system may be determined as a good interleaver pattern. According to an exemplary embodiment, the extrapolation based on a linear

81 function may be applied. However, various extrapolation methods may be applied. FIG. 16 illustrates an example of performance extrapolation predicted by the result of computation experiments.
7) The D number of interleaver patterns selected in step 6) are tested by conducting performance computation experiments in each channel. Herein, the PER level for testing is selected as PER required in the system (for example, FER=10^ ¨6 ) 8) When an error floor is not observed after the computation experiments, an interleaving pattern having the greatest SNR gain is determined as a final interleaving pattern.
FIG. 17 is a view schematically showing a process of determining B number of interleaver patterns in the steps 2), 3), 4), and 5) of the above-described method for determining the interleaving pattern in the case of AWGN and Rayleigh channels for example.
Referring to FIG. 17, necessary variables i, j, and etc. are initialized in operation S1701, and a noise threshold for the AWGN channel TH1[i] and a noise threshold for the Rayleigh channel TH2[i] are calculated in operation S1702. Then, a final determination noise threshold TH[i]
defined in step 4) is calculated in operation S1703, and is compared with a previously calculated final determination noise threshold TH[i-1] in operation S1704. When the final determination noise threshold TH[i] is smaller than the previously calculated final determination noise threshold TH[i-1], TH_S[i] is replaced with the TH[i] and is sotred in operation S1706. Next, i, j values increase by 1 in operation S1707 and this process is repeated until the i value exceeds A
which is pre-defined in operation S1708. In this case, A is the total number of interleaver patterns to be tested in steps 2), 3), 4), and 5) and A is typically determined to be greater than or equal to 10000. When all operations described above are completed, interleaver patterns corresponding to TH_S[0], TH_S[1], TH_S[B-1] which are stored in a descending order of final noise thresholds values in operation S1709.
The transmitting apparatus 100 may transmit the signal mapped onto the constellation to a receiving apparatus (for example, 1200 of FIG. 18). For example, the transmitting apparatus 100 may map the signal mapped onto the constellation onto an Orthogonal Frequency Division Multiplexing (OFDM) frame using OFDM, and may transmit the signal to the receiving apparatus 1200 through an allocated channel.
FIG. 18 is a block diagram to illustrate a configuration of a receiving apparatus according to an exemplary embodiment. Referring to FIG. 18, the receiving apparatus 1200 includes a

82 demodulator 1210, a multiplexer 1220, a deinterleaver 1230 and a decoder 1240.
The demodulator 1210 receives and demodulates a signal transmitted from the transmitting apparatus 100. Specifically, the demodulator 1210 generates a value corresponding to an LDPC
codeword by demodulating the received signal, and outputs the value to the multiplexer 1220. In this case, the demodulator 1210 may use a demodulation method corresponding to a modulation method used in the transmitting apparatus 100. To do so, the transmitting apparatus 100 may transmit information regarding the modulation method to the receiving apparatus 1200, or the transmitting apparatus 100 may perform modulation using a pre-defined modulation method between the transmitting apparatus 100 and the receiving apparatus 1200.
The value corresponding to the LDPC codeword may be expressed as a channel value for the received signal. There are various methods for determining the channel value, and for example, a method for determining a Log Likelihood Ratio (LLR) value may be the method for determining the channel value.
The LLR value is a log value for a ratio of the probability that a bit transmitted from the transmitting apparatus 100 is 0 and the probability that the bit is 1. In addition, the LLR value may be a bit value which is determined by a hard decision, or may be a representative value which is determined according to a section to which the probability that the bit transmitted from the transmitting apparatus 100 is 0 or 1 belongs.
The multiplexer 1220 multiplexes the output value of the demodulator 1210 and outputs the value to the deinterleaver 1230.
Specifically, the multiplexer 1220 is an element corresponding to a demultiplexer (not shown) provided in the transmitting apparatus 100, and performs an operation corresponding to the demultiplexer (not shown). That is, the multiplexer 1220 performs an inverse operation of the operation of the demultiplexer (not shown), and performs cell-to-bit conversion with respect to the output value of the demodulator 1210 and outputs the LLR value in the unit of bit. However, when the demultiplexer (not shown) is omitted from the transmitting apparatus 100, the multiplexer 1220 may be omitted from the receiving apparatus 1200.
The information regarding whether the demultiplexing operation is performed or not may be provided by the transmitting apparatus 100, or may be pre-defined between the transmitting apparatus 100 and the receiving apparatus 1200.
The deinterleaver 1230 deinterleaves the output value of the multiplexer 1220 and outputs the

83 values to the decoder 1240.
Specifically, the deinterleaver 1230 is an element corresponding to the interleaver 120 of the transmitting apparatus 100 and performs an operation corresponding to the interleaver 120. That is, the deinterleaver 1230 deinterleaves the LLR value by performing the interleaving operation of the interleaver 120 inversely.
To do so, the deinterleaver 1230 may include a block deinterleaver 1231, a group twist deinterleaver 1232, a group deinterleaver 1233, and a parity deinterleaver 1234 as shown in FIG.
18.
The block deinterleaver 1231 deinterleaves the output of the multiplexer 1220 and outputs the value to the group twist deinterleaver 1232.
Specifically, the block deinterleaver 1231 is an element corresponding to the block interleaver 124 provided in the transmitting apparatus 100 and performs the interleaving operation of the block interleaver 124 inversely.
That is, the block deinterleaver 1231 deinterleaves by writing the LLR value output from the multiplexer 1220 in each row in the row direction and reading each column of the plurality of rows in which the LLR value is written in the column direction by using at least one row formed of the plurality of columns.
In this case, when the block interleaver 124 interleaves by dividing the column into two parts, the block deinterleaver 1231 may deinterleave by dividing the row into two parts.
In addition, when the block interleaver 124 writes and reads in and from the bit group that does not belong to the first part in the row direction, the block deinterleaver 1231 may deinterleave by writing and reading values corresponding to the group that does not belong to the first part in the row direction.
Hereinafter, the block deinterleaver 1231 will be explained with reference to FIG. 20.
However, this is merely an example and the block deinterleaver 1231 may be implemented in other methods.
An input LLR vi (0<i<N1dpc) is written in a ri row and a ci column of the block deinterleaver 1231. Herein, ci=(i mod NO and ri = [
N, On the other hand, an output LLR cb(0.5i<Ncx Nri) is read from a ci column and a ri row of the

84 /
first part of the block deinterleaver 1231. Herein, ci = ¨ , [ ri.(i mod No).
Nrl In addition, an output LLR qi(I=Icx I%irii<Nidpc) is read from a ci column and a ri row of the [ (i ¨ NcxN,11 second part. Herein, c . i , ri.Nri+{(i-IsIcx Nri) mode Na}.
Nr2 The group twist deinterleaver 1232 deinterleaves the output value of the block deinterleaver 1231 and outputs the value to the group deinterleaver 1233.
Specifically, the group twist deinterleaver 1232 is an element corresponding to the group twist interleaver 123 provided in the transmitting apparatus 100, and may perform the interleaving operation of the group twist interleaver 123 inversely.
That is, the group twist deinterleaver 1232 may rearrange the LLR values of the same bit group by changing the order of the LLR values existing in the same bit group.
When the group twist operation is not performed in the transmitting apparatus 100, the group twist deinterleaver 1232 may be omitted.
The group deinterleaver 1233 (or the group-wise deinterleaver) deinterleaves the output value of the group twist deinterleaver 1232 and outputs the value to the parity deinterleaver 1234.
Specifically, the group deinterleaver 1233 is an element corresponding to the group interleaver 122 provided in the transmitting apparatus 100 and may perform the interleaving operation of the group interleaver 122 inversely.
That is, the group deinterleaver 1233 may rearrange the order of the plurality of bit groups in bit group wise. In this case, the group deinterleaver 1233 may rearrange the order of the plurality of bit groups in bit group wise by applying the interleaving method of Tables 11 to 22 inversely according to a length of the LDPC codeword, a modulation method and a code rate.
The parity deinterleaver 1234 performs parity deinterleaving with respect to the output value of the group deinterleaver 1233 and outputs the value to the decoder 1240.
Specifically, the parity deinterleaver 1234 is an element corresponding to the parity interleaver 121 provided in the transmitting apparatus 100 and may perform the interleaving operation of the parity interleaver 121 inversely. That is, the parity deinterleaver 1234 may deinterleave the LLR values corresponding to the parity bits from among the LLR values output from the group deinterleaver 1233. In this case, the parity deinterleaver 1234 may deinterleave the LLR value corresponding to the parity bits inversely to the parity interleaving method of

85 Equation 18.
However, the parity deinterleaver 1234 may be omitted depending on the decoding method and embodiment of the decoder 1240.
Although the deinterleaver 1230 of FIG. 18 includes three (3) or four (4) elements as shown in FIG. 19, operations of the elements may be performed by a single element.
For example, when bits each of which belongs to each of bit groups Xa, X1,3 Xc, Xd constitute a single modulation symbol, the deinterleaver 1230 may deinterleave these bits to locations corresponding to their bit groups based on the received single modulation symbol.
For example, when the code rate is 6/15 and the modulation method is 16-QAM, the group deinterleaver 1233 may perform deinterleaving based on table 11.
In this case, bits each of which belongs to each of bit groups X55, X15, X112, X122 may constitute a single modulation symbol. Since one bit in each of the bit groups X55, X15, X112, X122 constitutes a single modulation symbol, the deinterleaver 1230 may map bits onto decoding initial values corresponding to the bit groups X55, X15, X1123 X122 based on the received single modulation symbol.
The decoder 1240 may perform LDPC decoding by using the output value of the deinterleaver 1230. To achieve this, the decoder 1240 may include an LDPC
decoder (not shown) to perform the LDPC decoding.
Specifically, the decoder 1240 is an element corresponding to the encoder 110 of the transmitting apparatus 100 and may correct an error by performing the LDPC
decoding by using the LLR value output from the deinterleaver 1230.
For example, the decoder 1240 may perform the LDPC decoding in an iterative decoding method based on a sum-product algorithm. The sum-product algorithm is one example of a message passing algorithm, and the message passing algorithm refers to an algorithm which exchanges messages (e.g., LLR value) through an edge on a bipartite graph, calculates an output message from messages input to variable nodes or check nodes, and updates.
The decoder 1240 may use a parity check matrix when performing the LDPC
decoding. In this case, the parity check matrix used in the decoding may have the same configuration as that of the parity check matrix used in the encoding of the encoder 110, and this has been described above with reference to FIGs. 2 to 4.
In addition, information on the parity check matrix and information on the code rate, etc.

86 which are used in the LDPC decoding may be pre-stored in the receiving apparatus 1200 or may be provided by the transmitting apparatus 100.
FIG. 21 is a flowchart to illustrate an interleaving method of a transmitting apparatus according to an exemplary embodiment.
First, an LDPC codeword is generated by LDPC encoding based on a parity check matrix (S1410), and the LDPC codeword is interleaved (S1420).
Then, the interleaved LDPC codeword is mapped onto a modulation symbol (S1430). In this case, a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword may be mapped onto a predetermined bit in the modulation symbol.
Each of the plurality of bit groups may be formed of M number of bits, and M
may be a common divisor of Nidp, and Kidp, and may be determined to satisfy Qtapc4N1apc-K1dpc)/M.
Herein, Qmpc is a cyclic shift parameter value regarding columns in a column group of an information word submatrix of the parity check matrix, Nkipc is a length of the LDPC codeword, and Kldpc is a length of information word bits of the LDPC codeword.
Operation S1420 may include interleaving parity bits of the LDPC codeword, dividing the parity-interleaved LDPC codeword by the plurality of bit groups and rearranging the order of the plurality of bit groups in bit group wise, and interleaving the plurality of bit groups the order of which is rearranged.
The order of the plurality of bit groups may be rearranged in bit group wise based on the above-described Equation 21 presented above.
As described above, n(j) in Equation 21 may be determined based on at least one of a length of the LDPC codeword, a modulation method, and a code rate.
For example, when the LDPC codeword has a length of 64800, the modulation method is 16-QAM, and the code rate is 6/15, n(j) may be defined as in table 11.
In addition, when the LDPC codeword has a length of 64800, the modulation method is 16-QAM, and the code rate is 10/15, n(j) may be defined as in table 14.
In addition, when the LDPC codeword has a length of 64800, the modulation method is 16-QAM, and the code rate is 12/15, n(j) may be defined as in table 15.
In addition, when the LDPC codeword has a length of 64800, the modulation method is 64-QAM, and the code rate is 6/15, n(j) may be defined as in table 17.

87 In addition, when the LDPC codeword has a length of 64800, the modulation method is 64-QAM, and the code rate is 8/15, 7c(j) may be defined as in table 18.
In addition, when the LDPC codeword has a length of 64800, the modulation method is 64-QAM, and the code rate is 12/15, n(j) may be defined as in table 21.
The interleaving the plurality of bit groups may include: writing the plurality of bit groups in each of a plurality of columns in bit group wise in a column direction, and reading each row of the plurality of columns in which the plurality of bit groups are written in bit group wise in a row direction.
In addition, the interleaving the plurality of bit groups may include:
serially write, in the plurality of columns, at least some bit group which is writable in the plurality of columns in bit group wise from among the plurality of bit groups, and then dividing and writing the other bit groups in an area which remains after the at least some bit group is written in the plurality of columns in bit group wise.
A non-transitory computer readable medium, which stores a program for performing the interleaving methods according to various exemplary embodiments in sequence, may be provided.
The non-transitory computer readable medium refers to a medium that stores data semi-permanently rather than storing data for a very short time, such as a register, a cache, and a memory, and is readable by an apparatus. Specifically, the above-described various applications or programs may be stored in a non-transitory computer readable medium such as a compact disc (CD), a digital versatile disk (DVD), a hard disk, a Blu-ray disk, a universal serial bus (USB), a memory card, and a read only memory (ROM), and may be provided.
At least one of the components, elements or units represented by a block as illustrated in FIGs. 1, 5, 15, 18 and 19 may be embodied as various numbers of hardware, software and/or firmware structures that execute respective functions described above, according to an exemplary embodiment. For example, at least one of these components, elements or units may use a direct circuit structure, such as a memory, processing, logic, a look-up table, etc.
that may execute the respective functions through controls of one or more microprocessors or other control apparatuses. Also, at least one of these components, elements or units may be specifically embodied by a module, a program, or a part of code, which contains one or more executable instructions for performing specified logic functions. Also, at least one of these components,

88 elements or units may further include a processor such as a central processing unit (CPU) that performs the respective functions, a microprocessor, or the like. Further, although a bus is not illustrated in the above block diagrams, communication between the components, elements or units may be performed through the bus. Functional aspects of the above exemplary embodiments may be implemented in algorithms that execute on one or more processors.
Furthermore, the components, elements or units represented by a block or processing steps may employ any number of related art techniques for electronics configuration, signal processing and/or control, data processing and the like.
The foregoing exemplary embodiments and advantages are merely exemplary and are not to be construed as limiting the present inventive concept. The exemplary embodiments can be readily applied to other types of apparatuses. Also, the description of the exemplary embodiments is intended to be illustrative, and not to limit the scope of the inventive concept, and many alternatives, modifications, and variations will be apparent to those skilled in the art.

Claims (4)

CLAIMS:

1. A receiving apparatus comprising:
a receiver configured to receive a signal from a transmitting apparatus;
a demodulator configured to demodulate the signal to generate values according to a 16-quadrature amplitude modulation(QAM);
a deinterleaver configured to split the values into a plurality of groups, deinterleave the plurality of groups and deinterleave one or more values among the deinterleaved plurality of groups to provide deinterleaved values; and a decoder configured to decode the deinterleaved values based on a low density parity check (LDPC) code having a code rate being 6/15 and a code length being bits, wherein the plurality of groups are deinterleaved based on a following equation:
Y.pi.(j) = Xj for (0 <= j < N group) where Xj is a jth group among the plurality of groups, Yj is a jth group among the deinterleaved plurality of groups, Ngroup is a total number of the plurality of groups, and .pi.(j) denotes a deinterleaving order for the deinterleaving, and wherein the .pi.(j) is represented as follows:

2. The receiving apparatus of claim 1, wherein each of the plurality of groups comprises 360 values.

3. A receiving method comprising:
receiving a signal from a transmitting apparatus;
demodulating the signal to generate values according to a 16-quadrature amplitude modulation(QAM);
splitting the values into a plurality of groups;
deinterleaving the plurality of groups;
deinterleaving one or more values among the deinterleaved plurality of groups to provide deinterleaved values; and decoding the deinterleaved values based on a low density parity check (LDPC) code having a code rate being 6/15 and a code length being 64800 bits, wherein the plurality of groups are deinterleaved based on a following equation:
Y.pi.(j) = Xj for (0 <= j < Ngroup) where Xj is a jth group among the plurality of groups, Yj is a jth group among the deinterleaved plurality of groups, Ngroup is a total number of the plurality of groups, and Ir(j) denotes a deinterleaving order for the deinterleaving, and wherein the .pi.(j) is represented as follows:

4. The receiving method of claim 3, wherein each of the plurality of groups comprises 360 values.