KR20190064556A - Transmitting apparatus and interleaving method thereof - Google Patents

Abstract

A transmitting apparatus is disclosed. The transmitting apparatus comprises: an encoding unit for generating an LDPC codeword by performing LDPC encoding; an interleaver for interleaving LDPC codewords; and a modulation unit for mapping the interleaved LDPC codeword to a modulation symbol. Meanwhile, the modulation unit may map a bit included in a predetermined bit group among a plurality of bit groups constituting the LDPC codeword to a predetermined bit in the modulation symbol.

Description

[0001] TRANSMITTING APPARATUS AND INTERLEAVING METHOD THEREOF [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmitting apparatus and an interleaving method thereof, and more particularly, to a transmitting apparatus that processes and transmits data and an interleaving method therefor.

In the information society of the 21st century, broadcasting and communication services are in the era of full-scale digitalization, multi-channelization, broadband and high-quality. In particular, with the spread of high-definition digital TVs, PMPs, and mobile broadcasting devices, demand for supporting various receiving methods of digital broadcasting services is increasing.

In accordance with these requirements, the standard group has established various standards and provided various services that satisfy the needs of the users. Therefore, in order to provide a better service through better decryption and reception performance, do.

It is an object of the present invention to provide a transmitting apparatus capable of mapping a bit included in a predetermined bit group among a plurality of bit groups constituting an LDPC codeword to a predetermined bit in a modulation symbol and transmitting the bit, And to provide an interleaving method thereof.

According to an aspect of the present invention, there is provided a transmission apparatus including an encoder for performing LDPC encoding based on a parity check matrix to generate an LDPC codeword, an interleaver for interleaving the LDPC codeword, Wherein the modulator maps a bit included in a predetermined bit group among a plurality of bit groups constituting the LDPC codeword to a predetermined bit in the modulation symbol.

_Wherein each of the plurality of bit groups consists of M bits, M is a common divisor of N _ldpc and K _ldpc , and Q _ldpc = (N _{ldpc -} K _ldpc ) / M can be determined. In this case, Q _ldpc is the cyclic shift parameter value for the columns in the column group of the information word _sub- matrix constituting the parity check matrix, N _ldpc is the length of the LDPC codeword, and K _ldpc is the length of the LDPC codeword Is the length of the information bits.

The interleaver includes a parity interleaver for interleaving parity bits constituting the LDPC codeword, an LDPC codeword for separating the parity interleaved LDPC codeword into the plurality of bit groups, and rearranging the order of the plurality of bit groups into a bit group unit And a block interleaver for interleaving the plurality of bit groups in which the order is rearranged.

Here, the group interleaver may rearrange the order of the plurality of bit groups in a bit group unit based on Equation (21).

 In this case, the? (J) may be determined based on at least one of the length of the LDPC codeword, the modulation scheme, and the coding rate.

If the length of the LDPC codeword is 64800 and the modulation scheme is 16-QAM and the coding rate is 6/15, the above-mentioned? (J) can be defined as shown in Table 11 below.

The above-mentioned? (J) can be defined as shown in Table 14 below when the length of the LDPC codeword is 64800, the modulation scheme is 16-QAM, and the coding rate is 10/15.

If the length of the LDPC codeword is 64800 and the modulation scheme is 16-QAM and the coding rate is 12/15, the above-mentioned? (J) can be defined as shown in Table 15 below.

The above-mentioned? (J) can be defined as shown in Table 17 below when the length of the LDPC codeword is 64800, the modulation scheme is 64-QAM, and the coding rate is 6/15.

If the length of the LDPC codeword is 64800 and the modulation scheme is 64-QAM and the coding rate is 8/15, the above-mentioned? (J) can be defined as shown in Table 18 below.

The above-mentioned? (J) can be defined as shown in Table 21 when the length of the LDPC codeword is 64800, the modulation scheme is 64-QAM, and the coding rate is 12/15.

On the other hand, the block interleaver writes the plurality of bit groups in a column direction in each of a plurality of columns in a bit group unit, and each row of the plurality of columns in which the plurality of bit groups are written in a bit group unit, So that interleaving can be performed.

Here, the block interleaver sequentially writes at least a part of bit groups writable in units of a bit group into each of the plurality of columns among the plurality of bit groups, in each of the plurality of columns, At least some of the bit groups are written in units of bit groups, and the remaining bit groups are divided and written in the remaining area.

Meanwhile, an interleaving method according to an embodiment of the present invention includes generating an LDPC codeword by performing LDPC coding based on a parity check matrix, interleaving the LDPC codeword, and modulating the interleaved LDPC codeword And mapping the bits included in the predetermined bit group among the plurality of bit groups constituting the LDPC codeword to predetermined bits in the modulation symbol.

Here, each of the plurality of groups consists of M bits, M is a common divisor of N _ldpc and K _ldpc , and Q _ldpc = (N _{ldpc -} K _ldpc ) / M can be determined. In this case, Q _ldpc is the cyclic shift parameter value for the columns in the column group of the information word _sub- matrix constituting the parity check matrix, N _ldpc is the length of the LDPC codeword, and K _ldpc is the length of the LDPC codeword Is the length of the information bits.

The interleaving may include interleaving parity bits constituting the LDPC codeword, separating the parity interleaved LDPC codeword into the plurality of bit groups, rearranging the order of the plurality of bit groups into groups, And interleaving the plurality of bit groups in which the order is rearranged.

Here, the rearranging may reorder the order of the plurality of bit groups on a bit group basis based on Equation (21).

In this case, the? (J) may be determined based on at least one of the length of the LDPC codeword, the modulation scheme, and the coding rate.

If the length of the LDPC codeword is 64800 and the modulation scheme is 16-QAM and the coding rate is 6/15, the above-mentioned? (J) can be defined as shown in Table 11 below.

The above-mentioned? (J) can be defined as shown in Table 14 below when the length of the LDPC codeword is 64800, the modulation scheme is 16-QAM, and the coding rate is 10/15.

If the length of the LDPC codeword is 64800 and the modulation scheme is 16-QAM and the coding rate is 12/15, the above-mentioned? (J) can be defined as shown in Table 15 below.

The above-mentioned? (J) can be defined as shown in Table 17 below when the length of the LDPC codeword is 64800, the modulation scheme is 64-QAM, and the coding rate is 6/15.

If the length of the LDPC codeword is 64800 and the modulation scheme is 64-QAM and the coding rate is 8/15, the above-mentioned? (J) can be defined as shown in Table 18 below.

The above-mentioned? (J) can be defined as shown in Table 21 when the length of the LDPC codeword is 64800, the modulation scheme is 64-QAM, and the coding rate is 12/15.

The interleaving of the plurality of bit groups may include writing the plurality of bit groups in a column direction to each of the plurality of columns in a bit group unit, The interleaving can be performed by reading the row in the row direction.

The step of interleaving the plurality of bit groups sequentially writes at least a part of bit groups writable in units of a bit group into each of the plurality of columns in each of the plurality of bit groups sequentially in each of the plurality of columns, In each of the plurality of columns, the at least some bit groups are written in units of bit groups, and the remaining bit groups are divided and written in the remaining region.

According to various embodiments of the present invention, it is possible to provide better decoding and reception performance.

1 is a block diagram illustrating a configuration of a transmitting apparatus according to an embodiment of the present invention;
FIGS. 2 to 4 are views for explaining the structure of a parity check matrix according to various embodiments of the present invention,
5 is a block diagram illustrating a configuration of an interleaver according to an embodiment of the present invention.
6 to 8 are views for explaining an interleaving method according to an embodiment of the present invention,
9 to 14 are diagrams for explaining an interleaving operation of a block interleaver according to an embodiment of the present invention,
15 is a diagram for explaining an operation of a demultiplexer according to an embodiment of the present invention;
16 and 17 are diagrams for explaining a method of designing an interleaving pattern according to an embodiment of the present invention;
18 is a block diagram illustrating a configuration of a receiving apparatus according to an embodiment of the present invention;
FIG. 19 is a block diagram illustrating a configuration of a deinterleaver according to an embodiment of the present invention. FIG.
20 is a diagram for explaining a deinterleaving operation of a block deinterleaver according to an embodiment of the present invention, and
21 is a flowchart illustrating an interleaving method according to an embodiment of the present invention.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

1 is a block diagram illustrating a configuration of a transmitting apparatus according to an embodiment of the present invention. Referring to FIG. 1, a transmitting apparatus 100 includes an encoding unit 110, an interleaver 120, and a modulating unit 130 (or a constellation mapper).

The encoding unit 110 performs Low Density Parity Check (LDPC) encoding based on a parity check matrix (PCM) to generate an LDPC codeword. To this end, the encoding unit 110 may include an LDPC encoder (not shown) for performing LPDC encoding.

Specifically, the encoding unit 110 may perform LDPC encoding of input bits with information bits to generate an LDPC codeword composed of information bits and parity bits (i.e., LDPC parity bits) . In this case, since the LPDC code is a systematic code, information bits can be directly included in the LDPC codeword.

Here, the LDPC codeword is composed of information word bits and parity bits. For example, it consists LDPC codeword is N _ldpc bits and may comprise K _ldpc of bits comprising information bits and _parity N = N -K _{ldpc ldpc} parity bits consisting of bits.

In this case, the encoding unit 110 can generate LDPC codewords by performing LDPC encoding based on the parity check matrix. That is, the process for performing LDPC encoding is in terms of generating the LDPC codeword to satisfy the H and C ^T = 0, the encoding unit 110 may be used when LDPC encoding parity check matrix. Here, H denotes a parity check matrix, and C denotes an LDPC codeword.

To this end, the transmitting apparatus 100 may have a separate memory and store various types of parity check matrices.

For example, the transmitting apparatus 100 may be a DVB-C2 (Digital Video Broadcasting-Cable version 2), a DVB-S2 (Digital Video Broadcasting-Satellite-Second Generation) Or a parity check matrix defined in the ATSC (Advanced Television Systems Committee) 3.0 standard, which is currently being standardized, may be stored in the parity check matrix. However, this is only an example, and the transmitting apparatus 100 may store various types of parity check matrices in addition to the above.

Hereinafter, a structure of a parity check matrix according to various embodiments of the present invention will be described with reference to the accompanying drawings. In the parity check matrix below, the element excluding 1 is 0.

For example, the parity check matrix according to an embodiment of the present invention may have a structure as shown in FIG.

Referring to FIG. 2, the parity check matrix 200 includes an information word partial matrix 210, which is a partial matrix corresponding to information word bits, and a parity partial matrix 220, which is a partial matrix corresponding to parity bits.

The information word _sub- matrix 210 includes K _ldpc columns and the parity submatrix 220 includes N _parity = N _ldpc- K _ldpc columns. On the other hand, the number of rows of the parity check matrix 200 is equal to the number of columns N _parity = N _ldpc- K _ldpc of the parity partial matrix 220.

In the parity check matrix 200, N _ldpc denotes the length of the LDPC codeword, K _ldpc denotes the length of the information bits, and N _parity = N _ldpc -K _ldpc denotes the length of the parity bits. Here, the length of the LDPC codeword, information word bits, and parity bits means the number of bits included in each of the LDPC codeword, information word bits, and parity bits.

Hereinafter, the structure of the information word partial matrix 210 and the parity partial matrix 220 will be described.

The information word submatrix 210 is a matrix including K _ldpc columns (i.e., the 0th column to the K _ldpc -1 th column), and follows the following rules.

First, the K _ldpc columns constituting the information word submatrix 210 belong to the same M groups, and are divided into a total of K _ldpc / M column groups. The columns belonging to the same column group have cyclic shift by Q _ldpc . That is, Q _ldpc can be regarded as a cyclic shift parameter value for the columns in the column group of the information word _sub- matrix constituting the parity check matrix.

Here, M is the interval at which the pattern of the column is repeated in the information word _sub- matrix 210 (for example, M = 360), and Q _ldpc is the size at which each column is _cyclically shifted in the information word _sub- M is a common divisor of N _ldpc and K _ldpc , and Q _ldpc = (N _ldpc -K _ldpc ) / M is determined. Here, M and Q _ldpc are integers, and K _ldpc / M is an integer. Meanwhile, M and Q _ldpc can have various values according to the length of the LDPC codeword and the code rate.

For example, M = 360, and if the case of the LDPC codeword length N _ldpc is 64800 Q _ldpc is defined as shown in Table 1 below, M = 360 and the LDPC codeword length N _ldpc is 16200 to the Q _ldpc As shown in Table 2 below.

이라 하면, i 번째 열 그룹 내의 j 번째 열에서 k 번째 1이 위치한 행의 인덱스

는 하기의 수학식 1과 같이 결정된다.Second, the degree of the 0th column of the i-th (i = 0,1, .., K _ldpc / M-1) column group (where the degree is the number of 1 values existing in the column, (Or the index of all the rows belonging to is the same) is _denoted by D _i , and the position (or index) of each row having 1 in the 0th column of the i-th column group is

, The index of the row where the kth 1 is located in the jth column in the ith column group

Is determined according to the following equation (1).

Here, k = 0,1,2, ..., D _i -1, i = 0,1, ..., K _ldpc / M-1, j = 1,2, ..., M-1.

Equation (1) can be expressed equally as Equation (2) below.

Here, k = 0,1,2, ..., D _i -1, i = 0,1, ..., K _ldpc / M-1, j = 1,2, ..., M-1. Here, since j = 1, 2, ..., M-1, (j mod M) in Equation 2 can be seen as j.

는 i 번째 열 그룹 내의 j 번째 열에서 k 번째 1이 위치한 행의 인덱스, N_ldpc는 LDPC 부호어의 길이, K_ldpc는 정보어 비트들의 길이, D_i는 i 번째 열 그룹에 속하는 열들의 차수, M은 하나의 열 그룹에 속하는 열의 개수, Q_ldpc는 각 열이 시클릭 쉬프트되는 크기를 의미한다.In these equations,

The i index of the row to the j-th in the second column k 1 is located in the second column group, N _ldpc is the LDPC codeword length, K _ldpc is the length of the information bits, D _i is the order of the columns belonging to an i th column group, M is the number of columns belonging to one column group, and Q _ldpc is the size by which each column is _cyclically shifted.

값만을 알면 i 번째 열 그룹 내의 j 번째 열에서 k 번째 1이 있는 행의 인덱스

를 알 수 있게 된다. 그러므로, 각각의 열 그룹 내의 0 번째 열에서 k 번째 1이 있는 행의 인덱스 값을 저장하면, 도 2의 구조를 갖는 패리티 검사 행렬(200)(즉, 패리티 검사 행렬(200)의 정보어 부분 행렬(210))에서 1이 있는 열과 행의 위치가 파악될 수 있다.As a result, referring to these equations

If the value is known only, the index of the row having the kth 1 in the jth column in the ith column group

. Therefore, if the index value of the row having the kth 1 in the 0th column in each column group is stored, the parity check matrix 200 having the structure of FIG. 2 (i.e., the information word partial matrix of the parity check matrix 200) (210), the positions of columns and rows in which 1 is found can be grasped.

According to the above rules, the orders of the columns belonging to the ith column group are all the same as D _i . Accordingly, an LDPC code storing information on a parity check matrix according to the above rules can be briefly expressed as follows.

For example, when N _ldpc is 30, K _ldpc is 15, and Q _ldpc is 3, the position information of the row where the 1 is located in the 0th column of the 3 column groups can be expressed by the following mathematical formulas , Which may be referred to as a " weight-1 position sequence ".

는 i 번째 열 그룹 내의 j 번째 열에서 k 번째 1이 있는 행의 인덱스를 의미한다.From here,

Denotes an index of a row having a kth 1 in the jth column in the ith column group.

The weight-1 position sequences such as Equation (3) representing the index of the row where 1 is located in the 0th column of each column group can be expressed more simply as shown in Table 3 below.

Table 3 shows the position of an element having a value of 1 in the parity check matrix. The i-th weight-1 position sequence is represented by indexes of a row having a 1 in the 0-th column belonging to the i-th column group.

The information word sub-matrix 210 of the parity check matrix according to an embodiment of the present invention may be defined by the following Tables 4 to 8 based on the above description.

Specifically, Tables 4 to 8 show indexes of a row in which 1 is located in the 0th column of the i-th column group of the information word submatrix 210. [ That is, the information word sub-matrix 210 is composed of a plurality of column groups each including M columns, and the position of 1 in the 0th column of each of the plurality of column groups can be defined by Tables 4 to 8 .

Here, the indexes of the row where 1 is located in the 0th column of the i-th column group means "addresses of parity bit accumulators". In the meantime, the "addresses of parity bit accumulators" have the same meanings as those defined in the DVB-C2 / S2 / T2 standard or the ATSC 3.0 standard currently being established.

For example, when the length N _ldpc of the LDPC codeword is 64800, the coding rate is 6/15, and M is 360, the indexes of the row where 1 is located in the 0th column of the i-th column group of the information word submatrix 210 As shown in Table 4 below.

As another example, when the length N _ldpc of the LDPC codeword is 64800, the code rate is 8/15, and M is 360, the indexes of the row where 1 is located in the 0th column of the i-th column group of the information word submatrix 210 As shown in Table 5 below.

As another example, when the length N _ldpc of the LDPC codeword is 64800, the coding rate is 10/15, and M is 360, the indexes of the row where 1 is located in the 0th column of the i-th column group of the information word submatrix 210 As shown in Table 6 below.

As another example, when the length N _ldpc of the LDPC codeword is 64800, the coding rate is 10/15, and M is 360, the indexes of the row where 1 is located in the 0th column of the i-th column group of the information word submatrix 210 As shown in Table 7 below.

As another example, when the length N _ldpc of the LDPC codeword is 64800, the code rate is 12/15, and M is 360, the indexes of the row where 1 is located in the 0th column of the i-th column group of the information word submatrix 210 Table 8 shows the results.

In the above example, the case where the length of the LDPC codeword is 64,800 and the coding rate is 6/15, 8/15, 10/15, 12/15 is described. However, this is only an example, and the length of the LDPC codeword is The position of 1 in the information word sub-matrix 210 can be variously defined.

In the above Tables 4 to 8, even though the order of the numbers in the sequence corresponding to each i-th column group is changed, the sequence numbers of the columns corresponding to the i-th column group in Tables 4 to 8 May be an example of codes considered in the present invention.

In addition, even if the order of the sequences corresponding to each column group is changed in Tables 4 to 8, the logarithmic characteristics such as the cycle characteristics and the order distributions on the graph of the sign do not change, An example of a change is an example.

In addition, since the algebraic properties such as the cycle characteristic and the order distribution on the graph of the sign do not change as a result of adding a multiple of Q _ldpc to all the sequences corresponding to arbitrary column groups in Tables 4 to 8, The results obtained by adding a multiple of Q _ldpc to all of the sequences shown in Table 8 may be one example. Note that if a value is greater than (N _ldpc -K _ldpc ) by a factor of Q _ldpc times the given sequence, then the modulo operation (N _ldpc -K _ldpc ) To the value applied.

On the other hand, if the position of the row in which the 1 exists in the 0th column of the i-th column group of the information word sub-matrix 210 is defined as shown in Tables 4 to 8, it is _cyclically shifted by Q _ldpc , The position of the row where a 1 exists in the column can be defined.

For example, in the case of Table 4, in the case of the 0th column of the 0th column group of the information word partial matrix 210, 1 exists in the 1606th row, the 3402th row, the 4961th row,.

In this case, the index of the row where 1 is located in the first column of the 0th column group is 1714 (= 1606 + 108) because Q _ldpc = (N _ldpc -K _ldpc ) / M = (64800-25920) , 3510 (= 3402 + 108), 5069 (= 4961 + 108), ... and the index of the row where 1 is located in the second column of the 0th column group is 1822 (= 1714 + 108), 3618 +108), 5177 (= 5069 + 108), ....

By such a method, an index of a row in which 1 is located in every row of each column group can be defined.

In the parity check matrix 200 shown in FIG. 2, the parity partial matrix 220 may be defined as follows.

The parity partial matrix 220 is a partial matrix including N _ldpc- K _ldpc columns (i.e., K _ldpc th column to N _ldpc -1 th column), and has a dual diagonal or staircase structure. Therefore, the order of the remaining columns excluding the last column (i.e., N _ldpc- 1) in the parity part matrix 220 is 2, and the order of the last column is 1. [

As a result, the information word partial matrix 210 in the parity check matrix 200 is defined by Tables 4 to 8, and the parity partial matrix 220 may have a double diagonal structure.

2 is permutated based on the following equations (4) and (5), the parity check matrix 200 shown in FIG. 2 corresponds to the parity check matrix shown in FIG. 3 May be expressed in the form of a parity check matrix 300 shown in FIG.

A method of performing permutation based on Equation (4) and Equation (5) is as follows. Here, the low permutation and the column permutation are applied to the same principle. Hereinafter, the low permutation will be described as an example.

In the case of the low permutation, i, j satisfying X = Q _ldpc x i + j for the X th row is calculated, and the calculated i, j is substituted into M x j + i, so that the X th row is permutated Thereby generating a row. For example, in the case of the seventh row, since i and j satisfying 7 = 2 x i + j are 3,1, respectively, the seventh row is permutated to 10 x 1 + 3 = thirteenth row.

When the low permutation and the column permutation are performed in this manner, the parity check matrix of FIG. 2 can be expressed as shown in FIG.

Referring to FIG. 3, the parity check matrix 300 includes a parity check matrix 300 divided into a plurality of partial blocks, and a quasi-cyclic (M × M) Matrix.

Accordingly, the parity check matrix 300 having the structure as shown in FIG. 3 is configured in matrix units of M × M size. That is, the parity check matrix 300 is constructed by arranging partial matrices having M × M sizes in a plurality of partial blocks.

As described above, since the parity check matrix 300 is composed of M × M sub-matrixes, it is possible to designate M columns as a column-block and M rows as a row-block have. Thus, parity check matrix 300 has a structure as shown in FIG. 3 used in the present invention is N _{qc _ column} = N _ldpc / M column blocks and N _{qc _ row} = N _parity / M of which consists of a block of lines .

Hereinafter, a partial matrix having an M × M size will be described.

First, the 0-th line block _{(qc _} N _column -1) th column block A (330) is in the form of equation (6) below.

As described above, the A 330 is an M × M matrix, and the values of the 0th row and the (M-1) th column are both '0' 1) th row is '1' and all other values are '0'.

Second, in the parity part matrix _{(320) 0≤i≤ (N ldpc -K} ldpc) with respect to _{/ M-1 (K ldpc /} M + i) i -th row block of the first column block is a unit matrix I _{M × M} ( 340). Further, in _{0≤i≤ (N ldpc -K ldpc) /} M-2 with respect to the (K _ldpc / M + i) th column of the block (i + 1) th row block is an identity matrix I _{M × M} (340) .

또는, 순환 행렬 P가 시클릭 쉬프트된 행렬

이 합해진 형태(또는, 중첩된 형태)가 될 수 있다. Third, the block 350 composing the information word partial matrix 310 is a block in which the circulating matrix P is a cyclic shifted form

Alternatively, if the cyclic matrix P is a cyclic shifted matrix

(Or a superimposed form).

For example, when the superscript a _ij of the circulation matrix P is 1 (i.e., P ¹ ), the form of the block P 350 can be expressed as shown in Equation (7).

The circulating matrix P is a square matrix having an M × M size, and the circulating matrix P represents a matrix in which the weight of each of the M rows is 1 and the weight of each of the M columns is also 1. Then, the circulation matrix P represents the unit matrix I _{M × M} when the superscript a _ij is 0, that is, P ⁰ . And, for convenience in the notation, P ^∞ defines a zero matrix when the superscript a _ij is ∞.

In FIG. 3, a partial matrix existing at the intersection of the i-th row block and the j-th column block of the parity check matrix 300 may be. Thus, i and j represent the number of row blocks and column blocks of partial blocks corresponding to the information word portion. Thus, parity check matrix 300 is the total number of columns N _ldpc = M × N _{_ qc column,} the number of the entire line is the _parity N = M × N _{_ qc row.} That is, the parity check matrix 300 is composed of N _{_ qc column} of "column block" and N _{qc_row} of "line block".

Hereinafter, a method of performing LDPC encoding based on the parity check matrix 200 as shown in FIG. 2 will be described. Meanwhile, for convenience of description, the LDPC encoding process will be schematically described as an example in which the parity check matrix 200 is defined as shown in Table 4. [

라 하고, 길이가 N_ldpc-K_ldpc인 패리티 비트들을

라 할 때, 하기와 같은 과정에 의해 LDPC 부호화가 수행될 수 있다.First, information bits having a length of K _ldpc

And parity bits whose length is N _ldpc- K _ldpc

, LDPC encoding can be performed by the following process.

Step 1) Initialize parity bits to '0'. In other words,

Step 2) The 0th information bit bit i ₀ is accumulated in the parity bit having the address of the parity bit defined in the first row of Table 4 (i.e., the row with i = 0) as an index of the parity bit. This can be expressed as Equation (8) below.

는 바이너리 연산을 의미한다. 바이너리 연산에 의하면, 1

1은 0, 1

0은 1, 0

1은 1, 0

0은 0이다.Here, i ₀ is a 0th information bit, p _i is an i-th parity bit,

Means a binary operation. According to the binary operation, 1

1 is 0, 1

0 is 1, 0

1 is 1, 0

0 is zero.

Step 3) The remaining 359 information bits i _m (m = 1, 2, ..., 359) are accumulated in the parity bits. Herein, the remaining information bits may be information word bits belonging to the same column group as i ₀ . At this time, the address of the parity bit can be determined based on the following equation (9).

Here, x is an address of a parity bit accumulator corresponding to the information word bit i ₀ , Q _ldpc is a size in which each column is _cyclically shifted in a partial matrix corresponding to an information word, In case 108 can be. And, since m = 1, 2, ..., 359, (m mod 360) in the equation (9) can be seen as m.

As a result, each of the information bits _m (m = 1, 2, ..., 359) is accumulated in each parity bit having the index of the parity bit calculated based on Equation (9) An operation such as Equation (10) below can be performed on the bit i ₁ .

는 바이너리 연산을 의미한다. 바이너리 연산에 의하면, 1

1은 0, 1

0은 1, 0

1은 1, 0

0은 0이다.Here, i ₁ is a first information word bit, p _i is an i-th parity bit,

Means a binary operation. According to the binary operation, 1

1 is 0, 1

0 is 1, 0

1 is 1, 0

0 is zero.

Step 4) The 360th information word bit i ₃₆₀ is accumulated in the parity bit having the address of the parity bit defined in the second row (i.e., the row with i = 1) of Table 4 as an index of the parity bit.

Step 5) The remaining 359 information bits belonging to the same group as information bit i ₃₆₀ are accumulated in parity bits. At this time, the address of the parity bit may be determined based on Equation (9). However, in this case, x is the address of the parity bit accumulator corresponding to information bit i ₃₆₀ .

Step 6) Repeat steps 4 and 5 for all the column groups in Table 4 above.

Step 7) Finally, the parity bit p _i is calculated based on the following expression (11). At this time, i is initialized to 1.

는 바이너리 연산을 의미한다.In Equation (11), p _i is an i-th parity bit, N _ldpc is a length of an LDPC codeword, K _ldpc is a length of an information word in an LDPC codeword,

Means a binary operation.

As a result, the encoding unit 110 can calculate the parity bits according to the above-described method.

As another example, the parity check matrix according to an embodiment of the present invention may have a structure as shown in FIG.

Referring to FIG. 4, the parity check matrix 400 may be composed of five matrices A, B, C, Z, and D. In order to describe the structure of the parity check matrix 400, Will be described.

First, the parameter values M ₁ , M ₂ , Q ₁ , and Q ₂ associated with the parity check matrix 400 as shown in FIG. 4 can be defined as shown in Table 9 according to the length and coding rate of the LDPC codeword.

On the other hand, the matrix A is composed of K rows and g rows, and the matrix C is composed of K + g rows and N-K-g rows. Where K is the length of the information bits and N is the length of the LDPC codeword.

The indices of the rows in which the 1s in the 0th column of the i-th column group in the matrix A and the matrix C are located can be defined based on Table 10 below according to the length of the LDPC codeword and the coding rate. In this case, the interval at which the pattern of the column is repeated in the matrix A and the matrix C, that is, the number of columns belonging to the same group, can be 360. [

For example, when the length N of the LDPC codeword is 64800 and the coding rate is 6/15, the indexes of the row where the matrix A and the 0th column of the i th column group of the matrix C are located are shown in Table 10 below.

In the above example, only the case where the length of the LDPC codeword is 64800 and the coding rate is 6/15 has been described. However, this is merely an example, and even when the length of the LDPC codeword is 16200 or another code rate, The indexes of the rows where A and 1 in the 0th column of the i-th column group of the matrix C are defined can be variously defined.

Hereinafter, the positions of the rows in which the matrix A and the matrix C have 1s will be described in detail with reference to Table 10 as an example.

Referring to Table 9, since the length N of the LDPC codeword is 64800 and the coding rate is 6/15 in Table 10, M ₁ = 1080 and M ₂ = 37800 in the parity check matrix 400 defined by Table 10, Q ₁ = 3, and Q ₂ = 105.

Here, Q ₁ is the size in which the columns belonging to the same column group are cyclically shifted in the matrix A, and Q ₂ is the size in which the columns belonging to the same column group in the matrix C are cyclically shifted.

And L is the number of repeating patterns of the columns A and C, which is 360, for example, at a repetition interval of Q ₁ = M ₁ / L, Q ₂ = M ₂ / L, M ₁ = g and M ₂ = NKg .

On the other hand, the index of a row in which 1 is located in each of the matrices A and C can be determined based on the value of M ₁ .

For example, in the case of Table 10, M ₁ = in that it is 1080, the position of the line 1 are present in the 0 th column in i th column groups in the matrix A is determined based on the smaller values than 1080 in index values in Table 10 And the position of a row in which 1 is present in the 0th column of the i-th column group in the matrix C can be determined based on values of 1080 or more among the index values in Table 10. [

Specifically, the sequence corresponding to the 0th column group in Table 10 is "71, 276, 856, 6867, 12964, 17373, 18159, 26420, 28460, 28477". Therefore, in the 0th column of the 0th column group of the matrix A, 1 can be located in the 71st row, the 276th row and the 856th row, and in the 0th column of the matrix C, 6867th row , 12964th row, 17373th row, 18159th row, 26420th row, 28460th row, and 28477th row, respectively.

On the other hand, in the case of the matrix A, if the position of 1 in the 0th column of each column group is defined, the position of the row in which 1 exists in the other columns of each column group can be defined by Q ₁ , , If the position of 1 in the 0th column of each column group is defined, it can be cyclically shifted by Q ₂ to define the position of the row in which 1 exists in the other columns of each column group.

In the above example, in the 0th column of the 0th column group of the matrix A, 1 exists in the 71st row, 276th row, and 856th row. In this case, since Q ₁ = 3, the index of the row where 1 is located in the first column of the 0th column group is 74 (= 71 + 3), 279 (= 276 + 3), 859 (= 856 + 3) The index of the row in which the 1 is located in the second column of the 0th column group may be 77 (= 74 + 3), 282 (= 279 + 3), and 862 (= 859 + 3).

On the other hand, in the 0th column of the 0th column group of the matrix C, 1 exists in the 6867th row, 12964th row, 17373th row, 18159th row, 26420th row, 28460th row and 28477th row. In this case, since Q ₂ = 105, the index of the row in which 1 is located in the first column of the 0th column group is 6972 (= 6867 + 105), 13069 (= 12964 + 105), 17478 (= 17373 + 105) The index of the row in which the 1 is located in the second column of the 0th column group is 7077 (= 18159 + 105), 26525 (= 26420 + 105), 28565 (= 28460 + 105), 28582 = 6972 + 105), 13174 (= 13069 + 105), 17583 (= 17478 + 105), 18369 (= 18264 + 105), 26630 (= 26525 + 105), 28670 +105). ≪ / RTI >

According to this method, the positions of the rows in which 1 exists in all the column groups of the matrix A and the matrix C can be defined.

On the other hand, the matrix B has a double diagonal structure, the matrix D has a diagonal structure (i.e., the matrix D becomes an identity matrix), and the matrix Z can be a zero matrix.

As a result, the structure of the parity check matrix 400 shown in FIG. 4 can be defined by the matrices A, B, C, D, and Z having the above-described structure.

Hereinafter, a method of performing LDPC encoding based on the parity check matrix 400 as shown in FIG. 4 will be described. Meanwhile, for convenience of description, the LDPC encoding process will be schematically described as an example in which the parity check matrix 400 is defined as shown in Table 10. [

)를 포함하는 LDPC 부호어 Λ=(λ₀,λ₁,...,λ_N-1)=(s₀,s₁,...,S_K-1,p₀,p₁,...,

)가 생성될 수 있다.For example, in LDPC coding the information word block S = (s ₀ , s ₁ , ..., S _{K -1} ), the parity bit P = (p ₀ , p ₁ ,

) LDPC codeword _{Λ = (λ 0, λ 1} , ..., λ N-1) = (s 0, s 1, ..., S K-1, p 0, p 1, comprising a. .,

May be generated.

Here, each of M ₁ and M ₂ represents the size of each of the matrix B having the diagonal diagonal structure and the matrix C having the diagonal structure, and M ₁ = g and M ₂ = NKg.

Meanwhile, the process of calculating the parity bit can be expressed as follows. Hereinafter, for convenience of explanation, a case where the parity check matrix 400 is defined as shown in Table 10 will be described as an example.

Is initialized to the step _{1) λ i = s i (} i = 0,1, ..., K-1), p j = 0 (j = 0,1, ..., M 1 + M 2 -1) .

Step 2) The 0th information bit? ₀ is accumulated in the address of the parity bit defined in the first row of Table 10 (i.e., the row with i = 0). This can be expressed as Equation (12) below.

Step 3) For the next L-1 information bits? _M (m = 1,2, ..., L-1),? _M is accumulated in the parity bit address calculated based on Equation (13) do.

Here, x is the address of the parity bit accumulator corresponding to the 0th information bit? 0.

Q ₁ = M ₁ / L and Q ₂ = M ₂ / L. In Table 10, M ₁ = 1080, M ₂ = 37800, Q ₁ = 3, Q ₂ = 105, and L = ₂ are used as the LDPC codeword length N is 64800 and the coding rate is 6/15. 360.

Accordingly, an operation such as Equation (14) below can be performed on the first information bit? ₁ .

Step 4) Similar to the above-described method, in that the address of the parity bit such as the second row of Table 10 (i.e., the row of i = 1) is given to the _Lth information bit? _L , The address of the parity bit for one information bit? _M (m = L + 1, L + 2, ..., 2L-1) is calculated based on Expression (13). In this case, x is the address of the parity bit accumulator corresponding to the information bit? _L , and can be obtained based on the second row of Table 10.

Step 5) For the L new information bits of each group, the above-described process is repeated with the new rows of Table 10 as the address of the parity bit accumulator.

Step 6) After the above _- described processes are repeated from the codeword bits? ₀ to? _K-1 , the values for the following Expression (15) are sequentially calculated from i = 1.

까지를 하기의 수학식 16에 기초하여 산출한다. Step 7) From the parity bit < RTI ID = 0.0 > _K < / _{RTI &}

Is calculated based on the following expression (16).

까지에 대한 패리티 비트 누적기의 어드레스는 표 10 및 수학식 13에 기초하여 산출한다. Step 8) from a new L-bit codeword for each group λ _K

Is calculated based on Table 10 and Equation (13).

까지 적용된 이후, 대각 구조를 갖는 행렬 C에 대응되는 패리티 비트

부터

까지를 하기의 수학식 17에 기초하여 산출한다. Steps from 9) codeword bit λ _K

The parity bits corresponding to the matrix C having the diagonal structure

from

Is calculated based on the following expression (17).

As a result, the parity bits can be calculated according to this method.

Returning to FIG. 1, the encoding unit 110 may encode 3/15, 4/15, 5/15, 6/15, 7/15, 8/15, 9/15, 10/15, 11/15, 12/15 , 13/15, and so on. The encoding unit 110 may generate LDPC codewords having various lengths such as 16200 and 64800 based on the length of the information word bits and the code rate.

In this case, the encoding unit 110 can perform LDPC encoding using the parity check matrix, and the specific structure of the parity check matrix has been described above with reference to FIG. 2 to FIG.

In addition, the encoding unit 110 may perform BCH (Bose, Chaudhuri, Hocquenghem) encoding as well as LDPC encoding. For this, the encoding unit 110 may further include a BCH encoder (not shown) for performing BCH encoding.

In this case, the encoding unit 110 can perform encoding in the order of BCH encoding and LDPC encoding. Specifically, the encoding unit 110 performs BCH encoding on the input bits to add a BCH parity bit, performs LDPC encoding on the bits to which the BCH parity bit is added, as information bits, and generates an LDPC codeword You may.

The interleaver 120 interleaves the LDPC codeword. That is, the interleaver 120 receives the LDPC codeword from the encoding unit 110 and interleaves the LDPC codeword based on various interleaving rules.

In particular, the interleaver 120 may be configured so that the bits included in the predetermined bit group among the plurality of bit groups (or the plurality of groups or the plurality of blocks) constituting the LDPC codeword are mapped to predetermined bits in the modulation symbol, Words can be interleaved. Accordingly, the modulator 130 can map the bits included in the predetermined bit group among the plurality of bit groups constituting the LDPC codeword to predetermined bits in the modulation symbol.

5, the interleaver 120 includes a parity interleaver 121, a group interleaver (or a group-wise interleaver 122), a group twist interleaver 123, and a block interleaver 124 .

The parity interleaver 121 interleaves the parity bits constituting the LDPC codeword.

Specifically, when the LDPC codeword is generated based on the parity check matrix 200 having the structure as shown in FIG. 2, the parity interleaver 121 interleaves only the parity bits among the LDPC codewords using the following equation (18) .

)에 대해 패리티 인터리빙을 수행하여 U=(u₀,u₁,...,

)를 출력할 수 있다.Here, M is the interval at which the pattern of the column is repeated in the information word _sub- matrix 210, that is, the number of columns included in the column group (for example, M = 360), Q _ldpc is the The size of the column is the cyclic shift. That is, the parity interleaver 121 receives the LDPC codeword c = (c ₀ , c ₁ ,

) Are subjected to parity interleaving to obtain U = (u ₀ , u ₁ , ...,

Can be output.

In this manner, the parity-interleaved LDPC codeword can be configured such that a certain number of consecutive bits have similar decoding characteristics (e.g., cycle distribution, degree of column, etc.).

For example, an LDPC codeword may have the same characteristics in consecutive M bits. Here, M may be 360, for example, at a repetition interval of the column pattern in the information word sub-matrix 210. [

Specifically, the product of the LDPC codeword bits and the parity check matrix should be '0'. The sum of the products of the i-th LDPC codeword bit c _i (i = 0,1, ..., N _ldpc -1) from 0 to N _ldpc -1 and the column of the i-th parity check matrix is a '0' . Therefore, the i-th LDPC codeword bit can be regarded as corresponding to the i-th column of the parity check matrix.

In the case of the parity check matrix 200 as shown in FIG. 2, the information word submatrices 210 belong to the same group of M columns, respectively, and have the same characteristics in units of column groups (for example, Has the same degree distribution and the same cycle characteristics).

In this case, since the M consecutive bits in the information word bits correspond to the same column group of the information word sub-matrix 210, the information word bits can be composed of consecutive M bits having the same codeword characteristic . Meanwhile, if the parity bits of the LDPC codeword are interleaved by the parity interleaver 121, the parity bits of the LDPC codeword may be composed of consecutive M bits having the same codeword characteristic.

However, parity interleaving may not be performed on the LDPC codeword coded based on the parity check matrix 300 shown in FIG. 3 and the parity check matrix 400 shown in FIG. 4. In this case, Can be omitted.

The group interleaver 122 divides the parity interleaved LDPC codeword into a plurality of bit groups and rearranges the order of the plurality of bit groups into a bit group unit (bits group wise). That is, the group interleaver 122 can interleave a plurality of bit groups on a bit group basis.

For this purpose, the group interleaver 122 divides the parity-interleaved LDPC codeword into a plurality of bit groups using Equation (19) or (20) below.

는 k/360 이하의 가장 큰 정수를 나타낸다. In these equations, N _group denotes the total number of bit groups, X _j denotes a j-th bit group, and u _k denotes a k-th LDPC codeword bit input to the group interleaver 122. And,

Represents the largest integer of k / 360 or less.

On the other hand, in these equations, 360 represents an example of M, which is an interval in which a column pattern is repeated in an information word partial matrix. In these equations, 360 can be changed to M.

An LDPC codeword divided into a plurality of bit groups can be represented as shown in FIG.

Referring to FIG. 6, the LDPC codeword is divided into a plurality of bit groups, and each bit group is composed of consecutive M bits. Here, when M is 360, each of the plurality of bit groups may be composed of 360 bits. Accordingly, each bit group may be composed of bits corresponding to each column group of the parity check matrix.

Specifically, since the LDPC codeword is divided into M bits, the K _ldpc information bits are divided into (K _ldpc / M) bit groups, and the N _ldpc -K _ldpc parity bits are (N _ldpc -K _ldpc ) / And is divided into M bit groups. Accordingly, the LDPC codeword can be divided into a total of (N _ldpc / M) bit groups. For example, when M = 360 and the length N _ldpc of the LDPC codeword is 16200, the number N _group of groups constituting the LDPC codeword can be 45 (= 16200/360), M = 360 and the LDPC code When the length N _ldpc is 64800, the number N _group of the bit groups constituting the LDPC codeword can be 180 (= 64800/360).

The reason why the group interleaver 122 divides the LDPC codeword into the same bit group by consecutive M bits is because the LDPC coders have the same codeword characteristics in consecutive M bits as described above. Accordingly, when the LDPC codeword is divided into consecutive M bit units, bits having the same codeword characteristics can be included in the same bit group.

In the above example, the number of bits constituting each bit group is M. However, this is merely an example, and the number of bits constituting each bit group can be variously changed.

For example, the number of bits constituting each bit group may be a divisor of M. That is, the number of bits constituting each bit group may be a divisor of the number of columns constituting the column group of the information word partial matrix of the parity check matrix. In this case, each bit group may be composed of a few bits of M. For example, when the number of columns constituting the column group of the information word partial matrix is 360, that is, M = 360, the group interleaver 122 determines whether the number of bits constituting each bit group is 360 , The LDPC codeword can be divided into a plurality of bit groups.

Hereinafter, for convenience of explanation, only the case where the number of bits constituting the bit group is M will be described.

Thereafter, the group interleaver 122 interleaves the LDPC codeword on a bit group basis. Specifically, the group interleaver 122 may group the LDPC codewords into a plurality of bit groups, and rearrange the plurality of bit groups into bit group units. That is, the group interleaver 122 may rearrange the order of the plurality of bit groups constituting the LDPC codeword group by changing positions of the plurality of bit groups constituting the LDPC codeword.

Here, the group interleaver 122 may rearrange the order of the plurality of bit groups so that the bit groups including the bits mapped to the same modulation symbol among the plurality of bit groups are spaced apart by a predetermined interval.

In this case, the group interleaver 122 maps to the same modulation symbol in consideration of the number of rows and columns constituting the block interleaver 124, the number of bit groups constituting the LDPC codeword, the number of bits included in each bit group, The order of the plurality of bit groups may be rearranged on a bit group basis so that the bit groups including the bits to be allocated are spaced apart by a predetermined interval.

For this purpose, the group interleaver 122 can rearrange the order of the plurality of groups into a bit group unit by using the following equation (21).

Here, X _j denotes a j-th bit group before group interleaving, and Y _j denotes a j-th bit group after group interleaving. (J) is a parameter indicating an interleaving sequence and can be determined by at least one of the length of the LDPC codeword, the modulation method, and the coding rate.

Therefore, X _(j) represents the group of (j) th bit before group interleaving, and Equation (21) implies that the group of π (j) bits before interleaving is interleaved into the jth group of bits after interleaving.

Meanwhile, a specific example of π (j) according to an embodiment of the present invention can be defined as Tables 11 to 22 below.

In this case,? (J) is defined according to the length and coding rate of the LDPC codeword, and the parity check matrix is also defined according to the length and coding rate of the LDPC codeword. Therefore, when the LDPC coding is performed based on the specific parity check matrix according to the length and the coding rate of the LDPC codeword, the LDPC codeword is divided into the bit group < RTI ID = 0.0 > / RTI >

For example, when the encoding unit 110 performs LDPC encoding with a coding rate of 6/15 to generate an LDPC codeword having a length of 64,800, the group interleaver 122 performs the LDPC encoding on the basis of Tables 11 to 22 The interleaving can be performed using? (J) defined by the length of the LDPC codeword of 64800 and the coding rate of 6/15.

For example, if the length of the LDPC codeword is 64800, the coding rate is 6/15, and the modulation scheme is 16-QAM (quadrature amplitude modulation),? (J) can be defined as shown in Table 11 below. In particular, in the case of Table 11, it can be applied when LDPC coding is performed based on the parity check matrix defined by Table 4. [

For Table 11, the expression (21) is _{Y 0 = X π (0)} = X 55, Y 1 = X π (1) = X 146, Y 2 = X π (2) = X 83, ..., Y ₁₇₈ = X ₍₁₇₈₎ = X ₁₃₂ , Y ₁₇₉ = X ₍₁₇₉₎ = X ₁₃₅ . Accordingly, the group interleaver 122 sets the 55th bit group to 0, the 146th bit group to the 1st, the 83rd bit group to the 2nd, ..., the 132nd bit group to the 178th, 135 And the order of the plurality of bit groups can be rearranged on a bit group basis by changing the order of the < RTI ID = 0.0 >

As another example, when the length of the LDPC codeword is 64800, the coding rate is 8/15, and the modulation scheme is 16-QAM,? (J) can be defined as shown in Table 12 below. In particular, in the case of Table 12, it can be applied when LDPC coding is performed based on the parity check matrix defined by Table 5. [

For Table 12, the expression (21) is _{Y 0 = X π (0)} = X 58, Y 1 = X π (1) = X 55, Y 2 = X π (2) = X 111, ..., Y ₁₇₈ = X ₍₁₇₈₎ = X ₁₇₁ , Y ₁₇₉ = X ₍₁₇₉₎ = X ₁₅₅ . Accordingly, the group interleaver 122 sets the 58th bit group to 0, the 55th bit group to the 1st, the 111th bit group to the 2nd, ..., the 171st bit group to the 178th, 155 And the order of the plurality of bit groups can be rearranged on a bit group basis by changing the order of the < RTI ID = 0.0 >

As another example, when the length of the LDPC codeword is 64,800, the coding rate is 10/15, and the modulation scheme is 16-QAM,? (J) can be defined as shown in Table 13 below. In particular, in the case of Table 13, it can be applied when LDPC coding is performed based on the parity check matrix defined by Table 6. [

For Table 13, the expression (21) is _{Y 0 = X π (0)} = X 74, Y 1 = X π (1) = X 53, Y 2 = X π (2) = X 84, ..., Y ₁₇₈ = X ₍₁₇₈₎ = X ₁₅₉ , Y ₁₇₉ = X ₍₁₇₉₎ = X ₁₆₃ . Accordingly, the group interleaver 122 sets the 74th bit group to the 0th, the 53rd bit group to the 1st, the 84th bit group to the 2nd, ..., the 159th bit group to the 178th, 163 And the order of the plurality of bit groups can be rearranged on a bit group basis by changing the order of the < RTI ID = 0.0 >

As another example, when the length of the LDPC codeword is 64800 and the coding rate is 10/15 and the modulation scheme is 16-QAM,? (J) can be defined as shown in Table 14 below. Particularly, in the case of Table 14, it can be applied when LDPC coding is performed based on the parity check matrix defined by Table 7. [

For Table 14, the expression (21) is _{Y 0 = X π (0)} = X 68, Y 1 = X π (1) = X 71, Y 2 = X π (2) = X 54, ..., Y ₁₇₈ = X ₍₁₇₈₎ = X ₁₃₅ , Y ₁₇₉ = X ₍₁₇₉₎ = X ₂₄ . Accordingly, the group interleaver 122 sets the 68th bit group to 0, the 71st bit group to the 1st, the 54th bit group to the 2nd, ..., the 135th bit group to the 178th, 24 And the order of the plurality of bit groups can be rearranged on a bit group basis by changing the order of the < RTI ID = 0.0 >

As another example, if the length of the LDPC codeword is 64,800, the coding rate is 12/15, and the modulation scheme is 16-QAM,? (J) can be defined as shown in Table 15 below. Particularly, in the case of Table 15, it can be applied when LDPC coding is performed based on the parity check matrix defined by Table 8. [

For Table 15, the expression (21) is _{Y 0 = X π (0)} = X 120, Y 1 = X π (1) = X 32, Y 2 = X π (2) = X 38, ..., Y ₁₇₈ = X ₍₁₇₈₎ = X ₁₀₁ , Y ₁₇₉ = X ₍₁₇₉₎ = X ₃₉ . Accordingly, the group interleaver 122 sets the 120th bit group to 0, the 32nd bit group to the 1st, the 38th bit group to the 2nd, ..., the 101st bit group to 178th, 39 And the order of the plurality of bit groups can be rearranged on a bit group basis by changing the order of the < RTI ID = 0.0 >

As another example, when the length of the LDPC codeword is 64800 and the coding rate is 6/15 and the modulation scheme is 16-QAM,? (J) can be defined as shown in Table 16 below. Particularly, in case of Table 16, it can be applied when LDPC coding is performed based on the parity check matrix defined by Table 10.

For Table 16, the expression (21) is _{Y 0 = X π (0)} = X 163, Y 1 = X π (1) = X 160, Y 2 = X π (2) = X 138, ..., Y ₁₇₈ = X ₍₁₇₈₎ = X ₁₄₈ , Y ₁₇₉ = X ₍₁₇₉₎ = X ₉₈ . Accordingly, the group interleaver 122 sets the 163rd bit group to the 0th, 160th bit group to the 1st, 138th bit group to the 2nd, ..., 148th bit group to 178th, 98 And the order of the plurality of bit groups can be rearranged on a bit group basis by changing the order of the < RTI ID = 0.0 >

As another example, when the length of the LDPC codeword is 64,800, the coding rate is 6/15, and the modulation scheme is 64-QAM,? (J) can be defined as shown in Table 17 below. Particularly, in the case of Table 17, it can be applied when LDPC coding is performed based on the parity check matrix defined by Table 4. [

For Table 17, the expression (21) is _{Y 0 = X π (0)} = X 29, Y 1 = X π (1) = X 17, Y 2 = X π (2) = X 38, ..., Y ₁₇₈ = X ₍₁₇₈₎ = X ₁₁₇ , Y ₁₇₉ = X ₍₁₇₉₎ = X ₁₅₅ . Accordingly, the group interleaver 122 sets the 29th bit group to 0, the 17th bit group to the 1st, the 38th bit group to the 2nd, ..., the 117th bit group to the 178th, 155 And the order of the plurality of bit groups can be rearranged on a bit group basis by changing the order of the < RTI ID = 0.0 >

As another example, when the length of the LDPC codeword is 64,800, the coding rate is 8/15, and the modulation scheme is 64-QAM,? (J) can be defined as shown in Table 18 below. Particularly, in case of Table 18, it can be applied when LDPC coding is performed based on the parity check matrix defined by Table 5. [

For Table 18, the expression (21) is _{Y 0 = X π (0)} = X 86, Y 1 = X π (1) = X 71, Y 2 = X π (2) = X 51, ..., Y ₁₇₈ = X ₍₁₇₈₎ = X ₁₇₄ , Y ₁₇₉ = X ₍₁₇₉₎ = X ₁₂₈ . Accordingly, the group interleaver 122 sets the 86th group to the 0th, the 71st bit group to the 1st, the 51st bit group to the 2nd, ..., the 174th bit group to the 178th, the 128th The order of the plurality of bit groups can be rearranged in units of bit groups by changing the order of the bit groups to the 179th order.

As another example, when the length of the LDPC codeword is 64800, the coding rate is 10/15, and the modulation scheme is 64-QAM,? (J) can be defined as shown in Table 19 below. Particularly, in the case of Table 19, it can be applied when LDPC coding is performed based on the parity check matrix defined by Table 6. [

For Table 19, the expression (21) is _{Y 0 = X π (0)} = X 73, Y 1 = X π (1) = X 36, Y 2 = X π (2) = X 21, ..., Y ₁₇₈ = X ₍₁₇₈₎ = X ₁₄₉ , Y ₁₇₉ = X ₍₁₇₉₎ = X ₁₃₅ . Accordingly, the group interleaver 122 sets the 73rd bit group to 0, the 36th bit group to the 1st, the 21st bit group to the 2nd, ..., the 149th bit group to the 178th, 135 And the order of the plurality of bit groups can be rearranged on a bit group basis by changing the order of the < RTI ID = 0.0 >

As another example, if the length of the LDPC codeword is 64800, the coding rate is 10/15, and the modulation scheme is 64-QAM,? (J) can be defined as shown in Table 20 below. Particularly, in case of Table 20, it can be applied when LDPC coding is performed based on the parity check matrix defined by Table 7. [

For Table 20, Equation (21) is _{Y 0 = X π (0)} = X 113, Y 1 = X π (1) = X 115, Y 2 = X π (2) = X 47, ..., Y ₁₇₈ = X ₍₁₇₈₎ = X ₁₃₀ , Y ₁₇₉ = X ₍₁₇₉₎ = X ₁₇₆ . Accordingly, the group interleaver 122 sets the 113th bit group to 0, the 115th bit group to the 1st, the 47th bit group to the 2nd, ..., the 130th bit group to 178th, 176 And the order of the plurality of bit groups can be rearranged on a bit group basis by changing the order of the < RTI ID = 0.0 >

As another example, when the length of the LDPC codeword is 64,800, the coding rate is 12/15, and the modulation scheme is 64-QAM,? (J) can be defined as shown in Table 21 below. In particular, in the case of Table 21, it can be applied when LDPC coding is performed based on the parity check matrix defined by Table 8. [

For Table 21, the expression (21) is _{Y 0 = X π (0)} = X 83, Y 1 = X π (1) = X 93, Y 2 = X π (2) = X 94, ..., Y ₁₇₈ = X ₍₁₇₈₎ = X ₂ , Y ₁₇₉ = X ₍₁₇₉₎ = X ₁₄ . Accordingly, the group interleaver 122 sets the 83rd bit group to the 0th, the 93rd bit group to the 1st, the 94th bit group to the 2nd, ..., the 2nd bit group to the 178th, And the order of the plurality of bit groups can be rearranged on a bit group basis by changing the order of the < RTI ID = 0.0 >

As another example, when the length of the LDPC codeword is 64,800 and the coding rate is 6/15 and the modulation scheme is 64-QAM,? (J) can be defined as shown in Table 22 below. In particular, in the case of Table 22, it can be applied when LDPC coding is performed based on the parity check matrix defined by Table 10. [

For Table 22, the expression (21) is _{Y 0 = X π (0)} = X 175, Y 1 = X π (1) = X 177, Y 2 = X π (2) = X 173, ..., Y ₁₇₈ = X ₍₁₇₈₎ = X ₃₁ , Y ₁₇₉ = X ₍₁₇₉₎ = X ₇₂ . Accordingly, the group interleaver 122 sets the 175th bit group to the 0th, the 177th bit group to the 1st, the 173rd bit group to the 2nd, ..., the 31st bit group to the 178th, 72 And the order of the plurality of bit groups can be rearranged on a bit group basis by changing the order of the < RTI ID = 0.0 >

In the above example, only the case where the length of the LDPC codeword is 64800 and the coding rate is 6/15, 8/15, 10/15, and 12/15 has been described. However, this is only an example, 16200 or different code rates, the interleaving pattern can be defined in various ways.

As described above, the group interleaver 12 can rearrange the order of the plurality of bit groups into a bit group unit using Equation (21) and Tables 11 to 22.

In Table 11 to Table 22, "j-th block of Group-wise Interleaver output" denotes a bit group outputted j-th in the interleaver 122 after interleaving, and "π (j) quot; wise interleaver input "indicates a group of bits input to the group interleaver 122 at the < RTI ID = 0.0 >

The groups constituting the LDPC codeword are rearranged in units of bit groups by the group interleaver 122 and then block interleaved by a block interleaver 124 to be described later. j), "Order of bits group to be block interleaved".

According to this scheme, the group interleaved LDPC codeword is shown in FIG. Comparing the LDPC codeword shown in FIG. 7 with the LDPC codeword before the group interleaving shown in FIG. 6, it can be seen that the order of the plurality of bit groups constituting the LDPC codeword is rearranged.

순으로 배치되었다가, 그룹 인터리빙되어 비트 그룹 Y₀, 비트 그룹 Y₁,..., 비트 그룹

순으로 배치될 수 있다. 이 경우, 그룹 인터리빙에 의해 각 비트 그룹들이 배치되는 순서는 표 11 내지 표 22에 기초하여 결정될 수 있다.6 and 7, the LDPC codeword is divided into a bit group X ₀ , a bit group X ₁ ,

And then group interleaved to form a bit group Y ₀ , a bit group Y ₁ , ..., a bit group

. ≪ / RTI > In this case, the order in which the respective bit groups are arranged by the group interleaving can be determined based on Tables 11 to 22.

The group twisted interleaver 123 interleaves the bits in the same bit group. That is, the group twist interleaver 123 may rearrange the order of the bits in the same group by changing the order of the bits existing in the same bit group.

In this case, the group twist interleaver 123 may cyclically shift the bits in the same bit group by a predetermined number of bits, thereby rearranging the order of the bits in the same bit group.

For example, as shown in FIG. 8, the group twist interleaver 123 may cyclically shift the bits included in the bit group Y ₁ by one bit to the right. In this case, a click when the shift to the right by even bit in the group Y ₁ as shown in the 80th, 1st, 2nd, ..., bit was positioned at 358th, 359th bit are 1, when being shifted clicking The 359th preceding bit is located at the foremost position in the bit group Y ₁ and the bits located at the 0th, 1st, 2nd, ..., 358th positions before the cyclic shift are 1 bit As shown in FIG.

In addition, the group twist interleaver 123 may rearrange the order of the bits in each group by cyclically shifting a different number of bits for each bit group.

For example, the group twisted interleaver 123 cyclically shifts the bits included in the bit group Y ₁ by one bit in the right direction and cyclically shifts the bits included in the bit group Y ₂ by three bits in the right direction .

However, the above-described group twist interleaver 123 may be omitted in some cases.

Further, in the above-described example, the group twist interleaver 123 is described as being disposed after the group interleaver 122, but this is also only an example. That is, the group twist interleaver 123 may be arranged before the group interleaver 122 in that it changes the order of the bits constituting the corresponding bit group in the bit group but does not change the order of the bit groups themselves.

The block interleaver 124 interleaves a plurality of ordered groups of bits. Specifically, the block interleaver 124 can interleave a plurality of bit groups in which the order of the bit groups is rearranged by the group interleaver 122, on a bit group basis. Here, the block interleaver 124 is composed of a plurality of columns each including a plurality of rows. The block interleaver 124 classifies a plurality of rearranged bit groups based on the modulation order determined according to the modulation method, can do.

In this case, the block interleaver 124 can interleave a plurality of bit groups in which the order of the bit groups is rearranged by the group interleaver 122, on a bit group basis. More specifically, the block interleaver 124 interleaves the bit groups, part 1) and the second part (part 2) according to the modulation order.

Specifically, the block interleaver 124 divides each of the plurality of columns into a first part and a second part, sequentially writes a plurality of bit groups into a plurality of columns constituting the first part in units of a bit group , Dividing the bits constituting the rest of the bit groups into sub-bit groups each having a predetermined number of bits based on the number of the plurality of columns, dividing the divided sub-bit groups into a plurality of columns constituting the second part So that interleaving can be performed.

Here, the number of groups interleaved on a bit group basis may be determined according to at least one of the number of rows and columns constituting the block interleaver 124, the number of bit groups, and the number of bits included in each bit group. That is, the block interleaver 124 performs interleaving in units of a bit group among a plurality of bit groups considering at least one of the number of rows and columns constituting the block interleaver 124, the number of bit groups, and the number of bits included in each bit group. , Interleaving the corresponding bit group in units of bit groups, and dividing the bits constituting the remaining bit groups into sub-bit groups and interleaving. For example, the block interleaver 124 may interleave at least a part of a plurality of bit groups by a bit group unit using the first part, and may divide and interleave the remaining bit groups using the second part.

On the other hand, being interleaved on a bit group basis means that the bits included in the same bit group are written in the same column. That is, in the case of a bit group interleaved on a bit group basis, the block interleaver 124 writes the bits included in the same bit group into the same column without dividing the bits, and when the bit group is not interleaved on a bit group basis, It is possible to perform interleaving by dividing the bits and writing them in different columns.

Accordingly, the number of rows constituting the first part is a multiple of the number of bits (for example, 360) included in one bit group, and the number of rows constituting the second part is smaller than the number of bits included in one group .

In addition, all the bit groups interleaved by the first part are interleaved with the bits included in the same bit group written in the same column of the first part, and at least one bit group interleaved by the second part constitutes the second part Lt; / RTI > can be divided and written into at least two columns.

Details of this interleaving method will be described later.

Meanwhile, the interleaving performed in the group twisted interleaver 123 changes the order of the bits in the bit group, but does not change the order of the bit groups themselves by interleaving. Therefore, the order of the bit groups to be block interleaved in the block interleaver 124, that is, the order of the bit groups input to the block interleaver 124, can be determined by the group interleaver 122. For example, the order of the bit groups to be block interleaved by the block interleaver 124 may be determined by? (J) defined in Tables 11 to 22.

As described above, the block interleaver 124 can interleave a plurality of ordered bit groups in a bit group unit using a plurality of columns, each of which is a plurality of rows.

In this case, the block interleaver 124 can interleave the LDPC codeword by dividing a plurality of columns into at least two parts. For example, the block interleaver 124 may interleave a plurality of bit groups constituting an LDPC codeword by dividing each of the plurality of columns into a first part and a second part.

In this case, the block interleaver 124 divides each of the plurality of columns into N (N is an integer of 2 or more, depending on whether or not the number of bit groups constituting the LDPC codeword is an integral multiple of the number of columns constituting the block interleaver 124) ) And interleaving can be performed.

First, when the number of bit groups constituting the LDPC codeword is an integral multiple of the number of columns constituting the block interleaver 124, the block interleaver 124 sets each LDPC codeword Can be interleaved on a bit group basis.

Specifically, the block interleaver 124 writes a plurality of bit groups constituting an LDPC codeword in a column direction on a column group basis in a bit group basis, and sets each row of a plurality of columns in which a plurality of bit groups are written on a bit group basis It is possible to perform interleaving by reading in the row direction.

In this case, the block interleaver 124 divides the bits included in the bit group by a quotient obtained by dividing the number of bit groups constituting the LDPC codeword by the number of columns constituting the block interleaver 124, It is possible to perform interleaving by sequentially writing each row in the column direction and reading each row of the plurality of columns in which the bits are written in the row direction.

Hereinafter, for convenience of explanation, the bit group located at the j-th position after being interleaved by the group interleaver 122 is referred to as a bit group Y _j .

For example, it is assumed that the block interleaver 124 is composed of C columns each including R ₁ rows. Then, the LDPC code being configured by N-bit _group of the group eoga, it is assumed to be a multiple of the number of bit _group is a group N C.

In this case, when the number N _group of the bit groups constituting the LDPC codeword is divided by the number C of the columns constituting the block interleaver 124 as A (= N _group / C) (A is an integer larger than 0) The block interleaver 124 can sequentially write the A (= N _group / C) bit groups into each column in the column direction, and read the bits written in each column in the row direction to perform interleaving.

For example, as shown in Figure 9, a block interleaver 124 bit group (Y ₀₎ from the first row of the first column R ₁ th row, the bit group (Y _1), ..., a group (Y _{A 1)} light the bits included in, respectively, the (Y 1 _{a +1} th row from the first row R ₁ bit group (Y _a), the bit group of the second column), ..., bit group (Y _{2A -1)} bit group (Y _{-A CA),} the bit group (Y _{CA -A + 1)} from the light and the bits included in respective, ..., 1-th row of the column C row R ₁ ,. ..., And the bit group Y _{CA -1} , and read the bits written in each row of the plurality of columns in the row direction.

Accordingly, the block interleaver 124 interleaves all the bit groups constituting the LDPC codeword on a bit group basis.

However, if the number of bit groups constituting the LDPC codeword is not an integer multiple of the number of columns constituting the block interleaver 124, the block interleaver 124 divides each of the plurality of columns into two parts and outputs the LDPC codeword And interleaves the bits constituting the remaining bit groups and divides them into sub-bit groups and interleaves the sub-bit groups. In this case, the bits included in the bit groups of the remainder (remainder) when the bits included in the remaining bit groups, that is, the number of groups constituting the LDPC codeword, are divided by the number of columns, are interleaved on a bit group basis But can be interleaved in each column according to the number of columns.

Specifically, the block interleaver 124 may interleave the LDPC codeword by dividing each of the plurality of columns into two parts.

In this case, the block interleaver 124 multiplies the plurality of columns based on the number of columns constituting the block interleaver 124, the number of bit groups constituting the LDPC codeword and the number of bits constituting each of the plurality of bit groups A part and a second part.

Here, each of the plurality of bit groups may be composed of 360 bits. The number of bit groups constituting the LDPC codeword is determined according to the length of the LDPC codeword and the number of bits included in each bit group.

For example, if an LDPC codeword having a length of 16200 is divided into 360 bits, the LDPC codeword is divided into 45 bit groups. The LDPC codeword having a length of 64800 is divided into 360 bits The DPC codeword can be divided into 180 bit groups. In addition, the number of columns constituting the block interleaver 124 can be determined according to a modulation method, and a specific example related thereto will be described later.

Accordingly, the number of rows constituting each of the first and second parts is determined by the number of columns constituting the block interleaver 124, the number of bit groups constituting the LDPC codeword, and the number of bits constituting each of the plurality of bit groups May be determined based on the number.

 Specifically, in the first part, the LDPC codeword is configured according to the number of columns constituting the block interleaver 124, the number of bit groups constituting the LDPC codeword and the number of bits constituting each bit group in each of the plurality of columns The number of bits included in at least one bit group writable in units of bit groups in each of the plurality of columns among the plurality of bit groups to be written.

The second part is composed of a plurality of rows excluding rows corresponding to the number of bits contained in at least a part of bit groups writable in units of bit groups in each of a plurality of columns in each of a plurality of columns . Specifically, the number of rows of the second part may have the same value as the quotient of dividing the number of bits included in all bit groups except the bit group corresponding to the first part by the number of columns constituting the block interleaver 124 have. That is, the number of rows of the second part may have the same value as the quotient of dividing the number of bits included in the remaining bit groups written in the first part of the bit group constituting the LDPC codeword by the number of columns.

On the other hand, the block interleaver 124 divides each of the plurality of columns into a first part including a row as many as the number of bits included in a bit group writable in units of bit groups in each column, and a second part including a remaining row Each of the plurality of columns can be distinguished.

Accordingly, the first part may be composed of a number of bits included in the bit group, that is, an integer multiple of M. However, as described above, since the number of codeword bits constituting each bit group can be a divisor of M, the first part is constituted by a line of an integral multiple of the number of bits constituting each bit group .

In this case, the block interleaver 124 can perform interleaving by writing and reading the LDPC codewords in the first part and the second part in the same manner.

Specifically, the block interleaver 124 writes an LDPC codeword in a column direction in a plurality of columns constituting each of the first and second parts, and generates a plurality of LDPC codewords It is possible to perform the interleaving by reading the row in the row direction.

That is, the block interleaver 124 sequentially writes the bits included in at least a part of the bit groups writable in units of bit groups in each of the plurality of columns sequentially to each of the plurality of columns constituting the first part, The bits included in the remaining bit groups excluding at least some bit groups are divided into a plurality of columns constituting the second part in the column direction and the plurality of columns constituting the first and second parts angles The interleaving can be performed by reading the written bits in the row direction.

In this case, the block interleaver 124 may perform interleaving by dividing the remaining bit groups except for at least some bit groups in the plurality of groups based on the number of columns constituting the block interleaver 124.

Specifically, the block interleaver 124 divides the bits included in the remaining bit groups into a plurality of columns, writes each of the divided bits in a column direction to each of a plurality of columns constituting the second part, A plurality of columns constituting the second part in which the bits are written can be read in the row direction and interleaving can be performed.

That is, the block interleaver 124 determines whether the number of groups constituting the remaining bit group, that is, the group of LDPC codewords, written in the first part of the plurality of bit groups constituting the LDPC codeword is divided by the number of columns, ) Can be divided into the number of columns, and the divided bits can be sequentially written in the column direction in each column of the second part.

For example, it is assumed that the block interleaver 124 is composed of C columns each including R ₁ rows. And being configured LDPC code with N _group of bit groups eoga, is not a multiple of the number of N _group are C of groups of bits, A × C + 1 = is assumed a case where the N _group (A is an integer greater than 0) . That is, when the number of bit groups constituting the LDPC codeword is divided by the number of columns, it is assumed that the quotient is A and the remainder is 1.

In this case, as shown in FIGS. 10 and 11, the block interleaver 124 can divide each column into a first part including R ₁ rows and a second part including R ₂ rows. In this case, R ₁ may be equal to the number of bits included in a bit group that can be written in a bit group unit in each column, and R ₂ may be a value excluding R ₁ from the number of rows constituting each column.

That is, in the above-described example, the number of groups writable in units of bit groups in each column is A, and the first part of each column may be composed of the number of bits included in A groups, that is, A × M rows.

In this case, the block interleaver 124 writes the bits included in the group that can be written in each group into each column, that is, A groups, into the first part of each column in the column direction.

That is, as shown in FIGS. 10 and 11, the block interleaver 124 generates a bit group Y ₀ , a bit group Y ₁ ,..., A bit group Y ₁ , and a bit group Y 2 in the first row to the R ₁ row constituting the first part of the first column. ., groups of bits _{(Y a -1) (Y a} ) and light the bits included in each of the second bit group into a first part from the first row R ₁ column of the second line constituting the bit group (Y _{a 1} ), ..., and a bit group (Y _{2A -1} ) in the first row to the R ₁ -th row constituting the first part of the column C, (Y _{CA -A} ), a bit group (Y _{CA -A + 1} ), ..., and a bit group (Y _{CA -1} ).

As described above, the block interleaver 124 writes the bits included in the bit group writable in bit groups in each column into the first part of each column in a group unit.

That is, in the above example, the bits included in each of the bit group Y ₀ , the bit group Y ₁ , ..., and the bit group Y _{A -1} are all written in the first column without being divided, The bits included in each of the bit group Y _A , the bit group Y _{A +1} , ..., and the bit group Y _{2A -1} are all written in the second column without being divided, The bits included in each of the group (Y _{CA -A} ), the bit group (Y _{CA -A + 1} ), ..., and the bit group (Y _{CA -1} ) can be all written to the column C without being divided. Thus, it can be seen that all the bit groups interleaved by the first part are written in the same column of the first part as the bits included in the same bit group.

Thereafter, the block interleaver 124 divides the bits included in the remaining bit groups except the group written in the first part of each column among the plurality of bit groups, and writes the bits in the column direction to the second part of each column. At this time, the block interleaver 124 divides the bits included in the remaining bit groups except for the group written in the first part of each column into the number of columns so that the same number of bits are written in the second part of each column, The bits can be written in column direction in each column of the second part.

)가 제1 파트에 라이트되지 못하고 남게 된다. 이에 따라, 블록 인터리버(124)는 도 10과 같이 비트 그룹(

)에 포함된 비트들을 C 개로 분할하고, 분할된 각 비트들(즉, 마지막 비트 그룹(

)에 포함된 비트들 C로 나눈 몫만큼의 비트들)을 각 열의 제2 파트에 순차적으로 라이트할 수 있다. In the above example, since A x C + 1 = N _group is satisfied, when the bit groups constituting the LDPC codeword are sequentially written into the first part, the last bit group of the LDPC codeword

) Will not be written to the first part. As a result, the block interleaver 124 performs the bit group < RTI ID = 0.0 >

), And divides each of the divided bits (i.e., the last bit group (

) Of the bits divided by the bits C included in the column) in the second part of each column.

Here, each divided bit based on the number of columns may be referred to as a sub-bit group, in which case each of the sub-bit groups may be written to each column of the second part. That is, the bits included in the bit group can be divided to form a sub bit group.

That is, a block interleaver 124 from the first line to write a bit from the first line constituting the second part of the first column to the R _2-th row, and constituting a second part of the second column R ₂ row , And write the bits from the first row to the R ₂ -th row constituting the second part of the column C of the second column. At this time, the block interleaver 124 can write the bits in the column direction to the second part of each column as shown in FIG.

)은 M 개의 비트들로 구성되므로, 마지막 비트 그룹(

)에 포함된 비트들은 M/C 개씩 분할되어 각 컬럼에 라이트될 수 이다. 즉, 마지막 비트 그룹(

)에 포함된 비트들은 M/C 개씩 분할되고, 분할된 M/C 개씩 서브 비트 그룹을 형성하며, 서브 비트 그룹 각각이 제2 파트의 각 열에 라이트될 수 있다.That is, in the second part, the bits constituting the bit group can be written in a plurality of columns without being written in the same column. That is, in the above example, the last bit group (

) Is composed of M bits, the last bit group (

) Can be divided into M / C bits and written into each column. That is, the last bit group (

May be divided into M / C sub-groups, M / C sub-bit groups may be divided, and each sub-bit group may be written to each column of the second part.

Accordingly, it can be seen that at least one bit group interleaved by the second part is divided into at least two columns constituting the second part and the bits included in at least one bit group are written.

In the above example, the block interleaver 124 writes bits in the column direction in the second part, but this is merely an example. That is, the block interleaver 124 may write bits in a plurality of columns of the second part in the row direction. In this case, the block interleaver 124 can write the bits for the first part in the same manner as described above.

11, the block interleaver 124 writes bits in the first column from the first row to the first column constituting the second part in the first column to the first row constituting the second part in the first column, R 2 from the _second line constituting a second part in the second light, the bits from the second line to the second line constituting a second part in the C column, ..., and a first column constituting a part in the Bits from the C column to the R ₂ -th row constituting the second part.

On the other hand, the block interleaver 124 sequentially reads the bits written in each row of each part in the row direction. That is, as shown in FIGS. 10 and 11, the block interleaver 124 sequentially reads the bits written in the respective rows of the first part of the plurality of columns in the row direction and writes the written bits Can be sequentially read out in the row direction.

Accordingly, the block interleaver 124 can interleave a part of a plurality of bit groups constituting the LDPC codeword in units of a bit group, and perform interleaving by dividing the remaining part of the bit groups. That is, the block interleaver 124 writes LDPC codewords constituting a predetermined number of bit groups among a plurality of bit groups into a plurality of columns constituting the first part in units of a bit group, It is possible to divide and write data into each of the columns constituting the second part, and perform interleaving by reading a plurality of columns constituting the first and second parts in the row direction.

As described above, the block interleaver 124 can interleave a plurality of bit groups using the method described with reference to FIG. 9 through FIG.

In particular, in the case of FIG. 10, the bits included in the bit group not belonging to the first part are written in the column direction in the second part and read in the row direction, Can be redefined. As described above, the bits included in the bit group not belonging to the first part are interleaved, so that the bit error rate (BER) / frame error rate (FER) performance can be improved as compared with the case where the interleaving is not performed.

However, bit groups not belonging to the first part may not be interleaved as shown in FIG. That is, as shown in FIG. 11, the block interleaver 124 writes and reads the bits included in the bit group not belonging to the first part in the row direction in the second part, The bits may be output to the modulation unit 130 sequentially without changing their order. In this case, the bits included in the bit group not belonging to the first part may be outputted sequentially and mapped to the modulation symbol.

10 and 11, the last one of the plurality of bit groups is written in the second part. However, this is only an example, and the number of groups written in the second part is not limited to the LDPC codeword The number of rows and columns, the number of transmission antennas, and the like.

On the other hand, the block interleaver 124 may have a structure as shown in Tables 23 and 24 below.

Here, C (or N _c ) is the number of columns constituting the block interleaver 124, R ₁ is the number of rows constituting the first part in each column, R ₂ is the number of rows constituting the second part in each column The number of rows to be processed.

Referring to Table 23 and Table 24, the number of columns has the same value as the modulation order according to the modulation scheme, and each of the plurality of columns is constituted by a row of the value obtained by dividing the number of bits constituting the LDPC codeword by the number of the columns .

For example, when the length of the LDPC codeword is N _ldpc = 64800 and modulation is performed by the 16-QAM method, the modulation order of the 16-QAM is 4, so the block interleaver 124 is composed of four columns, Is composed of R ₁ + R ₂ = 16200 (= 64800/4) rows. As another example, when the length N _LDPC of the LDPC codeword is 64800 and the modulation is performed by the 64-QAM method, the modulation order of the 64-QAM is 6, so the block interleaver 124 is composed of 6 columns, R ₁ + R ₂ = 10800 (= 64800/6) rows.

On the other hand, with reference to Table 23 and Table 24, when the number of groups of bits constituting the LDPC codeword times the integer number of columns, the block interleaver 124 is R ₁ in that it performs the interleaving without separating each column The number of rows constituting each column becomes R ₂ = 0. When the number of groups constituting the LDPC codeword is not an integral multiple of the number of columns, the block interleaver 124 divides each column into a first part composed of R ₁ rows and a second part composed of R ₂ rows Interleaving is performed by dividing into two parts.

On the other hand, as shown in Tables 23 and 24, when the number of columns of the block interleaver 124 is equal to the number of bits constituting the modulation symbol, the bits included in the same bit group can be mapped to one bit in the modulation symbol .

For example, when N _ldpc = 64800 and the modulation scheme is 16-QAM, the block interleaver 124 may be composed of four columns each including 16,200 rows. In this case, the bits included in each of the plurality of bit groups are written into four columns, and the bits written to the same row in each column are sequentially output. In this case, when the modulation scheme is 16-QAM, the bits included in the same bit group, i.e., bits output from one column are mapped to one bit in the modulation symbol in that 4 bits constitute one modulation symbol . For example, the bits contained in the group written to the first column may be mapped to the first bit of each modulation symbol.

As another example, when N _ldpc = 64800 and the modulation scheme is 64-QAM, the block interleaver 124 may be composed of six columns each including 10800 rows. In this case, the bits included in each of the plurality of bit groups are written into six columns, and the bits written to the same row in each column are sequentially output. In this case, when the modulation scheme is 64-QAM, the bits included in the same bit group, i.e., bits output from one column are mapped to one bit in the modulation symbol in that 6 bits constitute one modulation symbol . For example, the bits contained in the group written to the first column may be mapped to the first bit of each modulation symbol.

Referring to Table 23 and Table 24, it can be seen that the number of all the rows of the block interleaver 124, that is, R ₁ + R ₂ is N _ldpc / C.

이고, 제2 파트의 행의 개수인 R₂는 N_ldpc/C-R₁이 될 수 있다. 여기에서,

는 N_group/C 이하의 가장 큰 정수를 나타낸다. 이와 같이, R₁은 각 비트 그룹에 포함된 비트의 개수인 M의 정수 배가 된다는 점에서, R₁에는 비트 그룹 단위의 비트들이 라이트될 수 있다.R ₁ , the number of rows of the first part, is an integer multiple of M (for example, M = 360), which is the number of bits included in each group

And R ₂ , the number of rows of the second part, can be N _ldpc / CR ₁ . From here,

_Represents the largest integer equal to or smaller than N _group / C. In this way, since R ₁ is an integer multiple of M, which is the number of bits included in each bit group, the bits in bit group units can be written to R ₁ .

Referring to Table 23 and Table 24, when the number of bit groups constituting the LDPC codeword is not a multiple of the number of columns, the block interleaver 124 divides each column into two parts and performs interleaving Able to know.

Specifically, the value obtained by dividing the length of the LDPC codeword by the number of columns is the total number of rows included in each column. At this time, when the number of bit groups constituting the LDPC codeword is a multiple of the number of columns, each column is not divided into two parts. However, when the number of bit groups constituting the LDPC codeword is not a multiple of the number of columns, each column can be divided into two parts.

For example, as shown in Table 23, it is assumed that the number of columns of the block interleaver 124 is equal to the number of bits constituting the modulation symbol, and the LDPC codeword is composed of 64,800 bits. At this time, each bit group constituting the LDPC codeword is composed of 360 bits, and the LDPC codeword is composed of 64800/360 = 180 bit groups.

On the other hand, when the modulation scheme is 16-QAM, the block interleaver 124 is composed of four columns, and each column can be composed of 64800/4 = 16,200 rows.

At this time, the value obtained by dividing the number of bit groups constituting the LDPC codeword by the number of columns is 180/4 = 45, so that the bits can be written into each column in units of bit groups without dividing each column into two parts. That is, in each column, bits included in 45 bit groups, that is, 45 × 360 = 16,200 bits, which is a quotient obtained by dividing the number of bit groups constituting the LDPC codeword by the number of columns, can be written.

However, when the modulation scheme is 256-QAM, the block interleaver 124 is composed of 8 columns, and each column can be composed of 64800/8 = 8100 rows.

At this time, since the value obtained by dividing the number of bit groups constituting the LDPC codeword by the number of columns is 180/8 = 22.5, the number of bit groups constituting the LDPC codeword is not an integer multiple of the number of columns. Accordingly, the block interleaver 124 divides each of the eight columns into two parts in order to perform interleaving on a bit group basis.

In this case, since the bits must be written in units of bit groups in the first part of each column, the number of bit groups that can be written in units of bit groups in the first part of each column is the number of groups constituting the LDPC codeword, Divided by 22, so that the first part of each column can be composed of 22 x 360 = 7920 rows. Accordingly, 7920 bits included in 22 bit groups can be written in the first part of each column.

On the other hand, the second part of each column is composed of a row excluding all the rows constituting the first part in the entire row of each column. Thus, the second part of each column may consist of 8100-7920 = 180 rows.

At this time, the bits included in the remaining bit groups that have not been written to the first part in the second part of each column can be divided and written.

Specifically, since 22 × 8 = 176 bit groups are written in the first part, the number of bit groups written in the second part is 180-176 = 4 (for example, the bit group Y ₀ ), the bit group (Y _1), the bit group (Y _2), ..., bit group (Y _178), the bit group (Y ₁₇₉₎ of the bit groups (Y _176), the bit group (Y _177), the bit group (Y ₁₇₈ ), bit group (Y ₁₇₉ )).

Accordingly, the block interleaver 124 can write the remaining four bit groups to the first part of the group constituting the LDPC codeword sequentially to the second part of each column.

That is, the block interleaver 124 writes 180 bits out of the 360 bits included in the bit group Y ₁₇₆ in the column direction from the first row to the 180th row of the second part of the first column, and the remaining 180 bits Can be written in the column direction from the first row to the 180th row of the second part of the second column. The block interleaver 124 writes 180 bits out of the 360 bits included in the bit group Y ₁₇₇ in the column direction from the first row to the 180th row of the second part of the third column and outputs the remaining 180 bits Can be written in the column direction from the first row to the 180th row of the second part of the fourth column. The block interleaver 124 writes 180 bits out of the 360 bits included in the bit group Y ₁₇₈ in the column direction from the first row to the 180th row of the second part of the fifth column and outputs the remaining 180 bits From the first row to the 180th row of the second part of the sixth column in the column direction. The block interleaver 124 writes 180 bits out of the 360 bits included in the bit group Y ₁₇₉ in the column direction from the first row to the 180th row of the second part of the seventh column and outputs the remaining 180 bits Can be written in the column direction from the first row to the 180th row of the second part of the eighth column.

Accordingly, the bits included in the remaining bit groups written in the first part can be divided into a plurality of columns without being written to the same column in the second part.

Hereinafter, a concrete example of the block interleaver 124 of FIG. 5 will be described in more detail with reference to FIG.

)는 V={Y₀,Y₁,...,

}과 같이 Y_j가 연속적으로 배치될 수 있다. The group interleaved LDPC codeword (v ₀ , v ₁ , ...,

) Is expressed as V = {Y ₀ , Y ₁ , ...,

Y _j} is such as may be placed consecutively.

After group interleaving, the LDPC codeword can be interleaved by the block interleaver 124 as shown in FIG. In this case, the block interleaver 124 can divide the plurality of columns into the first part and the second part based on the number of columns constituting the block interleaver 124 and the number of bits of the bit group. In this case, the bits constituting the bit group are written into the same column in the first part, and the bits constituting the bit group in the second part may be written into the plurality of columns.

Concretely, the input bit vi is serially written from the first part to the second part in a column wise manner, and is sequentially read from the first part to the second part in a row wise manner. do. Accordingly, the bits included in the same bit group in the first part can be mapped to one bit in each modulation symbol.

)은 360의 배수이므로, 복수의 비트 그룹이 제1 파트에 라이트될 수 있다. In this case, the number of columns and the number of rows of the first and second parts of the block interleaver 124 according to the modulation scheme and the length (i.e., code length) of the LDPC codeword can be as shown in Table 25 below. Here, the number of columns of the block interleaver 124 may be equal to the number of bits constituting the modulation symbol. The sum of N _r1 , the number of rows of the first part, and N _r2 , the number of rows of the second part, is equal to N _ldpc / N _c , where N _c is the number of columns. Then, N _r1 (=

Is a multiple of 360, a plurality of bit groups can be written to the first part.

Hereinafter, the operation of the block interleaver 124 will be described in more detail.

, r_i=(i mod N_r1)와 같다.Specifically, the input bit v _i (0? I <N _c × N _r1 ) is written to the row r _i of the c _i column of the first part of the block interleaver 124 as shown in FIG. Here, c _i and r _i are

, and r _i = (i mod N _r1 ).

, r_i=N_r1+{(i-N_c×N_r1) mod N_r2}와 같다.Then, the input bits, _{v i (N c × N r1} ≤i <N ldpc) are written into the second part of the column c _i r _i rows of the block interleaver (124). Here, c _i and r _i are

, r _i = N _r1 + {(iN _c × N _r1 ) mod N _r2 }.

, c_j=(j mod N_c)와 같다.On the other hand, the output bit q _j (0≤j <N _ldpc) are read out from the column c _j r _j of the line. Here, c _j and r _j are

, c _j = (j mod N _c ).

For example, when the length N _LDPC of the LDPC codeword is 64800 and the modulation scheme is 256-QAM, the order of bits output from the block interleaver 124 is (q ₀ , q ₁ , q ₂ , q ₆₃₃₅₇ , q ₆₃₃₅₈ , q ₆₃₃₅₉ , q ₆₃₃₆₀ , q ₆₃₃₆₁ , ..., q ₆₄₇₉₉ ) = (v ₀ , v ₇₉₂₀ , v ₁₅₈₄₀ , ..., v ₄₇₅₁₉ , v ₅₅₄₃₉ , v ₆₃₃₅₉ , v ₆₃₃₆₀ , v ₆₃₅₄₀ , ..., v ₆₄₇₉₉ ). Here, if the index in the right-hand term is described in more detail for all eight columns, 0, 7920, 15840, 23760, 31680, 39600, 47520, 55440, 1, 7921, 15841, 23761, 31681, 39601, 47521, 55441, ... , 7919, 15839, 23759, 31679, 39599, 47519, 55439, 63359, 63360, 63540, 63720, 63900, 64080, 64260, 64440, 64620, ... ... , 63539, 63719, 63899, 64079, 64259, 64439, 64619, 64799.

Hereinafter, the interleaving operation of the block interleaver 124 will be described in detail.

The block interleaver 124 writes a plurality of bit groups in a column direction in each column in a bit group unit and interleaves each row of a plurality of columns in which a plurality of bit groups are written in a bit group unit in the row direction .

In this case, the number of columns constituting the block interleaver 124 may vary depending on the modulation scheme, and the number of rows may be the length / number of columns of the LDPC codeword.

For example, if the modulation scheme is 16-QAM, the block interleaver 124 may be composed of four columns. At this time, if the length _Nldpc of the LDPC codeword is 64800, the number of rows can be 64800/4 = 16200. As another example, if the modulation scheme is 64-QAM, the block interleaver 124 may be composed of six columns. At this time, if the length _Nldpc of the LDPC codeword is 64800, the number of rows can be 64800/6 = 10800.

Hereinafter, a method in which the block interleaver 124 interleaves a plurality of bit groups on a bit group basis will be described in detail.

When the number of bit groups constituting the LDPC codeword is an integral multiple of the number of columns, the block interleaver 124 sequentially writes the bit groups corresponding to the number obtained by dividing the number of bit groups by the number of columns into each column sequentially in units of bit groups, Can be performed.

For example, when the modulation scheme is 16-QAM and the length N _LDPC of the LDPC codeword is 64800, the block interleaver 124 may be composed of four columns each including 16,200 rows. Here, when the length _Nldpc of the LDPC codeword is 64800, the LDPC codeword is divided into 64800/360 = 180 bit groups. Therefore, when the modulation scheme is 16-QAM, the number of bit groups constituting the LDPC codeword (= 180 ) Is an integer multiple of the number of columns (= 4). That is, when the number of bit groups constituting the LDPC codeword is divided by the number of columns, the remainder is not generated.

In this case, as shown in FIG. 13, the block interleaver 124 divides the bit group (Y ₀ ), the bit group (Y ₁ ), ..., and the bit group (Y ₄₄ ) And the bits included in the bit group Y ₄₅ , the bit group Y ₄₆ , ..., and the bit group Y ₈₉ are written in the 16200th row from the first row of the second column, Write the bits included in each of the bit group (Y ₉₀ ), the bit group (Y ₉₁ ), ..., and the bit group (Y ₁₃₄ ) to the 16200-th row from the first column of the third column, The bits included in each of the bit group Y ₁₃₅ , the bit group Y ₁₃₆ , ..., and the bit group Y ₁₇₉ are written in the 16200th row from the first row to the column. Then, the block interleaver 124 can sequentially read the bits written in the respective rows of the two columns in the row direction.

As another example, when the modulation scheme is 64-QAM and the length N _LDPC of the LDPC codeword is 64800, the block interleaver 124 may be composed of 6 columns each including 10800 rows. Here, when the length _Nldpc of the LDPC codeword is 64800, the LDPC codeword is divided into 64800/360 = 180 bit groups. Therefore, when the modulation scheme is 64-QAM, the number of bit groups constituting the LDPC codeword (= 180 ) Is an integer multiple of the number of columns (= 4). That is, when the number of bit groups constituting the LDPC codeword is divided by the number of columns, the remainder is not generated.

In this case, as shown in FIG. 14, the block interleaver 124 sets the bit group (Y ₀ ), the bit group (Y ₁ ), ..., and the bit group (Y ₂₉ ) in the first to 10800th rows of the first column And the bits included in each of the bit group Y ₃₀ , the bit group Y ₃₁ , ..., and the bit group Y ₅₉ are written in the 10800th row from the first row to the 10800th row of the second column And writes the bits included in each of the bit group (Y ₆₀ ), the bit group (Y ₆₁ ), ..., and the bit group (Y ₈₉ ) to the 10800th row from the first column of the third column, Bits included in each of the bit group (Y ₉₀ ), the bit group (Y ₉₁ ), ..., and the bit group (Y ₁₁₉ ) are written in the first to 10800th columns of the column, The bits included in the bit group Y ₁₂₀ , the bit group Y ₁₂₁ , ..., and the bit group Y ₁₄₉ are written into the 10800th row to the 10800th row from the 1st column to the 10800th row of the sixth column, The bit group (Y ₁₅₀ ) , The bit group Y ₁₅₁ , ..., and the bit group Y ₁₇₉ , respectively. Then, the block interleaver 124 can sequentially read the bits written in the respective rows of the two columns in the row direction.

In this manner, when the number of bit groups constituting the LDPC codeword is an integral multiple of the number of columns constituting the block interleaver 124, the block interleaver 124 interleaves the plurality of bit groups in group units, The bits belonging to the same bit group can be written in the same column.

In this manner, the block interleaver 124 can interleave a plurality of bit groups constituting the LDPC codeword using the method described in FIG. 13 and FIG.

The modulator 130 maps the interleaved LDPC codeword to a modulation symbol. Specifically, the modulator 130 demultiplexes the interleaved LDPC codeword, modulates the demultiplexed LDPC codeword, and maps the constellation.

In this case, the modulation unit 130 may generate the modulation symbols using the bits included in each of the plurality of bit groups.

That is, as described above, bits included in different bit groups are written in each column of the block interleaver 124, and the block interleaver 124 reads the bits written in the respective columns in the row direction. In this case, the modulator 130 maps the bits read from each column of the block interleaver 124 to each bit of the modulation symbol to generate a modulation symbol. Accordingly, each bit of the modulation symbol can be a bit included in a different bit group.

For example, it is assumed that a modulation symbol is composed of C bits. In this case, in the event that the bits read in each row of the C columns of the block interleaver 124 can be mapped to each bit of the modulation symbol, each bit of the modulation symbol consisting of C bits is eventually divided into C different bit groups Lt; / RTI &gt;

Hereinafter, this will be described in more detail.

First, the modulator 130 can demultiplex the interleaved LDPC codeword. For this, the modulator 130 may include a demultiplexer (not shown) for demultiplexing the interleaved LDPC codeword.

A demultiplexer (not shown) demultiplexes the interleaved LDPC codeword. More specifically, a demultiplexer (not shown) performs a serial-to-parallel conversion on the interleaved LDPC codewords and converts the interleaved LDPC codewords into cells having a predetermined number of bits Or a data cell (data dcell).

For example, as shown in FIG. 15, a demultiplexer (not shown) receives an LDPC codeword Q = (q ₀ , q ₁ , q ₂ , May be sequentially output to each of the plurality of sub-streams, and the input LDPC codeword bits may be converted into cells and output.

In this case, bits having the same index in each of the plurality of sub-streams can constitute the same cell. In this way, each cell _{(y 0, 0, y 1} , 0, ..., y η MOD -1,0) = (q 0, q 1, ..., q ηMOD-1), (y 0 _{, 1} , y _{1 , 1} , ..., y _{η MOD -1,1} ) = (q _{η MOD} , q _{η MOD +1} , ..., q _{2 × η MOD -1} ) Lt; / RTI &gt;

On the other hand, the number N _substreams of the sub-streams is equal to the number of bits η _MOD of the modulation symbols. Accordingly, the number of bits constituting each cell may be the same as the number of bits constituting the modulation symbol (i.e., modulation order).

For example, if the modulation scheme is 16-QAM, the number of sub-streams N _substreams = 4 can be obtained since the number of bits η _MOD = 4 constituting the modulation symbol, and each cell is represented by (y _0,0 , y _{1 , 0, y 2,0, y 3,0} ) = (q 0, q 1, q 2, q 3), (y 0, 1, y 1, 1, y 2, 1, y 3, 1) = _{(q 4, q 5, q} 6, q 7), (y 0,2, y 1,2, y 2,2, y 3,2) = (q 8, q 9, q 10, q 11), ... &lt; / RTI &gt;

As another example, if the modulation scheme is 64-QAM, the number of bits η _MOD = 6 constituting the modulation symbol can be N, so that the number of _substreams N _substreams = 6, and each cell can be represented by (y _{0,0 , 0, y 2,0, y 3,0,} y 4,0, y 5,0) = (q 0, q 1, q 2, q 3, q 4, q 5), (y 0,1, y _{1,1, y 2,1, y 3,1,} y 4,1, y 5,1) = (q 6, q 7, q 8, q 9, q 10, q 11), (y 0,2 , y _1,2 , y _2,2 , y _3,2 , y _4,2 , y _5,2 ) = (q ₁₂ , q ₁₃ , q ₁₄ , q ₁₅ , q ₁₆ , q ₁₇ ) As shown in FIG.

Meanwhile, the modulator 130 may map the demultiplexed LDPC codeword to the modulation symbol.

Specifically, the modulator 130 outputs bits (i.e., cells) output from the demultiplexer (not shown) to quadrature phase shift keying (QPSK), 16-QAM, 64-QAM, 256-QAM, 1024- -QAM, and the like. For example, when the modulation scheme is QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM or 4096-QAM, the number η _MOD of the bits constituting the modulation symbol Order) can be 2, 4, 6, 8, 10, and 12, respectively.

In this case, since each cell output from the demultiplexer (not shown) is composed of as many bits as the number of bits constituting the modulation symbol, the modulator 130 sequentially transmits each cell output from the demultiplexer (not shown) constellation point) to generate a modulation symbol. Here, the modulation symbols correspond to the constellation points in the constellation.

However, in some cases, the above-described demultiplexer (not shown) may be omitted. In this case, the modulator 130 sequentially separates the interleaved bits by a predetermined number and maps the interleaved bits to the property points to generate modulation symbols. In this case, the modulator 130 may generate the modulation symbols by mapping the interleaved bits sequentially to the _ST points in the 侶_MOD bits according to the modulation scheme.

Meanwhile, the modulator 130 may perform modulation by mapping the cells output from the demultiplexer (not shown) to sex points using a non-uniform constellation (NUC) scheme.

In the case of non uniform constellation method, if we define the property of the first quadrant, the property of the other three quadrants can be determined by the following method. For example, if the set of stores defined for the first quadrant is X, then -conj (X) for the second quadrant, conj (X) for the third quadrant, and - (X) for the fourth quadrant .

In other words, if you define the first quadrant, the other quadrants can be expressed as:

1 Quarter (= 1 quadrant) = X

2 Quarter = -conj (X)

3 Quarter = conj (X)

4 Quarter = -X

Specifically, when non-uniform M-QAM is used, _{M storages} can be defined as z = {z ₀ , z ₁ , ..., z _{M -1} }. In this case, when a sex shop existing in the first quadrant is defined as {x ₀ , x ₁ , x ₂ , ..., x _{M / 4-1} }, z can be defined as follows.

z ₀ to z _{M / 4-1} = x ₀ to x _{M / 4}

z _{M / 4} to z _{2 x M / 4-1} = -conj (x ₀ to x _{M / 4} )

z _{2 x M / 4} to z _{3 x M / 4-1} = conj (x ₀ to x _{M / 4} )

z _{3 x M / 4} to z _{4 x M / 4-1} = - (x ₀ to x _{M / 4} )

을 인덱스로 하는 z_L로 매핑하여, 출력 비트들을 non-uniform constellation 방식으로 성성점에 맵핑할 수 있다. Therefore, the modulator 130 outputs the output bits [y ₀ , ..., y _m-1 ] output from the demultiplexer (not shown)

To an index z _L to map output bits to sexual points in a non-uniform constellation scheme.

Meanwhile, an example of the constellation defined according to the non-uniform constellation scheme described above is a constellation defined by the following Tables 26 to 30 when the coding rates are 5/15, 7/15, 9/15, 11/15, As shown in Fig.

In these Tables 26 to 30, Table 26 shows non-uniform QPSK, Table 27 shows non-uniform 16-QAM, Table 28 and Table 29 show non-uniform 64-QAM, and Table 30 shows non-uniform 256-QAM .

Referring to these tables, the property points of the first quadrant can be defined based on Tables 26 to 30, and the constellation points for the remaining three quadrants can be defined based on the above-described method.

However, this is only an example, and the modulator 130 may map the output bits output from the demultiplexer (not shown) to the store in various manners.

The reason for performing the interleaving in the above-described manner in the present invention is as follows.

Specifically, when LDPC codeword bits are mapped to modulation symbols, they have different reliability (i. E., Reception performance or reception probability) depending on the location mapped in the modulation symbol. Meanwhile, the LDPC codeword bits may have different codeword characteristics according to the structure of the parity check matrix. That is, the LDPC codeword bits may have different codeword characteristics according to the number of 1s in the column of the parity check matrix, that is, the column order.

Accordingly, in the present invention, the interleaver 120 may be configured such that the LDPC codeword bits having a specific codeword property are mapped to specific bits in the modulation symbol, considering both the codeword characteristics of the LDPC codeword bits and the reliability of the bits constituting the modulation symbol Interleaving is performed.

For example, when the LDPC codeword composed of the bit group X ₀ to the bit group X ₁₇₉ is group interleaved based on Expression 21 and Table 11, the group interleaver 122 outputs the bit group X ₅₅ , the bit group X ₁₄₆ , Group X ₈₃ , ..., bit group X ₁₃₂ , and bit group X _{135 in this} order.

In this case, when the modulation scheme is 16-QAM, the number of columns constituting the block interleaver 124 is four, and each column may be composed of 16,200 rows.

Accordingly, 45 bit groups (X ₅₅ , X ₁₄₆ , X ₈₃ , X ₅₂ , X ₆₂ , X ₁₇₆ , X ₁₆₀ , X ₆₈ , X ₅₃ , X ₅₆ , and X ₈₁ of the 180 groups constituting the LDPC codeword _{, X 97, X 79, X} 113, X 163, X 61, X 58, X 69, X 133, X 108, X 66, X 71, X 86, X 144, X 57, X 67, X 116, X _{59, X 70, X 156,} X 172, X 65, X 149, X 155, X 82, X 138, X 136, X 141, X 111, X 96, X 170, X 90, X 140, X 64, X ₁₅₉ ) are input to the first column of the block interleaver 124 and 45 bits groups (X ₁₅ , X ₁₄ , X ₃₇ , X ₅₄ , X ₄₄ , X ₆₃ , X ₄₃ , X ₁₈ , X ₄₇ , X _{7 , X 25, X 34, X} 29, X 30, X 26, X 39, X 16, X 41, X 45, X 36, X 0, X 23, X 32, X 28, X 27, X 38, X _{48, X 33, X 22,} X 49, X 51, X 60, X 46, X 21, X 4, X 3, X 20, X 13, X 50, X 35, X 24, X 40, X 17, X _42, X ₆₎ are two and input the second column, 45-bit groups _{(X 112, X 93, X} 127, X 101, X 94, X 115, X 105, X 31, X 19 of the block interleaver 124 , X ₁₇₇ , X ₇₄ , X _{1 0, X 145, X 162,} X 102, X 120, X 126, X 95, X 73, X 152, X 129, X 174, X 125, X 72, X 128, X 78, X 171, X 8, X ₁₄₂ , X ₁₇₈ , X ₁₅₄ , X ₈₅ , X ₁₀₇ , X ₇₅ , X ₁₂ , X ₉ , X ₁₅₁ , X ₇₇ , X ₁₁₇ , X ₁₀₉ , X ₈₀ , X ₁₀₆ , X ₁₃₄ , X ₉₈ , X ₁ ) a block three and inputs the second column of the interleaver 124, the 45-bit group _{(X 122, X 173, X} 161, X 150, X 110, X 175, X 166, X 131, X 119, X 103, X _{139, X 148, X 157,} X 114, X 147, X 87, X 158, X 121, X 164, X 104, X 89, X 179, X 123, X 118, X 99, X 88, X 11, X ₉₂ , X ₁₆₅ , X ₈₄ , X ₁₆₈ , X ₁₂₄ , X ₁₆₉ , X ₂ , X ₁₃₀ , X ₁₆₇ , X ₁₅₃ , X ₁₃₇ , X ₁₄₃ , X ₉₁ , X ₁₀₀ , X ₅ , X ₇₆ , X ₁₃₂ , X ₁₃₅ ) may be input to the fourth column of the block interleaver 124.

The block interleaver 124 may successively output the bits input from the first row to the last row of each column and the bits output from the block interleaver 124 may be sequentially input to the modulator 130 . In this case, the demultiplexer (not shown) may be omitted or the demultiplexer (not shown) may sequentially output the input bits without changing the order of the input bits. Accordingly, the bits included in each of the bit group X ₅₅ , the bit group X ₁₅ , the bit group X ₁₁₂ , and the bit group X ₁₂₂ can constitute a modulation symbol.

On the other hand, when the modulation scheme is 64-QAM, the number of columns constituting the block interleaver 124 is 6, and each column may be composed of 10800 rows.

Accordingly, 30 bit groups (X ₅₅ , X ₁₄₆ , X ₈₃ , X ₅₂ , X ₆₂ , X ₁₇₆ , X ₁₆₀ , X ₆₈ , X ₅₃ , X ₅₆ and X ₈₁ of the 180 groups constituting the LDPC codeword _{, X 97, X 79, X} 113, X 163, X 61, X 58, X 69, X 133, X 108, X 66, X 71, X 86, X 144, X 57, X 67, X 116, X _59, X _70, X ₁₅₆₎ first is input to the second column, 30-bit groups of the block interleaver _{(124) (X 172, X} 65, X 149, X 155, X 82, X 138, X 136, X 141, _{X 111, X 96, X 170} , X 90, X 140, X 64, X 159, X 15, X 14, X 37, X 54, X 44, X 63, X 43, X 18, X 47, X 7 X ₂₅ , X ₃₄ , X ₂₉ , X ₃₀ and X ₂₆ are input to the second column of the block interleaver 124 and 30 bit groups (X ₃₉ , X ₁₆ , X ₄₁ , X ₄₅ , X ₃₆ , X _{0, X 23, X 32,} X 28, X 27, X 38, X 48, X 33, X 22, X 49, X 51, X 60, X 46, X 21, X 4, X 3, X 20, X ₁₃ , X ₅₀ , X ₃₅ , X ₂₄ , X ₄₀ , X ₁₇ , X ₄₂ and X ₆ are input to the third column of the block interleaver 124, _{(X 112, X 93, X} 127, X 101, X 94, X 115, X 105, X 31, X 19, X 177, X 74, X 10, X 145, X 162, X 102, X 120, X _126, fourth of _{X 95, X 73, X 152} , X 129, X 174, X 125, X 72, X 128, X 78, X 171, X 8, X 142, X 178) is a block interleaver (124) is input to the column, 30-bit groups _{(X 154, X 85, X} 107, X 75, X 12, X 9, X 151, X 77, X 117, X 109, X 80, X 106, X 134, X 98 _{, X 1, X 122, X} 173, X 161, X 150, X 110, X 175, X 166, X 131, X 119, X 103, X 139, X 148, X 157, X 114, X 147) the five and input the second column, 30-bit groups of the block interleaver _{(124) (X 87, X} 158, X 121, X 164, X 104, X 89, X 179, X 123, X 118, X 99, X 88, _{X 11, X 92, X 165} , X 84, X 168, X 124, X 169, X 2, X 130, X 167, X 153, X 137, X 143, X 91, X 100, X 5, X 76 , X ₁₃₂ , and X ₁₃₅ may be input to the sixth column of the block interleaver 124.

The block interleaver 124 may successively output the bits input from the first row to the last row of each column and the bits output from the block interleaver 124 may be sequentially input to the modulator 130 . In this case, the demultiplexer (not shown) may be omitted or the demultiplexer (not shown) may sequentially output the input bits without changing the order of the input bits. Accordingly, the bits included in each of the bit group X ₅₅ , the bit group X ₁₇₂ , the bit group X ₃₉ , the bit group X ₁₁₂ , the bit group X ₁₅₄ , and the bit group X ₈₇ can constitute a modulation symbol.

As described above, in the present invention, it is possible to achieve both excellent reception performance and decoding performance on the receiving side in that a specific bit is mapped to a specific bit in a modulation symbol through interleaving.

That is, when mapping the LDPC codeword bits having excellent decoding performance to the bits having high reliability among the bits constituting the modulation symbol, the decoding performance may be improved at the receiving side, but the LDPC codeword bits A problem that can not be solved can occur. When the LDPC codeword bits having excellent decoding performance are mapped to the bits having poor reliability among the bits constituting the modulation symbol, the initial reception performance is excellent and the overall performance may be excellent. However, Error propagation may occur.

Therefore, when mapping LDPC codeword bits to modulation symbols, LDPC codeword bits having specific codeword characteristics are considered in consideration of both the codeword characteristics of the LDPC codeword bits and the reliability of the bits constituting the modulation symbol. Mapped to a specific bit in the modulation symbol and transmitted to the receiving side. Thus, it is possible to achieve both excellent reception performance and decoding performance on the receiving side.

In the following, a method for determining? (J), which is a parameter used for group interleaving in various embodiments of the present invention, will be described.

According to the embodiment of the present invention, when the length of the LDPC codeword is 64800, since the size of the bit group is 360, 180 bit groups exist and the possible interleaving patterns are 180? (Where factorial means A! = A * (A-1) * ... * 2 * 1 for integer A).

In this case, since the reliability levels between the bits constituting the modulation symbol are the same according to the modulation order, a large number of interleaving patterns may be regarded as the same interleaving operation considering the theoretical performance. For example, when the theoretical reliability of the X axis or real part MSB bits and the Y axis or imaginary part MSB bits constituting a certain modulation symbol are the same, a certain bit is mapped to two MSBs The theoretical performance is the same regardless of how it is interleaved.

However, the closer to the actual channel environment, the less theoretical predictions become. For example, in a modulation scheme such as QPSK, in a part of a symmetric channel such as an AWGN channel, theoretically, two bits constituting a symbol are completely identical in reliability. Therefore, even if any interleaving scheme is used, There should be no difference in performance, but there is a difference in performance depending on the interleaving method in a real channel environment. Performance of the well-known Rayleigh channel, not the actual channel, depends on the interleaving method. The performance of QPSK depends on the reliability of the bits constituting the symbol according to the modulation scheme. One obvious limitation exists.

In addition, since the performance of code by interleaving may vary greatly depending on the channel for evaluating the performance, it is necessary to always determine the channel in consideration of deriving the interleaving pattern. For example, in general, a good interleaving pattern in an AWGN channel is not good for a Rayleigh channel. If the channel environment in which a given system is used is closer to the Rayleigh channel, a good interleaving pattern It may be better to choose a better interleaving pattern on the Rayleigh channel.

In conclusion, in order to derive the code interleaving pattern, a good interleaving pattern can be obtained by considering various channel environments considered in the system, not by considering only the specific channel environment. In addition, since there is a limit to judge actual performance only by the theoretical performance prediction, it is necessary to finally determine the interleaving pattern after confirming the performance through the computation of the direct performance.

However, in many cases the number of possible interleaving patterns is too large to apply all of the above procedures (eg 180!), So designing a good interleaver to efficiently reduce the number of interleaving patterns for performance prediction and testing It is a key part.

Accordingly, in the present invention, the interleaver is designed through the following process.

1) Determine the channels C ₁ , C ₂ , ..., C _k to be considered in the system.

2) Generate an arbitrary interleaver pattern.

3) The interleaver generated in 2) is applied to each channel determined in 1) to predict the theoretical performance value. There are various methods for estimating the theoretical performance values, but the present invention uses a well-known noise threshold determination method such as density evolution analysis. Here, the noise threshold is a value that can be represented by the minimum SNR required for error-free transmission, assuming that the length of a code is infinite and the code is represented by a Tanner graph and satisfies the cycle-free characteristic. Although the density evolution analysis method itself can be implemented in various ways, it is not a core of the present invention, so a detailed description thereof will be omitted.

4) For the i-th interleaver, when the noise threshold for each channel is denoted as TH ₁ [i], TH ₂ [i], ..., TH _k [i], the final decision threshold is defined as .

_{TH [i] = W 1 *} TH 1 [i] + W 2 * TH 2 [i] + ... + W k * TH k [i],

Here, W ₁ + W ₂ + ... + W k = 1, and W ₁ , W ₂ , ..., W _k > 0 are satisfied.

The values of W ₁ , W ₂ , ..., W _k are adjusted so that the value for the important channel is large and the value for the less important channel is small according to the importance of the channel (for example, considering AWGN and Rayleigh channels, W ₁ = 0.25 and W ₂ = 0.75 when it is determined that the importance of one of the channels is higher when the weight value is W ₁ and W ₂ ).

5) Select interleaver B in order of least number of interleaver patterns tested and perform performance computation experiment directly on each channel. Here, the FER level for the test is determined to be 10 &lt; -3 &gt; (e.g., B = 100).

6) Select the D interleaver patterns with the best performance among the B interleavers tested in 5) (eg D = 5).

Usually, the interleaver having a large SNR gain in the FER = 10 ^ -3 region in the step 5) can be selected as an interleaver having excellent performance, but in the present invention, as shown in FIG. 16, From the results of computational experiments, the performance of the FER required by the system is predicted through extrapolation, and the interleaver with good performance is evaluated as an excellent interleaver by comparing the expected performance at the FER required in the system. In the present invention, extrapolation based on a linear function is applied for convenience, but various other extrapolation methods may be applied. Meanwhile, FIG. 16 shows an example of the performance extrapolation expected from the computation experiment result.

7) Perform the performance computation experiment on each channel directly with D interleaver patterns selected in 6). Here, the FER level for the test is selected as the FER required by the system (eg FER = 10 ^ -6).

8) An error floor is not observed after the computational experiment is completed, and the interleaving pattern with the greatest SNR gain is determined as the final interleaving pattern.

Meanwhile, FIG. 17 is a diagram simply showing a process of determining patterns of B interleavers in steps 2), 3), 4) and 5) among the methods of determining the interleaving pattern as described above, for example, AWGN and Rayleigh channels .

Referring to Figure 17, and calculates the first, initializing the values of the variables i, j, such as required in S1701, and then, the noise threshold for the AWGN channel in S1702 TH ₁ [i], the noise threshold TH ₂ [i] for the Rayleigh Channel . Then, the final decision noise threshold TH [i] defined in step 4) is calculated in step S1703, and then, in step S1704, the final decision noise threshold and the size of the previous step are compared. In step S1706, if the final decision noise threshold value is small, TH_S [i] is appropriately substituted and stored. Thereafter, in step S1707, the values of i and j are steamped one by one, and the process is repeated until the value of i exceeds the predetermined value in step S1708. In this case, the A value is the total number of interleavers to be tested in 2), 3), 4) and 5), and typically the A value is determined to be 10000 or more. When the above process is complete S1709 TH _S [0] is stored as a small sequence in the final noise _{threshold, TH S [1], ...} , and the final selection of interleaver pattern corresponding to TH _S [B-1] value.

On the other hand, the transmitting apparatus 100 can modulate the signal mapped to the constellation and transmit it to the receiving apparatus (for example, 1200 in Fig. 18). For example, the transmitting apparatus 100 may map a signal mapped to constellation to an OFDM frame using an Orthogonal Frequency Division Multiplexing (OFDM) scheme, and transmit the mapped signal to the receiving apparatus 1200 through the allocated channel

18 is a block diagram illustrating a configuration of a receiving apparatus according to an embodiment of the present invention. Referring to FIG. 18, a receiving apparatus 1200 includes a demodulator 1210, a multiplexer 1220, a deinterleaver 1230, and a decoder 1240.

The demodulation unit 1210 receives and demodulates the signal transmitted from the transmission apparatus 100. Specifically, the demodulator 1210 demodulates the received signal to generate a value corresponding to the LDPC codeword, and outputs the value to the multiplexer 1220. In this case, the demodulating unit 1210 can perform demodulation so as to correspond to the modulation scheme used in the transmitting apparatus 100. To this end, the transmitting apparatus 100 may transmit the information on the modulation scheme to the receiving apparatus 1200, or the transmitting apparatus 100 may transmit the modulation scheme to the receiving apparatus 1200 using the predetermined modulation scheme, Can be performed.

Here, the value corresponding to the LDPC codeword can be expressed by the channel value for the received signal. There are various methods for determining the channel value, for example, a method of determining a log likelihood ratio (LLR) value.

The LLR value can be represented by a value obtained by taking a log as a ratio of the probability that the bits transmitted from the transmitting apparatus 100 are 0 and the probability of one day. Alternatively, the LLR value may be a bit value determined according to a hard decision, and the LLR value may be a representative value determined according to a period in which the probability that the bit transmitted from the transmitting apparatus 100 is 0 or 1 .

The multiplexer 1220 multiplexes the output value of the demodulator 1210 and outputs it to the deinterleaver 1230.

Specifically, the multiplexer 1220 corresponds to a demultiplexer (not shown) included in the transmission apparatus 100, and performs an operation corresponding to a demultiplexer (not shown). That is, the multiplexer 1220 inversely performs an operation performed in the demultiplexer (not shown), performs a cell-to-bit conversion on the output value of the demodulator 1210, and outputs an LLR value Can be output. However, if a demultiplexer (not shown) is omitted from the transmitting apparatus 100, the multiplexer 1220 of the receiving apparatus 1200 may be omitted.

Information on whether the demultiplexing operation is performed may be provided from the transmission apparatus 100 or may be stored in advance between the transmission apparatus 100 and the reception apparatus 1200. [

The deinterleaver 1230 deinterleaves the output value of the multiplexer 1220 and outputs it to the decoding unit 1240.

Specifically, the deinterleaver 1230 corresponds to the interleaver 120 of the transmission apparatus 100, and performs an operation corresponding to the interleaver 120. [ That is, the deinterleaver 1230 deinterleaves the LLR values by performing the interleaving operation performed in the interleaver 120 inversely.

The deinterleaver 1230 may include a block deinterleaver 1231, a group twist deinterleaver 1232, a group deinterleaver 1233, and a parity deinterleaver 1234 as shown in FIG.

The block deinterleaver 1231 deinterleaves the output of the multiplexer 1220 and outputs it to the group twist deinterleaver 1232.

Specifically, the block deinterleaver 1231 is a component corresponding to the block interleaver 124 included in the transmission apparatus 100, and can perform the interleaving operation performed in the block interleaver 124 inversely.

That is, the block deinterleaver 1231 writes the LLR value output from the multiplexer 1220 in each row in the row direction using at least one row composed of a plurality of columns, and outputs the LLR values of the plurality of rows It is possible to perform deinterleaving by reading the column in the column direction.

In this case, when the block interleaver 124 divides a column into two parts and performs interleaving, the block deinterleaver 1231 can perform deinterleaving by dividing a row into two parts.

When the block interleaver 124 writes and reads in a row direction a bit group that does not belong to the first part, the block deinterleaver 1231 writes the value corresponding to the group not belonging to the first part in the row direction And read and perform deinterleaving.

Hereinafter, the block deinterleaver 1231 will be described with reference to FIG. However, this is merely an example, and it goes without saying that the block deinterleaver 1231 can be implemented by other methods.

,

이다.The input LLR v _i (0? I <N _ldpc ) is written to the r _i row, c _i column of the block deinterleaver 1231. From here,

,

to be.

,

이다.On the other hand, the output LLR q _i (0? I <N _c × N _r1 ) is read from the c _i column and the r _i row of the first part of the block deinterleaver 1231. From here,

,

to be.

,

이다.The output _{LLR q i (N c × N} r1 ≤i <N ldpc) is lead from the second part of the column c _i, r _i the row of the block deinterleaver 1231. From here,

,

to be.

The group twist deinterleaver 1232 deinterleaves the output value of the block deinterleaver 1231 and outputs the deinterleaved output value to the group deinterleaver 1233.

Specifically, the group twist deinterleaver 1232 is a component corresponding to the group twist interleaver 123 provided in the transmitting apparatus 100, and can perform the interleaving operation performed in the group twist interleaver 123 inversely .

That is, the group twist deinterleaver 1232 can rearrange the LLR values in the same group by changing the order of the LLR values existing in the same group. On the other hand, if the group twist operation is not performed in the transmitting apparatus 100, the group twist deinterleaver 1232 may be omitted.

The group deinterleaver 1233 (or group-wide deinterleaver) deinterleaves the output value of the group twist deinterleaver 1232 and outputs it to the parity deinterleaver 1234.

Specifically, the group deinterleaver 1233 is a component corresponding to the group interleaver 122 provided in the transmitting apparatus 100, and can perform the interleaving operation performed in the group interleaver 122 inversely.

That is, the group deinterleaver 1233 can rearrange the order of the plurality of bit groups into a bit group unit. In this case, the group deinterleaver 1233 applies the interleaving scheme defined in Table 11 to Table 22 inversely according to the length, modulation scheme, and coding rate of the LDPC codeword, Can be rearranged.

The parity deinterleaver 1234 performs parity deinterleaving on the output value of the group deinterleaver 1233 and outputs it to the decoding unit 1240.

Specifically, the parity deinterleaver 1234 is a component corresponding to the parity interleaver 121 provided in the transmitting apparatus 100, and can perform the interleaving operation performed in the parity interleaver 121 inversely. That is, the parity deinterleaver 1234 can deinterleave the LLR values corresponding to the parity bits among the LLR values output from the group deinterleaver 1233. In this case, the parity deinterleaver 1234 can deinterleave the LLR values corresponding to the parity bits inversely to the parity interleaving method of Equation (18).

However, the parity deinterleaver 1234 may be omitted according to the decoding method and implementation of the decoding unit 1240.

Meanwhile, the deinterleaver 1230 of FIG. 18 may be composed of three or four components as shown in FIG. 19, but the operation of the components may be performed by one component. For example, a bit group of X _a, X _b, X _c, if one of the bits belonging to each bit group to form one modulation symbol with respect to the X _d, a received one in the deinterleaver 1230 of Based on the modulation symbols, to positions corresponding to the bit groups.

For example, if the coding rate is 6/15 and the modulation scheme is 16-QAM, the group deinterleaver 1233 can perform deinterleaving based on Table 11. [

In this case, one bit included in each of the bit groups X ₅₅ , X ₁₅ , X ₁₁₂ , and X ₁₂₂ constitutes one modulation symbol. Since one bit of each of the bit groups X ₅₅ , X ₁₅ , X ₁₁₂ and X ₁₂₂ constitutes one modulation symbol, the deinterleaver 1230 generates bit groups X ₅₅ and X ₁₅ , X ₁₁₂ , and X ₁₂₂ , respectively.

The decoding unit 1240 may perform LDPC decoding using the output value of the deinterleaver 1230. For this, the decoding unit 1240 may include an LDPC decoder (not shown) for performing LDPC decoding.

More specifically, the decoding unit 1240 is a component corresponding to the encoding unit 110 of the transmission apparatus 100 and performs LDPC decoding using the LLR value output from the deinterleaver 1230 to correct errors have

For example, the decoding unit 1240 may perform LDPC decoding using iterative decoding based on a sum-product algorithm. Here, the summing algorithm is a kind of message passing algorithm, and the message passing algorithm is a method of exchanging messages (e.g., LLR values) via edges on a bipartite graph, It shows an algorithm for calculating and updating an output message from input messages.

 Meanwhile, the decoding unit 1240 may use a parity check matrix for LDPC decoding. In this case, the parity check matrix used in decoding may have the same structure as the parity check matrix used in encoding in the encoding unit 110, which has been described above with reference to FIG. 2 through FIG.

Information on the parity check matrix used in the LDPC decoding, information on the coding rate, and the like may be stored in the receiving apparatus 1200 or may be provided from the transmitting apparatus 100.

21 is a flowchart illustrating an interleaving method of a transmitting apparatus according to an embodiment of the present invention.

First, an LDPC encoding is performed based on a parity check matrix (S1410), and an LDPC codeword is interleaved (S1420)

Thereafter, the interleaved LDPC codeword is mapped to a modulation symbol (S1430). In this case, the bits included in the predetermined bit group among the plurality of bit groups constituting the LDPC codeword can be mapped to predetermined bits in the modulation symbol.

Here, each of the plurality of bit groups is composed of M bits, and M is a common divisor of N _ldpc and K _ldpc , and Q _ldpc = (N _{ldpc -} K _ldpc ) / M can be determined. In this case, Q _ldpc is the cyclic shift parameter value for the columns in the column group of the information word _sub- matrix constituting the parity check matrix, N _ldpc is the length of the LDPC codeword, and K _ldpc is the information word constituting the LDPC codeword The length of the bits.

In step S1420, the parity bits constituting the LDPC codeword are interleaved, the parity interleaved LDPC codeword is divided into a plurality of bit groups, the order of the plurality of bit groups is rearranged on a bit group basis, A plurality of bit groups can be interleaved.

Here, the order of the plurality of groups can be rearranged on a bit group basis based on the above-described expression (21).

On the other hand, as described in the expression (21),? (J) in the expression (21) can be determined based on at least one of the length of the LDPC codeword, the modulation method and the coding rate.

For example, π (j) can be defined as Table 11 above when the length of the LDPC codeword is 64800 and the modulation scheme is 16-QAM and the coding rate is 6/15.

(J) can be defined as shown in Table 14 when the length of the LDPC codeword is 64800, the modulation method is 16-QAM, and the coding rate is 10/15.

In addition, π (j) can be defined as shown in Table 15 when the length of the LDPC codeword is 64800, the modulation scheme is 16-QAM, and the coding rate is 12/15.

The above-mentioned? (J) can be defined as shown in Table 17 below when the length of the LDPC codeword is 64800 and the modulation scheme is 64-QAM and the coding rate is 6/15.

The above-mentioned? (J) can be defined as shown in Table 18 below when the length of the LDPC codeword is 64800 and the modulation scheme is 64-QAM and the coding rate is 8/15.

The above-mentioned? (J) can be defined as shown in Table 21 when the length of the LDPC codeword is 64800, the modulation scheme is 64-QAM, and the coding rate is 12/15.

On the other hand, when a plurality of bit groups are interleaved, a plurality of bit groups are written in a column direction in each of a plurality of columns in a bit group unit, and each row of a plurality of columns in which a plurality of bit groups are written in bit group units, So that interleaving can be performed.

Here, at least a part of bit groups writable in units of a bit group are sequentially written into each of the plurality of columns in each of the plurality of bit groups, and then at least a part of the bit groups in each of the plurality of columns are written into the bit group The remaining bit groups can be divided and written into the remaining area written in units.

Meanwhile, a non-transitory computer readable medium may be provided in which a program for sequentially performing the interleaving method according to the present invention is stored.

A non-transitory readable medium is a medium that stores data for a short period of time, such as a register, cache, memory, etc., but semi-permanently stores data and is readable by the apparatus. In particular, various applications or programs may be stored on non-volatile readable media such as CD, DVD, hard disk, Blu-ray disk, USB, memory card, ROM,

Although the buses are not shown in the above-described block diagrams for the transmitting apparatus and the receiving apparatus, the communication between the respective elements in each apparatus may be performed via the bus. Further, each apparatus may further include a processor such as a CPU, a microprocessor, or the like that performs the various steps described above.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the present invention.

100: transmitting apparatus 110:
120: interleaver 130:

Claims (4)

In the transmitting apparatus,
An encoder for encoding information word bits based on a low density parity check (LDPC) code to generate a codeword;
An interleaver interleaving the codeword; And
And a mapper for mapping the bits of the interleaved code word to the stores. The method according to claim 1,
The interleaver includes:
Interleaves the parity bits generated by the encoding, and interleaves the codeword including the information bits and the interleaved parity bits. In the transmission method,
Encoding information word bits based on a low density parity check (LDPC) code to generate a codeword;
Interleaving the codeword; And
And mapping the bits of the interleaved code word to the stores. The method of claim 3,
Wherein the interleaving comprises:
Interleaves the parity bits generated by the encoding, and interleaves the codeword including the information bits and the interleaved parity bits.

Images