KR102245527B1 - Transmitting apparatus and interleaving method thereof - Google Patents

Abstract

The transmitting device is started. The present transmission apparatus includes an encoder that generates an LDPC codeword by performing LDPC encoding, an interleaver that interleaves the LDPC codeword, and a modulator that maps the interleaved LDPC codeword to a modulation symbol, and the modulator configures the LDPC codeword. A bit included in a preset bit group among a plurality of bit groups may be mapped to a preset bit in a modulation symbol.

Description

Transmitting device and its interleaving method {TRANSMITTING APPARATUS AND INTERLEAVING METHOD THEREOF}

The present invention relates to a transmitting apparatus and an interleaving method thereof, and more particularly, to a transmitting apparatus that processes and transmits data, and an interleaving method thereof.

In the information society of the 21st century, broadcasting and communication services are entering the era of full-scale digitalization, multi-channelization, broadbandization, and high quality. In particular, as the spread of high-definition digital TVs, PMPs, and portable broadcasting devices is expanding in recent years, there is an increasing demand for supporting various reception methods for digital broadcasting services.

In response to these demands, the standard group has established various standards to provide various services that can satisfy the needs of users, so it is requested to find a way to provide better services through better decoding and reception performance. do.

The present invention is in accordance with the above-described necessity, and an object of the present invention is a transmission apparatus capable of transmitting by mapping a bit included in a preset bit group among a plurality of bit groups constituting an LDPC codeword to a preset bit in a modulation symbol, and It is to provide his interleaving method.

In order to achieve the above object, a transmission apparatus according to an embodiment of the present invention includes an encoder for generating an LDPC codeword by performing LDPC encoding based on a parity check matrix, an interleaver for interleaving the LDPC codeword, and the interleaving. And a modulator for mapping the LDPC codeword to a modulation symbol, wherein the modulator maps a bit included in a preset bit group among a plurality of bit groups constituting the LDPC codeword to a preset bit in the modulation symbol.

Here, each of the plurality of bit groups is composed of M bits, M is a common factor of _{N ldpc} and K _{ldpc , and Q ldpc} = (N _ldpc -K _ldpc )/M may be determined to be established. In this case, Q _ldpc is a cyclic shift parameter value for columns within a column group of an information word submatrix constituting the parity check matrix, N _ldpc is the length of the LDPC codeword, and K _ldpc is the LDPC codeword. It is the length of the information word bits.

Meanwhile, the interleaver divides the parity interleaver for interleaving parity bits constituting the LDPC codeword, the parity interleaved LDPC codeword into the plurality of bit groups, and rearranges the order of the plurality of bit groups in units of bit groups. And a block interleaver for interleaving a plurality of bit groups in which the order is rearranged.

Here, the group interleaver may rearrange the order of the plurality of bit groups in bit group units based on Equation 21 below.

In this case, π(j) may be determined based on at least one of a length, a modulation method, and a code rate of the LDPC codeword.

In addition, when the length of the LDPC codeword is 64800, the modulation method is 16-QAM, and the code rate is 6/15, π(j) may be defined as shown in Table 11 below.

In addition, when the length of the LDPC codeword is 64800, the modulation method is 16-QAM, and the code rate is 10/15, π(j) may be defined as shown in Table 14 below.

In addition, when the length of the LDPC codeword is 64800, the modulation method is 16-QAM, and the code rate is 12/15, π(j) may be defined as shown in Table 15 below.

In addition, when the length of the LDPC codeword is 64800, the modulation method is 64-QAM, and the code rate is 6/15, π(j) may be defined as shown in Table 17 below.

In addition, when the length of the LDPC codeword is 64800, the modulation method is 64-QAM, and the code rate is 8/15, π(j) may be defined as shown in Table 18 below.

In addition, when the length of the LDPC codeword is 64800, the modulation method is 64-QAM, and the code rate is 12/15, π(j) may be defined as shown in Table 21 below.

Meanwhile, the block interleaver writes the plurality of bit groups in a column direction to each of a plurality of columns in a bit group unit, and reads each row of the plurality of columns in which the plurality of bit groups are written in a bit group unit in a row direction. Thus, interleaving can be performed.

Here, the block interleaver sequentially writes at least some bit groups that can be written in bit group units to each of the plurality of columns among the plurality of bit groups in each of the plurality of columns, and then sequentially writes the plurality of columns to each of the plurality of columns. At least some bit groups may be written in bit group units, and the remaining bit groups may be divided and written in the remaining area.

Meanwhile, the interleaving method according to an embodiment of the present invention includes generating an LDPC codeword by performing LDPC encoding based on a parity check matrix, interleaving the LDPC codeword, and modulating the interleaved LDPC codeword. And mapping to a symbol, and the mapping may map a bit included in a preset bit group among a plurality of bit groups constituting the LDPC codeword to a preset bit in the modulation symbol.

Here, each of the plurality of groups is composed of M bits, M is a common factor of _{N ldpc} and K _{ldpc , and Q ldpc} = (N _ldpc -K _ldpc )/M may be determined to be established. In this case, Q _ldpc is a cyclic shift parameter value for columns within a column group of an information word submatrix constituting the parity check matrix, N _ldpc is the length of the LDPC codeword, and K _ldpc is the LDPC codeword. It is the length of the information word bits.

In addition, the interleaving may include interleaving parity bits constituting the LDPC codeword, dividing the parity-interleaved LDPC codeword into the plurality of bit groups, and rearranging the order of the plurality of bit groups in groups. And interleaving a plurality of bit groups in which the order is rearranged.

Here, in the rearranging step, the order of the plurality of bit groups may be rearranged in bit group units based on Equation 21 below.

In this case, π(j) may be determined based on at least one of a length, a modulation method, and a code rate of the LDPC codeword.

In addition, when the length of the LDPC codeword is 64800, the modulation method is 16-QAM, and the code rate is 6/15, π(j) may be defined as shown in Table 11 below.

In addition, when the length of the LDPC codeword is 64800, the modulation method is 16-QAM, and the code rate is 10/15, π(j) may be defined as shown in Table 14 below.

In addition, when the length of the LDPC codeword is 64800, the modulation method is 16-QAM, and the code rate is 12/15, π(j) may be defined as shown in Table 15 below.

In addition, when the length of the LDPC codeword is 64800, the modulation method is 64-QAM, and the code rate is 6/15, π(j) may be defined as shown in Table 17 below.

In addition, when the length of the LDPC codeword is 64800, the modulation method is 64-QAM, and the code rate is 8/15, π(j) may be defined as shown in Table 18 below.

In addition, when the length of the LDPC codeword is 64800, the modulation method is 64-QAM, and the code rate is 12/15, π(j) may be defined as shown in Table 21 below.

Meanwhile, the interleaving of the plurality of bit groups includes writing the plurality of bit groups in a column direction in each of a plurality of columns in a bit group unit, and each of the plurality of columns in which the plurality of bit groups are written in a bit group unit. Interleaving can be performed by reading rows in the row direction.

Here, the interleaving of the plurality of bit groups may include sequentially writing at least some bit groups that can be written to each of the plurality of columns of the plurality of bit groups in a bit group unit to each of the plurality of columns, and then, the In each of the plurality of columns, the at least some bit groups may be written in bit group units, and the remaining bit groups may be divided and written in the remaining area.

According to various embodiments of the present invention, it is possible to provide better decoding and reception performance.

1 is a block diagram illustrating a configuration of a transmission device according to an embodiment of the present invention.
2 to 4 are diagrams for explaining the structure of a parity check matrix according to various embodiments of the present invention;
5 is a block diagram illustrating a configuration of an interleaver according to an embodiment of the present invention;
6 to 8 are diagrams for explaining an interleaving method according to an embodiment of the present invention;
9 to 14 are diagrams for explaining an interleaving operation of a block interleaver according to an embodiment of the present invention;
15 is a diagram for explaining an operation of a demultiplexer according to an embodiment of the present invention;
16 and 17 are diagrams for explaining a method of designing an interleaving pattern according to an embodiment of the present invention;
18 is a block diagram illustrating a configuration of a receiving device according to an embodiment of the present invention.
19 is a block diagram illustrating a configuration of a deinterleaver according to an embodiment of the present invention;
20 is a diagram illustrating a deinterleaving operation of a block deinterleaver according to an embodiment of the present invention, and
21 is a flowchart illustrating an interleaving method according to an embodiment of the present invention.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

1 is a block diagram illustrating a configuration of a transmission device according to an embodiment of the present invention. Referring to FIG. 1, the transmission device 100 includes an encoder 110, an interleaver 120, and a modulator 130 (or, it may be referred to as a'constellation mapper').

The encoder 110 generates an LDPC codeword by performing Low Density Parity Check (LDPC) encoding based on a parity check matrix (PCM). To this end, the encoder 110 may include an LDPC encoder (not shown) that performs LPDC encoding.

Specifically, the encoder 110 may perform LDPC encoding on the input bits as information word bits, thereby generating an LDPC codeword composed of information word bits and parity bits (ie, LDPC parity bits). . In this case, since the LPDC code is a systematic code, the information word bits may be included in the LDPC code word as it is.

Here, the LDPC codeword is composed of information word bits and parity bits. For example, the LDPC codeword is composed of _{N ldpc} bits, and may include information word bits composed of _{K ldpc bits and parity} bits composed of N parity = N _ldpc -K _{ldpc bits.}

In this case, the encoder 110 may generate an LDPC codeword by performing LDPC encoding based on the parity check matrix. That is, since the process of performing LDPC encoding is a process of ^{generating an LDPC codeword to satisfy H·C T} = 0, the encoder 110 may use a parity check matrix during LDPC encoding. Here, H denotes a parity check matrix, and C denotes an LDPC codeword.

To this end, the transmission device 100 may include a separate memory to pre-store various types of parity check matrices.

For example, the transmission device 100 may include Digital Video Broadcasting-Cable version 2 (DVB-C2), Digital Video Broadcasting-Satellite-Second Generation (DVB-S2), Digital Video Broadcasting-Second Generation Terrestria (DVB-T2), etc. The parity check matrix defined in the standard of is stored in advance, or the parity check matrix defined in the Advanced Television Systems Committee (ATSC) 3.0 standard, a North American digital broadcasting standard system currently being established, may be pre-stored. However, this is only an example, and the transmission device 100 may pre-store various types of parity check matrices.

Hereinafter, a structure of a parity check matrix according to various embodiments of the present invention will be described with reference to the accompanying drawings. In the following parity check matrix, elements except 1 are 0.

For example, the parity check matrix according to an embodiment of the present invention may have a structure as shown in FIG. 2.

Referring to FIG. 2, the parity check matrix 200 includes an information word partial matrix 210 that is a partial matrix corresponding to information word bits and a parity partial matrix 220 that is a partial matrix corresponding to parity bits.

_{The information word sub-} matrix 210 includes K ldpc columns, and the parity _sub - _{matrix 220 includes N parity} =N _{ldpc -K ldpc} columns. Meanwhile, the number of rows of the parity check matrix 200 is equal to _{the number of columns of the parity sub} -matrix 220 N parity =N _{ldpc -K ldpc.}

In addition, in the parity check matrix 200, N _ldpc represents the length of the LDPC codeword, K _ldpc represents the length of the information word bits, and N _parity =N _ldpc -K _ldpc represents the length of the parity bits. Here, the lengths of the LDPC codeword, information word bits, and parity bits mean the number of bits included in each of the LDPC codeword, information word bits, and parity bits.

Hereinafter, the structure of the information word sub-matrix 210 and parity sub-matrix 220 will be described.

_{The information word sub-} matrix 210 is a matrix including K ldpc columns (ie, K _ldpc -1 th column from the 0 th column), and follows the following rules.

_{First, K ldpc} columns constituting the information word submatrix 210 belong to the same group by M, and are divided into a _{total of K ldpc /M column groups.} Columns belonging to the same column group have a relationship that is cyclic shifted by _{Q ldpc.} That is, Q _ldpc can be viewed as a cyclic shift parameter value for columns within a column group of an information word submatrix constituting a parity check matrix.

Here, M is an interval at which a column pattern is repeated in the information word partial matrix 210 (for example, M=360), and Q _ldpc is a size at which each column is cyclically shifted in the information word partial matrix 210. M is a _{common divisor of N ldpc} and K _ldpc , and Q _ldpc = (N _ldpc -K _ldpc )/M is determined to be established. Here, M and Q _ldpc are integers, and K _ldpc /M is also an integer. Meanwhile, M and Q _ldpc may have various values according to the length and code rate of the LDPC codeword.

For example, when M=360 and the length N _ldpc of the LDPC codeword is 64800, Q _ldpc is defined as in Table 1 below, and when M=360 and the length N _ldpc of the LDPC codeword is 16200, Q _ldpc is as follows: It can be defined as shown in Table 2 of.

이라 하면, i 번째 열 그룹 내의 j 번째 열에서 k 번째 1이 위치한 행의 인덱스

는 하기의 수학식 1과 같이 결정된다.Second, the degree of the 0th column of the i-th (i=0,1,..,K _ldpc /M-1) column group (here, the degree is the number of 1 values in the column, in the same column group). The order of all the columns belonging to it is the same), and D _i , and the position (or index) of each row with a 1 in the 0th column of the i-th column group.

In this case, the index of the row in which the k-th 1 is located in the j-th column in the i-th column group.

Is determined as in Equation 1 below.

Here, k=0,1,2,..,D _i -1, i=0,1,..,K _ldpc /M-1, j=1,2,...,M-1.

Meanwhile, Equation 1 may be expressed in the same manner as in Equation 2 below.

Here, k=0,1,2,..,D _i -1, i=0,1,..,K _ldpc /M-1, j=1,2,...,M-1. Here, since j=1,2,...,M-1, (j mod M) in Equation 2 can be viewed as j.

는 i 번째 열 그룹 내의 j 번째 열에서 k 번째 1이 위치한 행의 인덱스, N_ldpc는 LDPC 부호어의 길이, K_ldpc는 정보어 비트들의 길이, D_i는 i 번째 열 그룹에 속하는 열들의 차수, M은 하나의 열 그룹에 속하는 열의 개수, Q_ldpc는 각 열이 시클릭 쉬프트되는 크기를 의미한다.In these equations,

Is the index of the row where the k-th 1 is located in the j-th column in the i-th column group, N _ldpc is the length of the LDPC codeword, K _ldpc is the length of the information word bits, D _i is the order of the columns belonging to the i-th column group, M is the number of columns belonging to one column group, and Q _ldpc is the size at which each column is cyclically shifted.

값만을 알면 i 번째 열 그룹 내의 j 번째 열에서 k 번째 1이 있는 행의 인덱스

를 알 수 있게 된다. 그러므로, 각각의 열 그룹 내의 0 번째 열에서 k 번째 1이 있는 행의 인덱스 값을 저장하면, 도 2의 구조를 갖는 패리티 검사 행렬(200)(즉, 패리티 검사 행렬(200)의 정보어 부분 행렬(210))에서 1이 있는 열과 행의 위치가 파악될 수 있다.After all, referring to these equations

If only the value is known, the index of the row with the k-th 1 in the j-th column in the i-th column group

Will be able to know. Therefore, if the index value of the row with the k-th 1 in the 0-th column in each column group is stored, the parity check matrix 200 having the structure of FIG. 2 (that is, the information word partial matrix of the parity check matrix 200) In (210)), the position of the column and row with 1 can be determined.

According to the above-described rules, all the orders of columns belonging to the i-th column group are the same as _{D i.} Accordingly, the LDPC code storing information on the parity check matrix according to the above-described rules can be briefly expressed as follows.

For example, when N _ldpc is 30, K _ldpc is 15, and Q _ldpc is 3, the positional information of the row where 1 is located in the 0th column of the 3 column group can be expressed as a sequence such as Equation 3 below. And this may be referred to as a'weight-1 position sequence'.

는 i 번째 열 그룹 내의 j 번째 열에서 k 번째 1이 있는 행의 인덱스를 의미한다.From here,

Denotes the index of the row with the k-th 1 in the j-th column in the i-th column group.

Weight-1 position sequences, such as Equation 3, representing the index of the row where 1 is located in the 0-th column of each column group may be more simplified as shown in Table 3 below.

Table 3 shows the positions of elements having a value of 1 in the parity check matrix, and the i-th weight-1 position sequence is represented by the indexes of the row with 1 in the 0-th column belonging to the i-th column group.

Based on the above description, the information word partial matrix 210 of the parity check matrix according to an embodiment of the present invention may be defined by Tables 4 to 8 below.

Specifically, Tables 4 to 8 show the indexes of the row at which 1 is located in the 0-th column of the i-th column group of the information word submatrix 210. That is, the information word submatrix 210 is composed of a plurality of column groups each including M columns, and the position of 1 in the 0th column of each of the plurality of column groups may be defined by Tables 4 to 8. .

Here, the indexes of the row where 1 is located in the 0-th column of the i-th column group means “addresses of parity bit accumulators”. Meanwhile, since “addresses of parity bit accumulators” has the same meaning as defined in standards such as DVB-C2/S2/T2 or ATSC 3.0 standards currently being established, detailed descriptions will be omitted.

For example, if the length N _ldpc of the LDPC codeword is 64800, the code rate is 6/15, and M is 360, the indexes of the row where 1 is located in the 0th column of the i-th column group of the information word submatrix 210 are It is shown in Table 4 below.

As another example, if the length N _ldpc of the LDPC codeword is 64800, the code rate is 8/15, and M is 360, the indexes of the row at which 1 is located in the 0-th column of the i-th column group of the information word submatrix 210 are It is shown in Table 5 below.

As another example, when the length N _ldpc of the LDPC codeword is 64800, the code rate is 10/15, and M is 360, the indexes of the row at which 1 is located in the 0-th column of the i-th column group of the information word submatrix 210 are It is shown in Table 6 below.

As another example, when the length N _ldpc of the LDPC codeword is 64800, the code rate is 10/15, and M is 360, the indexes of the row at which 1 is located in the 0-th column of the i-th column group of the information word submatrix 210 are It is shown in Table 7 below.

As another example, when the length N _ldpc of the LDPC codeword is 64800, the code rate is 12/15, and M is 360, the indexes of the row at which 1 is located in the 0-th column of the i-th column group of the information word submatrix 210 are It is shown in Table 8 below.

Meanwhile, in the above-described example, only cases where the length of the LDPC codeword is 64800 and the code rates are 6/15, 8/15, 10/15, and 12/15 have been described, but this is only an example and the length of the LDPC codeword is Even in the case of 16200 or having a different code rate, the position of 1 in the information word partial matrix 210 may be variously defined.

On the other hand, in that the parity check matrix of the same sign even if the order of the numbers in the sequence corresponding to each i-th column group is changed in Tables 4 to 8 described above, the sequence corresponding to each i-th column group in Tables 4 to 8 A case in which the order within is changed may be an example of a code considered in the present invention.

In addition, since algebraic characteristics such as cycle characteristics and order distribution on the graph of signs do not change even if the order of arrangement of the sequences corresponding to each column group in Tables 4 to 8 is changed, the order of arrangement of the sequences shown in Tables 4 to 8 is changed. The change can be an example.

_{In addition, as a result of adding multiples of Q ldpc} equally to all the sequences corresponding to an arbitrary column group in Tables 4 to 8, also because algebraic characteristics such as cycle characteristics or order distribution on the sign graph do not change, Table 4 The result of adding multiples of _{Q ldpc} equally to all the sequences shown in Table 8 may be an example. It should be noted here that if the value is more than _{(N ldpc} -K _{ldpc ) when the given sequence is added by a multiple of Q ldpc , the value is modulo (N ldpc} -K _ldpc ). It means that you have to apply it by replacing it with the applied value.

On the other hand, as shown in Tables 4 to 8, when the position of the row in which 1 is present in the 0-th column of the i-th column group of the information word submatrix 210 is defined, it is _cyclically shifted by Q ldpc to The position of the row with 1 in the column can be defined.

For example, in the case of Table 4, in the case of the 0th column of the 0th column group of the information word submatrix 210, 1 is present in the 1606th row, the 3402th row, the 4961th row, ....

In this case, since Q _ldpc =(N _ldpc -K _ldpc )/M=(64800-25920)/360=108, the index of the row where 1 is located in the 1st column of the 0th column group is 1714(=1606+108) , 3510(=3402+108), 5069(=4961+108),..., and the index of the row where 1 is located in the 2nd column of the 0th column group is 1822(=1714+108), 3618(=3510 +108), 5177(=5069+108),... can be.

In this way, the index of the row where 1 is located in all rows of each column group can be defined.

Meanwhile, in the parity check matrix 200 as shown in FIG. 2, the parity partial matrix 220 may be defined as follows.

The parity partial matrix 220 is a partial matrix including N _ldpc -K _ldpc columns (ie, _{N ldpc} -1 rows from _{K ldpc} th column), and has a dual diagonal or staircase structure. _{Accordingly, the order of the remaining columns except for the last column (ie, N ldpc} -1st column) among the columns included in the parity sub-matrix 220 is 2, and the order of the last column is 1.

Consequently, in the parity check matrix 200, the information word sub-matrix 210 is defined by Tables 4 to 8, and the parity sub-matrix 220 may have a double diagonal structure.

Meanwhile, when the columns and rows of the parity check matrix 200 shown in FIG. 2 are permutated based on Equations 4 and 5 below, the parity check matrix 200 shown in FIG. It may be represented in the form of a parity check matrix 300 shown in FIG.

A method of performing permutation based on Equation 4 and Equation 5 is as follows. Here, since the same principle applies to row permutation and column permutation, the row permutation will be described as an example.

In the case of row permutation, _{i and j satisfying X=Q ldpc} ×i+j are calculated for the X-th row, and the calculated i and j are substituted for M × j+i to permutate the X-th row. Yields a row. For example, in the case of the 7th row, i,j satisfying 7=2×i+j becomes 3,1, respectively, so the 7th row is permutated to 10×1+3=13th row.

When row permutation and column permutation are performed in this manner, the parity check matrix of FIG. 2 can be expressed as shown in FIG. 3.

Referring to FIG. 3, the parity check matrix 300 divides the parity check matrix 300 into a plurality of partial blocks, and each of the partial blocks is quasi-cyclic of M×M size. It has a form that matches the matrix.

Accordingly, the parity check matrix 300 having the structure as shown in FIG. 3 is configured in units of an M×M matrix. That is, the parity check matrix 300 is configured by arranging partial matrices having a size of M×M in a plurality of partial blocks.

As described above, since the parity check matrix 300 is composed of a quasi-circular matrix unit of M×M size, M columns may be referred to as column-blocks and M rows may be referred to as row-blocks. have. Accordingly, the parity check matrix 300 having the structure as shown in FIG. 3 used in the present invention _{is composed of N qc _ column} = N _ldpc / M column blocks and N _{qc _ row} = N _parity / M row blocks. It can be seen as.

Hereinafter, a partial matrix having an M×M size will be described.

_{First, the (N qc _ column} -1)-th column block A 330 of the 0-th row block has the form of Equation 6 below.

As such, A(330) is an M×M matrix, and the values of the 0th row and the (M-1)th column are all '0', and for 0≤i≤(M-2), the values of the i-th column are (i+ 1) The first row is '1' and all other values are '0'.

Second, in the parity part matrix _{(320) 0≤i≤ (N ldpc -K} ldpc) with respect to _{/ M-1 (K ldpc /} M + i) i -th row block of the first column block is a unit matrix I _{M × M} ( 340). Further, in _{0≤i≤ (N ldpc -K ldpc) /} M-2 with respect to the (K _ldpc / M + i) th column of the block (i + 1) th row block is an identity matrix I _{M × M} (340) It is composed.

또는, 순환 행렬 P가 시클릭 쉬프트된 행렬

이 합해진 형태(또는, 중첩된 형태)가 될 수 있다. Third, the block 350 constituting the information word sub-matrix 310 is a cyclic matrix P in the form of a cyclic shift.

Or, a matrix in which the cyclic matrix P is cyclically shifted

This can be a combined form (or a superimposed form).

_{For example, when the superscript a ij} of the cyclic matrix P is 1 (ie, P ¹ ), the shape of the block P 350 may be expressed as Equation 7 below.

The circulating matrix P is a square matrix having a size of M×M, and the circulating matrix P represents a matrix in which the weight of each of the M rows is 1 and the weight of each of the M columns is also 1. Then, the permutation matrix P is a superscript a _ij is at 0 i.e., P ^0, represents an identity matrix I _{M × M.} And, for convenience of notation _{, when the superscript a ij} is ∞, that is, P ^∞ defines a zero matrix.

Meanwhile, in FIG. 3, a partial matrix existing at a point where the i-th row block and the j-th column block of the parity check matrix 300 intersect may be. Accordingly, i and j denote the number of row blocks and column blocks of partial blocks corresponding to the information word part. Accordingly, in the parity check matrix 300, the total number of columns is N _ldpc = M×N _{qc _ column} , and the total number of rows is N _parity = M×N _{qc _ row} . That is, the parity check matrix 300 is composed of N _{_ qc column} of "column block" and N _{qc_row} of "line block".

Hereinafter, a method of performing LDPC encoding based on the parity check matrix 200 as shown in FIG. 2 will be described. Meanwhile, for convenience of description, the LDPC encoding process will be schematically described as an example when the parity check matrix 200 is defined as shown in Table 4.

라 하고, 길이가 N_ldpc-K_ldpc인 패리티 비트들을

라 할 때, 하기와 같은 과정에 의해 LDPC 부호화가 수행될 수 있다.First, information word bits of _{length K ldpc}

And parity bits of length N _ldpc -K _ldpc

In this case, LDPC encoding may be performed by the following process.

Step 1) Parity bits are initialized to '0'. In other words,

_{Step 2) The 0-th information word bit i 0} is accumulated in the parity bit having the address of the parity bit defined in the first row of Table 4 (that is, the row with i=0) as the index of the parity bit. This can be expressed as Equation 8 below.

는 바이너리 연산을 의미한다. 바이너리 연산에 의하면, 1

1은 0, 1

0은 1, 0

1은 1, 0

0은 0이다.Here, i ₀ is the 0-th information word bit, p _i is the i-th parity bit,

Means binary operation. According to binary arithmetic, 1

1 is 0, 1

0 is 1, 0

1 is 1, 0

0 is 0.

Step 3) The remaining 359 information word bits i _m (m=1,2,...,359) are accumulated in the parity bit. Here, the remaining information word bits may be information word bits belonging to the same column group as _{i 0.} In this case, the address of the parity bit may be determined based on Equation 9 below.

Here, x is the address of the parity bit accumulator corresponding to the _{information word bit i 0 , Q ldpc} is the size at which each column is cyclically shifted in the partial matrix corresponding to the information word, as shown in Table 4. If it can be 108. And, since m=1,2,...,359, (m mod 360) in Equation 9 can be seen as m.

_{As a result, information word bits i m} (m = 1, 2, ..., 359) are accumulated in each of the parity bits having the address of the parity bit calculated based on Equation 9 as an index. For example, information An operation such as Equation 10 below may be performed on a bit i _1.

는 바이너리 연산을 의미한다. 바이너리 연산에 의하면, 1

1은 0, 1

0은 1, 0

1은 1, 0

0은 0이다.Here, i ₁ is the first information word bit, p _i is the i-th parity bit,

Means binary operation. According to binary arithmetic, 1

1 is 0, 1

0 is 1, 0

1 is 1, 0

0 is 0.

_{Step 4) The 360th information word bit i 360} is accumulated in the parity bit having the address of the parity bit defined in the second row of Table 4 (that is, the row with i=1) as the index of the parity bit.

Step 5) The remaining 359 information word bits belonging to the same group as the _{information word bit i 360 are accumulated in the parity bit.} In this case, the address of the parity bit may be determined based on Equation 9. However, in this case, x becomes the address of the parity bit accumulator corresponding to the _{information word bit i 360.}

Step 6) The same process as in Step 4 and Step 5 described above is repeated for all column groups in Table 4.

Step 7) Finally, the parity bit p _i is calculated based on Equation 11 below. At this time, i is initialized to 1.

는 바이너리 연산을 의미한다.In Equation 11, p _i is the i-th parity bit, N _ldpc is the length _{of the LDPC codeword, K ldpc} is the length of the information word among the LDPC codewords,

Means binary operation.

As a result, the encoder 110 can calculate parity bits according to the above-described method.

As another example, the parity check matrix according to an embodiment of the present invention may have a structure as shown in FIG. 4.

Referring to FIG. 4, the parity check matrix 400 may be composed of five matrices (A, B, C, Z, D). Hereinafter, each matrix is used to describe the structure of the parity check matrix 400 Let's explain the structure of

_{First, parameter values M 1} , M ₂ , Q ₁ , and Q ₂ related to the parity check matrix 400 as shown in FIG. 4 may be defined as shown in Table 9 below according to the length and code rate of the LDPC codeword.

Meanwhile, the matrix A is composed of K columns and g rows, and the matrix C is composed of K+g columns and N-K-g rows. Here, K is the length of the information word bits, and N is the length of the LDPC codeword.

In addition, in the matrix A and the matrix C, the indexes of the row in which 1 is located in the 0-th column of the i-th column group may be defined based on Table 10 below according to the length and code rate of the LDPC codeword. Even in this case, the interval at which the column pattern is repeated in each of the matrix A and the matrix C, that is, the number of columns belonging to the same group may be 360.

For example, when the length N of the LDPC codeword is 64800 and the code rate is 6/15, the indexes of the row at which 1 is located in the 0-th column of the i-th column group of the matrix A and the matrix C are shown in Table 10 below.

Meanwhile, in the above-described example, only the case where the length of the LDPC codeword is 64800 and the code rate is 6/15 is described, but this is only an example, and even when the length of the LDPC codeword is 16200 or has a different code rate, the matrix The indexes of the row at which 1 is located in the 0-th column of the i-th column group of A and matrix C may be variously defined.

Hereinafter, using Table 10 as an example, the positions of the rows in which 1 is present in the matrix A and the matrix C will be described in detail.

In Table 10, since the length N of the LDPC codeword is 64800 and the code rate is 6/15, referring to Table 9, in the parity check matrix 400 defined by Table 10, M ₁ =1080, M ₂ =37800, It can be Q ₁ =3, Q _{2 =105.}

Here, Q ₁ is a size at which columns belonging to the same column group in matrix A are cyclically shifted, and Q ₂ is a size at which columns belonging to the same column group in matrix C are cyclically shifted.

And, Q ₁ =M ₁ /L, Q ₂ =M ₂ /L, M ₁ =g, M ₂ =NKg, L is the interval at which the column pattern is repeated in each of the matrices A and C, for example, 360 I can.

Meanwhile, the index of the row where 1 is located in each of the matrices A and C may be determined based on the value of _{M 1.}

For example, in the case of Table 10, in that M ₁ =1080, the position of the row in which 1 is present in the 0-th column of the i-th column group in the matrix A will be determined based on values smaller than 1080 among the index values of Table 10. In the matrix C, the position of the row in which 1 is present in the 0-th column of the i-th column group may be determined based on values of 1080 or more among the index values of Table 10.

Specifically, the sequence corresponding to the 0th column group in Table 10 is "71, 276, 856, 6867, 12964, 17373, 18159, 26420, 28460, 28477". Therefore, in the case of the 0th column of the 0th column group of matrix A, 1 may be located in each of the 71st row, 276th row, and 856th row, and in the case of the 0th column of the 0th column group of matrix C, the 6867th row , 1 may be located in the 12964th row, the 17373th row, the 18159th row, the 26420th row, the 28460th row, and the 28477th row, respectively.

On the other hand, in the case of matrix A, when the position of 1 in the 0th column of each column group is defined, the position of the row where 1 is present in the other column of each column group can be defined by cyclic shifting _{it by Q 1, and matrix C} In the case of, when the position of 1 in the 0-th column of each column group is defined, the position of the row in which 1 exists in the other column of each column group may be defined by cyclic shifting _{it by Q 2.}

In the above example, in the case of the 0th column of the 0th column group of the matrix A, 1 is present in the 71st row, the 276th row, and the 856th row. In this case, since Q ₁ =3, the index of the row where 1 is located in the 1st column of the 0th column group is 74(=71+3), 279(=276+3), 859(=856+3), The index of the row where 1 is located in the second column of the 0-th column group may be 77 (=74+3), 282 (=279+3), or 862 (=859+3).

Meanwhile, in the case of the 0th column of the 0th column group of the matrix C, 1 is present in the 6867th row, 12964th row, 17373th row, 18159th row, 26420th row, 28460th row, and 28477th row. In this case, since Q ₂ =105, the index of the row where 1 is located in the 1st column of the 0th column group is 6972(=6867+105), 13069(=12964+105), 17478(=17373+105), 18264 (=18159+105), 26525(=26420+105), 28565(=28460+105), 28582(=28477+105), and the index of the row where 1 is located in the 2nd column of the 0th column group is 7077( =6972+105), 13174(=13069+105), 17583(=17478+105), 18369(=18264+105), 26630(=26525+105), 28670(=28565+105), 28687(=28582 +105).

In this manner, the position of the row in which 1 is present in all column groups of the matrix A and the matrix C may be defined.

Meanwhile, the matrix B has a double diagonal structure, the matrix D has a diagonal structure (that is, the matrix D becomes an identity matrix), and the matrix Z may be a zero matrix.

As a result, the structure of the parity check matrix 400 as shown in FIG. 4 can be defined by the matrices A, B, C, D, and Z having the above-described structure.

Hereinafter, a method of performing LDPC encoding based on the parity check matrix 400 as shown in FIG. 4 will be described. Meanwhile, for convenience of explanation, the LDPC encoding process will be schematically described as an example when the parity check matrix 400 is defined as shown in Table 10.

)를 포함하는 LDPC 부호어 Λ=(λ₀,λ₁,...,λ_N-1)=(s₀,s₁,...,S_K-1,p₀,p₁,...,

)가 생성될 수 있다.For example, when LDPC encoding an information block S=(s ₀ ,s ₁ ,...,S _{K -1} ), parity bit P=(p ₀ ,p ₁ ,...,

) Containing LDPC codewords Λ=(λ ₀ ,λ ₁ ,...,λ _N-1 )=(s ₀ ,s ₁ ,...,S _K-1 ,p ₀ ,p ₁ ,.. .,

) Can be created.

Here, _{each of M 1} and M ₂ represents the size of each of the matrix B having the double diagonal structure and the matrix C having the diagonal structure, and M ₁ =g and M ₂ =NKg.

Meanwhile, the process of calculating the parity bit can be expressed as follows. Hereinafter, for convenience of description, a case where the parity check matrix 400 is defined as shown in Table 10 will be described as an example.

Step 1) _{Initialize λ i} =s _i (i=0,1,...,K-1), p _j =0 (j=0,1,...,M ₁ +M ₂ -1) .

_{Step 2) The 0-th information word bit λ 0} is accumulated in the address of the parity bit defined in the first row of Table 10 (that is, the row with i=0). This can be expressed as Equation 12 below.

Step 3) For the next L-1 information word bits λ _m (m=1,2,...,L-1), λ _m is accumulated in the parity bit address calculated based on Equation 13 below. do.

Here, x is the address of the parity bit accumulator corresponding to the 0-th information word bit λ0.

And, Q ₁ =M ₁ /L, Q ₂ =M ₂ /L. In addition, in Table 10, since the length N of the LDPC codeword is 64800 and the code rate is 6/15, referring to Table 9, M ₁ =1080, M ₂ =37800, Q ₁ =3, Q ₂ =105, L= It can be 360.

Accordingly, an operation such as Equation 14 below may be performed on the first information word bit λ _1.

Step 4) In analogy in that the L-th information bits λ _L are the two of the parity bit, such as a second line (i.e., i = 1 row) addresses of the table 10 is given for the above-described manner, since the L- 1 information bits _{λ m (m = L + 1} , L + 2, ..., 2L-1) is calculated on the basis of the addresses of the parity bit for the equation (13). In this case, x is _{the address of the parity bit accumulator corresponding to the information word bit λ L} , and can be obtained based on the second row of Table 10.

Step 5) For the L new information word bits of each group, the above-described process is repeated with the new rows in Table 10 as addresses of the parity bit accumulator.

Step 6) After the _{above-described process is repeated from codeword bits λ 0} to λ _K-1 , values for Equation 15 below are sequentially calculated from i=1.

까지를 하기의 수학식 16에 기초하여 산출한다. Step 7) From _{parity bit λ K} corresponding to matrix B having a double diagonal structure

Up to is calculated based on the following equation (16).

까지에 대한 패리티 비트 누적기의 어드레스는 표 10 및 수학식 13에 기초하여 산출한다. Step 8) From L new codeword bits λ _{K of each group}

The address of the parity bit accumulator for up to is calculated based on Table 10 and Equation 13.

까지 적용된 이후, 대각 구조를 갖는 행렬 C에 대응되는 패리티 비트

부터

까지를 하기의 수학식 17에 기초하여 산출한다. Step 9) From codeword bit λ _K

After applied to, parity bits corresponding to matrix C having a diagonal structure

from

Up to is calculated based on the following equation (17).

Eventually, parity bits can be calculated according to this method.

Returning to FIG. 1, the encoding unit 110 is 3/15, 4/15, 5/15, 6/15, 7/15, 8/15, 9/15, 10/15, 11/15, 12/15 LDPC encoding can be performed using various code rates such as, 13/15, and the like. In addition, the encoder 110 may generate LDPC codewords having various lengths such as 16200, 64800, etc. based on the length and code rate of the information word bits.

In this case, the encoder 110 may perform LDPC encoding using the parity check matrix, and the detailed structure of the parity check matrix has been described above with reference to FIGS. 2 to 4.

In addition, the encoder 110 may perform not only LDPC encoding but also Bose, Chaudhuri, Hocquenghem (BCH) encoding. To this end, the encoder 110 may further include a BCH encoder (not shown) that performs BCH encoding.

In this case, the encoder 110 may perform encoding in the order of BCH encoding and LDPC encoding. Specifically, the encoder 110 performs BCH encoding on the input bits to add a BCH parity bit, and LDPC encoding the bits to which the BCH parity bit is added as information word bits to generate an LDPC codeword. You may.

The interleaver 120 interleaves the LDPC codeword. That is, the interleaver 120 may receive the LDPC codeword from the encoder 110 and interleave the LDPC codeword based on various interleaving rules.

In particular, the interleaver 120 is configured such that the bits included in a preset bit group among a plurality of bit groups (or a plurality of groups or blocks) constituting the LDPC codeword are mapped to a preset bit in the modulation symbol. Language can be interleaved. Accordingly, the modulator 130 may map a bit included in a preset bit group among a plurality of bit groups constituting the LDPC codeword to a preset bit in the modulation symbol.

To this end, as shown in FIG. 5, the interleaver 120 includes a parity interleaver 121, a group interleaver (or, a group-wise interleaver, 122), a group twist interleaver 123, and a block interleaver 124. Can include.

The parity interleaver 121 interleaves parity bits constituting the LDPC codeword.

Specifically, when the LDPC codeword is generated based on the parity check matrix 200 having the structure as shown in FIG. 2, the parity interleaver 121 interleaves only parity bits among the LDPC codewords using Equation 18 below. I can.

)에 대해 패리티 인터리빙을 수행하여 U=(u₀,u₁,...,

)를 출력할 수 있다.Here, M is the interval at which the column pattern is repeated in the information word submatrix 210, that is, the number of columns included in the column group (for example, M=360), and Q _ldpc is each This is the size at which the column is cyclically shifted. That is, the parity interleaver 121 is the LDPC codeword c=(c ₀ ,c ₁ ,...,

) By performing parity interleaving to U=(u ₀ ,u ₁ ,...,

) Can be printed.

The parity-interleaved LDPC codeword in this way may be configured such that a certain number of consecutive bits have similar decoding characteristics (eg, cycle distribution, order of columns, etc.).

For example, the LDPC codeword may have the same characteristics in units of M consecutive bits. Here, M is an interval at which a column pattern is repeated in the information word partial matrix 210, and may be 360, for example.

Specifically, the product of the LDPC codeword bits and the parity check matrix should be '0'. This means that the sum of the products of the i-th LDPC codeword bit c _i (i=0,1,..., N _ldpc -1) from 0 to N _ldpc -1 and the columns of the i-th parity check matrix is a '0' vector. It means it should be. Accordingly, it can be seen that the i-th LDPC codeword bit corresponds to the i-th column of the parity check matrix.

On the other hand, in the case of the parity check matrix 200 as shown in FIG. 2, each of the information word submatrix 210 belongs to the same group by M columns, and has the same characteristics in units of column groups (e.g., columns in the same column group are It has the same order distribution and the same cycle characteristics).

In this case, since M consecutive bits of the information word bits correspond to the same column group of the information word submatrix 210, the information word bits may be composed of M consecutive bits having the same codeword characteristics. . Meanwhile, when parity bits of the LDPC codeword are interleaved by the parity interleaver 121, the parity bits of the LDPC codeword may also be composed of M consecutive bits having the same codeword characteristics.

However, parity interleaving may not be performed for LDPC codewords encoded based on the parity check matrix 300 as shown in FIG. 3 and the parity check matrix 400 as shown in FIG. 4. In this case, the parity interleaver 121 Can be omitted.

The group interleaver 122 may divide the parity-interleaved LDPC codeword into a plurality of bit groups, and rearrange the order of the plurality of bit groups in bits group wise. That is, the group interleaver 122 may interleave a plurality of bit groups in bit group units.

To this end, the group interleaver 122 divides the parity-interleaved LDPC codeword into a plurality of bit groups using Equation 19 or Equation 20 below.

는 k/360 이하의 가장 큰 정수를 나타낸다. In these equations, N _group denotes the total number of bit groups, X _j denotes the j-th bit group, and u _k denotes the k-th LDPC codeword bit input to the group interleaver 122. And,

Represents the largest integer of k/360 or less.

Meanwhile, in these equations, 360 denotes an example of M, which is an interval at which a column pattern is repeated in the information word partial matrix, and in these equations, 360 can be changed to M.

Meanwhile, LDPC codewords divided into a plurality of bit groups may be represented as shown in FIG. 6.

Referring to FIG. 6, it can be seen that the LDPC codeword is divided into a plurality of bit groups, and each bit group is composed of M consecutive bits. Here, when M is 360, each of the plurality of bit groups may consist of 360 bits. Accordingly, each bit group may be composed of bits corresponding to each column group of the parity check matrix.

Specifically, since the LDPC codeword is divided by M bits, K _ldpc information word bits are _{divided into (K ldpc} /M) bit groups, and N _ldpc -K _ldpc parity bits are (N _ldpc -K _ldpc )/ It is divided into M bit groups. Accordingly, the LDPC codeword _{can be divided into a total of (N ldpc} /M) bit groups. For example, when M=360 and the length N _ldpc of the LDPC codeword is 16200, the number of groups constituting the LDPC codeword N _group may be 45 (=16200/360), and M=360 and the LDPC code When the length of the word N _ldpc is 64800, the number of bit groups constituting the LDPC codeword N _group may be 180 (=64800/360).

As described above, the group interleaver 122 divides the LDPC codeword into the same bit group by M consecutive bits because the LDPC codeword has the same codeword characteristics in units of M consecutive bits as described above. Accordingly, when the LDPC codeword is divided into M consecutive bits, bits having the same codeword characteristics may be included in the same bit group.

Meanwhile, in the above-described example, it has been described that the number of bits constituting each bit group is M, but this is only an example, and the number of bits constituting each bit group can be variously changed.

For example, the number of bits constituting each bit group may be a factor of M. That is, the number of bits constituting each bit group may be a factor of the number of columns constituting the column group of the information word partial matrix of the parity check matrix. In this case, each bit group may consist of a divisor of M bits. For example, when the number of columns constituting the column group of the information word submatrix is 360, that is, when M = 360, the group interleaver 122 uses any one of the divisors of 360 where the number of bits constituting each bit group is The LDPC codeword can be divided into a plurality of bit groups so as to be.

However, hereinafter, for convenience of description, only the case where the number of bits constituting the bit group is M will be described.

Thereafter, the group interleaver 122 interleaves the LDPC codeword in units of bit groups. Specifically, the group interleaver 122 may group the LDPC codewords into a plurality of bit groups, and rearrange the plurality of bit groups by bit group units. That is, the group interleaver 122 may rearrange the order of the plurality of bit groups constituting the LDPC codeword in groups by changing positions of the plurality of bit groups constituting the LDPC codeword.

Here, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group units so that bit groups including bits mapped to the same modulation symbol among the plurality of bit groups are spaced apart by a preset interval.

In this case, the group interleaver 122 maps to the same modulation symbol in consideration of the number of rows and columns constituting the block interleaver 124, the number of bit groups constituting the LDPC codeword, and the number of bits included in each bit group. The order of the plurality of bit groups may be rearranged in units of bit groups so that bit groups including the bits are spaced apart by a predetermined interval.

To this end, the group interleaver 122 may rearrange the order of the plurality of groups in units of bit groups using Equation 21 below.

Here, X _j denotes the j-th bit group before group interleaving, and Y _j denotes the j-th bit group after group interleaving. In addition, π(j) is a parameter indicating an interleaving order, and may be determined by at least one of a length of an LDPC codeword, a modulation method, and a code rate.

Accordingly, X _π(j) represents the π(j)-th bit group before group interleaving, and Equation 21 means that the π(j)-th bit group before interleaving is interleaved into the j-th bit group.

Meanwhile, a specific example of π(j) according to an embodiment of the present invention may be defined as shown in Tables 11 to 22 below.

In this case, π(j) is defined according to the length and code rate of the LDPC codeword, and the parity check matrix is also defined according to the length and code rate of the LDPC codeword. Therefore, when LDPC coding is performed based on a specific parity check matrix according to the length and code rate of the LDPC codeword, the LDPC codeword is a bit group based on π(j) that satisfies the length and code rate of the LDPC codeword. It can be interleaved in units.

For example, when the encoder 110 performs LDPC encoding at a code rate of 6/15 to generate an LDPC codeword having a length of 64800, the group interleaver 122 is selected from Tables 11 to 22 below. Interleaving may be performed using π(j) defined in the LDPC codeword having a length of 64800 and a code rate of 6/15.

For example, when the length of the LDPC codeword is 64800, the code rate is 6/15, and the modulation method is 16-QAM (quadrature amplitude modulation), π(j) may be defined as shown in Table 11 below. In particular, in the case of Table 11, it can be applied when LDPC encoding is performed based on the parity check matrix defined by Table 4.

In the case of Table 11, Equation 21 is Y ₀ =X _π(0) =X ₅₅ , Y ₁ =X _π(1) =X ₁₄₆ , Y ₂ =X _π(2) =X ₈₃ ,..., Y _It can be expressed as 178 =X _π(178) =X ₁₃₂ , Y ₁₇₉ =X _π(179) =X _135. Accordingly, the group interleaver 122 sets the 55th bit group to the 0th, the 146th bit group to the 1st, the 83th bit group to the 2nd,..., the 132th bit group to the 178th, and 135 The order of the plurality of bit groups may be rearranged in units of bit groups by changing the order of the 179th bit group to the 179th bit group.

As another example, when the length of the LDPC codeword is 64800, the code rate is 8/15, and the modulation method is 16-QAM, π(j) may be defined as shown in Table 12 below. In particular, in the case of Table 12, it can be applied when LDPC encoding is performed based on the parity check matrix defined by Table 5.

For Table 12, Equation 21 is Y ₀ =X _π(0) =X ₅₈ , Y ₁ =X _π(1) =X ₅₅ , Y ₂ =X _π(2) =X ₁₁₁ ,..., Y _It can be expressed as 178 =X _π(178) =X ₁₇₁ , Y ₁₇₉ =X _π(179) =X _155. Accordingly, the group interleaver 122 sets the 58th bit group to the 0th, the 55th bit group to the 1st, the 111th bit group to the 2nd,..., the 171th bit group to the 178th, and 155 The order of the plurality of bit groups may be rearranged in units of bit groups by changing the order of the 179th bit group to the 179th bit group.

As another example, when the length of the LDPC codeword is 64800, the code rate is 10/15, and the modulation method is 16-QAM, π(j) may be defined as shown in Table 13 below. In particular, in the case of Table 13, it can be applied when LDPC encoding is performed based on the parity check matrix defined by Table 6.

For Table 13, Equation 21 is Y ₀ =X _π(0) =X ₇₄ , Y ₁ =X _π(1) =X ₅₃ , Y ₂ =X _π(2) =X ₈₄ ,..., Y _It can be expressed as 178 =X _π(178) =X ₁₅₉ , Y ₁₇₉ =X _π(179) =X _163. Accordingly, the group interleaver 122 sets the 74th bit group to the 0th, the 53rd bit group to the 1st, the 84th bit group to the 2nd,..., the 159th bit group to the 178th, and 163 The order of the plurality of bit groups may be rearranged in units of bit groups by changing the order of the 179th bit group to the 179th bit group.

As another example, when the length of the LDPC codeword is 64800, the code rate is 10/15, and the modulation method is 16-QAM, π(j) may be defined as shown in Table 14 below. In particular, in the case of Table 14, it can be applied when LDPC encoding is performed based on the parity check matrix defined by Table 7.

For Table 14, Equation 21 is Y ₀ =X _π(0) =X ₆₈ , Y ₁ =X _π(1) =X ₇₁ , Y ₂ =X _π(2) =X ₅₄ ,..., Y _It can be expressed as 178 =X _π(178) =X ₁₃₅ , Y ₁₇₉ =X _π(179) =X _24. Accordingly, the group interleaver 122 sets the 68th bit group to the 0th, the 71st bit group to the 1st, the 54th bit group to the 2nd,..., the 135th bit group to the 178th, and 24 The order of the plurality of bit groups may be rearranged in units of bit groups by changing the order of the 179th bit group to the 179th bit group.

As another example, when the length of the LDPC codeword is 64800, the code rate is 12/15, and the modulation method is 16-QAM, π(j) may be defined as shown in Table 15 below. In particular, in the case of Table 15, it can be applied when LDPC encoding is performed based on the parity check matrix defined by Table 8.

In the case of Table 15, Equation 21 is Y ₀ =X _π(0) =X ₁₂₀ , Y ₁ =X _π(1) =X ₃₂ , Y ₂ =X _π(2) =X ₃₈ ,..., Y _It can be expressed as 178 =X _π(178) =X ₁₀₁ , Y ₁₇₉ =X _π(179) =X _39. Accordingly, the group interleaver 122 sets the 120th bit group to the 0th, the 32nd bit group to the 1st, the 38th bit group to the 2nd,..., the 101th bit group to the 178th, and 39 The order of the plurality of bit groups may be rearranged in units of bit groups by changing the order of the 179th bit group to the 179th bit group.

As another example, when the length of the LDPC codeword is 64800, the code rate is 6/15, and the modulation method is 16-QAM, π(j) may be defined as shown in Table 16 below. In particular, in the case of Table 16, it can be applied when LDPC encoding is performed based on the parity check matrix defined by Table 10.

For Table 16, Equation 21 is Y ₀ =X _π(0) =X ₁₆₃ , Y ₁ =X _π(1) =X ₁₆₀ , Y ₂ =X _π(2) =X ₁₃₈ ,..., Y _It can be expressed as 178 =X _π(178) =X ₁₄₈ , Y ₁₇₉ =X _π(179) =X _98. Accordingly, the group interleaver 122 sets the 163th bit group to the 0th, the 160th bit group to the 1st, the 138th bit group to the 2nd,..., the 148th bit group to the 178th, and 98 The order of the plurality of bit groups may be rearranged in units of bit groups by changing the order of the 179th bit group to the 179th bit group.

As another example, when the length of the LDPC codeword is 64800, the code rate is 6/15, and the modulation method is 64-QAM, π(j) may be defined as shown in Table 17 below. In particular, in the case of Table 17, it can be applied when LDPC encoding is performed based on the parity check matrix defined by Table 4.

In the case of Table 17, Equation 21 is Y ₀ =X _π(0) =X ₂₉ , Y ₁ =X _π(1) =X ₁₇ , Y ₂ =X _π(2) =X ₃₈ ,..., Y _It can be expressed as 178 =X _π(178) =X ₁₁₇ , Y ₁₇₉ =X _π(179) =X _155. Accordingly, the group interleaver 122 sets the 29th bit group to the 0th, the 17th bit group to the 1st, the 38th bit group to the 2nd,..., the 117th bit group to the 178th, and 155 The order of the plurality of bit groups may be rearranged in units of bit groups by changing the order of the 179th bit group to the 179th bit group.

As another example, when the length of the LDPC codeword is 64800, the code rate is 8/15, and the modulation method is 64-QAM, π(j) may be defined as shown in Table 18 below. In particular, in the case of Table 18, it can be applied when LDPC encoding is performed based on the parity check matrix defined by Table 5.

For Table 18, Equation 21 is Y ₀ =X _π(0) =X ₈₆ , Y ₁ =X _π(1) =X ₇₁ , Y ₂ =X _π(2) =X ₅₁ ,..., Y _It can be expressed as 178 =X _π(178) =X ₁₇₄ , Y ₁₇₉ =X _π(179) =X _128. Accordingly, the group interleaver 122 is the 86th group as the 0th, the 71st bit group as the 1st, the 51st bit group as the second, ..., the 174th bit group as the 178th, and the 128th The order of the plurality of bit groups may be rearranged in units of bit groups by changing the order of the bit groups to the 179th.

As another example, when the length of the LDPC codeword is 64800, the code rate is 10/15, and the modulation method is 64-QAM, π(j) may be defined as shown in Table 19 below. In particular, in the case of Table 19, it can be applied when LDPC encoding is performed based on the parity check matrix defined by Table 6.

In the case of Table 19, Equation 21 is Y ₀ =X _π(0) =X ₇₃ , Y ₁ =X _π(1) =X ₃₆ , Y ₂ =X _π(2) =X ₂₁ ,..., Y _It can be expressed as 178 =X _π(178) =X ₁₄₉ , Y ₁₇₉ =X _π(179) =X _135. Accordingly, the group interleaver 122 sets the 73th bit group to the 0th, the 36th bit group to the 1st, the 21st bit group to the 2nd,..., the 149th bit group to the 178th, and 135 The order of the plurality of bit groups may be rearranged in units of bit groups by changing the order of the 179th bit group to the 179th bit group.

As another example, when the length of the LDPC codeword is 64800, the code rate is 10/15, and the modulation method is 64-QAM, π(j) may be defined as shown in Table 20 below. In particular, in the case of Table 20, it can be applied when LDPC encoding is performed based on the parity check matrix defined by Table 7.

In the case of Table 20, Equation 21 is Y ₀ =X _π(0) =X ₁₁₃ , Y ₁ =X _π(1) =X ₁₁₅ , Y ₂ =X _π(2) =X ₄₇ ,..., Y _It can be expressed as 178 =X _π(178) =X ₁₃₀ , Y ₁₇₉ =X _π(179) =X _176. Accordingly, the group interleaver 122 sets the 113th bit group to the 0th, the 115th bit group to the 1st, the 47th bit group to the 2nd,..., the 130th bit group to the 178th, and 176 The order of the plurality of bit groups may be rearranged in units of bit groups by changing the order of the 179th bit group to the 179th bit group.

As another example, when the length of the LDPC codeword is 64800, the code rate is 12/15, and the modulation method is 64-QAM, π(j) may be defined as shown in Table 21 below. In particular, in the case of Table 21, it can be applied when LDPC encoding is performed based on the parity check matrix defined by Table 8.

In the case of Table 21, Equation 21 is Y ₀ =X _π(0) =X ₈₃ , Y ₁ =X _π(1) =X ₉₃ , Y ₂ =X _π(2) =X ₉₄ ,..., Y _It can be expressed as 178 =X _π(178) =X ₂ , Y ₁₇₉ =X _π(179) =X _14. Accordingly, the group interleaver 122 sets the 83th bit group to the 0th, the 93th bit group to the 1st, the 94th bit group to the 2nd,..., the 2nd bit group to the 178th, and 14 The order of the plurality of bit groups may be rearranged in units of bit groups by changing the order of the 179th bit group to the 179th bit group.

As another example, when the length of the LDPC codeword is 64800, the code rate is 6/15, and the modulation method is 64-QAM, π(j) may be defined as shown in Table 22 below. In particular, in the case of Table 22, it can be applied when LDPC encoding is performed based on the parity check matrix defined by Table 10.

In the case of Table 22, Equation 21 is Y ₀ =X _π(0) =X ₁₇₅ , Y ₁ =X _π(1) =X ₁₇₇ , Y ₂ =X _π(2) =X ₁₇₃ ,..., Y _It can be expressed as 178 =X _π(178) =X ₃₁ , Y ₁₇₉ =X _π(179) =X _72. Accordingly, the group interleaver 122 sets the 175th bit group to the 0th, the 177th bit group to the 1st, the 173th bit group to the 2nd,..., the 31st bit group to the 178th, and 72 The order of the plurality of bit groups may be rearranged in units of bit groups by changing the order of the 179th bit group to the 179th bit group.

Meanwhile, in the above-described example, only cases where the length of the LDPC codeword is 64800 and the code rates are 6/15, 8/15, 10/15, and 12/15 have been described, but this is only an example, and the length of the LDPC codeword is Even in the case of 16200 or other code rates, the interleaving pattern may be variously defined.

In this way, the group interleaver 12 may rearrange the order of the plurality of bit groups in units of bit groups using Equation 21 and Tables 11 to 22.

Meanwhile, in Tables 11 to 22, "j-th block of Group-wise Interleaver output" denotes the j-th bit group output from the group interleaver 122 after interleaving, and "π(j)-th block of Group- “Wise Interleaver input” indicates a group of bits input to the group interleaver 122 for the π(j)-th.

In addition, in that the groups constituting the LDPC codeword are rearranged in bit group units by the group interleaver 122 and then block interleaved by the block interleaver 124 to be described later, π ( With respect to j), it was described as "Order of bits group to be block interleaved".

According to this method, the group-interleaved LDPC codeword is shown in FIG. 7. When comparing the LDPC codeword shown in FIG. 7 with the LDPC codeword before group interleaving shown in FIG. 6, it can be seen that the order of a plurality of bit groups constituting the LDPC codeword is rearranged.

순으로 배치되었다가, 그룹 인터리빙되어 비트 그룹 Y₀, 비트 그룹 Y₁,..., 비트 그룹

순으로 배치될 수 있다. 이 경우, 그룹 인터리빙에 의해 각 비트 그룹들이 배치되는 순서는 표 11 내지 표 22에 기초하여 결정될 수 있다.That is, as shown in FIGS. 6 and 7, the LDPC codeword is a bit group X ₀ , a bit group X ₁ ,..., a bit group before group interleaving.

Arranged in order, group interleaved, bit group Y ₀ , bit group Y ₁ ,..., bit group

They can be placed in order. In this case, the order in which each bit group is arranged by group interleaving may be determined based on Tables 11 to 22.

The group twist interleaver 123 interleaves bits within the same bit group. That is, the group twist interleaver 123 may rearrange the order of bits in the same group by changing the order of bits existing in the same bit group.

In this case, the group twist interleaver 123 cyclically shifts the bits in the same bit group by a predetermined number of bits, and rearranges the order of the bits in the same bit group.

For example, as shown in FIG. 8, the group twist interleaver 123 may cyclically shift the bits included in the bit _{group Y 1 by 1 bit in the right direction.} In this case, as shown in Fig. 8, the bits located _{at the 0th, 1st, 2nd, ..., 358th, 359th in bit group Y 1} are cyclically shifted to the right by 1 bit, and then cyclically shifted. The previous bit at the 359th position _{is located at the front of the bit group Y 1} , and the bits at the 0th, 1st, 2nd, ..., 358th before cyclic shifting are sequentially 1 bit to the right. It is shifted and positioned.

In addition, the group twist interleaver 123 cyclically shifts a different number of bits for each bit group to rearrange the order of bits in each group.

For example, the group twist interleaver 123 cyclically _{shifts the bits included in the bit group Y 1} by 1 bit in the right direction, and cyclically shifts the bits _{included in the bit group Y 2} by 3 bits in the right direction. I can.

However, the group twist interleaver 123 described above may be omitted in some cases.

Further, in the above-described example, it has been described that the group twist interleaver 123 is disposed after the group interleaver 122, but this is also only an example. That is, the group twist interleaver 123 may be disposed before the group interleaver 122 in that the order of bits constituting the corresponding bit group within the bit group is changed, and the order of the bit group itself is not changed.

The block interleaver 124 interleaves a plurality of bit groups in which the order is rearranged. Specifically, the block interleaver 124 may interleave a plurality of bit groups in which the order of bit groups is rearranged by the group interleaver 122 in bit group units. Here, the block interleaver 124 is composed of a plurality of columns each including a plurality of rows, and interleaving by dividing a plurality of bit groups rearranged based on a modulation order determined according to a modulation method. can do.

In this case, the block interleaver 124 may interleave a plurality of bit groups in which the order of the bit groups is rearranged by the group interleaver 122 in bit group units. Specifically, the block interleaver 124 includes a first part ( A plurality of bit groups rearranged using part 1) and part 2 may be classified according to a modulation order to be interleaved.

Specifically, the block interleaver 124 divides each of a plurality of columns into a first part and a second part, and sequentially writes a plurality of bit groups to a plurality of columns constituting the first part in bit group units. , The bits constituting the remaining bit groups are divided into sub bits groups each composed of a preset number of bits based on the number of columns, and the divided sub bit groups are sequentially divided into a plurality of columns constituting the second part. Interleaving can be performed by writing to.

Here, the number of groups interleaved in bit group units may be determined according to at least one of the number of rows and columns constituting the block interleaver 124, the number of bit groups, and the number of bits included in each bit group. That is, the block interleaver 124 interleaves in a bit group unit among a plurality of bit groups in consideration of at least one of the number of rows and columns constituting the block interleaver 124, the number of bit groups, and the number of bits included in each bit group. A bit group to be used may be determined, a corresponding bit group may be interleaved in bit group units, and bits constituting the remaining bit groups may be collected and divided into sub bit groups for interleaving. For example, the block interleaver 124 may interleave at least a part of a plurality of bit groups using a first part in bit group units, and divide the remaining bit groups using a second part to perform interleaving.

Meanwhile, interleaving by bit group means that bits included in the same bit group are written to the same column. That is, the block interleaver 124 writes the bits included in the same bit group to the same column without dividing the bits included in the same bit group in case of a bit group interleaved in a bit group unit, and includes a bit group in the bit group that is not interleaved in a bit group unit. Interleaving can be performed by dividing the generated bits and writing them to different columns.

Accordingly, the number of rows constituting the first part is a multiple of the number of bits included in one bit group (for example, 360), and the number of rows constituting the second part is less than the number of bits included in one group. I can.

In addition, all bit groups interleaved by the first part are interleaved by writing bits included in the same bit group to the same column of the first part, and at least one bit group interleaved by the second part constitutes a second part. It can be divided into at least two columns and lighted.

Details of this interleaving method will be described later.

Meanwhile, the interleaving performed by the group twist interleaver 123 only changes the order of bits within the bit group, and the order of the bit group itself is not changed by interleaving. Accordingly, the order of the bit groups block interleaved by the block interleaver 124, that is, the order of the bit groups input to the block interleaver 124 may be determined by the group interleaver 122. For example, the order of the bit groups block-interleaved by the block interleaver 124 may be determined by π(j) defined in Tables 11 to 22.

As described above, the block interleaver 124 may interleave a plurality of bit groups, in which the order is rearranged, in a bit group unit, using a plurality of columns each consisting of a plurality of rows.

In this case, the block interleaver 124 may interleave the LDPC codeword by dividing the plurality of columns into at least two parts. For example, the block interleaver 124 may interleave a plurality of bit groups constituting the LDPC codeword by dividing each of a plurality of columns into a first part and a second part.

In this case, the block interleaver 124 divides each of the plurality of columns N (N is an integer of 2 or more) depending on whether the number of bit groups constituting the LDPC codeword is an integer multiple of the number of columns constituting the block interleaver 124. Interleaving can be performed by dividing into parts of ).

First, when the number of bit groups constituting the LDPC codeword is an integer multiple of the number of columns constituting the block interleaver 124, the block interleaver 124 configures the LDPC codeword without dividing parts into each of the plurality of columns. A plurality of bit groups to be interleaved may be interleaved in units of bit groups.

Specifically, the block interleaver 124 writes a plurality of bit groups constituting the LDPC codeword in a column direction to each column in bit group units, and writes each row of a plurality of columns in which the plurality of bit groups are written in bit group units. Interleaving can be performed by reading in the row direction.

In this case, the block interleaver 124 divides the number of bit groups constituting the LDPC codeword by the number of columns constituting the block interleaver 124 and divides the bits included in the bit group into each of the plurality of columns. Interleaving may be performed by sequentially writing in a column direction and reading each row of a plurality of columns to which bits are written in a row direction.

Hereinafter, for convenience of description, a bit group positioned at the j-th after being interleaved by the group interleaver 122 is referred to as bit group Y _j .

For example, it is assumed that the block interleaver 124 is _{composed of C columns including R 1 row.} Then, the LDPC code being configured by N-bit _group of the group eoga, it is assumed to be a multiple of the number of bit _group is a group N C.

In this case, if the quotient of the number of bit groups constituting the LDPC codeword N _group divided by the number C of columns constituting the block interleaver 124 is A (=N _group /C) (A is an integer greater than 0), The block interleaver 124 may perform interleaving _{by sequentially writing A (=N group} /C) bit groups in each column in a column direction and reading bits written in each column in a row direction.

For example, as shown in Figure 9, a block interleaver 124 bit group (Y ₀₎ from the first row of the first column R ₁ th row, the bit group (Y _1), ..., a group (Y _{A 1)} light the bits included in, respectively, the (Y 1 _{a +1} th row from the first row R ₁ bit group (Y _a), the bit group of the second column), ..., bit group (Y _{2A -1)} bit group (Y _{-A CA),} the bit group (Y _{CA -A + 1)} from the light and the bits included in respective, ..., 1-th row of the column C row R ₁ ,. .., bits _{included in each of the bit groups Y CA -1} can be written, and bits written in each row of a plurality of columns can be read in a row direction.

Accordingly, the block interleaver 124 interleaves all bit groups constituting the LDPC codeword in bit group units.

However, when the number of bit groups constituting the LDPC codeword is not an integer multiple of the number of columns constituting the block interleaver 124, the block interleaver 124 divides each of the plurality of columns into two parts, Some of the plurality of bit groups constituting a may be interleaved in bit group units, and bits constituting the remaining bit groups may be collected and divided into sub bit groups for interleaving. In this case, the bits included in the remaining bit group, that is, the bits included in the bit group as much as the remainder when the number of groups constituting the LDPC codeword is divided by the number of columns, are interleaved in bit group units. Rather, it may be divided into each column and interleaved according to the number of columns.

Specifically, the block interleaver 124 may interleave the LDPC codeword by dividing each of the plurality of columns into two parts.

In this case, the block interleaver 124 first selects a plurality of columns based on the number of columns constituting the block interleaver 124, the number of bit groups constituting the LDPC codeword, and the number of bits constituting each of the plurality of bit groups. It can be divided into a part and a second part.

Here, each of the plurality of bit groups may consist of 360 bits. In addition, the number of bit groups constituting the LDPC codeword is determined according to the length of the LDPC codeword and the number of bits included in each bit group.

For example, if an LDPC codeword with a length of 16200 is divided so that each bit group consists of 360 bits, the LDPC codeword is divided into 45 bit groups, and an LDPC codeword with a length of 64800 is composed of 360 bits in each bit group. If possible, the DPC codeword can be divided into 180 bit groups. In addition, the number of columns constituting the block interleaver 124 may be determined according to a modulation method, and a specific example related thereto will be described later.

Accordingly, the number of rows constituting each of the first part and the second part is the number of columns constituting the block interleaver 124, the number of bit groups constituting the LDPC codeword, and bits constituting each of the plurality of bit groups. It can be determined based on the number.

Specifically, in each of the plurality of columns, the first part configures the LDPC codeword according to the number of columns constituting the block interleaver 124, the number of bit groups constituting the LDPC codeword, and the number of bits constituting each bit group. The plurality of columns of the plurality of bit groups may be composed of as many rows as the number of bits included in at least one bit group that can be written in bit group units.

In addition, the second part is composed of rows excluding rows as many as the number of bits included in at least some bit groups that can be written to each of the plurality of columns in bit group units in each of the plurality of columns. Can be. Specifically, the number of rows of the second part may have the same value as the quotient obtained by dividing the number of bits included in all bit groups except for the bit group corresponding to the first part by the number of columns constituting the block interleaver 124. have. That is, the number of rows of the second part may have the same value as a quotient obtained by dividing the number of bits included in the remaining bit groups after being written to the first part of the bit groups constituting the LDPC codeword by the number of columns.

Meanwhile, the block interleaver 124 includes a first part including a number of rows as many as the number of bits included in a bit group that can be written in each bit group unit in each column, and a second part including the remaining rows. Each of the plurality of columns can be distinguished.

Accordingly, the first part may be composed of rows as many as the number of bits included in the bit group, that is, an integer multiple of M. However, as described above, since the number of codeword bits constituting each bit group can be a factor of M, the first part is composed of rows equal to an integer multiple of the number of bits constituting each bit group. It could be.

In this case, the block interleaver 124 may perform interleaving by writing and reading the LDPC codeword in the first part and the second part in the same manner.

Specifically, the block interleaver 124 writes the LDPC codeword in a column direction to a plurality of columns constituting each of the first part and the second part, and a plurality of the LDPC codewords constituting each of the first part and the second part to which the LDPC codeword is written. Interleaving can be performed by reading the columns of in the row direction.

That is, the block interleaver 124 sequentially writes bits included in at least some bit groups that can be written in bit group units in each of the plurality of columns to each of the plurality of columns constituting the first part, and By dividing the bits included in the remaining bit groups except at least some bit groups, writing them in a column direction to each of the plurality of columns constituting the second part, and each of the plurality of columns constituting each of the first part and the second part Interleaving may be performed by reading the bits written in the row direction.

In this case, the block interleaver 124 may perform interleaving by dividing the remaining bit groups excluding at least some bit groups from the plurality of groups based on the number of columns constituting the block interleaver 124.

Specifically, the block interleaver 124 divides the bits included in the remaining bit groups into a plurality of columns, writes each of the divided bits to each of the plurality of columns constituting the second part in a column direction, and Interleaving may be performed by reading a plurality of columns constituting the second part to which bits are written in a row direction.

That is, the block interleaver 124 writes to the first part of the plurality of bit groups constituting the LDPC codeword, and the remaining bit groups, that is, the remaining bit groups, when the number of groups constituting the LDPC codeword is divided by the number of columns. ) Bits included in the bit group may be divided by the number of columns, and the divided bits may be sequentially written to each column of the second part in the column direction.

For example, it is assumed that the block interleaver 124 is _{composed of C columns including R 1 row.} And being configured LDPC code with N _group of bit groups eoga, is not a multiple of the number of N _group are C of groups of bits, A × C + 1 = is assumed a case where the N _group (A is an integer greater than 0) . That is, when the number of bit groups constituting the LDPC codeword is divided by the number of columns, it is assumed that the quotient is A and the remainder is 1.

In this case, the block interleaver 124 may be divided into a second part including a first part and R ₂ rows of each column stores the _first row R as shown in Figs. In this case, R ₁ may be as many as the number of bits included in a bit group that can be written in bit group units in each column, and R ₂ may be a value excluding _{R 1} from the number of rows constituting each column.

That is, in the above-described example, the number of groups that can be written to each column in bit group units is A, and the first part of each column may be composed of the number of bits included in the A group, that is, A×M rows.

In this case, the block interleaver 124 writes bits included in groups that can be written to each column in a group unit, that is, groups of A, in the column direction to the first part of each column.

That is, a block interleaver 124 as shown in Figures 10 and 11 the first column, the first part 1 bit group (Y ₀₎ from the first row R _1, the second row, the bit group (Y _1), constituting a. ., groups of bits _{(Y a -1) (Y a} ) and light the bits included in each of the second bit group into a first part from the first row R ₁ column of the second line constituting the bit group (Y _{a +1),} ..., bit group (Y _{-1 2A)} and light the bits included in respective, ..., the first row from the first row R ₁ bit group constituting a first part of the column C Bits included in each of (Y _{CA -A} ), bit group (Y _{CA -A+1} ),... and bit group (Y _{CA -1) are written.}

In this way, the block interleaver 124 writes the bits included in the bit group, which can be written in each column in bit group units, to the first part of each column in group units.

That is, in the above-described example, the bits _{included in each of the bit group (Y 0} ), the bit group (Y ₁ ), ..., and the bit group (Y _{A -1} ) are not divided and are all written to the first column, Bits included in each of the bit group (Y _A ), bit group (Y _{A +1} ),..., bit group (Y _{2A -1} ) are not divided and are all written to the second column, ..., bit Bits included in each of the group (Y _{CA -A} ), the bit group (Y _{CA -A+1} ), ..., and the bit group (Y _{CA -1} ) may be written to the Cth column without being divided. In this way, in all bit groups interleaved by the first part, it can be seen that bits included in the same bit group are written to the same column of the first part.

Thereafter, the block interleaver 124 may divide bits included in the remaining bit groups excluding the group written to the first part of each column among the plurality of bit groups, and write the bits included in the second part of each column in the column direction. At this time, the block interleaver 124 divides the bits included in the remaining bit groups excluding the group written to the first part of each column by the number of columns so that the same number of bits is written to the second part of each column, Bits may be lit in each column of the second part in the column direction.

)가 제1 파트에 라이트되지 못하고 남게 된다. 이에 따라, 블록 인터리버(124)는 도 10과 같이 비트 그룹(

)에 포함된 비트들을 C 개로 분할하고, 분할된 각 비트들(즉, 마지막 비트 그룹(

)에 포함된 비트들 C로 나눈 몫만큼의 비트들)을 각 열의 제2 파트에 순차적으로 라이트할 수 있다. In the above example, since A×C+1=N _group is satisfied, when the bit groups constituting the LDPC codeword are sequentially written to the first part, the group, which is the last bit group of the LDPC codeword (

) Is not lighted on the first part and remains. Accordingly, the block interleaver 124 is a bit group (

The bits included in) are divided into C, and each of the divided bits (i.e., the last bit group (

Bits equal to the quotient divided by bits C included in )) may be sequentially written to the second part of each column.

Here, each of the bits divided based on the number of columns may be referred to as a sub-bit group. In this case, it can be seen that each sub-bit group is written to each column of the second part. That is, bits included in the bit group may be divided to form a sub bit group.

That is, a block interleaver 124 from the first line to write a bit from the first line constituting the second part of the first column to the R _2-th row, and constituting a second part of the second column R ₂ row to write the bits, ..., it is possible to write a bit to the _second R-th row in the first line constituting the second part of the C column. In this case, the block interleaver 124 may write bits to the second part of each column in the column direction as shown in FIG. 10.

)은 M 개의 비트들로 구성되므로, 마지막 비트 그룹(

)에 포함된 비트들은 M/C 개씩 분할되어 각 컬럼에 라이트될 수 이다. 즉, 마지막 비트 그룹(

)에 포함된 비트들은 M/C 개씩 분할되고, 분할된 M/C 개씩 서브 비트 그룹을 형성하며, 서브 비트 그룹 각각이 제2 파트의 각 열에 라이트될 수 있다.That is, in the second part, bits constituting a bit group are not written to the same column, but may be written to a plurality of columns. That is, in the above example, the last bit group (

) Consists of M bits, so the last bit group (

The bits included in) can be divided into M/C pieces and written to each column. That is, the last bit group (

The bits included in) are divided into M/C pieces, each divided M/C pieces form a sub-bit group, and each sub-bit group may be written to each column of the second part.

Accordingly, the at least one bit group interleaved by the second part may be viewed as being written by dividing the bits included in the at least one bit group into at least two columns constituting the second part.

Meanwhile, in the above-described example, it has been described that the block interleaver 124 writes bits to the second part in the column direction, but this is only an example. That is, the block interleaver 124 may write bits to a plurality of columns of the second part in a row direction. In this case, the block interleaver 124 may write bits for the first part in the same manner as described above.

Specifically, referring to FIG. 11, the block interleaver 124 writes bits from the first row constituting the second part in the first column to the first row constituting the second part in the Cth column, and the first column R 2 from the _second line constituting a second part in the second light, the bits from the second line to the second line constituting a second part in the C column, ..., and a first column constituting a part in the it is possible to write a bit to the second row R ₂ constituting the second part in the C column.

Meanwhile, the block interleaver 124 sequentially reads the bits written to each row of each part in the row direction. That is, the block interleaver 124 sequentially reads the bits written to each row of the first part of a plurality of columns in the row direction, and the bits written to each row of the second part of the plurality of columns, as shown in FIGS. 10 and 11. They can be sequentially read in the row direction.

Accordingly, the block interleaver 124 may perform interleaving by interleaving some of the plurality of bit groups constituting the LDPC codeword in bit group units, and dividing the rest of the bit groups. That is, the block interleaver 124 writes the LDPC codewords constituting a predetermined number of bit groups among the plurality of bit groups in a bit group unit to a plurality of columns constituting the first part, and writes the bits constituting the remaining bit groups. Interleaving may be performed by collectively dividing and writing each column constituting the second part, and reading a plurality of columns constituting the first and second parts in a row direction.

In this way, the block interleaver 124 may interleave a plurality of bit groups using the method described with reference to FIGS. 9 to 11.

In particular, in the case of FIG. 10, bits included in a bit group not belonging to the first part are written in a column direction and read in a row direction to the second part, so the order of the bits included in the bit group not belonging to the first part Can be redefined. As described above, since bits included in a bit group that do not belong to the first part are interleaved, bit error rate (BER)/frame error rate (FER) performance may be improved compared to a case where interleaving is not performed.

However, as shown in FIG. 11, bit groups that do not belong to the first part may not be interleaved. That is, as shown in FIG. 11, the block interleaver 124 writes and reads bits included in the bit group not belonging to the first part in the row direction to the second part. The bits may be sequentially output to the modulator 130 without changing the order. In this case, bits included in a bit group that do not belong to the first part may be sequentially output and mapped to a modulation symbol.

Meanwhile, in FIGS. 10 and 11, it has been described that the last one bit group among a plurality of bit groups is written to the second part, but this is only an example, and the number of groups written to the second part constitutes an LDPC codeword. It goes without saying that it can be changed in various ways depending on the total number of groups, the number of columns and rows, and the number of transmit antennas.

Meanwhile, the block interleaver 124 may have a structure as shown in Tables 23 and 24 below.

Here, C (or N _c ) is the number of columns constituting the block interleaver 124, R ₁ is the number of rows constituting the first part in each column, and R ₂ is the second part constituting each column. Is the number of rows to do.

Referring to Tables 23 and 24, the number of columns has the same value as the modulation order according to the modulation method, and each of the plurality of columns consists of rows as many as the number of bits constituting the LDPC codeword divided by the number of columns. I can see that it is.

For example, when the length of the LDPC codeword N _ldpc =64800 and modulation is performed in the 16-QAM method, the modulation order is 4 in the case of 16-QAM, so the block interleaver 124 consists of 4 columns, and each column It can be seen that is composed of R ₁ + R ₂ =16200 (=64800/4) rows. As another example, when the length of the LDPC codeword N _ldpc =64800 and modulation is performed in the 64-QAM method, the modulation order is 6 in the case of 64-QAM, so the block interleaver 124 consists of 6 columns, and each column is It can be seen that it consists of R ₁ + R ₂ =10800 (=64800/6) rows.

On the other hand, with reference to Table 23 and Table 24, when the number of groups of bits constituting the LDPC codeword times the integer number of columns, the block interleaver 124 is R ₁ in that it performs the interleaving without separating each column It becomes the number of rows constituting each column, and R ₂ =0. On the contrary, if the number of the group constituting the LDPC codeword that is not an integral multiple of the number of the columns, the block interleaver 124 is first composed of the first part and R ₂ rows which make up each column to the R ₁ rows Interleaving is performed by dividing it into 2 parts.

Meanwhile, as shown in Tables 23 and 24, when the number of columns of the block interleaver 124 is the same as the number of bits constituting a modulation symbol, bits included in the same bit group may be mapped to one bit in the modulation symbol. .

For example, when N _ldpc =64800 and the modulation scheme is 16-QAM, the block interleaver 124 may be configured with 4 columns each including 16200 rows. In this case, bits included in each of the plurality of bit groups are written to four columns, and bits that have been written to the same row in each column are sequentially output. In this case, when the modulation method is 16-QAM, since 4 bits constitute one modulation symbol, bits included in the same bit group, that is, bits output from one column, are mapped to one bit in the modulation symbol. I can. For example, bits included in a group written to the first column may be mapped to the first bit of each modulation symbol.

As another example, when N _ldpc =64800 and the modulation scheme is 64-QAM, the block interleaver 124 may be configured with 6 columns each including 10800 rows. In this case, bits included in each of the plurality of bit groups are written to six columns, and bits that have been written to the same row in each column are sequentially output. In this case, if the modulation method is 64-QAM, since 6 bits constitute one modulation symbol, bits included in the same bit group, that is, bits output from one column, are mapped to one bit in the modulation symbol. I can. For example, bits included in a group written to the first column may be mapped to the first bit of each modulation symbol.

Meanwhile, referring to Tables 23 and 24, it can be seen that the total number of rows of the block interleaver 124, that is, R ₁ +R ₂ is N _{ldpc /C.}

이고, 제2 파트의 행의 개수인 R₂는 N_ldpc/C-R₁이 될 수 있다. 여기에서,

는 N_group/C 이하의 가장 큰 정수를 나타낸다. 이와 같이, R₁은 각 비트 그룹에 포함된 비트의 개수인 M의 정수 배가 된다는 점에서, R₁에는 비트 그룹 단위의 비트들이 라이트될 수 있다. _{And, R 1, which} is the number of rows of the first part, is an integer multiple of M (eg, M=360), which is the number of bits included in each group.

_{And R 2, which} is the number of rows of the second part, may be _{N ldpc} /CR _1. From here,

_Represents the largest integer of N group /C or less. In this way, since R ₁ is an integer multiple of M, which is the number of bits included in each bit group, bits of a bit group unit may be written to _{R 1.}

In addition, referring to Tables 23 and 24, when the number of bit groups constituting the LDPC codeword is not a multiple of the number of columns, the block interleaver 124 divides each column into two parts and performs interleaving. Able to know.

Specifically, a value obtained by dividing the length of the LDPC codeword by the number of columns is the number of total rows included in each column. In this case, when the number of bit groups constituting the LDPC codeword is a multiple of the number of columns, each column is not divided into two parts. However, when the number of bit groups constituting the LDPC codeword is not a multiple of the number of columns, each column may be divided into two parts.

For example, as shown in Table 23, it is assumed that the number of columns of the block interleaver 124 is the same as the number of bits constituting the modulation symbol, and the LDPC codeword is composed of 64800 bits. At this time, each bit group constituting the LDPC codeword is composed of 360 bits, and the LDPC codeword is composed of 64800/360=180 bit groups.

On the other hand, when the modulation scheme is 16-QAM, the block interleaver 124 may consist of 4 columns, and each column may consist of 64800/4=16200 rows.

In this case, since a value obtained by dividing the number of bit groups constituting the LDPC codeword by the number of columns is 180/4=45, bits can be written to each column in bit group units without dividing each column into two parts. That is, bits included in 45 bit groups, that is, 45×360=16200 bits, which are the quotient obtained by dividing the number of bit groups constituting the LDPC codeword by the number of columns, may be written to each column.

However, when the modulation scheme is 256-QAM, the block interleaver 124 may be composed of eight columns, and each column may be composed of 64800/8=8100 rows.

At this time, since the number of bit groups constituting the LDPC codeword divided by the number of columns is 180/8=22.5, the number of bit groups constituting the LDPC codeword is not an integer multiple of the number of columns. Accordingly, the block interleaver 124 divides each of the eight columns into two parts in order to perform interleaving in units of a bit group.

At this time, since bits must be written in bit group units to the first part of each column, the number of bit groups that can be written in bit group units to the first part of each column is the number of groups constituting the LDPC codeword as the number of columns. There are 22 divided quotients, and accordingly, the first part of each column may consist of 22×360=7920 rows. Accordingly, 7920 bits included in 22 bit groups may be written to the first part of each column.

On the other hand, the second part of each column is composed of rows excluding the row constituting the first part from all rows of each column. Accordingly, the second part of each column may consist of 8100-7920=180 rows.

In this case, bits included in the remaining bit groups that have not been written to the first part may be divided and written to the second part of each column.

Specifically, since 22×8=176 bit groups are written to the first part, the number of bit groups to be written to the second part is 180-176=4 (e.g., bit groups constituting the LDPC codeword (Y ₀ ), bit group (Y ₁ ), bit group (Y ₂ ),..., bit group (Y ₁₇₈ ), bit group (Y ₁₇₉ ) of bit group (Y ₁₇₆ ), bit group (Y ₁₇₇ ), bit group (Y ₁₇₈ ), may be a bit group (Y _{179 )).}

Accordingly, the block interleaver 124 may sequentially write the remaining 4 bit groups to the second part of each column after being written to the first part of the group constituting the LDPC codeword.

That is, the block interleaver 124 writes _{180 bits out of 360 bits included in the bit group (Y 176} ) in the column direction from the first row to the 180th row of the second part of the first column, and the remaining 180 bits May be lit in the column direction from the first row to the 180th row of the second part of the second column. In addition, the block interleaver 124 writes _{180 bits out of 360 bits included in the bit group Y 177} in the column direction from the first row to the 180th row of the second part of the third column, and the remaining 180 bits May be lit in the column direction from the first row to the 180th row of the second part of the fourth column. In addition, the block interleaver 124 writes _{180 bits out of 360 bits included in the bit group Y 178} in the column direction from the first row to the 180th row of the second part of the fifth column, and the remaining 180 bits May be lit in the column direction from the first row to the 180th row of the second part of the sixth column. In addition, the block interleaver 124 writes _{180 bits out of 360 bits included in the bit group Y 179} in the column direction from the 1st row to the 180th row of the second part of the 7th column, and the remaining 180 bits May be lit in the column direction from the first row to the 180th row of the second part of the eighth column.

Accordingly, bits included in the bit group remaining after being written to the first part may not be written to the same column in the second part, but may be divided and written into a plurality of columns.

Hereinafter, a specific example of the block interleaver 124 of FIG. 5 will be described in more detail with reference to FIG. 12.

)는 V={Y₀,Y₁,...,

}과 같이 Y_j가 연속적으로 배치될 수 있다. Group interleaved LDPC codeword (v ₀ ,v ₁ ,...,

) Is V=(Y ₀ ,Y ₁ ,...,

As in }, Y _j can be arranged continuously.

After group interleaving, the LDPC codeword may be interleaved by the block interleaver 124 as shown in FIG. 12. In this case, the block interleaver 124 may divide a plurality of columns into a first part and a second part based on the number of columns constituting the block interleaver 124 and the number of bits of the bit group. In this case, bits constituting a bit group may be written in the same column in the first part, and bits constituting the bit group may be written in a plurality of columns in the second part.

Specifically, the input bit vi is sequentially written from the first part to the second part in a column wise direction, and sequentially read from the first part to the second part in a row direction. do. Accordingly, bits included in the same bit group in the first part may be mapped to one bit in each modulation symbol.

)은 360의 배수이므로, 복수의 비트 그룹이 제1 파트에 라이트될 수 있다. In this case, the number of columns and the number of rows of the first part and the second part of the block interleaver 124 according to the modulation method and the length of the LDPC codeword (ie, code length) may be as shown in Table 25 below. Here, the number of columns of the block interleaver 124 may be the same as the number of bits constituting the modulation symbol. In addition, the sum of the number of rows of the first part _{N r1 and the number of rows of the second part N r2} is equal to N _ldpc /N _c (here, N _c is the number of columns). And, N _r1 (=

) Is a multiple of 360, so a plurality of bit groups may be written to the first part.

Hereinafter, the operation of the block interleaver 124 will be described in more detail.

, r_i=(i mod N_r1)와 같다.Specifically, as shown in FIG. 12, the input bit v _i (0≦i<N _c ×N _r1 ) is written to the r _{i row of the c i} column of the first part of the block interleaver 124. Where c _i and r _i are respectively

and r _i =(i mod N _r1 ).

, r_i=N_r1+{(i-N_c×N_r1) mod N_r2}와 같다.Then, the input bits, _{v i (N c × N r1} ≤i <N ldpc) are written into the second part of the column c _i r _i rows of the block interleaver (124). Where c _i and r _i are respectively

, r _i =N _r1 +{(iN _c ×N _r1 ) mod N _r2 }.

, c_j=(j mod N_c)와 같다.On the other hand, the output bit q _{j (0≦} j<N ldpc) is read in the c _{j column of the r j row.} Here, c _j and r _j are respectively

, c _j = (j mod N _c ).

For example, when the length N _ldpc of the LDPC codeword is 64800 and the modulation method is 256-QAM, the order of bits output from the block interleaver 124 is (q ₀ ,q ₁ ,q ₂ ,..., q ₆₃₃₅₇ ,q ₆₃₃₅₈ ,q ₆₃₃₅₉ ,q ₆₃₃₆₀ ,q ₆₃₃₆₁ ,...,q ₆₄₇₉₉ )=(v ₀ ,v ₇₉₂₀ ,v ₁₅₈₄₀ ,...,v ₄₇₅₁₉ ,v ₅₅₄₃₉ ,v ₆₃₃₅₉ ,v ₆₃₃₆₀ ,v ₆₃₅₄₀ ,...,v ₆₄₇₉₉ ). Here, if the index in the right term is expressed in more detail for all eight columns, 0, 7920, 15840, 23760, 31680, 39600, 47520, 55440, 1, 7921, 15841, 23761, 31681, 39601, 47521, 55441,… … , 7919, 15839, 23759, 31679, 39599, 47519, 55439, 63359, 63360, 63540, 63720, 63900, 64080, 64260, 64440, 64620, ... … , 63539, 63719, 63899, 64079, 64259, 64439, 64619, 64799.

Hereinafter, for a specific example, an interleaving operation of the block interleaver 124 will be described.

The block interleaver 124 writes a plurality of bit groups in a column direction to each column in bit group units, and reads each row of a plurality of columns in which a plurality of bit groups are written in bit group units in a row direction to perform interleaving. I can.

In this case, the number of columns constituting the block interleaver 124 may vary according to a modulation method, and the number of rows may be the length/number of columns of LDPC codewords.

For example, when the modulation scheme is 16-QAM, the block interleaver 124 may be configured with four columns. _{In this case, when the length N ldpc} of the LDPC codeword is 64800, the number of rows may be 64800/4=16200. As another example, when the modulation scheme is 64-QAM, the block interleaver 124 may be configured with six columns. _{In this case, when the length N ldpc} of the LDPC codeword is 64800, the number of rows may be 64800/6=10800.

Hereinafter, a method of interleaving a plurality of bit groups in a bit group unit by the block interleaver 124 will be described in detail.

When the number of bit groups constituting the LDPC codeword is an integer multiple of the number of columns, the block interleaver 124 interleaves by sequentially writing bit groups equal to the value obtained by dividing the number of bit groups by the number of columns into each column. You can do it.

For example, when the modulation scheme is 16-QAM and the length N _ldpc of the LDPC codeword is 64800, the block interleaver 124 may be configured with 4 columns each including 16200 rows. Here, when the length N _ldpc of the LDPC codeword is 64800, the LDPC codeword is divided into 64800/360=180 bit groups, so when the modulation method is 16-QAM, the number of bit groups constituting the LDPC codeword (=180 ) Is an integer multiple of the number of columns (=4). That is, when the number of bit groups constituting the LDPC codeword is divided by the number of columns, the remainder does not occur.

In this case, as shown in FIG. 13, the block interleaver 124 includes a bit group (Y ₀ ), a bit group (Y ₁ ), ..., and a bit group (Y ₄₄ ) in the 16200th row from the first row of the first column. The bits included in the second column are written, and the bits included in each of the bit group (Y ₄₅ ), the bit group (Y ₄₆ ), ..., and the bit group (Y ₈₉ ) are written from the first row to the 16200th row of the second column. Writes, and writes the bits included in each of the _{bit group (Y 90} ), bit group (Y ₉₁ ), ..., bit group (Y ₁₃₄ ) from the first row to the 16200th row of the third column, and the fourth Bits included in each of the _{bit group (Y 135} ), the bit group (Y ₁₃₆ ), ..., and the bit group (Y ₁₇₉ ) are written to the 16200th row from the first row of the column. In addition, the block interleaver 124 may sequentially read bits written in each row of two columns in a row direction.

As another example, when the modulation scheme is 64-QAM and the length N _ldpc of the LDPC codeword is 64800, the block interleaver 124 may be configured with 6 columns each including 10800 rows. Here, when the length N _ldpc of the LDPC codeword is 64800, the LDPC codeword is divided into 64800/360=180 bit groups, so when the modulation method is 64-QAM, the number of bit groups constituting the LDPC codeword (=180 ) Is an integer multiple of the number of columns (=4). That is, when the number of bit groups constituting the LDPC codeword is divided by the number of columns, the remainder does not occur.

In this case, as shown in FIG. 14, the block interleaver 124 includes a bit group (Y ₀ ), a bit group (Y ₁ ), ..., and a bit group (Y ₂₉ ) in the first row to the 10800th row of the first column. The bits included in are written, and the bits included in each of the bit group (Y ₃₀ ), the bit group (Y ₃₁ ),..., and the bit group (Y ₅₉ ) are written from the first row to the 10800th row of the second column. Write, write the bits included in each of the _{bit group (Y 60} ), the bit group (Y ₆₁ ), ..., and the bit group (Y ₈₉ ) to the 10800th row from the first row of the third column, and the fourth _{Write the bits included in each of the bit group (Y 90} ), bit group (Y ₉₁ ),..., and bit group (Y ₁₁₉ ) to the 10800th row from the 1st row of the column, and the 1st row of the 5th column Write the bits included in each of the bit group (Y ₁₂₀ ), bit group (Y ₁₂₁ ),..., and bit group (Y ₁₄₉ ) to the 10800th row, and from the 1st row to the 10800th row of the 6th column. Bits included in each of the bit group (Y ₁₅₀ ), bit group (Y ₁₅₁ ),..., and bit group (Y _{179) are written.} In addition, the block interleaver 124 may sequentially read bits written in each row of two columns in a row direction.

In this way, when the number of bit groups constituting the LDPC codeword is an integer multiple of the number of columns constituting the block interleaver 124, the block interleaver 124 interleaves a plurality of bit groups in groups, and accordingly, Bits belonging to the same bit group may be written to the same column.

As described above, the block interleaver 124 may interleave a plurality of bit groups constituting the LDPC codeword using the method described with reference to FIGS. 13 and 14.

The modulator 130 maps the interleaved LDPC codeword to a modulation symbol. Specifically, the modulator 130 may demultiplex the interleaved LDPC codeword, modulate the demultiplexed LDPC codeword, and map the demultiplexed LDPC codeword to a constellation.

In this case, the modulator 130 may generate a modulation symbol using bits included in each of the plurality of bit groups.

That is, as described above, bits included in different bit groups are written to each column of the block interleaver 124, and the block interleaver 124 reads the bits written to each column in a row direction. In this case, the modulator 130 maps the bits read from each column of the block interleaver 124 to each bit of the modulation symbol to generate a modulation symbol. Accordingly, each bit of the modulation symbol may be a bit included in a different bit group.

For example, it is assumed that the modulation symbol is composed of C bits. In this case, since the bits read from each row of C columns of the block interleaver 124 can be mapped to each bit of the modulation symbol, in the end, each bit of the modulation symbol composed of C bits is C different bit groups. It can be the bits included in.

Hereinafter, this will be described in more detail.

First, the modulator 130 may demultiplex the interleaved LDPC codeword. To this end, the modulator 130 may include a demultiplexer (not shown) for demultiplexing the interleaved LDPC codeword.

A demultiplexer (not shown) demultiplexes the interleaved LDPC codeword. Specifically, the demultiplexer (not shown) performs serial-to-parallel transformation on the interleaved LDPC codeword, and converts the interleaved LDPC codeword into a cell having a certain number of bits ( Alternatively, it may be demultiplexed into a data cell (data dcell).

For example, as shown in FIG. 15, the demultiplexer (not shown) receives the LDPC codeword Q=(q ₀ ,q ₁ ,q ₂ ,...) output from the interleaver 120, and the input LDPC codeword bits They may be sequentially output to each of a plurality of sub-streams, converting the input LDPC codeword bits into cells, and outputting them.

In this case, bits having the same index in each of the plurality of sub-streams may constitute the same cell. Accordingly, each cell is (y _{0 ,0} ,y _{1 ,0} ,...,y _{η MOD -1,0} )=(q ₀ ,q ₁ ,...,q _ηMOD-1 ), (y _{0 ,1} ,y _{1 ,1} ,...,y _{η MOD -1,1} )=(q _{η MOD} ,q _{η MOD +1} ,...,q _{2 ×η MOD -1} ),... Can be configured.

Meanwhile, the number of _substreams N substreams is equal to the number of bits constituting the modulation symbol η _MOD. Accordingly, the number of bits constituting each cell may be equal to the number of bits constituting a modulation symbol (ie, a modulation order).

For example, if the modulation scheme is 16-QAM, _{since the number of bits constituting the modulation symbol η MOD} =4, the number of _substreams N substreams =4, and each of the cells is (y _0,0 ,y _{1 ,0} ,y _2,0 ,y _3,0 )=(q ₀ ,q ₁ ,q ₂ ,q ₃ ), (y _{0 ,1} ,y _{1 ,1} ,y _{2 ,1} ,y _{3 ,1} )= (q ₄ ,q ₅ ,q ₆ ,q ₇ ), (y _0,2 ,y _1,2 ,y _2,2 ,y _3,2 )=(q ₈ ,q ₉ ,q ₁₀ ,q ₁₁ ), It can be composed of ...

As another example, when the modulation scheme is 64-QAM, _{since the number of bits constituting the modulation symbol η MOD} =6, the number of _substreams N substreams =6, and each of the cells is (y _0,0 ,y _{1, 0} ,y _2,0 ,y _3,0 ,y _4,0 ,y _5,0 )=(q ₀ ,q ₁ ,q ₂ ,q ₃ ,q ₄ ,q ₅ ), (y _0,1 ,y _1,1 ,y _2,1 ,y _3,1 ,y _4,1 ,y _5,1 )=(q ₆ ,q ₇ ,q ₈ ,q ₉ ,q ₁₀ ,q ₁₁ ), (y _0,2 ,y _1,2 ,y _2,2 ,y _3,2 ,y _4,2 ,y _5,2 )=(q ₁₂ ,q ₁₃ ,q ₁₄ ,q ₁₅ ,q ₁₆ ,q ₁₇ ),... It can be configured as

Meanwhile, the modulator 130 may map the demultiplexed LDPC codeword to a modulation symbol.

Specifically, the modulator 130 performs quadrature phase shift keying (QPSK), 16-QAM, 64-QAM, 256-QAM, 1024-QAM, 4096 for bits (ie, cells) output from the demultiplexer (not shown). -Can be modulated using various modulation schemes such as QAM. For example, when the modulation method is QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, 4096-QAM, the number of bits constituting the modulation symbol η _MOD (i.e., modulation The order) can be 2,4,6,8,10,12 respectively.

In this case, since each cell output from the demultiplexer (not shown) consists of as many bits as the number of bits constituting the modulation symbol, the modulator 130 sequentially selects each cell output from the demultiplexer (not shown) at a constellation point ( constellation point) to generate a modulation symbol. Here, the modulation symbol corresponds to a constellation point in a constellation.

However, in some cases, the above-described demultiplexer (not shown) may be omitted. In this case, the modulator 130 may sequentially divide the interleaved bits by a certain number and map them to a constellation point to generate a modulation symbol. In this case, the modulator 130 may generate a modulation symbol by sequentially mapping the _{interleaved bits to a constellation point by η MOD bits according to a modulation method.}

Meanwhile, the modulator 130 may perform modulation by mapping cells output from a demultiplexer (not shown) to a constellation point using a non-uniform constellation (NUC) method.

In the non-uniform constellation method, when a constellation point of one quadrant is defined, constellation points for the other three quadrants may be determined by the following method. For example, if the set of constellation points defined for the first quadrant is X, it is -conj(X) for the 2nd quadrant, conj(X) for the 3rd quadrant, and -(X) for the 4th quadrant. .

That is, if one quadrant is defined, the other quadrant can be expressed as follows.

1 Quarter = X

2 Quarter(2 quadrant) = -conj(X)

3 Quarter(3 quadrant) = conj(X)

4 Quarter = -X

Specifically, when using non-uniform M-QAM, M constellation points can be defined _{as z={z 0} , z ₁ ,..., z _{M -1 }.} At this time, when the constellation point existing in the first quadrant is defined as {x ₀ , x ₁ , x ₂ ,..., x _{M /4-1} }, z can be defined as follows.

z ₀ to z _{M /4 -1} = x ₀ to x _{M /4}

z _{M /4} to z _{2 ×M/4-1} = -conj(x ₀ to x _{M /4} )

z _{2 ×M/4} to z _{3 ×M/4-1} = conj(x ₀ to x _{M /4} )

z _{3 ×M/4} to z _{4 ×M/4-1} = -(x ₀ to x _{M /4} )

을 인덱스로 하는 z_L로 매핑하여, 출력 비트들을 non-uniform constellation 방식으로 성성점에 맵핑할 수 있다. Therefore, the modulator 130 is an output bit output from the demultiplexer (not shown) [y ₀ ,...,y _m-1 ]

_{By mapping z L} as an index, output bits can be mapped to constellation points in a non-uniform constellation method.

Meanwhile, an example of a constellation defined according to the above-described non-uniform constellation method is Tables 26 to 30 below when the code rate is 5/15, 7/15, 9/15, 11/15, and 13/15. It can be expressed as

In these Tables 26 to 30, Table 26 shows non-uniform QPSK, Table 27 shows non-uniform 16-QAM, Table 28 and Table 29 shows non-uniform 64-QAM, and Table 30 shows non-uniform 256-QAM. .

Referring to these tables, constellation points for one quadrant may be defined based on Tables 26 to 30, and constellation points for the other three quadrants may be defined based on the above-described method.

However, this is only an example, and the modulator 130 may map output bits output from the demultiplexer (not shown) to constellation points in various ways.

Meanwhile, the reason for performing interleaving in the above-described manner in the present invention is as follows.

Specifically, when LDPC codeword bits are mapped to a modulation symbol, they have different reliability (ie, reception performance or reception probability) according to a mapped position in the modulation symbol. Meanwhile, according to the structure of the parity check matrix, LDPC codeword bits may have different codeword characteristics. That is, the LDPC codeword bits may have different codeword characteristics according to the number of 1s in the column of the parity check matrix, that is, the column order.

Therefore, in the present invention, the interleaver 120 considers both the codeword characteristics of the LDPC codeword bits and the reliability of the bits constituting the modulation symbol so that the LDPC codeword bits having a specific codeword characteristic are mapped to a specific bit in the modulation symbol. Interleaving is performed.

For example, _{when group interleaving is performed on an LDPC codeword composed of bit group X 0} to bit group X ₁₇₉ based on Equation 21 and Table 11, the group interleaver 122 includes a bit group X ₅₅ , a bit group X ₁₄₆ , and a bit It can output in the order of group X ₈₃ ,..., bit group X ₁₃₂ and bit group X _135.

In this case, when the modulation scheme is 16-QAM, the number of columns constituting the block interleaver 124 is 4, and each column may be composed of 16200 rows.

_{Accordingly, 45 bit groups (X 55} , X ₁₄₆ , X ₈₃ , X ₅₂ , X ₆₂ , X ₁₇₆ , X ₁₆₀ , X ₆₈ , X ₅₃ , X ₅₆ , X _{81) out} of 180 groups constituting the LDPC codeword. , X ₉₇ , X ₇₉ , X ₁₁₃ , X ₁₆₃ , X ₆₁ , X ₅₈ , X ₆₉ , X ₁₃₃ , X ₁₀₈ , X ₆₆ , X ₇₁ , X ₈₆ , X ₁₄₄ , X ₅₇ , X ₆₇ , X ₁₁₆ , X ₅₉ , X ₇₀ , X ₁₅₆ , X ₁₇₂ , X ₆₅ , X ₁₄₉ , X ₁₅₅ , X ₈₂ , X ₁₃₈ , X ₁₃₆ , X ₁₄₁ , X ₁₁₁ , X ₉₆ , X ₁₇₀ , X ₉₀ , X ₁₄₀ , X ₆₄ , X ₁₅₉ ) is input to the first column of the block interleaver 124, and a group of 45 bits (X ₁₅ , X ₁₄ , X ₃₇ , X ₅₄ , X ₄₄ , X ₆₃ , X ₄₃ , X ₁₈ , X ₄₇ , X ₇ , X ₂₅ , X ₃₄ , X ₂₉ , X ₃₀ , X ₂₆ , X ₃₉ , X ₁₆ , X ₄₁ , X ₄₅ , X ₃₆ , X ₀ , X ₂₃ , X ₃₂ , X ₂₈ , X ₂₇ , X ₃₈ , X ₄₈ , X ₃₃ , X ₂₂ , X ₄₉ , X ₅₁ , X ₆₀ , X ₄₆ , X ₂₁ , X ₄ , X ₃ , X ₂₀ , X ₁₃ , X ₅₀ , X ₃₅ , X ₂₄ , X ₄₀ , X ₁₇ , X ₄₂ , X ₆ ) is input to the second column of the block interleaver 124, and a group of 45 bits (X ₁₁₂ , X ₉₃ , X ₁₂₇ , X ₁₀₁ , X ₉₄ , X ₁₁₅ , X ₁₀₅ , X ₃₁ , X ₁₉ , _X177 , X ₇₄ , X ₁₀ , X ₁₄₅ , X ₁₆₂ , X ₁₀₂ , X ₁₂₀ , X ₁₂₆ , X ₉₅ , X ₇₃ , X ₁₅₂ , X ₁₂₉ , X ₁₇₄ , X ₁₂₅ , X ₇₂ , X ₁₂₈ , X ₇₈ , X ₁₇₁ , X ₈ , X ₁₄₂ , X _{17 8} , X ₁₅₄ , X ₈₅ , X ₁₀₇ , X ₇₅ , X ₁₂ , X ₉ , X ₁₅₁ , X ₇₇ , X ₁₁₇ , X ₁₀₉ , X ₈₀ , X ₁₀₆ , X ₁₃₄ , X ₉₈ , X ₁ ) This block interleaver Entered in the third column of (124), and a group of 45 bits (X ₁₂₂ , X ₁₇₃ , X ₁₆₁ , X ₁₅₀ , X ₁₁₀ , X ₁₇₅ , X ₁₆₆ , X ₁₃₁ , X ₁₁₉ , X ₁₀₃ , X ₁₃₉ , X ₁₄₈ , X ₁₅₇ , X ₁₁₄ , X ₁₄₇ , X ₈₇ , X ₁₅₈ , X ₁₂₁ , X ₁₆₄ , X ₁₀₄ , X ₈₉ , X ₁₇₉ , X ₁₂₃ , X ₁₁₈ , X ₉₉ , X ₈₈ , X ₁₁ , X ₉₂ , X ₁₆₅ , X ₈₄ , X ₁₆₈ , X ₁₂₄ , X ₁₆₉ , X ₂ , X ₁₃₀ , X ₁₆₇ , X ₁₅₃ , X ₁₃₇ , X ₁₄₃ , X ₉₁ , X ₁₀₀ , X ₅ , X ₇₆ , X ₁₃₂ , X ₁₃₅ ) It may be input to the fourth column of the block interleaver 124.

In addition, the block interleaver 124 may sequentially output bits input to the first row to the last row of each column, and bits output from the block interleaver 124 may be sequentially input to the modulator 130. . In this case, the demultiplexer (not shown) may be omitted, or the demultiplexer (not shown) may sequentially output the input bits without changing the order of the input bits. Accordingly, bits _{included in each of the bit group X 55} , the bit group X ₁₅ , the bit group X ₁₁₂ , and the bit group X ₁₂₂ may constitute a modulation symbol.

Meanwhile, when the modulation scheme is 64-QAM, the number of columns constituting the block interleaver 124 is 6, and each column may be composed of 10800 rows.

_{Accordingly, 30 bit groups (X 55} , X ₁₄₆ , X ₈₃ , X ₅₂ , X ₆₂ , X ₁₇₆ , X ₁₆₀ , X ₆₈ , X ₅₃ , X ₅₆ , X _{81) out} of 180 groups constituting the LDPC codeword. , X ₉₇ , X ₇₉ , X ₁₁₃ , X ₁₆₃ , X ₆₁ , X ₅₈ , X ₆₉ , X ₁₃₃ , X ₁₀₈ , X ₆₆ , X ₇₁ , X ₈₆ , X ₁₄₄ , X ₅₇ , X ₆₇ , X ₁₁₆ , X ₅₉ , X ₇₀ , X ₁₅₆ ) are input to the first column of the block interleaver 124, and 30 bit groups (X ₁₇₂ , X ₆₅ , X ₁₄₉ , X ₁₅₅ , X ₈₂ , X ₁₃₈ , X ₁₃₆ , X ₁₄₁ , X ₁₁₁ , X ₉₆ , X ₁₇₀ , X ₉₀ , X ₁₄₀ , X ₆₄ , X ₁₅₉ , X ₁₅ , X ₁₄ , X ₃₇ , X ₅₄ , X ₄₄ , X ₆₃ , X ₄₃ , X ₁₈ , X ₄₇ , X ₇ , X ₂₅ , X ₃₄ , X ₂₉ , X ₃₀ , X ₂₆ ) are input to the second column of the block interleaver 124, and 30 bit groups (X ₃₉ , X ₁₆ , X ₄₁ , X ₄₅ , X ₃₆ , X ₀ , X ₂₃ , X ₃₂ , X ₂₈ , X ₂₇ , X ₃₈ , X ₄₈ , X ₃₃ , X ₂₂ , X ₄₉ , X ₅₁ , X ₆₀ , X ₄₆ , X ₂₁ , X ₄ , X ₃ , X ₂₀ , X ₁₃ , X ₅₀ , X ₃₅ , X ₂₄ , X ₄₀ , X ₁₇ , X ₄₂ , X ₆ ) are input to the third column of the block interleaver 124, and 30 bit groups (X ₁₁₂ , X ₉₃ , X ₁₂₇ , X ₁₀₁ , X ₉₄ , X ₁₁₅ , X ₁₀₅ , X ₃₁ , X ₁₉ , X ₁₇₇ , X ₇₄ , X ₁₀ , X ₁₄₅ , X ₁₆₂ , X ₁₀₂ , X ₁₂₀ , X ₁₂₆ , X ₉₅ , X ₇₃ , X ₁₅₂ , X ₁₂₉ , X ₁₇₄ , X ₁₂₅ , X ₇₂ , X ₁₂₈ , X ₇₈ , X ₁₇₁ , X ₈ , X ₁₄₂ , X ₁₇₈ ) are input to the fourth column of the block interleaver 124, and 30 bit groups (X ₁₅₄ , X ₈₅ , X ₁₀₇ , X ₇₅ , X ₁₂ , X ₉ , X ₁₅₁ , X ₇₇ , X ₁₁₇ , X ₁₀₉ , X ₈₀ , X ₁₀₆ , X ₁₃₄ , X ₉₈ , X ₁ , X ₁₂₂ , X ₁₇₃ , X ₁₆₁ , X ₁₅₀ , X ₁₁₀ , X ₁₇₅ , X ₁₆₆ , X ₁₃₁ , X ₁₁₉ , X ₁₀₃ , X ₁₃₉ , X ₁₄₈ , X ₁₅₇ , X ₁₁₄ , X ₁₄₇ ) are input to the fifth column of the block interleaver 124, and 30 bit groups (X ₈₇ , X ₁₅₈ , X ₁₂₁ , X ₁₆₄ , X ₁₀₄ , X ₈₉ , X ₁₇₉ , X ₁₂₃ , X ₁₁₈ , X ₉₉ , X ₈₈ , X ₁₁ , X ₉₂ , X ₁₆₅ , X ₈₄ , X ₁₆₈ , X ₁₂₄ , X ₁₆₉ , X ₂ , X ₁₃₀ , X ₁₆₇ , X ₁₅₃ , X ₁₃₇ , X ₁₄₃ , X ₉₁ , X ₁₀₀ , X ₅ , X ₇₆ , X ₁₃₂ , X ₁₃₅ ) may be input to the sixth column of the block interleaver 124.

In addition, the block interleaver 124 may sequentially output bits input to the first row to the last row of each column, and bits output from the block interleaver 124 may be sequentially input to the modulator 130. . In this case, the demultiplexer (not shown) may be omitted, or the demultiplexer (not shown) may sequentially output the input bits without changing the order of the input bits. Accordingly, bits _{included in each of the bit group X 55} , the bit group X ₁₇₂ , the bit group X ₃₉ , the bit group X ₁₁₂ , the bit group X ₁₅₄ , and the bit group X ₈₇ may constitute a modulation symbol.

As described above, in the present invention, since a specific bit is mapped to a specific bit in a modulation symbol through interleaving, both excellent reception performance and decoding performance can be achieved at the receiving side.

That is, if LDPC codeword bits with excellent decoding performance are mapped to bits with excellent reliability among the bits constituting the modulation symbol, the decoding performance may be excellent at the receiving side, but LDPC codeword bits with excellent decoding performance are received. There may be a problem that cannot be done. In addition, when LDPC codeword bits with excellent decoding performance are mapped to bits with low reliability among the bits constituting a modulation symbol, the initial reception performance is excellent and the overall performance may be excellent, but the decoding is not good. If a lot of files are received, error propagation may occur.

Accordingly, in the present invention, when mapping LDPC codeword bits to modulation symbols, the LDPC codeword bits having specific codeword characteristics are selected by considering both the codeword characteristics of the LDPC codeword bits and the reliability of the bits constituting the modulation symbols. It is mapped to a specific bit in the modulation symbol and transmitted to the receiving side. Accordingly, it is possible to achieve both excellent reception performance and decoding performance at the receiving side.

Meanwhile, a method of determining π(j), which is a parameter used for group interleaving, in various embodiments of the present invention will be described below.

According to an embodiment of the present invention, when the length of the LDPC codeword is 64800, since the size of the bit group is set to 360, there are 180 bit groups, and a total of 180 possible interleaving patterns! (Here, factorial means A! = A*(A-1)* ... *2*1 for the integer A) A number of cases may exist.

In this case, since there is a case in which the reliability level between bits constituting the modulation symbol is the same according to the modulation order, a large number of interleaving patterns may be regarded as the same interleaving operation in consideration of theoretical performance. For example, when the theoretical reliability of the X-axis or real part MSB bits constituting a modulation symbol and the Y-axis or imaginary part MSB bits are the same, a certain bit is mapped to two MSBs. No matter how interleaved in any way, the theoretical performance will be the same.

However, the closer it is to the actual channel environment, the little by little these theoretical predictions become inaccurate. For example, in a modulation scheme such as QPSK, in a part of a very symmetric channel such as an AWGN channel, two bits constituting a symbol theoretically have the same reliability, so no matter which interleaving scheme is used, theoretically There should be no difference in performance, but in an actual channel environment, a difference in performance occurs according to the interleaving method. The performance of the well-known Rayleigh channel, not the actual channel, can also be predicted to a certain degree by simply predicting the performance with the reliability of the bits constituting the symbol according to the modulation method so that the performance of the QPSK varies greatly depending on the interleaving method. One obviously has limitations.

In addition, since the performance of the code by interleaving can vary greatly depending on the channel for evaluating the performance, the interleaving pattern must always be determined in consideration of the channel. For example, in general, a good interleaving pattern in the AWGN channel is not good in the Rayleigh channel. If the channel environment in which a given system is used is often closer to the Rayleigh channel, then the AWGN channel is more likely to have a good interleaving pattern. It may be better to choose a better interleaving pattern in the Rayleigh channel.

In conclusion, in order to derive an interleaving pattern of a code, a good interleaving pattern can be obtained by considering not only a specific channel environment but also various channel environments considered in the system. In addition, since there is a limit to determining the actual performance using only the theoretical performance prediction, the interleaving pattern must be finally determined after confirming the performance through a direct computational experiment on the performance.

However, in many cases, since the number of possible interleaving patterns is too large to apply all the above-described processes (e.g. 180!), it is necessary to efficiently reduce the number of interleaving patterns to predict and test performance. This is the key part.

Accordingly, in the present invention, the interleaver is designed through the following process.

1) Determine the channels C ₁ , C ₂ , ..., C _k to be considered in the system.

2) Generate an arbitrary interleaver pattern.

3) The interleaver generated in 2) is applied to each channel determined in 1) to predict the theoretical performance value. There are various methods for predicting the theoretical performance value, but in the present invention, a well-known noise threshold determination method such as density evolution analysis is used. Here, the noise threshold is a value that can be expressed as the minimum necessary SNR for error-free transmission, assuming that the length of the code is infinite and the cycle-free characteristic is satisfied when the code is expressed in a Tanner graph. The density evolution analysis method itself can be implemented in various ways, but a detailed description thereof will be omitted since it is not the core of the present invention.

4) When the noise threshold for each channel of the i-th generated interleaver is expressed as TH ₁ [i], TH ₂ [i], ..., TH _k [i], the final decision threshold is defined as follows. .

TH[i] = W ₁ *TH ₁ [i] + W ₂ *TH ₂ [i] + ... + W _k *TH _k [i],

Here, W ₁ +W ₂ +... +Wk=1, W ₁ ,W ₂ ,...,W _k > 0 are satisfied.

As for _{the values of W 1} , W ₂ , ..., W _k, the value for the important channel is large and the value for the less important channel is adjusted according to the importance of the channel (e.g., when considering the AWGN and Rayleigh channels, respectively. When the weight value is W ₁ , W ₂ , if it is judged that the importance of either channel is higher, W ₁ =0.25, W ₂ =0.75 can be set.)

5) Among the tested interleaver patterns, B interleavers are selected in the order of the lowest TH[i] value, and a performance computational experiment is directly performed on each channel. Here, the FER level for the test is determined to be 10^-3 (eg B=100).

6) Among the B interleavers tested in 5), the D interleaver patterns with the best performance are selected (e.g., D=5).

Typically, in step 5), an interleaver with a high SNR gain in the region of FER = 10^-3 can be selected as an interleaver with excellent performance. However, in the present invention, as shown in FIG. From the results of computational experiments, the performance of the FER required by the system is predicted through extrapolation, and the expected performance of the FER required by the system is compared to determine the interleaver with good performance as an excellent interleaver. In the present invention, for convenience, a method of extrapolation based on a linear function is applied, but various other extrapolation methods may be applied. Meanwhile, FIG. 16 shows an example of performance extrapolation expected from the results of a computational experiment.

7) Perform a performance computation experiment on each channel directly with the D interleaver patterns selected in 6). Here, the FER level for the test is selected as the FER required by the system (eg, FER=10^-6).

8) After completion of the computational experiment, no error floor phenomenon is observed, and the interleaving pattern with the largest SNR gain is determined as the final interleaving pattern.

On the other hand, FIG. 17 is a diagram schematically illustrating a process of determining a pattern of B interleavers in processes 2), 3), 4), and 5) of the above-described method of determining an interleaving pattern using AWGN and Rayleigh channels as an example. .

Referring to Figure 17, and calculates the first, initializing the values of the variables i, j, such as required in S1701, and then, the noise threshold for the AWGN channel in S1702 TH ₁ [i], the noise threshold TH ₂ [i] for the Rayleigh Channel . Next, the final decision noise threshold TH[i] defined in step 4) is calculated in S1703, and then, in S1704, the final decision noise threshold and the magnitude of the previous step are compared. In step S1706, when a case where the final decision noise threshold is small, the TH_S[i] value is appropriately substituted and stored. After that, the i and j values are vaporized one by one in S1707, and the same process is repeated until the i value exceeds the predetermined value of A in S1708. In this case, the A value is the total number of interleavers to be tested in 2), 3), 4), and 5), and the A value is usually determined to be 10000 or more. When all of the above processes are completed, the interleaver pattern corresponding to the values of _{TH S} [0], TH _S [1], ..., TH _S [B-1] stored in the order of smallest final noise threshold is finally selected in S1709.

Meanwhile, the transmission device 100 may modulate the signal mapped to the constellation and transmit it to the reception device (eg, 1200 of FIG. 18 ). For example, the transmitting device 100 may map a signal mapped to a constellation to an OFMD frame using an Orthogonal Frequency Division Multiplexing (OFDM) method, and transmit the mapped signal to the receiving device 1200 through an allocated channel.

18 is a block diagram illustrating a configuration of a receiving device according to an embodiment of the present invention. Referring to FIG. 18, the reception device 1200 includes a demodulation unit 1210, a multiplexer 1220, a deinterleaver 1230, and a decoding unit 1240.

The demodulator 1210 receives and demodulates the signal transmitted from the transmission device 100. Specifically, the demodulator 1210 demodulates the received signal to generate a value corresponding to the LDPC codeword, and outputs the same to the multiplexer 1220. In this case, the demodulation unit 1210 may perform demodulation to correspond to the modulation method used in the transmission device 100. To this end, the transmission device 100 may transmit information on the modulation method to the reception device 1200, or the transmission device 100 modulates using a predefined modulation method with the reception device 1200. You can do it.

Here, the value corresponding to the LDPC codeword may be expressed as a channel value for the received signal. There may be various methods of determining the channel value, for example, a method of determining a Log Likelihood Ratio (LLR) value.

The LLR value may be expressed as a value obtained by taking a log in the ratio of the probability that the bit transmitted from the transmission device 100 is 0 and the probability that it is 1. Alternatively, the LLR value may be a bit value itself determined according to a hard decision, and the LLR value is a representative value determined according to a section to which the probability that the bit transmitted from the transmitting device 100 is 0 or 1 belongs. It could be.

The multiplexer 1220 multiplexes the output values of the demodulator 1210 and outputs the multiplexed values to the deinterleaver 1230.

Specifically, the multiplexer 1220 is a component corresponding to a demultiplexer (not shown) provided in the transmission device 100 and performs an operation corresponding to a demultiplexer (not shown). That is, the multiplexer 1220 reverses the operation performed by the demultiplexer (not shown), converts the output value of the demodulator 1210 to cell-to-bit, and converts the LLR value in bit units. Can be printed. However, when the demultiplexer (not shown) is omitted in the transmitting device 100, the multiplexer 1220 of the receiving device 1200 may be omitted.

Meanwhile, information on whether to perform the demultiplexing operation may be provided from the transmitting device 100 or previously stored between the transmitting device 100 and the receiving device 1200.

The deinterleaver 1230 deinterleaves the output value of the multiplexer 1220 and outputs it to the decoder 1240.

Specifically, the deinterleaver 1230 is a component corresponding to the interleaver 120 of the transmission device 100 and performs an operation corresponding to the interleaver 120. That is, the deinterleaver 1230 reversely performs the interleaving operation performed by the interleaver 120 to deinterleave the LLR value.

To this end, the deinterleaver 1230 may include a block deinterleaver 1231, a group twist deinterleaver 1232, a group deinterleaver 1233, and a parity deinterleaver 1234 as shown in FIG. 19.

The block deinterleaver 1231 deinterleaves the output of the multiplexer 1220 and outputs this to the group twist deinterleaver 1232.

Specifically, the block deinterleaver 1231 is a component corresponding to the block interleaver 124 provided in the transmission device 100 and may reversely perform an interleaving operation performed by the block interleaver 124.

That is, the block deinterleaver 1231 writes the LLR values output from the multiplexer 1220 in the row direction to each row using at least one row consisting of a plurality of columns, and each of the plurality of rows to which the LLR values are written. Deinterleaving can be performed by leading the column in the column direction.

In this case, when interleaving is performed by dividing a column into two parts in the block interleaver 124, the block deinterleaver 1231 may perform deinterleaving by dividing a row into two parts.

In addition, when the block interleaver 124 writes and reads a bit group not belonging to the first part in the row direction, the block deinterleaver 1231 writes a value corresponding to the group not belonging to the first part in the row direction. And deinterleaving may be performed by reading.

Hereinafter, the block deinterleaver 1231 will be described with reference to FIG. 20. However, this is only an example, and it goes without saying that the block deinterleaver 1231 may be implemented in other ways.

,

이다.The input LLR v _{i (0≦} i<N ldpc) is written to _{the r i} row and c _i column of the block deinterleaver 1231. From here,

,

to be.

,

이다.On the other hand, the output LLR q _i (0≦i<N _c ×N _r1 ) is read from _{the c i} column and r _i row of the first part of the block deinterleaver 1231. From here,

,

to be.

,

이다.The output _{LLR q i (N c × N} r1 ≤i <N ldpc) is lead from the second part of the column c _i, r _i the row of the block deinterleaver 1231. From here,

,

to be.

The group twist deinterleaver 1232 deinterleaves the output value of the block deinterleaver 1231 and outputs this to the group deinterleaver 1233.

Specifically, the group twist deinterleaver 1232 is a component corresponding to the group twist interleaver 123 included in the transmission device 100, and may reversely perform an interleaving operation performed by the group twist interleaver 123. .

That is, the group twist deinterleaver 1232 may rearrange the LLR values in the same group by changing the order of the LLR values existing in the same group. Meanwhile, when the group twist operation is not performed in the transmission device 100, the group twist deinterleaver 1232 may be omitted.

The group deinterleaver 1233 (or group-wise deinterleaver) deinterleaves the output value of the group twist deinterleaver 1232 and outputs it to the parity deinterleaver 1234.

Specifically, the group deinterleaver 1233 is a component corresponding to the group interleaver 122 provided in the transmission device 100 and may reversely perform an interleaving operation performed by the group interleaver 122.

That is, the group deinterleaver 1233 may rearrange the order of the plurality of bit groups in units of bit groups. In this case, the group deinterleaver 1233 reversely applies the interleaving method defined as shown in Tables 11 to 22 according to the length, modulation method, and code rate of the LDPC codeword to determine the order of the plurality of bit groups in bit group units. Can be rearranged.

The parity deinterleaver 1234 performs parity deinterleaving on the output value of the group deinterleaver 1233 and outputs the parity deinterleaving to the decoder 1240.

Specifically, the parity deinterleaver 1234 is a component corresponding to the parity interleaver 121 provided in the transmission device 100 and may perform an interleaving operation performed by the parity interleaver 121 in reverse. That is, the parity deinterleaver 1234 may deinterleave LLR values corresponding to parity bits among LLR values output from the group deinterleaver 1233. In this case, the parity deinterleaver 1234 may deinterleave LLR values corresponding to parity bits in the reverse of the parity interleaving method of Equation 18.

However, the parity deinterleaver 1234 may be omitted depending on the decoding method and implementation of the decoder 1240.

Meanwhile, the deinterleaver 1230 of FIG. 18 may be composed of three or four components as shown in FIG. 19, but operations of the components may be performed as one component. For example, when one bit belonging to each bit group for bit groups _{X a} , X _b , X _c , and X _{d constitutes one modulation symbol, the deinterleaver 1230} Deinterleaving may be performed to positions corresponding to bit groups based on the modulation symbol.

For example, when the code rate is 6/15 and the modulation method is 16-QAM, the group deinterleaver 1233 may perform deinterleaving based on Table 11.

In this case, one bit included in each of the _{bit groups X 55} , X ₁₅ , X ₁₁₂ , and X _{122 constitutes one modulation symbol.} Since each bit in bit groups X ₅₅ , X ₁₅ , X ₁₁₂ , and X ₁₂₂ constitutes one modulation symbol, the deinterleaver 1230 is based on one received modulation symbol, and the bit groups X ₅₅ and X ₁₅ , X ₁₁₂ , and X ₁₂₂ may be mapped to initial decoding values.

The decoder 1240 may perform LDPC decoding using an output value of the deinterleaver 1230. To this end, the decoder 1240 may include an LDPC decoder (not shown) for performing LDPC decoding.

Specifically, the decoding unit 1240 is a component corresponding to the encoding unit 110 of the transmission device 100, and can correct an error by performing LDPC decoding using the LLR value output from the deinterleaver 1230. have

For example, the decoder 1240 may perform LDPC decoding using an iterative decoding method based on a sum-product algorithm. Here, the summation algorithm is a kind of message passing algorithm, and the message passing algorithm is to exchange messages (e.g., LLR values) through edges on a bipartite graph, and to variable nodes or check nodes. Represents an algorithm that calculates and updates an output message from input messages.

Meanwhile, the decoder 1240 may use a parity check matrix during LDPC decoding. In this case, the parity check matrix used for decoding may have the same structure as the parity check matrix used for encoding in the encoder 110, which has been described above with reference to FIGS. 2 to 4.

Meanwhile, information on a parity check matrix used during LDPC decoding and information on a code rate may be previously stored in the reception device 1200 or may be provided from the transmission device 100.

21 is a flowchart illustrating an interleaving method of a transmitting device according to an embodiment of the present invention.

First, LDPC encoding is generated based on the parity check matrix (S1410), and the LDPC codeword is interleaved (S1420).

Thereafter, the interleaved LDPC codeword is mapped to the modulation symbol (S1430). In this case, a bit included in a preset bit group among a plurality of bit groups constituting the LDPC codeword may be mapped to a preset bit in the modulation symbol.

Here, each of the plurality of bit groups is composed of M bits, M is a common factor of _{N ldpc} and K _{ldpc , and Q ldpc} = (N _ldpc -K _ldpc )/M may be determined to be established. In this case, Q _ldpc is the information word constituting the parity check matrix, the cyclic shift parameter value for columns within the column group of the submatrix, N _ldpc is the length of the LDPC codeword, and K _ldpc is the information word constituting the LDPC codeword. It is the length of bits.

Meanwhile, in step S1420, the parity bits constituting the LDPC codeword are interleaved, the parity-interleaved LDPC codeword is divided into a plurality of bit groups, the order of the plurality of bit groups is rearranged in bit group units, and the order is rearranged. A plurality of bit groups may be interleaved.

Here, the order of the plurality of groups may be rearranged in units of bit groups based on Equation 21 described above.

Meanwhile, as described in Equation 21, π(j) in Equation 21 may be determined based on at least one of a length, a modulation method, and a code rate of the LDPC codeword.

For example, when the length of the LDPC codeword is 64800, the modulation method is 16-QAM, and the code rate is 6/15, π(j) may be defined as shown in Table 11 above.

In addition, π(j) may be defined as in Table 14 above when the length of the LDPC codeword is 64800, the modulation method is 16-QAM, and the code rate is 10/15.

In addition, π(j) may be defined as shown in Table 15 above when the LDPC codeword has a length of 64800, a modulation method is 16-QAM, and a code rate is 12/15.

In addition, when the length of the LDPC codeword is 64800, the modulation method is 64-QAM, and the code rate is 6/15, π(j) may be defined as shown in Table 17 below.

In addition, when the length of the LDPC codeword is 64800, the modulation method is 64-QAM, and the code rate is 8/15, π(j) may be defined as shown in Table 18 below.

In addition, when the length of the LDPC codeword is 64800, the modulation method is 64-QAM, and the code rate is 12/15, π(j) may be defined as shown in Table 21 below.

On the other hand, in the case of interleaving a plurality of bit groups, a plurality of bit groups are written in a column direction in each of a plurality of columns in a bit group unit, and each row of a plurality of columns in which a plurality of bit groups are written in a bit group unit is written in a row direction. Interleaving can be performed by reading.

Here, after sequentially writing at least some bit groups that can be written to each of the plurality of columns in bit group units among the plurality of bit groups, in each of the plurality of columns, at least some bit groups in each of the plurality of columns are bit groups. The remaining bit groups can be divided and written in the remaining area after being written as a unit.

Meanwhile, a non-transitory computer readable medium in which a program sequentially performing the interleaving method according to the present invention is stored may be provided.

The non-transitory readable medium refers to a medium that stores data semi-permanently and can be read by a device, rather than a medium that stores data for a short moment, such as a register, a cache, and a memory. Specifically, various applications or programs may be provided by being stored in a non-transitory readable medium such as a CD, DVD, hard disk, Blu-ray disk, USB, memory card, ROM, or the like.

In addition, although a bus is not shown in the above-described block diagram showing the transmitting device and the receiving device, communication between components in each device may be performed through a bus. In addition, each device may further include a processor such as a CPU or a microprocessor that performs the various steps described above.

In addition, although the preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the specific embodiments described above, and the technical field to which the present invention belongs without departing from the gist of the present invention claimed in the claims. In addition, various modifications are possible by those of ordinary skill in the art, and these modifications should not be individually understood from the technical spirit or prospect of the present invention.

100: transmitting device 110: encoding unit
120: interleaver 130: modulator

Claims (4)

In the transmission device,
An encoder for generating parity bits by encoding information word bits based on a low density parity check (LDPC) code according to a code rate of 6/15 and a code length of 64800;
Interleaving the parity bits, dividing the codeword into a plurality of bit groups, interleaving the plurality of bit groups, and using a plurality of columns divided into first and second parts of the interleaved plurality of bit groups An interleaver for interleaving bits to provide an interleaved codeword;
A mapper for mapping bits of the interleaved codeword to constellation points for 16-QAM (quadrature amplitude modulation); And
Includes; a transmitter for transmitting a signal based on the constellation points to a receiving device,
The codeword includes the information word bits and the interleaved parity bits,
The plurality of bit groups are interleaved based on the following relational expression:
Y _j =X _π(j) for (0≤j<N _group )
Here, X _j is a j-th bit group among the plurality of bit groups, Y _j is a j-th bit group among the plurality of interleaved bit groups, N _group is the total number of the plurality of bit groups, and π ( j) is a permutation order for the interleaving,
The π(j) is represented as in the following table.

The method of claim 1,
Each of the plurality of bit groups includes 360 bits. In the transmission method,
Generating parity bits by encoding information word bits based on a low density parity check (LDPC) code according to a code rate of 6/15 and a code length of 64800;
Interleaving the parity bits;
Dividing the codeword into a plurality of bit groups;
Interleaving the plurality of bit groups;
Interleaving bits of the plurality of interleaved bit groups using a plurality of columns divided into first and second parts to provide an interleaved codeword;
Mapping bits of the interleaved codeword to constellation points for 16-QAM (quadrature amplitude modulation); And
Including; transmitting a signal based on the constellation points to a receiving device,
The codeword includes the information word bits and the interleaved parity bits,
The plurality of bit groups are interleaved based on the following relational expression, a transmission method:
Y _j =X _π(j) for (0≤j<N _group )
Here, X _j is a j-th bit group among the plurality of bit groups, Y _j is a j-th bit group among the plurality of interleaved bit groups, N _group is the total number of the plurality of bit groups, and π ( j) is a permutation order for the interleaving,
The π(j) is represented as in the following table.

The method of claim 3,
Each of the plurality of bit groups includes 360 bits.

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