KR102258098B1 - Transmitting apparatus and signal processing method thereof - Google Patents

Abstract

The transmitting device is started. The transmitting apparatus includes an encoder that generates LDPC codewords by performing LDPC encoding, an interleaver that divides the LDPC codeword into a plurality of bit groups and interleaves, and modulates the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. Including a modulator, the interleaver includes a block interleaver composed of a plurality of columns each including a plurality of rows, and the block interleaver includes a first part and a plurality of columns according to the number of the plurality of columns and the number of bit groups. The LDPC codeword is interleaved by dividing it into the second part.

Description

Transmitting device and its signal processing method {TRANSMITTING APPARATUS AND SIGNAL PROCESSING METHOD THEREOF}

The present invention relates to a transmission apparatus and a signal processing method thereof, and more particularly, to a transmission apparatus that processes and transmits data, and a signal processing method thereof.

In a communication/broadcasting system, link performance may be significantly degraded due to various noise and fading phenomena of a channel, and inter-symbol interference (ISI). Therefore, in order to implement high-speed digital communication/broadcasting systems that require high data throughput and reliability, such as next-generation mobile communication, digital broadcasting, and portable Internet, it is required to develop a technology for overcoming noise, fading, and inter-symbol interference. . As a part of research to overcome noise, etc., in recent years, research on error-correcting codes has been actively conducted as a method to increase the reliability of communication by efficiently restoring distortion of information.

LDPC (Low Density Parity Check) codes, first introduced by Gallager in the 1960s, have long been forgotten due to the complexity that is difficult to implement at the technology level at the time. However, as the turbo code proposed by Berrou, Glavieux, and Thitimajshima in 1993 showed a performance close to the channel capacity of Shannon, many interpretations of the performance and characteristics of the turbo code were performed and iterative decoding. (Iterative decoding) and graph-based channel coding have been studied a lot. As a result of this, as LDPC codes were re-researched in the late 1990s, decoding by applying iterative decoding based on sum-product algorithm on the Turner graph corresponding to LDPC codes It has been found to have a performance close to the channel capacity of the paddy field.

When transmitting an LDPC code using a higher-order modulation scheme, performance may vary depending on a method of mapping codeword bits to higher-order modulation bits. Therefore, there is a need for a method of mapping the LDPC codeword bits to higher order modulation bits for an LDPC code having excellent performance.

The present invention is in accordance with the above-described necessity, and an object of the present invention is a transmission apparatus capable of transmitting by mapping a bit included in a preset group among a plurality of groups constituting an LDPC codeword to a preset bit in a modulation symbol, and a signal thereof. It is to provide a treatment method.

In order to achieve the above object, a transmitting apparatus according to an embodiment of the present invention includes an encoder for generating an LDPC codeword by performing LDPC encoding, an interleaver and modulation for dividing the LDPC codeword into a plurality of bit groups and interleaving them. And a modulator configured to generate a modulation symbol by modulating the interleaved LDPC codeword according to a method, wherein the interleaver includes a block interleaver composed of a plurality of columns each including a plurality of rows, and the block interleaver comprises: The LDPC codewords are interleaved by dividing each of the plurality of columns into a first part and a second part according to the number of columns and the number of bit groups.

Here, the number of the plurality of columns has the same value as the modulation order according to the modulation method, and each of the plurality of columns is a row equal to a value obtained by dividing the number of bits constituting the LDPC codeword by the number of columns. It can be composed of.

In addition, in each of the plurality of columns, the first part includes the plurality of bit groups constituting the LDPC codeword according to the number of the plurality of columns, the number of bit groups, and the number of bits constituting each bit group. Each of the plurality of columns is composed of rows as many as the number of bits included in at least some bit groups that can be written in bit group units, and the second part is a row constituting each of the plurality of columns in each of the plurality of columns. In each of the plurality of columns, each of the plurality of columns may be composed of rows excluding as many rows as the number of bits included in at least some bit groups that can be written in bit group units.

Here, the number of rows of the second part has a value equal to the quotient obtained by dividing the number of bits included in all bit groups except for the bit group corresponding to the first part by the number of columns constituting the block interleaver. I can.

In addition, the block interleaver sequentially writes bits included in at least some bit groups that can be written in units of the bit group to each of a plurality of columns constituting the first part, and at least some bits in the plurality of bit groups Bits included in the remaining bit groups excluding the group may be divided based on the number of the plurality of columns, and sequentially written to each of the plurality of columns constituting the second part.

Here, the block interleaver divides the bits included in the remaining bit group into the number of columns, and writes each of the divided bits to each of the plurality of columns constituting the second part in a column direction, , Interleaving may be performed by reading a plurality of columns constituting the first part and the second part in a row direction.

Meanwhile, the modulation order may be 2,4,6,8,10,12 when the modulation scheme is QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, or 4096-QAM.

On the other hand, the signal processing method of the transmitting apparatus according to an embodiment of the present invention includes the steps of generating an LDPC codeword by performing LDPC encoding, dividing the LDPC codeword into a plurality of bit groups, and interleaving the LDPC codeword into a plurality of bit groups. And generating a modulation symbol by modulating the interleaved LDPC codeword, wherein the interleaving includes a plurality of columns each including a plurality of rows according to the number of the plurality of columns and the number of bit groups. Dividing into a first part and a second part, the LDPC codeword is interleaved.

Here, the number of the plurality of columns has the same value as the modulation order according to the modulation method, and each of the plurality of columns is a row equal to a value obtained by dividing the number of bits constituting the LDPC codeword by the number of columns. It can be composed of.

In addition, in each of the plurality of columns, the first part includes the plurality of bit groups constituting the LDPC codeword according to the number of the plurality of columns, the number of bit groups, and the number of bits constituting each bit group. Each of the plurality of columns is composed of rows as many as the number of bits included in at least some bit groups that can be written in bit group units, and the second part is a row constituting each of the plurality of columns in each of the plurality of columns. In each of the plurality of columns, each of the plurality of columns may be composed of rows excluding as many rows as the number of bits included in at least some bit groups that can be written in bit group units.

Here, the number of rows of the second part may have the same value as a quotient obtained by dividing the number of bits included in all bit groups except for the bit group corresponding to the first part by the number of columns.

In addition, the interleaving may include sequentially writing bits included in at least some bit groups that can be written in units of the bit group to each of a plurality of columns constituting the first part, and at least some of the bits in the plurality of bit groups. Bits included in the remaining bit groups excluding the bit group may be divided based on the number of the plurality of columns, and sequentially written to each of the plurality of columns constituting the second part.

Here, in the interleaving, the bits included in the remaining bit group are divided into the number of columns, and each of the divided bits is written to each of the plurality of columns constituting the second part in a column direction. In addition, interleaving may be performed by reading a plurality of columns constituting the first part and the second part in a row direction.

Meanwhile, the modulation order may be 2,4,6,8,10,12 when the modulation scheme is QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, or 4096-QAM.

According to various embodiments of the present invention, it is possible to provide better decoding and reception performance.

1 is a block diagram illustrating a configuration of a transmission device according to an embodiment of the present invention.
2 and 3 are diagrams for explaining the structure of a parity check matrix according to an embodiment of the present invention;
4 is a block diagram illustrating a structure of an interleaver according to an embodiment of the present invention;
5 to 7 are diagrams illustrating a method of processing LDPC codewords in groups according to an embodiment of the present invention;
8 to 11 are diagrams for explaining a structure of a block interleaver and an interleaving method according to an embodiment of the present invention;
12 and 13 are diagrams for explaining an operation of a demultiplexer according to an embodiment of the present invention;
14 is a diagram for explaining an example of a uniform constellation modulation scheme according to an embodiment of the present invention;
15 to 19 are diagrams for explaining an example of a non-uniform constellation modulation scheme according to an embodiment of the present invention;
20 is a block diagram illustrating a structure of an interleaver according to another embodiment of the present invention;
21 and 23 are diagrams for explaining a structure of a block-row interleaver and an interleaving method according to an embodiment of the present invention;
24 is a block diagram illustrating a configuration of a receiving device according to an embodiment of the present invention.
25 and 27 are block diagrams for explaining the structure of a deinterleaver according to an embodiment of the present invention;
26 is a view for explaining a block deinterleaver according to an embodiment of the present invention;
28 is a flowchart illustrating a signal processing method according to an embodiment of the present invention.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

1 is a block diagram illustrating a configuration of a transmission device according to a first embodiment of the present invention. Referring to FIG. 1, the transmission device 100 includes an encoder 110, an interleaver 120, and a modulator 130 (or, it may be referred to as a'constellation mapper').

The encoder 110 generates an LDPC codeword by performing LDPC (Low Density Parity Check) encoding. To this end, the encoder 110 may include an LDPC encoder (not shown) that performs LPDC encoding.

Specifically, the encoder 110 may perform LDPC encoding on the input bits as information word bits, thereby generating an LDPC codeword composed of information word bits and parity bits (ie, LDPC parity bits). . In this case, since the LPDC code is a systematic code, the information word bits may be included in the LDPC code word as it is.

In this case, the LDPC codeword is composed of information word bits and parity bits. For example, the LDPC codeword is composed of _{N ldpc} bits, and may include information word bits composed of _{K ldpc bits and parity} bits composed of N parity = N _ldpc -K _{ldpc bits.}

In this case, the encoder 110 may generate an LDPC codeword by performing LDPC encoding based on a parity check matrix (PCM). That is, since the process of performing LDPC encoding is a process of ^{generating an LDPC codeword to satisfy H·C T} = 0, the encoder 110 may use a parity check matrix during LDPC encoding. Here, H denotes a parity check matrix, and C denotes an LDPC codeword.

To this end, the transmission device 100 may include a separate memory to pre-store various types of parity check matrices.

For example, the transmission device 100 may include Digital Video Broadcasting-Cable version 2 (DVB-C2), Digital Video Broadcasting-Satellite-Second Generation (DVB-S2), Digital Video Broadcasting-Second Generation Terrestria (DVB-T2), etc. The parity check matrix defined in the standard of is stored in advance, or the parity check matrix defined in the Advanced Television Systems Committee (ATSC) 3.0 standard, a North American digital broadcasting standard system currently being established, may be pre-stored. However, this is only an example, and the transmission device 100 may pre-store various types of parity check matrices.

Hereinafter, a structure of a parity check matrix will be described in detail with reference to FIGS. 2 and 3.

Referring to FIG. 2, the parity check matrix 200 includes an information word partial matrix 210 that is a partial matrix corresponding to information word bits and a parity partial matrix 220 that is a partial matrix corresponding to parity bits. The elements of the parity check matrix 200 except for 1 are 0.

_{The information word sub-} matrix 210 includes K ldpc columns, and the parity _sub - _{matrix 220 includes N parity} =N _{ldpc -K ldpc} columns. Meanwhile, the number of rows of the parity check matrix 200 is equal to _{the number of columns of the parity sub} -matrix 220 N parity =N _{ldpc -K ldpc.}

In addition, in the parity check matrix 200, N _ldpc represents the length of the LDPC codeword, K _ldpc represents the length of the information bits, and N _parity =N _ldpc -K _ldpc represents the length of the parity bits. Here, the lengths of the LDPC codeword, information word bits, and parity bits mean the number of bits included in each of the LDPC codeword, information word bits, and parity bits.

Hereinafter, the structure of the information word sub-matrix 210 and parity sub-matrix 220 will be described.

_{The information word sub-} matrix 210 is a matrix including K ldpc columns (ie, K _ldpc -1 th column from the 0 th column), and follows the following rules.

_{First, K ldpc} columns constituting the information word submatrix 210 belong to the same group by M, and are divided into a _{total of K ldpc /M column groups.} Columns belonging to the same column group have a relationship that is cyclic shifted by _{Q ldpc.}

Here, M is an interval at which a column pattern is repeated in the information word partial matrix 210 (for example, M=360), and Q _ldpc is a size at which each column is cyclically shifted in the information word partial matrix 210. M and Q _ldpc are integers, and _{are determined so that Q ldpc} = (N _ldpc -K _ldpc )/M is established. At this time, K _ldpc /M is also an integer. Meanwhile, M and Q _ldpc may have various values according to the length and code rate of the LDPC codeword.

For example, when M=360 and the length N _ldpc of the LDPC codeword is 64800, Q _ldpc is defined as in Table 1 below, and when M=360 and the length N _ldpc of the LDPC codeword is 16200, Q _ldpc is as follows: It can be defined as shown in Table 2 of.

이라 하면, i 번째 열 그룹 내의 j 번째 열에서 k 번째 무게-1(weight-1)이 위치한 행의 인덱스

(즉, i 번째 열 그룹 내의 j 번째 열에서 k 번째 1이 위치한 행의 인덱스)는 하기의 수학식 1과 같이 결정된다.Second, the degree of the 0th column of the i-th (i=0,1,..,K _ldpc /M-1) column group (here, the degree is the number of 1 values in the column, in the same column group). The order of all the columns belonging to it is the same), and D _i , and the position (or index) of each row with a 1 in the 0th column of the i-th column group.

In this case, the index of the row where the kth weight-1 is located in the j-th column in the i-th column group.

(That is, the index of the row in which the k-th 1 is located in the j-th column in the i-th column group) is determined as in Equation 1 below.

Here, k=0,1,2,..,D _i -1, i=0,1,..,K _ldpc /M-1, j=1,2,...,M-1.

Meanwhile, Equation 1 may be expressed in the same manner as in Equation 2 below.

Here, k=0,1,2,..,D _i -1, i=0,1,..,K _ldpc /M-1, j=1,2,...,M-1.

는 i 번째 열 그룹 내의 j 번째 열에서 k 번째 무게-1이 위치한 행의 인덱스, N_ldpc는 LDPC 부호어의 길이, K_ldpc는 정보어 비트들의 길이, D_i는 i 번째 열 그룹에 속하는 열들의 차수, M은 하나의 열 그룹에 속하는 열의 개수, Q_ldpc는 각 열이 시클릭 쉬프트되는 크기를 의미한다.In these equations,

Is the index of the row in which the k-th weight-1 is located in the j-th column in the i-th column group, N _ldpc is the length of the LDPC codeword, K _ldpc is the length of the information word bits, and D _i is the columns belonging to the i-th column group. The order, M is the number of columns belonging to one column group, and Q _ldpc is the size at which each column is cyclically shifted.

값만을 알면 i 번째 열 그룹 내의 j 번째 열에서 k 번째 무게-1이 있는 행의 인덱스

를 알 수 있게 된다. 그러므로, 각각의 열 그룹 내의 첫 번째 열에서 k 번째 무게-1이 있는 행의 인덱스 값을 저장하면, 도 2의 구조를 갖는 패리티 검사 행렬(200)(즉, 패리티 검사 행렬(200)의 정보어 부분 행렬(210))에서 무게-1이 있는 열과 행의 위치가 파악될 수 있다.After all, referring to these equations

If only the value is known, the index of the row with kth weight-1 in the jth column in the ith column group

Will be able to know. Therefore, if the index value of the row with the kth weight-1 in the first column in each column group is stored, the parity check matrix 200 having the structure of FIG. 2 (that is, the information word of the parity check matrix 200) In the partial matrix 210, the positions of the columns and rows with weight-1 may be identified.

According to the above-described rules, all the orders of columns belonging to the i-th column group are the same as _{D i.} Accordingly, the LDPC code storing information on the parity check matrix according to the above-described rules can be briefly expressed as follows.

For example, the N _ldoc 30, K _ldpc is 15, Q _ldpc the case of three, position information of the rows are in weight -1 in the 0th column of the three columns group to represented by a sequence such as the equation (3) May be, and this may be referred to as a'weight-1 position sequence'.

는 i번째 열 그룹 내의 j번째 열에서 k번째 무게-1이 있는 행의 인덱스를 의미한다.From here,

Denotes the index of the row with the k-th weight-1 in the j-th column in the i-th column group.

Weight-1 position sequences such as Equation 3 indicating the index of the row at which 1 is located in the 0th column of each column group may be more simply expressed as shown in Table 3 below.

Table 3 shows the positions of elements with weight-1, that is, 1 in the parity check matrix, and the i-th weight-1 position sequence is the row with weight-1 in the 0-th column belonging to the i-th column group. Expressed by indices.

Based on the above description, the information word partial matrix 210 of the parity check matrix according to an embodiment of the present invention may be defined by Tables 4 to 22 below.

Specifically, Tables 4 to 22 show the indexes of the row in which 1 is located in the 0-th column of the i-th column group of the information word submatrix 210. That is, the information word submatrix 210 is composed of a plurality of column groups each including M columns, and the position of 1 in the 0-th column of each of the plurality of column groups may be defined by Tables 4 to 22. .

Here, the indexes of the row where 1 is located in the 0-th column of the i-th column group means “addresses of parity bit accumulators”. Meanwhile, since “addresses of parity bit accumulators” has the same meaning as defined in standards such as DVB-C2/S2/T2 or ATSC 3.0 standards currently being established, detailed descriptions will be omitted.

As an example, if the length N _ldpc of the LDPC codeword is 16200, the code rate is 5/15, and M is 360, the indexes of the row at which 1 is located in the 0th column of the i-th column group of the information word submatrix 210 are It is shown in Table 4 below.

As another example, if the length N _ldpc of the LDPC codeword is 16200, the code rate is 6/15, and M is 360, the indexes of the row at which 1 is located in the 0th column of the i-th column group of the information word submatrix 210 are It is shown in Table 5 below.

As another example, when the length N _ldpc of the LDPC codeword is 16200, the code rate is 7/15, and M is 360, the index of the row at which 1 is located in the 0-th column of the i-th column group of the information word submatrix 210 They are shown in Table 6 below.

As another example, when the length N _ldpc of the LDPC codeword is 16200, the code rate R is 8/15, and M is 360, The indices are the same as in Table 7, Table 8, or Table 9 below.

As another example, when the length N _ldpc of the LDPC codeword is 16200, the code rate is 9/15, and M is 360, the index of the row where 1 is located in the 0th column of the i-th column group of the information word submatrix 210 They are shown in Table 10 below.

As another example, when the length N _ldpc of the LDPC codeword is 16200, the code rate is 10/15, and M is 360, the index of the row at which 1 is located in the 0th column of the i-th column group of the information word submatrix 210 They are shown in Table 11, Table 12, or Table 13 below.

As another example, when the length N _ldpc of the LDPC codeword is 16200, the code rate is 11/15, and M is 360, the index of the row at which 1 is located in the 0-th column of the i-th column group of the information word submatrix 210 They are shown in Table 14 below.

As another example, when the length N _ldpc of the LDPC codeword is 16200, the code rate is 12/15, and M is 360, the index of the row at which 1 is located in the 0-th column of the i-th column group of the information word submatrix 210 They are shown in Table 15 or Table 16 below.

As another example, when the length N _ldpc of the LDPC codeword is 16200, the code rate is 13/15, and M is 360, the index of the row at which 1 is located in the 0-th column of the i-th column group of the information word submatrix 210 They are shown in Table 17 below.

As another example, when the length N _ldpc of the LDPC codeword is 64800, the code rate is 6/15, and M is 360, the index of the row at which 1 is located in the 0-th column of the i-th column group of the information word submatrix 210 They are shown in Table 18 below.

As another example, when the length N _ldpc of the LDPC codeword is 64800, the code rate is 7/15, and M is 360, the index of the row at which 1 is located in the 0th column of the i-th column group of the information word submatrix 210 They are shown in Table 19 or Table 20 below.

As another example, when the length N _ldpc of the LDPC codeword is 64800, the code rate is 8/15, and M is 360, the index of the row at which 1 is located in the 0-th column of the i-th column group of the information word submatrix 210 They are shown in Table 21 below.

As another example, when the length N _ldpc of the LDPC codeword is 64800, the code rate is 9/15, and M is 360, the index of the row at which 1 is located in the 0th column of the i-th column group of the information word submatrix 210 They are shown in Table 22 below.

In that the parity check matrix of the same sign even if the order of the numbers in the sequence corresponding to each i-th column group is changed in Tables 4 to 20 described above, the order in the sequence corresponding to each i-th column group in Tables 4 to 22 A case in which is changed may be an example of a code considered in the present invention.

In addition, since algebraic characteristics such as cycle characteristics and order distribution on the graph of signs do not change even if the order of arrangement of the sequences corresponding to each column group in Tables 4 to 22 is changed, the order of arrangement of the sequences shown in Tables 4 to 22 is changed. The change can be an example.

_{In addition, as a result of adding multiples of Q ldpc} equally to all the sequences corresponding to an arbitrary column group in Tables 4 to 22, also because algebraic characteristics such as cycle characteristics or order distribution on the graph of signs do not change, Table 4 A result of adding multiples of _{Q ldpc} equally to all the sequences shown in Table 22 may be an example. It should be noted here that if the value is more than _{(N ldpc} -K _{ldpc ) when the given sequence is added by a multiple of Q ldpc , the value is modulo (N ldpc} -K _ldpc ). It means that you have to apply it by replacing it with the applied value.

On the other hand, as shown in Tables 4 to 22, when the position of the row in which 1 is present in the 0-th column of the i-th column group of the information word sub-matrix 210 is defined, it is _cyclically shifted by Q ldpc to The position of the row with 1 in the column can be defined.

For example, in the case of Table 4, in the case of the 0th column of the 0th column group of the information word submatrix 210, the 245th row, the 449th row, the 491th row, ... There is 1 in

In this case, since Q _ldpc =(N _ldpc -K _ldpc )/M=(16200-5400)/360=30, the index of the row where 1 is located in the 1st column of the 0th column group is 275(=245+30) , 479(=449+30), 521(=491+30),... , And the index of the row where 1 is located in the second column of the 0-th column group may be 305 (=275+30), 509 (=479+30), 551 (=521+30),...

In this way, the index of the row where 1 is located in all rows of each column group can be defined.

Meanwhile, in the parity check matrix 200 as shown in FIG. 2, the parity partial matrix 220 may be defined as follows.

A parity part matrix (220) is a sub-matrix that includes N columns _{ldpc ldpc} -K (i. E., K _ldpc second column from the second column N _ldpc -1), and has a dual-diagonal (diagonal dual or staircase) structure. _{Accordingly, the order of the remaining columns except for the last column (ie, N ldpc} -1st column) among the columns included in the parity sub-matrix 220 is 2, and the order of the last column is 1.

Consequently, in the parity check matrix 200, the information word sub-matrix 210 is defined by Tables 4 to 22, and the parity sub-matrix 220 may have a double diagonal structure.

Meanwhile, when the columns and rows of the parity check matrix 200 shown in FIG. 2 are permutated based on Equations 4 and 5 below, the parity check matrix 200 shown in FIG. It may be represented in the form of a parity check matrix 300 shown in FIG.

A method of performing permutation based on Equation 4 and Equation 5 is as follows. Here, since the same principle applies to row permutation and column permutation, the row permutation will be described as an example.

In the case of row permutation, _{i and j satisfying X=Q ldpc} ×i+j are calculated for the X-th row, and the calculated i and j are substituted for M×j+i, and the X-th row is permutated. Will yield. For example, in the case of the 7th row, i,j satisfying 7=2×i+j becomes 3,1, respectively, so the 7th row is permutated to 10×1+3=13th row.

When row permutation and column permutation are performed in this manner, the parity check matrix of FIG. 2 can be expressed as shown in FIG. 3.

Referring to FIG. 3, the parity check matrix 300 divides the parity check matrix 300 into a plurality of partial blocks, and each of the partial blocks is quasi-cyclic of M×M size. It has a form that matches the matrix.

Accordingly, the parity check matrix 300 having the structure as shown in FIG. 3 is configured in units of an M×M matrix. That is, the parity check matrix 300 is configured by arranging partial matrices having a size of M×M in a plurality of partial blocks.

As described above, since the parity check matrix 300 is composed of a quasi-circular matrix unit of M×M size, M columns may be referred to as column-blocks and M rows may be referred to as row-blocks. have. Accordingly, the parity check matrix 300 having the structure as shown in FIG. 3 used in the present invention _{is composed of N qc _ column} = N _ldpc / M column blocks and N _{qc _ row} = N _parity / M row blocks. It can be seen as.

Hereinafter, a partial matrix having an M×M size will be described.

First, the (N _{qc _ column} -1)-th column block of the 0-th row block has the form of Equation 6 below.

As such, A(330) is an M×M matrix, and values of the 0th row and the (M-1)th column are all '0', and for 0≤i≤(M-2), the values of the i-th column are (i+ 1) The first row is '1' and all other values are '0'.

Second, in the parity part matrix _{(320) 0≤i≤ (N ldpc -K} ldpc) with respect to _{/ M-1 (K ldpc /} M + i) i -th row block of the first column block is a unit matrix I _{M × M} ( 340). Further, in _{0≤i≤ (N ldpc -K ldpc) /} M-2 with respect to the (K _ldpc / M + i) th column of the block (i + 1) th row block is an identity matrix I _{M × M} (340) It is composed.

또는, 순환 행렬 P가 시클릭 쉬프트된 행렬

이 합해진 형태(또는, 중첩된 형태)가 될 수 있다. Third, the block 350 constituting the information word sub-matrix 310 is a cyclic matrix P in the form of a cyclic shift.

Or, a matrix in which the cyclic matrix P is cyclically shifted

This can be a combined form (or a superimposed form).

For example, a form in which the cyclic matrix P is cyclically shifted by 1 in the right direction may be expressed as Equation 7 below.

The circulating matrix P is a square matrix having a size of M×M, and the circulating matrix P represents a matrix in which the weight of each of the M rows is 1 and the weight of each of the M columns is also 1. In addition _{, when the superscript a ij} is 0, that is, P ⁰ represents the identity matrix I _{M ×M} , and when the superscript a _ij is ∞, that is, P ^∞ represents a zero matrix.

가 될 수 있다. 따라서, i와 j는 정보어 부분에 해당하는 부분 블록들의 행 블록과 열 블록의 개수를 나타낸다. 따라서, 패리티 검사 행렬(300)은 전체 열의 개수가 N_ldpc=M×N_{qc _ column}이고, 전체 행의 개수가 N_parity=M×N_{qc _ row}가 된다. 즉, 패리티 검사 행렬(300)은 N_{qc _ column} 개의 "열 블록"과 N_{qc _ row} 개의 "행 블록"으로 구성된다.Meanwhile, in FIG. 3, the partial matrix present at the intersection of the i-th row block and the j-th column block of the parity check matrix 300 is

Can be. Accordingly, i and j denote the number of row blocks and column blocks of partial blocks corresponding to the information word part. Accordingly, in the parity check matrix 300, the total number of columns is N _ldpc = M×N _{qc _ column} , and the total number of rows is N _parity = M×N _{qc _ row} . That is, the parity check matrix 300 is composed of N _{_ qc column} of "column block" and N _{qc _ row} of "line block".

Returning to FIG. 1, the encoding unit 110 includes various codes such as 5/15, 6/15, 7/15, 8/15, 9/15, 10/15, 11/15, 12/15, 13/15, etc. LDPC encoding can be performed using the rate. In addition, the encoder 110 may generate LDPC codewords having various lengths such as 16200, 64800, etc. based on the length and code rate of the information word bits.

In this case, the encoder 110 may perform LDPC encoding using the parity check matrix, and a specific structure of the parity check matrix has been described above with reference to FIGS. 2 and 3.

In addition, the encoder 110 may perform not only LDPC encoding but also Bose, Chaudhuri, Hocquenghem (BCH) encoding. To this end, the encoder 110 may further include a BCH encoder (not shown) that performs BCH encoding.

In this case, the encoder 110 may perform encoding in the order of BCH encoding and LDPC encoding. Specifically, the encoder 110 performs BCH encoding on the input bits to add a BCH parity bit, and LDPC encoding the bits to which the BCH parity bit is added as information word bits to generate an LDPC codeword. You may.

The interleaver 120 interleaves the LDPC codeword. That is, the interleaver 120 may receive the LDPC codeword from the encoder 110 and interleave the LDPC codeword based on various interleaving rules.

In particular, the interleaver 120 includes a plurality of groups (or a plurality of bit groups or blocks) constituting the LDPC codeword, so that the bits included in the preset group are mapped to the preset bits in the modulation symbol. Can be interleaved. Accordingly, the modulator 130 may map a bit included in a preset group among a plurality of groups constituting the LDPC codeword to a preset bit in the modulation symbol.

Hereinafter, the interleaving rule used by the interleaver 120 will be described in more detail by dividing the cases.

block Interleaver When to use

According to an embodiment of the present invention, the interleaver 120 interleaves the LDPC codeword through the following method, so that a bit included in a preset group among a plurality of groups constituting the interleaved LDPC codeword is included in the modulation symbol. It can be mapped to a preset bit. Refer to FIG. 4 for a detailed description.

4 is a block diagram illustrating a structure of an interleaver according to an embodiment of the present invention. Referring to FIG. 4, the interleaver 120 includes a parity interleaver 121, a group interleaver (or group-wise interleaver, 122), a group twist interleaver 123, and a block interleaver 124.

The parity interleaver 121 interleaves parity bits constituting the LDPC codeword.

Specifically, when the LDPC codeword is generated based on the parity check matrix 200 having the structure as shown in FIG. 2, the parity interleaver 121 interleaves only parity bits among the LDPC codewords using Equation 8 below. I can.

)에 대해 패리티 인터리빙을 수행하여 U=(u₀,u₁,…,

)를 출력할 수 있다.Here, M is the interval at which the column pattern is repeated in the information word submatrix 210, that is, the number of columns included in the column group (for example, M=360), and Q _ldpc is each This is the size at which the column is cyclically shifted. That is, the parity interleaver 121 uses the LDPC codeword c=(c ₀ ,c ₁ ,...,

) By performing parity interleaving to U=(u ₀ ,u ₁ ,…,

) Can be printed.

Meanwhile, when the LDPC codeword coded based on the parity check matrix 200 shown in FIG. 2 is parity interleaved based on Equation 8, the parity interleaved LDPC codeword is coded by the parity check matrix 300 shown in FIG. It becomes the same as the LDPC codeword. Accordingly, when the LDPC codeword is generated based on the parity check matrix 300 as shown in FIG. 3, the parity interleaver 121 may be omitted.

Meanwhile, the LDPC codewords encoded based on the parity check matrix 200 having the shape of FIG. 2 and then parity-interleaved and the LDPC codewords coded based on the parity check matrix 300 having the shape of FIG. Consecutive bits may be configured to have similar decoding characteristics (eg, cycle distribution, order of columns, etc.).

For example, the LDPC codeword may have the same characteristics in units of M consecutive bits. Here, M is an interval at which a column pattern is repeated in the information word partial matrix, and may be 360, for example.

Specifically, the product of the LDPC codeword bits and the parity check matrix must be '0', which means that i is the i-th LDPC codeword bit c _{i from 0 to N ldpc} -1 (i=0,1,..., N _{This means that the sum of the products of ldpc} -1) and the column of the i-th parity check matrix must be a '0' vector. Accordingly, it can be seen that the i-th LDPC codeword bit corresponds to the i-th column of the parity check matrix.

Meanwhile, in the case of the parity check matrix 200 as shown in FIG. 2, the information word sub-matrix 210 belongs to the same group for each of M columns, and has the same characteristics for each column group (e.g., in the same column group). The columns have the same order distribution and the same cycle characteristics).

In this case, since M consecutive bits of the information word bits correspond to the same column group of the information word submatrix 210, the information word bits may be composed of M consecutive bits having the same codeword characteristics. . Meanwhile, when parity bits of the LDPC codeword are interleaved by the parity interleaver 121, the parity bits of the LDPC codeword may also be composed of M consecutive bits having the same codeword characteristics.

Meanwhile, in the case of the parity check matrix 300 as shown in FIG. 3, the information word partial matrix 310 and the parity partial matrix 320 of the parity check matrix 300 include M columns by row and column permutation. Since each column group has the same characteristics, the information word bits and the parity bits of the LDPC codeword encoded based on the parity check matrix 300 may be composed of consecutive M bits having the same codeword characteristics. .

Here, since row permutation only rearranges the order of rows in the parity check matrix, it does not affect the algebraic characteristics of the LDPC code itself, such as cycle characteristics, order distribution, and minimum distance. In addition, in the case of column permutation, the LDPC encoded by the parity check matrix 300 as shown in FIG. 3 is performed on the parity sub-matrix 320 to correspond to the parity interleaving performed by the parity interleaver 121. The parity bits of the codeword may be composed of M consecutive bits, such as the parity bits of the LDPC codeword coded by the parity check matrix 200 as shown in FIG. 2.

In this way, bits constituting the LDPC codeword may have the same characteristics in units of consecutive M bits.

The group interleaver 122 may divide the LDPC codeword into a plurality of groups, and rearrange the order of the plurality of groups in a group wise manner. Alternatively, the group interleaver 122 may divide the parity-interleaved LDPC codeword into a plurality of groups, and rearrange the order of the plurality of groups in a group wise manner.

That is, the group interleaver 122 may interleave a plurality of groups in group units.

To this end, the group interleaver 122 divides the parity interleaved LDPC codeword into a plurality of groups using Equation 9 or Equation 10 below.

는 k/360 이하의 가장 큰 정수를 나타낸다. In these equations, N _group denotes the total number of groups, X _j denotes the j-th group, and u _k denotes the k-th LDPC codeword bit input to the group interleaver 122. And,

Represents the largest integer of k/360 or less.

Meanwhile, in these equations, 360 denotes an example of M, which is an interval at which a column pattern is repeated in the information word partial matrix, and in these equations, 360 can be changed to M.

Meanwhile, LDPC codewords divided into a plurality of groups may be represented as shown in FIG. 5.

Referring to FIG. 5, it can be seen that the LDPC codeword is divided into a plurality of groups, and each group is composed of M consecutive bits. Here, when M is 360, each of the plurality of groups may consist of 360 bits. Accordingly, each group may be composed of bits corresponding to each column group of the parity check matrix.

Specifically, since the LDPC codeword is divided by M consecutive bits, K _ldpc information word bits are _{divided into (K ldpc} /M) groups, and N _ldpc -K _ldpc parity bits are (N _ldpc -K _ldpc ) It is divided into /M groups. Accordingly, LDPC codewords can be classified into a _{total of (N ldpc /M) groups.} For example, when M=360, when the length of the LDPC codeword N _ldpc is 64800, the number of groups N _group is 180, and when the length N _ldpc of the LDPC codeword is 16200, the number of groups N _group is 45. I can.

As described above, the group interleaver 122 divides the LDPC codeword into the same group by M consecutive bits because the LDPC codeword has the same codeword characteristics in units of M consecutive bits as described above. Accordingly, when the LDPC codeword is divided into M consecutive bits, bits having the same codeword characteristics may be included in the same group.

Meanwhile, in the above-described example, it has been described that the number of bits constituting each group is M, but this is only an example, and the number of bits constituting each group can be variously changed.

For example, the number of bits constituting each group may be a factor of M. That is, the number of bits constituting each group may be a factor of the number of columns constituting the column group of the submatrix information word of the parity check matrix. In this case, each group may consist of a divisor of M bits. For example, when the number of columns constituting the column group of the information word submatrix is 360, that is, when M=360, the group interleaver 122 determines which one of the divisors of 360 is the number of bits constituting each group. As far as possible, the LDPC codewords can be divided into a plurality of groups.

However, hereinafter, for convenience of description, only the case where the number of bits constituting the group is M will be described.

Thereafter, the group interleaver 122 interleaves the LDPC codeword in group units. That is, the group interleaver 122 may rearrange the order of a plurality of groups constituting the LDPC codeword in groups by changing positions of a plurality of groups constituting the LDPC codeword.

Here, the group interleaver 122 may rearrange the order of the plurality of groups in groups so that groups including bits mapped to the same modulation symbol among the plurality of groups are spaced apart by a predetermined interval.

In this case, the group interleaver 122 considers the number of rows and columns constituting the block interleaver 124, the number of groups constituting the LDPC codeword, and the number of bits included in each group. The order of a plurality of groups may be rearranged in group units so that groups including the groups are spaced apart by a predetermined interval.

To this end, the group interleaver 122 may rearrange the order of a plurality of groups in group units using Equation 11 below.

Here, X _j denotes the j-th group before group interleaving, and Y _j denotes the j-th group after group interleaving. In addition, π(j) is a parameter indicating an interleaving order, and may be determined by at least one of a length, a code rate, and a modulation method of the LDPC codeword.

Accordingly, X _π(j) denotes the π(j)-th group before group interleaving, and Equation 11 means that the π(j)-th group before interleaving is interleaved into the j-th group after interleaving.

Meanwhile, a specific example of π(j) according to an embodiment of the present invention may be defined as shown in Tables 23 to 27 below.

In this case, π(j) is defined according to the length and code rate of the LDPC codeword, and the parity check matrix is also defined according to the length and code rate of the LDPC codeword. Therefore, when LDPC coding is performed based on a specific parity check matrix according to the length and code rate of the LDPC codeword, the LDPC codeword is group-wise based on π(j) that satisfies the length and code rate of the LDPC codeword. Can be interleaved with.

For example, when the encoder 110 performs LDPC encoding at a code rate of 10/15 to generate an LDPC codeword having a length of 16200, the group interleaver 122 is selected from Tables 23 to 27 below. Interleaving may be performed using π(j) defined in the LDPC codeword having a length of 16200 and a code rate of 10/15.

For example, when the length of the LDPC codeword is 16200, the code rate is 10/15, and the modulation method is 16-QAM (quadrature amplitude modulation), the group interleaver 122 uses π(j) defined as shown in Table 23. Interleaving can be performed by using.

Meanwhile, a specific example of π(j) is as follows.

As an example, when the length N _ldpc of the LDPC codeword is 16200, the code rate is 10/15, 11/15, 12/15, 13/15, and the modulation method is 16-QAM, π(j) is shown in Table 23 below. It can be defined as

In the case of Table 23, Equation 11 is Y ₀ =X _π(0) =X ₃₅ , Y ₁ =X _π(1) =X ₃₁ , Y ₂ =X _π(2) =X ₃₉ ,..., Y ₄₃ =X _π(43) =X ₁₅ , Y ₄₄ =X _π(44) =X ₄₄ . Accordingly, the group interleaver 122 is the 35th group as the 0th, the 31st group as the 1st, the 39th group as the 2nd, ..., the 15th group as the 43rd, and the 44th group as 44 The order of the plurality of groups may be rearranged in units of groups by changing the order.

As another example, when the length N _ldpc of the LDPC codeword is 16200, the code rate is 6/15, 7/15, 8/15, 9/15, and the modulation method is 64-QAM, π(j) is shown in Table 24 below. It can be defined as

In the case of Table 24, Equation 11 is Y ₀ =X _π(0) =X ₁₈ , Y ₁ =X _π(1) =X ₃₁ , Y ₂ =X _π(2) =X ₄₁ ,..., Y ₄₃ =X _π(43) =X ₄₃ , Y ₄₄ =X _π(44) =X ₄₄ . Accordingly, the group interleaver 122 is the 18th group as the 0th, the 31st group as the 1st, the 41st group as the second, ..., the 43rd group as the 43rd, and the 44th group as 44 The order of the plurality of groups may be rearranged in units of groups by changing the order of the first time.

As another example, when the length N _ldpc of the LDPC codeword is 16200, the code rate is 10/15, 11/15, 12/15, 13/15, and the modulation method is 256-QAM, π(j) is shown in Table 25 below. It can be defined as

In the case of Table 25, Equation 11 is Y ₀ =X _π(0) =X ₄ , Y ₁ =X _π(1) =X ₁₃ , Y ₂ =X _π(2) =X ₃₁ ,..., Y ₄₃ =X _π(43) =X ₄₃ , Y ₄₄ =X _π(44) =X ₄₄ . Accordingly, the group interleaver 122 is the 4th group as the 0th, the 13th group as the 1st, the 31st group as the 2nd, ..., the 43rd group as the 43rd, and the 44th group as 44 The order of the plurality of groups may be rearranged in units of groups by changing the order.

As another example, when the length N _ldpc of the LDPC codeword is 16200, the code rate is 6/15, 7/15, 8/15, 9/15, and the modulation method is 1024-QAM, π(j) is shown in Table 26 below. It can be defined as

In the case of Table 26, Equation 11 is Y ₀ =X _π(0) =X ₁₀ , Y ₁ =X _π(1) =X ₂ , Y ₂ =X _π(2) =X ₂₈ ,..., Y ₄₃ =X _π(43) =X ₄₃ , Y ₄₄ =X _π(44) =X ₄₄ . Accordingly, the group interleaver 122 is the 10th group as the 0th, the 2nd group as the 1st, the 28th group as the 2nd, ..., the 43rd group as the 43rd, and the 44th group as 44 The order of the plurality of groups may be rearranged in units of groups by changing the order.

As another example, when the length N _ldpc of the LDPC codeword is 64800, the code rates are 6/15, 7/15, 8/15, 9/15, and the modulation method is 256-QAM, π(j) is shown in Table 27 below. It can be defined as

In the case of Table 27, Equation 11 is Y ₀ =X _π(0) =X ₉ , Y ₁ =X _π(1) =X ₆ , Y ₂ =X _π(2) =X ₁₆₀ ,..., Y _It can be expressed as 178 =X _π(178) =X ₁₇₇ , Y ₁₇₉ =X _π(179) =X _176. Accordingly, the group interleaver 122 sets the ninth group to the 0th, the 6th group to the 1st, the 160th group to the second,..., the 177th group to the 178th, and the 176th group to the 179 The order of the plurality of groups may be rearranged in units of groups by changing the order.

In this way, the group interleaver 12 may rearrange the order of a plurality of groups in group units using Equation 11 and Tables 23 to 27.

On the other hand, in that the groups constituting the LDPC codeword are rearranged in group units by the group interleaver 122 and then block interleaved by the block interleaver 124, which will be described later, π(j ) In relation to "Order of bits group to be block interleaved".

According to this method, the group-interleaved LDPC codeword is shown in FIG. 6. When comparing the LDPC codeword shown in FIG. 6 with the LDPC codeword before group interleaving shown in FIG. 5, it can be seen that the order of a plurality of groups constituting the LDPC codeword is rearranged.

That is, as shown in FIGS. 5 and 6, the LDPC codeword is group X ₀ , group X ₁ , and so on before group interleaving. , Group X _{Ngroup -1} , group interleaved, group Y ₀ , group Y ₁ ,... , Group Y may be arranged in the order of _{Ngroup -1.} In this case, the order in which the groups are arranged by group interleaving may be determined based on Tables 23 to 27.

The group twist interleaver 123 interleaves the bits in the same group. That is, the group twist interleaver 123 may rearrange the order of bits in the same group by changing the order of bits existing in the same group.

In this case, the group twist interleaver 123 cyclically shifts the bits in the same group by a predetermined number of bits, and rearranges the order of the bits in the same group.

For example, as shown in FIG. 7, the group twist interleaver 123 may _{cyclically shift bits included in group Y 1} by 1 bit in the right direction. In this case, FIG. 7 in a group Y ₁ as the 0th, 1st, 2nd, ... , 358th and 359th bits are cyclically shifted to the right by 1 bit, and the 359th bit before the cyclic shift _{is located at the front of the group Y 1} and 0 before the cyclic shift is performed. 1st, 1st, 2nd,... The bits located at the 358th and 358th are in turn shifted to the right by 1 bit and located.

In addition, the group twist interleaver 123 cyclically shifts a different number of bits for each group to rearrange the order of bits in each group.

For example, the group twist interleaver 123 may cyclically _{shift the bits included in group Y 1} by 1 bit in the right direction, and cyclically shift the _{bits included in group Y 2} by 3 bits in the right direction. .

However, the group twist interleaver 123 described above may be omitted in some cases.

Further, in the above-described example, it has been described that the group twist interleaver 123 is disposed after the group interleaver 122, but this is also only an example. That is, the group twist interleaver 123 may be disposed before the group interleaver 122 in that the order of bits constituting a corresponding group within the group is changed, but not the order of the group itself.

The block interleaver 124 interleaves a plurality of groups in which the order is rearranged. Specifically, the block interleaver 124 is composed of a plurality of columns each including a plurality of rows, and each of the plurality of columns is a first part (part 1) according to the number of the plurality of columns and the number of groups. ) And the second part (part 2), the LDPC codeword can be interleaved.

In this case, a plurality of groups in which the order of the groups is rearranged by the group interleaver 122 may be interleaved in a group unit. Specifically, the block interleaver 124 includes a plurality of rearranged groups using the first part and the second part. Groups of can be divided according to modulation orders and interleaved.

Here, the number of groups interleaved in a group unit may be determined according to at least one of the number of rows and columns constituting the block interleaver 124, the number of groups, and the number of bits included in each group. That is, the block interleaver 124 determines a group interleaved in a group unit among a plurality of groups in consideration of at least one of the number of rows and columns constituting the block interleaver 124, the number of groups, and the number of bits included in each group. And, a corresponding group may be interleaved in a group unit, and the remaining groups may be divided and interleaved. For example, the block interleaver 124 may interleave at least a part of a plurality of groups in a group unit using a first part, and divide the remaining groups using a second part to perform interleaving.

Meanwhile, interleaving in a group unit means that bits included in the same group are written to the same column. That is, the block interleaver 124 writes the bits included in the same group to the same column without dividing the bits included in the same group in the case of a group interleaved in a group unit, and divides the bits included in the group in the case of a group not interleaved in a group unit Interleaving can be performed by writing to another row.

Accordingly, all groups interleaved by the first part are interleaved by writing bits included in the same group to the same column of the first part, and at least one group interleaved by the second part is at least It can be split into two columns and lighted.

Details of this interleaving method will be described later.

Meanwhile, the interleaving performed by the group twist interleaver 123 only changes the order of bits within the group, and the order of the group itself is not changed by interleaving. Accordingly, the order of the groups block interleaved by the block interleaver 124, that is, the order of the groups input to the block interleaver 124 may be determined by the group interleaver 122. For example, the order of groups to be block interleaved by the block interleaver 124 may be determined by π(j) defined in Tables 23 to 27.

As described above, the block interleaver 124 may be composed of a plurality of columns each including a plurality of rows, and the LDPC codeword may be interleaved by dividing the plurality of columns into at least two parts.

For example, the block interleaver 124 may interleave a plurality of groups constituting the LDPC codeword by dividing each of a plurality of columns into a first part and a second part.

In this case, the block interleaver 124 divides each of the plurality of columns N (N is an integer of 2 or more) depending on whether the number of groups constituting the LDPC codeword is an integer multiple of the number of columns constituting the block interleaver 124. Interleaving can be performed by dividing into parts of.

First, when the number of groups constituting the LDPC codeword is an integer multiple of the number of columns constituting the block interleaver 124, the block interleaver 124 configures the LDPC codeword without dividing each of the plurality of columns. A plurality of groups may be interleaved in a group unit.

Specifically, the block interleaver 124 writes a plurality of groups constituting the LDPC codeword in a column direction to each column in a group unit, and executes each row of a plurality of columns in which a plurality of groups are written in a group unit. Interleaving can be performed by reading in the direction.

In this case, the block interleaver 124 divides the number of groups constituting the LDPC codeword by the number of columns constituting the block interleaver 124 and divides the bits included in the group into a column direction in each of the plurality of columns. Interleaving may be performed by sequentially writing and reading each row of a plurality of columns to which bits are written in a row direction.

Hereinafter, for convenience of description, a group positioned at the j-th after being interleaved by the group interleaver 122 is referred to as group Y _j .

For example, it is assumed that the block interleaver 124 is _{composed of C columns including R 1 row.} And, consists of a LDPC codeword Y _group groups, it is assumed to be a multiple of the number of the Y _group is a group C.

In this case, since the quotient of the number of groups constituting the LDPC codeword, Ygroup, divided by the number C of the columns constituting the block interleaver 124 is Y group/C, the block interleaver 124 creates Y _group /C groups in each column. Interleaving may be performed by sequentially writing in a column direction and reading bits written in each column in a row direction.

For example, as shown in Figure 8, a block interleaver 124 1 from row R ₁ groups to the second row (Y _0), a group of the first column (Y _1), ..., a group (Y _{p -1} ) Write the bits included in each, and from the first row of the second column to the first row of R, _each of the group (Y _p ), group (Y _{p +1} ),..., group (Y _{q -1} ) the light with the bit, and ..., from the first row of the first column C ₁ group, R (Y _z), the group (Y _{z +1)} th row, ..., the group (Y _{Ngroup -1),} respectively Bits included in are written, and bits written in each row of a plurality of columns may be read in a row direction.

Accordingly, the block interleaver 124 interleaves all groups constituting the LDPC codeword in group units.

However, when the number of groups constituting the LDPC codeword does not become an integer multiple of the number of columns constituting the block interleaver 124, the block interleaver 124 divides each of the plurality of columns into two parts to determine the LDPC codeword. Some of the plurality of constituent groups may be interleaved in group units, and the remaining groups may be divided and interleaved. In this case, the bits included in the remaining group, that is, the bits included in the group as much as the remaining (remainder) when the number of groups constituting the LDPC codeword is divided by the number of columns, are not interleaved in a group unit. According to the number, each column may be divided and interleaved.

Specifically, the block interleaver 124 may interleave the LDPC codeword by dividing each of the plurality of columns into two parts.

In this case, the block interleaver 124 divides a plurality of columns into a first part and a plurality of columns based on the number of columns constituting the block interleaver 124, the number of groups constituting the LDPC codeword, and the number of bits constituting each of the plurality of groups. It can be divided into the second part.

Here, each of the plurality of groups may consist of 360 bits. In addition, the number of groups constituting the LDPC codeword is determined according to the length of the LDPC codeword and the number of bits included in each group. For example, if the LDPC codeword of length 16200 is divided so that each group consists of 360 bits, the LDPC codeword is divided into 45 groups, and the LDPC codeword of length 64800 is divided so that each group consists of 360 bits. DPC codewords can be classified into 180 groups. In addition, the number of columns constituting the block interleaver 124 may be determined according to a modulation method, and a specific example related thereto will be described later.

Accordingly, the number of rows constituting each of the first part and the second part is based on the number of columns constituting the block interleaver 124, the number of groups constituting the LDPC codeword, and the number of bits constituting each of the plurality of groups. Can be determined.

Specifically, in each of the plurality of columns, the first part comprises a plurality of LDPC codewords according to the number of columns constituting the block interleaver 124, the number of groups constituting the LDPC codeword, and the number of bits constituting each group. Each of the plurality of groups of may be composed of as many rows as the number of bits included in at least one group that can be written in a group unit.

In addition, the second part may be composed of rows in each of the plurality of columns, excluding rows as many as the number of bits included in at least some groups that can be written to each of the plurality of columns in a group unit. have. Specifically, the number of rows of the second part may have the same value as a quotient obtained by dividing the number of bits included in all bit groups except for the group corresponding to the first part by the number of columns constituting the block interleaver 124. . That is, the number of rows of the second part may have the same value as the quotient obtained by dividing the number of bits included in the remaining groups after being written to the first part among the groups constituting the LDPC codeword by the number of columns.

On the other hand, the block interleaver 124 includes a first part including a number of rows as many as the number of bits included in a group that can be written in a group unit in each column, and a second part including the remaining rows. Each of the columns can be identified.

Accordingly, the first part may be composed of rows as many as the number of bits included in the group, that is, an integer multiple of M. However, as described above, since the number of codeword bits constituting each group may be a factor of M, the first part may be composed of rows as many as an integer multiple of the number of bits constituting each group. have.

In this case, the block interleaver 124 may perform interleaving by writing and reading the LDPC codeword in the first part and the second part in the same manner.

Specifically, the block interleaver 124 writes the LDPC codeword in a column direction to a plurality of columns constituting each of the first part and the second part, and a plurality of the LDPC codewords constituting each of the first part and the second part to which the LDPC codeword is written. Interleaving can be performed by reading the columns of in the row direction.

That is, the block interleaver 124 sequentially writes bits included in at least some groups that can be written in a group unit in each of the plurality of columns to each of the plurality of columns constituting the first part, and writes at least some of the bits included in the plurality of columns constituting the first part. The bits included in the group other than the group are divided and written in a column direction to each of the plurality of columns constituting the second part, and the bits written to each of the plurality of columns constituting each of the first part and the second part are row Interleaving can be performed by reading in the direction.

In this case, the block interleaver 124 may perform interleaving by dividing the remaining groups excluding at least some of the groups from the plurality of groups based on the number of columns constituting the block interleaver 124.

Specifically, the block interleaver 124 divides the bits included in the remaining group into a plurality of columns, writes each of the divided bits to each of the plurality of columns constituting the second part in a column direction, and Interleaving may be performed by reading a plurality of columns constituting the second part to which they are written in a row direction.

That is, the block interleaver 124 writes to the first part of the plurality of groups constituting the LDPC codeword, and the remaining group, that is, the remaining group when the number of groups constituting the LDPC codeword is divided by the number of columns. Bits included in the group of are divided by the number of columns, and the divided bits may be sequentially written to each column of the second part in a column direction.

For example, it is assumed that the block interleaver 124 is _{composed of C columns including R 1 row.} And, it consists of a LDPC codeword _group Y groups, is not a multiple of the number of the Y _group is a group C, it is assumed the case of _{A × C + 1 = Y group} (A is an integer greater than 0). That is, when the number of groups constituting the LDPC codeword is divided by the number of columns, it is assumed that the quotient is A and the remainder is 1.

In this case, the block interleaver 124 may be divided into a second part including a first part and R ₂ rows of each column stores the _first row R as shown in Figs. In this case, R ₁ may be as many as the number of bits included in a group that can be written in a group unit in each column, and R ₂ may be a value excluding _{R 1} from the number of rows constituting each column.

That is, in the above-described example, the number of groups that can be written to each column in a group unit is A, and the first part of each column may consist of the number of bits included in the A group, that is, A×M rows.

In this case, the block interleaver 124 writes bits included in groups that can be written to each column in a group unit, that is, groups of A, in the column direction to the first part of each column.

That is, a block interleaver 124 is 9 and the first group from the row R _1, the second row (Y ₀₎ constituting a first part of the first column as shown in Figure 10, the group (Y _1), ..., group (Y _{n -1)} and light the bits included in each of the first group from the row R ₁ row constituting a first part of the second column (Y _n), the group (Y _{n +1)} ,. ., a group (Y _{m -1)} and light the bits included in respective, ..., the first group from the row R ₁ row constituting a first part of the column C (Y _e), group ( Bits included in each of Y _{e +1} ),..., and groups (Y _{Ngroup -2) are written.}

In this way, the block interleaver 124 writes bits included in a group that can be written in a group unit to each column in a group unit to the first part of each column.

That is, in the above-described example, _{the bits included in each of the group (Y 0} ), group (Y ₁ ), ..., group (Y _{n -1} ) are not divided and are all written to the first column, and the group (Y 1) _{The bits included in each of n} ), group (Y _{n +1} ),..., group (Y _{m -1} ) are not divided and are all written to the second column, ..., group (Y _e ), group Bits included in each of (Y _{e +1} ), ..., and group (Y _{Ngroup -2} ) may be written to the Cth column without being divided. In this way, in all groups interleaved by the first part, it can be seen that bits included in the same group are written to the same column of the first part.

Thereafter, the block interleaver 124 may divide bits included in a group other than the group written to the first part of each column among the plurality of groups, and write the bits included in the second part of each column in the column direction. At this time, the block interleaver 124 divides the bits included in the remaining groups excluding the group written to the first part of each column by the number of columns so that the same number of bits is written to the second part of each column, Can be lighted in each column of the second part in the column direction.

Here, each of the bits divided based on the number of columns may be referred to as a sub bit group. In this case, it can be seen that each sub bit group is written to each column of the second part.

In the above example, since A×C+1=Y _group is satisfied, when the groups constituting the LDPC codeword are sequentially written to the first part, the last group (Y _Ngroup-1 ) of the LDPC codeword is removed. Part 1 cannot be lighted and remains. _{Accordingly, the block interleaver 124 divides the bits included in the group (Y Ngroup -1} ) into C pieces as shown in FIG. 9, and divides each of the divided bits (that is, the bits included in the _{last group (Y Ngroup -1 )).} Bits equal to the quotient divided by C) may be sequentially written to the second part of each column.

That is, a block interleaver 124 from the first line to write a bit from the first line constituting the second part of the first column to the R _2-th row, and constituting a second part of the second column R ₂ row to write the bits, ..., it is possible to write a bit to the _second R-th row in the first line constituting the second part of the C column. In this case, the block interleaver 124 may write bits to the second part of each column in the column direction as shown in FIG. 9.

That is, in the second part, bits constituting a bit group are not written to the same column, but may be written to a plurality of columns. That is, in the above-described example, since the last group (Y _{Ngroup -1} ) is composed of M bits, _{the bits included in the last group (Y Ngroup -1} ) may be divided by M/C and written to each column. . That is, the bits included in the last group (Y _{Ngroup -1} ) are divided by M/C, and each divided M/C forms a sub-bit group, and each sub-bit group may be written to each column of the second part. .

Accordingly, the at least one group interleaved by the second part may be viewed as being written by dividing the bits included in the at least one group into at least two columns constituting the second part.

Meanwhile, in the above-described example, it has been described that the block interleaver 124 writes bits to the second part in the column direction, but this is only an example. That is, the block interleaver 124 may write bits to a plurality of columns of the second part in a row direction. In this case, the block interleaver 124 may write bits for the first part in the same manner as described above.

Specifically, referring to FIG. 10, the block interleaver 124 writes bits from the first row constituting the second part in the first column to the first row constituting the second part in the Cth column, and the first column. R 2 from the _second line constituting a second part in the second light, the bits from the second line to the second line constituting a second part in the C column, ..., and a first column constituting a part in the it is possible to write a bit to the second row R ₂ constituting the second part in the C column.

Meanwhile, the block interleaver 124 sequentially reads the bits written to each row of each part in the row direction. That is, the block interleaver 124 sequentially reads bits written in each row of a first part of a plurality of columns in a row direction, and bits written to each row of a second part of a plurality of columns, as shown in FIGS. 9 and 10 They can be sequentially read in the row direction.

Accordingly, the block interleaver 124 may perform interleaving by interleaving some of the plurality of groups constituting the LDPC codeword in group units, and dividing the rest of the groups. That is, the block interleaver 124 writes the LDPC codewords constituting a predetermined number of groups among the plurality of groups in a group unit to a plurality of columns constituting the first part, and writes the LDPC codewords constituting the remaining groups to the second. Interleaving may be performed by dividing and writing each column constituting a part, and reading a plurality of columns constituting the first and second parts in a row direction.

As such, the block interleaver 124 may interleave a plurality of groups using the method described with reference to FIGS. 8 to 10.

In particular, in the case of FIG. 9, the order of bits included in the group not belonging to the first part is rearranged in that bits included in the group not belonging to the first part are written in the column direction and read in the row direction to the second part. Can be. As described above, since bits included in a group not belonging to the first part are interleaved, bit error rate (BER)/frame error rate (FER) performance may be improved compared to a case where interleaving is not performed.

However, as shown in FIG. 10, a group that does not belong to the first part may not be interleaved. That is, as shown in FIG. 10, since the block interleaver 124 writes and reads bits included in a group not belonging to the first part in the row direction to the second part, bits included in the group not belonging to the first part are The order may not be changed and may be sequentially output to the modulator 130. In this case, bits included in a group not belonging to the first part may be sequentially output and mapped to a modulation symbol.

Meanwhile, in FIGS. 9 and 10, it has been described that the last one of the plurality of groups is written to the second part, but this is only an example, and the number of groups written to the second part is a group constituting the LDPC codeword. It goes without saying that it can be changed in various ways depending on the total number of, the number of columns and rows, and the number of transmit antennas.

Meanwhile, the block interleaver 124 may have different structures depending on whether bits included in the same group are mapped to one bit in the modulation symbol, or bits included in the same group are mapped to two bits in the modulation symbol. .

On the other hand, in the case of a transmission/reception system using a plurality of antennas, the number of columns constituting the block interleaver 124 may be determined by simultaneously considering the number of bits constituting the modulation symbol and the number of antennas used. For example, in a system in which bits included in the same group are mapped to one bit in a modulation symbol, and in a system using two antennas, the block interleaver 124 sets the number of columns to a multiple of the number of bits constituting the modulation symbol. You can decide.

First, when bits included in the same group are mapped to one bit in a modulation symbol, the block interleaver 124 may have a structure as shown in Tables 28 and 29 below.

Here, C (or N _c ) is the number of columns constituting the block interleaver 124, R ₁ is the number of rows constituting the first part in each column, and R ₂ is the second part constituting each column. Is the number of rows to do.

Referring to Tables 28 and 29, the number of columns has the same value as the modulation order according to the modulation method, and each of the plurality of columns is a row equal to the value obtained by dividing the number of bits constituting the LDPC codeword by the number of columns. It can be seen that it is composed of.

For example, when the length of the LDPC codeword is Nldpc=64800 and modulation is performed in the 16-QAM method, the modulation order is 4 in the case of 16-QAM, so the block interleaver 124 is composed of 4 columns, and each column is It can be seen that it consists of R1+R2=16200 (=64800/4) rows.

On the other hand, with reference to Table 28 and Table 29, when the number of the group constituting the LDPC codeword times the integer number of columns, the block interleaver 124 is the R ₁ each, in that interleaving without separate each column This is the number of rows that make up a column, and R ₂ =0. On the contrary, if the number of the group constituting the LDPC codeword that is not an integral multiple of the number of columns, the block interleaver 124, the second consisting of a first part and R ₂ rows which make up each column to the R ₁ rows Interleaving is performed by dividing into parts.

Meanwhile, as shown in Tables 28 and 29, when the number of columns of the block interleaver 124 is the same as the number of bits constituting a modulation symbol, bits included in the same group may be mapped to one bit in the modulation symbol.

For example, when N _ldpc =64800 and the modulation scheme is 16-QAM, the block interleaver 124 may be configured with 4 columns each including 16200 rows. In this case, a plurality of groups are written to four columns in a group unit, and bits written to the same row in each column are sequentially output. In this case, when the modulation scheme is 16-QAM, since 4 bits constitute one modulation symbol, bits included in the same group, that is, bits output from one column, may be mapped to one bit in the modulation symbol. have. For example, bits included in a group written to the first column may be mapped to the first bit of each modulation symbol.

Meanwhile, when bits included in the same group are mapped to two bits in a modulation symbol, the block interleaver 124 may have a structure as shown in Tables 30 and 31 below.

Here, C (or N _c ) is the number of columns constituting the block interleaver 124, R ₁ is the number of rows constituting the first part in each column, and R ₂ is the second part constituting each column. Is the number of rows to do.

Table 30 and a reference to Table 31, constituting the case where the number of groups constituting the LDPC codeword times the integer number of rows block interleaver 124 R ₁ in that it performs the interleaving does not separate each column, each column It becomes the number of rows and R ₂ =0. On the contrary, if the number of the group constituting the LDPC codeword that is not an integral multiple of the number of columns, the block interleaver 124, the second consisting of a first part and R ₂ rows which make up each column to the R ₁ rows Interleaving is performed by dividing into parts.

As shown in Tables 30 and 31, when the number of columns of the block interleaver 124 is half of the number of bits constituting the modulation symbol, bits included in the same group may be mapped to two bits in the modulation symbol.

For example, when N _ldpc =64800 and the modulation scheme is 16-QAM, the block interleaver 124 may be configured with two columns each including 32,400 rows. In this case, a plurality of groups are written in two columns in a group unit, and bits written in the same row in each column are sequentially output. Meanwhile, when the modulation scheme is 16-QAM, since 4 bits constitute one modulation symbol, bits output from two rows constitute one modulation symbol. Accordingly, bits included in the same group, that is, bits output from one column may be mapped to two bits in the modulation symbol. For example, bits included in a group written to the first column may be mapped to bits existing at two arbitrary positions in the modulation symbol.

Meanwhile, referring to Tables 28 to 31, it can be seen that the total number of rows of the block interleaver 124, that is, R ₁ +R ₂ is N _{ldpc /C.}

이고, 제2 파트의 행의 개수인 R₂는 N_ldpc/C-R₁이 될 수 있다. 여기에서,

는 N_group/C 이하의 가장 큰 정수를 나타낸다. 이와 같이, R₁은 각 그룹에 포함된 비트의 개수인 M의 정수 배가 된다는 점에서 R₁에는 그룹 단위의 비트들이 라이트될 수 있다. _{And, R 1, which} is the number of rows of the first part, is an integer multiple of M (eg, M=360), which is the number of bits included in each group.

_{And R 2, which} is the number of rows of the second part, may be _{N ldpc} /CR _1. From here,

_Represents the largest integer of N group /C or less. In this way, since R ₁ is an integer multiple of M, which is the number of bits included in each group, bits of a group unit may be written to _{R 1.}

In addition, referring to Tables 28 to 31, it can be seen that when the number of groups constituting the LDPC codeword is not a multiple of the number of columns, the block interleaver 124 divides each column into two parts and performs interleaving. I can.

Specifically, a value obtained by dividing the length of the LDPC codeword by the number of columns is the number of total rows included in each column. In this case, when the number of groups constituting the LDPC codeword is a multiple of the number of columns, each column is not divided into two parts. However, when the number of groups constituting the LDPC codeword is not a multiple of the number of columns, each column may be divided into two parts.

For example, as shown in Table 28, it is assumed that the number of columns of the block interleaver 124 is the same as the number of bits constituting the modulation symbol, and the LDPC codeword is composed of 64800 bits. At this time, each group constituting the LDPC codeword is composed of 360 bits, and the LDPC codeword is composed of 64800/360=180 groups.

On the other hand, when the modulation scheme is 16-QAM, the block interleaver 124 may consist of 4 columns, and each column may consist of 64800/4=16200 rows.

In this case, since the value obtained by dividing the number of groups constituting the LDPC codeword by the number of columns is 180/4=45, bits may be written to each column in group units without dividing each column into two parts. That is, bits included in 45 groups, that is, 45×360=16200 bits, which are the quotient obtained by dividing the number of groups constituting the LDPC codeword by the number of columns, may be written to each column.

However, when the modulation scheme is 256-QAM, the block interleaver 124 may be composed of eight columns, and each column may be composed of 64800/8=8100 rows.

At this time, since the number of groups constituting the LDPC codeword divided by the number of columns is 180/8=22.5, the number of groups constituting the LDPC codeword is not an integer multiple of the number of columns. Accordingly, the block interleaver 124 divides each of the eight columns into two parts in order to perform interleaving in a group unit.

At this time, since bits must be written in a group unit to the first part of each column, the number of groups that can be written in a group unit to the first part of each column is the number of groups constituting the LDPC codeword divided by the number of columns. The quotient becomes 22, and accordingly, the first part of each column may be composed of 22×360=7920 rows. Accordingly, 7920 bits included in 22 groups may be written to the first part of each column.

On the other hand, the second part of each column is composed of rows excluding the row constituting the first part from all rows of each column. Accordingly, the second part of each column may consist of 8100-7920=180 rows.

In this case, bits included in the remaining groups that have not been written to the first part may be divided and written to the second part of each column.

Specifically, since 22 × 8 = 176 groups are written to the first part, the number of groups to be written to the second part is 180-176 = 4 (for example, groups constituting the LDPC codeword (Y ₀ ), group Among (Y ₁ ), group (Y ₂ ),..., group (Y ₁₇₈ ), group (Y ₁₇₉ ), group (Y ₁₇₆ ), group (Y ₁₇₇ ), group (Y ₁₇₈ ), group (Y ₁₇₉ ) Can be).

Accordingly, the block interleaver 124 may sequentially write the remaining four groups to the second part of each column after being written to the first part of the groups constituting the LDPC codeword.

That is, the block interleaver 124 writes _{180 bits out of 360 bits included in the group (Y 176} ) in the column direction from the first row to the 180th row of the second part of the first column, and writes the remaining 180 bits. It is possible to light in the column direction from the first row to the 180th row of the second part of the second column. In addition, the block interleaver 124 writes _{180 bits out of the 360 bits included in the group Y 177} in the column direction from the first row to the 180th row of the second part of the third column, and writes the remaining 180 bits. It is possible to light in the column direction from the first row to the 180th row of the second part of the fourth column. In addition, the block interleaver 124 writes _{180 bits out of the 360 bits included in the group Y 178} in the column direction from the first row to the 180th row of the second part of the fifth column, and writes the remaining 180 bits. From the first row to the 180th row of the second part of the sixth column, it is possible to light in the column direction. In addition, the block interleaver 124 writes _{180 bits out of 360 bits included in the group Y 179} in the column direction from the first row to the 180th row of the second part of the seventh column, and writes the remaining 180 bits. From the first row to the 180th row of the second part of the eighth column, it is possible to light in the column direction.

Accordingly, bits included in the group remaining after being written to the first part may not be written to the same column in the second part, but may be divided and written into a plurality of columns.

Hereinafter, a specific example of the block interleaver of FIG. 4 will be described in more detail with reference to FIG. 11.

)는 V={Y₀,Y₁,…,

}과 같이 Y_j가 연속적으로 배치될 수 있다. Group interleaved LDPC codeword (v ₀ ,v ₁ ,...,

) Is V=(Y ₀ ,Y ₁ ,... ,

As in }, Y _j can be arranged continuously.

After group interleaving, the LDPC codeword may be interleaved by the block interleaver 124 shown in FIG. 11. In this case, the block interleaver 124 may divide a plurality of columns into a first part and a second part based on the number of columns constituting the block interleaver 124 and the number of bits of the group. In this case, bits constituting a group may be written in the same column in the first part, and bits constituting the group may be written in a plurality of columns in the second part.

Specifically, the input bit v _i is sequentially written from the first part to the second part in a column wise direction, and sequentially from the first part to the second part in a row direction. Leads. Accordingly, bits included in the same group in the first part may be mapped to one bit in each modulation symbol.

)은 360의 배수이므로, 복수의 비트 그룹이 제1 파트에 라이트될 수 있다. In this case, the number of columns and the number of rows of the first part and the second part of the block interleaver 124 according to the modulation method and the length of the LDPC codeword (ie, code length) may be as shown in Table 32 below. Here, the number of columns of the block interleaver 124 may be the same as the number of bits constituting the modulation symbol. In addition, the sum of the number of rows of the first part _{N r1 and the number of rows of the second part N r2} is equal to N _ldpc /N _c (here, N _c is the number of columns). And, N _r1 (=

) Is a multiple of 360, so a plurality of bit groups may be written to the first part.

Hereinafter, the operation of the block interleaver 124 will be described in more detail.

, r_i=(i mod N_r1)와 같다.Specifically, as shown in FIG. 11, the input bit v _i (0≦i<N _c ×N _r1 ) is written to the r _{i row of the c i} column of the first part of the block interleaver 124. Where c _i and r _i are respectively

and r _i =(i mod N _r1 ).

, r_i=N_r1+{(i-N_c×N_r1) mod N_r2}와 같다.Then, the input bits, _{v i (N c × N r1} ≤i <N ldpc) are written into the second part of the column c _i r _i rows of the block interleaver (124). Where c _i and r _i are respectively

, r _i =N _r1 +{(iN _c ×N _r1 ) mod N _r2 }.

, c_j=(j mod N_c)와 같다.On the other hand, the output bit q _{j (0≦} j<N ldpc) is read in the c _{j column of the r j row.} Here, c _j and r _j are respectively

, c _j = (j mod N _c ).

For example, when the length N _ldpc of the LDPC codeword is 64800 and the modulation method is 256-QAM, the order of bits output from the block interleaver 124 is (q ₀ ,q ₁ ,q ₂ ,..., q ₆₃₃₅₇ ,q ₆₃₃₅₈ ,q ₆₃₃₅₉ ,q ₆₃₃₆₀ ,q ₆₃₃₆₁ ,...,q ₆₄₇₉₉ )= (v ₀ ,v ₇₉₂₀ ,v ₁₅₈₄₀ ,...,v ₄₇₅₁₉ ,v ₅₅₄₃₉ ,v ₆₃₃₅₉ ,v ₆₃₃₆₀ ,v ₆₃₅₄₀ ,...,v ₆₄₇₉₉ ). Here, if the index in the right term is expressed in more detail for all eight columns, 0, 7920, 15840, 23760, 31680, 39600, 47520, 55440, 1, 7921, 15841, 23761, 31681, 39601, 47521, 55441,… … , 7919, 15839, 23759, 31679, 39599, 47519, 55439, 63359, 63360, 63540, 63720, 63900, 64080, 64260, 64440, 64620, ... … , 63539, 63719, 63899, 64079, 64259, 64439, 64619, 64799.

Meanwhile, in the above-described example, it has been described that the number of columns constituting the block interleaver 124 has the same value as the modulation order or has the same value as half the modulation order, but this is only an example, and the block interleaver 124 The number of columns constituting may be a multiple value of the modulation order. In this case, the number of rows constituting each column may be a value obtained by dividing the length of the LDPC codeword by the number of columns.

For example, when the modulation scheme is QPSK (that is, the modulation order is 2), the number of columns constituting the block interleaver 124 may be 4 instead of 2. In this case, when the length Nldpc of the LDPC codeword is 16200, the number of rows constituting each column may be 4050 (=16200/4).

Meanwhile, the block interleaver 124 performs interleaving in the same manner as when the number of columns has the same value as the modulation order or the same value as half of the modulation order even when the number of columns has a multiple value of the modulation order. In that it can be, a detailed description thereof will be omitted.

In this case, since the number of columns constituting the block interleaver 124 may have the same value as the modulation order or may be an integer multiple of the modulation order, the number of rows of the second part excluding the group corresponding to the first part. It may have the same value as the quotient obtained by dividing the number of bits included in all bit groups by a modulation order or a multiple of the modulation order.

Returning to FIG. 1, the modulator 130 modulates the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. Specifically, the modulator 130 may demultiplex the interleaved LDPC codeword, modulate the demultiplexed LDPC codeword, and map the demultiplexed LDPC codeword to a constellation to generate a modulation symbol.

In this case, the modulator 130 may generate a modulation symbol using bits included in each of the plurality of groups.

That is, as described above, bits included in different groups are written to each column of the block interleaver 124, and the block interleaver 124 reads bits written to each column in a row direction. In this case, the modulator 130 maps the bits read from each column of the block interleaver 124 to each bit of the modulation symbol to generate a modulation symbol. Accordingly, each bit of the modulation symbol may be a bit included in a different group.

For example, it is assumed that the modulation symbol is composed of C bits. In this case, since the bits read from each row of C columns of the block interleaver 124 can be mapped to each bit of the modulation symbol, in the end, each bit of the modulation symbol composed of C bits is in C different groups. It can be included bits.

Hereinafter, this will be described in more detail.

First, the modulator 130 may demultiplex the interleaved LDPC codeword. To this end, the modulator 130 may include a demultiplexer (not shown) for demultiplexing the interleaved LDPC codeword.

A demultiplexer (not shown) demultiplexes the interleaved LDPC codeword. Specifically, the demultiplexer (not shown) performs serial-to-parallel transformation on the interleaved LDPC codeword, and converts the interleaved LDPC codeword into a cell having a certain number of bits ( Alternatively, it may be demultiplexed into a data cell.

For example, as shown in FIG. 12, the demultiplexer (not shown) receives the LDPC codeword Q=(q ₀ ,q ₁ ,q ₂ ,...) output from the interleaver 120, and the input The LDPC codeword bits may be sequentially output to one of a plurality of sub-streams, and the input LDPC codeword bits may be converted into cells and then output.

Here, the number of _substreams N substreams may be equal to the number of bits constituting the modulation symbol η _MOD, and the number of bits constituting the cell may be equal to _{N ldpc} /η _{MOD. Meanwhile, the number of cells generated according to η MOD} according to the modulation method and the length N _ldpc of the LDPC codeword may be as shown in Table 33 below.

Meanwhile, bits having the same index in each of a plurality of sub-streams may constitute the same cell. That is, each cell in FIG. 12 is (y _{0 ,0} ,y _{1 ,0} ,...,y _{η MOD -1,0} ), (y _0,1 ,y _1,1 ,..., y _{η MOD} It can be expressed as _{-1,1 ),...}

Meanwhile, a method of demultiplexing LDPC codeword bits inputted by a demultiplexer (not shown) may be various. That is, the demultiplexer (not shown) may change the order of LDPC codeword bits and output them to each of a plurality of sub-streams, or may sequentially output the LDPC codeword bits to each of the plurality of streams without changing the order of the LDPC codeword bits. This operation may be determined according to the number of columns used for interleaving in the block interleaver 124.

Specifically, when the block interleaver 124 includes half the columns of the number of bits constituting the modulation symbol, the demultiplexer (not shown) changes the order of the input LDPC codeword bits to each of the plurality of substreams. It can be output, and an example of a method of changing the order is shown in Table 34 below.

For example, in Table 34, the modulation scheme is 16-QAM. In the case of 16-QAM, since the number of bits constituting the modulation symbol is 4, the number of sub-streams is 4. In this case, the demultiplexer (not shown) outputs the bits in which the index i satisfies i mod 4 = 0 among the sequentially input bits, and outputs the bits in which the index i satisfies i mod 4 = 1 Bits satisfying i mod 4 = 2 are output as a second sub stream, bits satisfying i mod 4 = 2 are output as a first sub stream, and bits satisfying i mod 4 = 3 can be output as a third sub stream. have.

Accordingly, the LDPC codeword bits (q ₀ ,q ₁ ,q ₂ ,...) input to the demultiplexer (not shown) are (y _{0 ,0} ,y _{1 ,0} ,y _{2 ,0} ,y _{3 , 0} )=(q ₀ ,q ₂ ,q ₁ ,q ₃ ), (y _0,1 ,y _1,1 ,y _2,1 ,y _3,1 )=(q ₄ ,q ₆ ,q ₅ ,q ₇ ),... can be output as cells.

On the other hand, when the block interleaver 124 includes the same number of columns as the number of bits constituting the modulation symbol, the demultiplexer (not shown) sequentially performs each of the plurality of streams without changing the order of the input LDPC codeword bits. Can be printed on. That is, as shown in FIG. 13, the demultiplexer (not shown) _{sequentially outputs input LDPC codeword bits (q 0} ,q ₁ ,q ₂ ,...) to each sub-stream, and accordingly, Each cell is (y _0,0 ,y _1,0 ,…,y _{η MOD -1,0} )=(q ₀ ,q ₁ ,…,q _{η MOD -1} ), (y _{0 ,1} ,y _{1 , 1} ,...,y _{η MOD -1,1} )=(q _{η MOD} ,q _{η MOD +1} ,...,q _{2 ×ηMOD-1} ),...

Meanwhile, in the above-described example, it has been described that the demultiplexer (not shown) sequentially outputs the input LDPC codeword bits to each of the plurality of streams without changing the order of the inputted LDPC codeword bits, but this is only an example. That is, according to an embodiment of the present invention, when the block interleaver 124 includes the same number of columns as the number of bits constituting the modulation symbol, the demultiplexer (not shown) may be omitted.

Meanwhile, the modulator 130 may map the demultiplexed LDPC codeword to a modulation symbol. However, as described above, when the demultiplexer (not shown) is omitted, the modulator 130 may map the LDPC codeword bits output from the interleaver 120, that is, the block-interleaved LDPC codeword bits, to the modulation symbol. have.

Specifically, the modulator 130 performs various modulations such as QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, 4096-QAM, etc. for bits (ie, cells) output from the demultiplexer (not shown). It can be modulated using a method. Here, when the modulation schemes are QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM, _{respectively, the number of bits constituting the modulation symbol η MOD} (i.e., modulation order) is 2 It can be 4,6,8,10,12.

In this case, since each cell output from the demultiplexer (not shown) consists of as many bits as the number of bits constituting the modulation symbol, the modulator 130 sequentially transfers each cell output from the demultiplexer (not shown) to a constellation point. By mapping, a modulation symbol can be generated. Here, the modulation symbol corresponds to a constellation point in a constellation.

However, when the demultiplexer (not shown) is omitted, the modulator 130 may generate a modulation symbol by sequentially dividing the interleaved bits by a certain number of bits and mapping them to constellation points. In this case, the modulator 130 may generate a modulation symbol by sequentially using _{η MOD bits according to a modulation method.}

Meanwhile, the modulator 130 may perform modulation by mapping cells output from a demultiplexer (not shown) to a constellation point using a uniform constellation (UC) method.

Here, the uniform constellation method refers to a method of mapping a modulation symbol to a constellation point so that the real component Re(z _q ) of the constellation point and the imaginary component Im(z _q ) have symmetrical properties and the modulation symbols are formed at equal intervals. Accordingly, in the uniform constellation scheme, at least two of the modulation symbols mapped to the constellation may have the same demodulation performance.

Meanwhile, an example of a method of generating a modulation symbol using a uniform constellation method according to an embodiment of the present invention may be shown in Tables 35 to 42 below, and an example of the case of uniform constellation 64-QAM is shown in FIG. 14. Shown.

Here, Tables 35 and 36 are used to determine the real component Re (z _q ) and the imaginary component Im (z _q ) in the case of performing modulation in the QPSK method, respectively, and Tables 37 and 38 are each 16- It is used to determine the real component Re(z _q ) and the imaginary component Im(z _q ) in the case of performing modulation in the QAM method, and Tables 39 and 40 are the real components in case of performing the modulation in the 64-QAM method. It is used to determine Re(z _q ) and the imaginary component Im(z _q ), and Tables 41 and 42 show the real component Re(z _q ) and the imaginary component Im(z) when modulation is performed in a 256-QAM method. _q ) is used to determine.

Referring to Tables 35 to 42 described above, it is noted that performance (eg, reliability) varies depending on whether a plurality of bits constituting a modulation symbol correspond to a most significant byte (MSB) and a least significant bit (LSB). Able to know.

For example, in the case of 16-QAM, each of the first and second bits of the four bits constituting the modulation symbol is the real component Re(z _q ) and the imaginary component Im(z) of the constellation point to which the modulation symbol is mapped. _q ) Bits that determine each sign, and the third and fourth bits are bits that determine the size of the constellation point to which the modulation symbol is mapped.

In this case, it can be considered that the reliability is higher than that of the third and fourth bits, the first bit and the second bit determining the size of the four bits constituting the modulation symbol.

As another example, in the case of 64-QAM, each of the first and second bits of the six bits constituting the modulation symbol is the real component Re(zq) and the imaginary component Im(zq) of the constellation point to which the modulation symbol is mapped. These are the bits that determine the sign of. And, the third bit to the sixth bit are bits that determine the size of the constellation point to which the modulation symbol is mapped, and the third bit and the fourth bit determine a relatively large size, and the fifth bit and the sixth bit Determines a relatively small size (e.g., whether the size of the constellation point to which the modulation symbol is mapped by the third bit belongs to (-7, -5) or (-3, -1), If (-7, -5) is determined by the third bit, whether -7 or -5 is determined by the fourth bit).

In this case, among the six bits constituting the modulation symbol, the first and second bits that determine the sign have the highest reliability, and the third and fourth bits that determine the relatively large size are relatively It can be said that the reliability is higher than the fifth and sixth bits, which are the bits that determine the small size.

As described above, in the case of the uniform constellation method, each of the bits constituting the modulation symbol may have different reliability depending on the mapped position in the modulation symbol.

Meanwhile, the modulator 130 may perform modulation by mapping cells output from a demultiplexer (not shown) to a constellation point using a non-uniform constellation (NUC) method.

Specifically, the modulator 130 uses non-uniform 16-QAM, non-uniform 64-QAM, non-uniform 256-QAM, non-uniform 1024-QAM, and non-uniform bits output from the demultiplexer (not shown). It can be modulated using various modulation schemes such as 4096-QAM.

Hereinafter, a method of generating a modulation symbol using a non-uniform constellation method according to an embodiment of the present invention will be described.

First, the characteristics of the non-uniform constellation method are outlined as follows.

Unlike the uniform constellation method, the constellation points may not be regularly arranged in the non uniform constellation method. Accordingly, when the non-uniform constellation method is used, performance for an SNR less than a specific value can be improved compared to the uniform constellation method, and a high SNR gain can be obtained.

Meanwhile, the constellation may be characterized by one or more parameters such as an interval between constellation points. Since constellation points in the uniform constellation method are regularly distributed, the number of parameters required to specify the uniform constellation method may be 1, whereas in the case of the non uniform constellation method, the number of parameters required to specify the non uniform constellation method. It is relatively large, and the number of parameters may increase as the constellation degree (eg, the number of constellation points) increases.

On the other hand, in the case of non-uniform constellation, the x-axis and y-axis may be designed to be symmetric or may be designed not to be symmetric. If it is designed not symmetrically, better performance can be guaranteed, but decoding complexity may increase.

Hereinafter, an example of a non-symmetric design will be presented. In this case, if only the constellation point of the first quadrant is defined, the position of the constellation point with respect to the other third quadrant can be determined by the following method. For example, if the set of constellation points defined for the first quadrant is X, it is -conj(X) for the 2nd quadrant, conj(X) for the 3rd quadrant, and -(X) for the 4th quadrant. .

That is, if one quadrant is defined, the other quadrant can be expressed as follows.

1 Quarter = X

2 Quarter(2 quadrant) = -conj(X)

3 Quarter(3 quadrant) = conj(X)

4 Quarter = -X

Specifically, when using non-uniform M-QAM, M constellation points can be defined _{as z={z 0} , z ₁ ,..., z _{M -1 }.} At this time, the constellation points existing in the first quadrant are {x ₀ , x ₁ , x ₂ ,… When defined as, x _{M /4-1} }, z can be defined as follows.

z ₀ to z _{M /4 -1} = x ₀ to x _{M /4}

z _{M /4} to z _{2 ×M/4-1} = -conj(x ₀ to x _{M /4} )

z _{2 ×M/4} to z _{3 ×M/4-1} = conj(x ₀ to x _{M /4} )

z _{3 ×M/4} to z _{4 ×M/4-1} = -(x ₀ to x _{M /4} )

을 인덱스로 하는 z_L로 매핑하여, 출력 비트들을 non-uniform constellation 방식으로 성성점에 맵핑할 수 있다. 이러한 방식에 따라 non-uniform constellation 방식에 따른 성상도의 일 예는 도 15 내지 도 19와 같다.Accordingly, the modulator 130 is an output bit output from the demultiplexer (not shown) [y ₀ ,... ,y _{m -1} ]

_{By mapping z L} as an index, output bits can be mapped to constellation points in a non-uniform constellation method. An example of a constellation diagram according to a non-uniform constellation method according to this method is shown in FIGS. 15 to 19.

On the other hand, an example of a specific method of performing modulation in a non-uniform constellation method so that the modulator 130 is not symmetrical is shown in Tables 43 to 46 below. That is, according to an embodiment of the present invention, constellation points existing in the first quadrant are defined through Tables 43 to 46, and constellation points existing in the remaining quadrants are defined by the above-described method, and a non-uniform constellation method is used. Modulation can be performed.

In these Tables 43 to 46, Table 43 represents non-uniform 16-QAM, Table 44 and Table 45 represent non-uniform 64-QAM, and Table 46 represents non-uniform 256-QAM. It can be seen that the method can be applied.

Meanwhile, when a non-uniform constellation is designed so that the x-axis and y-axis are symmetrical, it can be expressed similarly to the uniform QAM, and examples are given in Tables 47 to 49 below.

In Tables 47 to 49, Tables 47 and 48 are tables for determining a real component Re(z _q ) and an imaginary component Im(z _q ) when modulation is performed in a non-uniform 1024-QAM scheme. That is, Table 47 shows the real part of 1024-QAM, and Table 48 shows the imaginary part of 1024-QAM. In addition, Table 49 shows an example of performing modulation in a non-uniform 1024-QAM scheme, and indicates x _i values in Tables 47 and 48.

As shown in Tables 47 to 49, in the non-uniform constellation scheme, modulation symbols may be mapped to constellation points without being symmetric, and thus modulation symbols mapped to constellation points may have different demodulation performances. That is, bits constituting the modulation symbol may have different performances.

For example, referring to FIG. 15 showing an example in which modulation is performed in a non-uniform 64-QAM scheme, the modulation symbol 10 is (y ₀ ,y ₁ ,y ₂ ,y ₃ ,y ₄ , y ₅ )=(0,0,1,0,1,0), and the performance (eg, capacity) of the bits constituting the modulation symbol 10 is C(y ₀ )>C(y ₁ )>C(y ₂ )>C(y ₃ )>C(y ₄ )>C(y ₅ ).

Meanwhile, the constellation in the uniform constellation method and the non-uniform constellation method may be rotated and/or scaled (here, scaling factors applied to the real axis and the imaginary axis may be the same or different from each other), and different modifications It is obvious that this can be applied. In addition, the illustrated constellations represent the relative positions of the constellations, which can be derived from other constellations by rotation, scaling and/or other suitable transformations.

In this way, the modulator 130 may map a modulation symbol to a constellation point using a uniform constellation method and a non-uniform constellation method. In this case, as described above, the performance of the bits constituting the modulation symbol may be different.

Meanwhile, according to the structure of the parity check matrix, LDPC codeword bits may have different codeword characteristics. That is, the LDPC codeword bits may have different codeword characteristics according to the number of 1s in the column of the parity check matrix, that is, the column order.

Accordingly, in the present invention, the interleaver 120 performs interleaving so that the LDPC codeword bits can be mapped to the modulation symbol in consideration of both the codeword characteristics of the LDPC codeword bits and the reliability of the bits constituting the modulation symbol.

In particular, when non-uniform QAM is used, since the performance of all the bits constituting the modulation symbol is different, the number of columns of the block interleaver 124 is configured equal to the number of bits constituting the modulation symbol, so that the LDPC codeword is configured. One of a plurality of groups can be mapped to a bit present at the same position in each modulation symbol.

That is, if LDPC codeword bits with excellent decoding performance are mapped to bits with excellent reliability among the bits constituting the modulation symbol, the decoding performance may be excellent at the receiving side, but LDPC codeword bits with excellent decoding performance are received. There may be a problem that cannot be done. In addition, when LDPC codeword bits with excellent decoding performance are mapped to bits with low reliability among the bits constituting a modulation symbol, the initial reception performance is excellent and the overall performance may be excellent, but the decoding is not good. If a lot of files are received, error propagation may occur.

Accordingly, in the present invention, when mapping LDPC codeword bits to modulation symbols, the LDPC codeword bits having specific codeword characteristics are selected by considering both the codeword characteristics of the LDPC codeword bits and the reliability of the bits constituting the modulation symbols. It is mapped to a specific bit in the modulation symbol and transmitted to the receiving side. Accordingly, it is possible to achieve both excellent reception performance and decoding performance at the receiving side.

In this case, in the present invention, the LDPC codeword is divided into groups consisting of M (=360) bits each having the same codeword characteristics, and the bits are mapped to bits at a specific position of the modulation symbol in groups. Bits having specific codeword characteristics can be efficiently mapped to specific positions within a modulation symbol. In addition, as described above, the number of bits constituting the group may be a factor of M. However, for convenience of description, the number of codeword bits constituting the group is limited to the case of M.

That is, the modulator 130 may map at least one bit included in a preset group among a plurality of groups constituting the LDPC codeword to a preset bit in the modulation symbol. Here, each of the plurality of groups may consist of M (=360) bits.

For example, in the case of 16-QAM, at least one bit included in a preset group among a plurality of groups may be mapped to a first bit in a modulation symbol, or may be mapped to a first bit and a second bit.

As described above, the reason why the modulator 130 can map at least one bit included in the preset group among the plurality of groups to the preset bit in the modulation symbol is as follows.

As described above, the block interleaver 124 interleaves a plurality of groups constituting the LDPC codeword in group units, and the demultiplexer (not shown) demultiplexes the bits output from the block interleaver 124, and the modulator ( 130) sequentially maps the demultiplexed bits (ie, cells) to a modulation symbol.

Accordingly, the group interleaver 122 disposed before the block interleaver 124 considers a demultiplexing operation performed by a demultiplexer (not shown), and groups including bits to be mapped to a bit at a specific position in the modulation symbol are included in the block interleaver 124 The LDPC codewords are interleaved in groups so that they can be written in the same column of ).

Specifically, the group interleaver 122 rearranges the order of a plurality of groups in groups so that at least one group including bits mapped to the same position of different modulation symbols are arranged adjacent to each other in sequence. Thus, the block interleaver 124 may write a preset group to a preset column. That is, the group interleaver 122 interleaves a plurality of groups constituting the LDPC codeword in group units based on Tables 23 to 27 described above, and includes at least one bit each including bits mapped to the same position of each modulation symbol. The groups are adjacent to each other, and the block interleaver 124 performs interleaving by writing at least one adjacent group to the same column.

Accordingly, the modulator 130 may generate a modulation symbol by mapping a bit output from a preset column of the block interleaver 124 to a preset bit in the modulation symbol. In this case, the bits included in one group may be mapped to one of the bits constituting the modulation symbol or to two of the bits constituting the modulation symbol.

For a more detailed description, a case in which an LDPC codeword having a length of 16200 is modulated with non-uniform 64-QAM will be described as an example.

The group interleaver 122 divides the LDPC codeword into 16200/360=45 groups, and interleaves a plurality of groups in group units.

In this case, the group interleaver 122 determines the number of groups that can be written to each column of the block interleaver 124 based on the number of columns of the block interleaver 124, and selects a plurality of groups based on the determined number of groups. Interleaving can be performed in groups.

Here, the group written to the same column in the block interleaver 124 is mapped to one specific bit or two specific bits among the bits constituting the modulation symbol according to the number of columns of the block interleaver 124, so the group interleaver 122 ) Is a group unit so that groups including bits that need to be mapped to the corresponding bit are arranged adjacent to each other in consideration of the bit property of the modulation symbol, and the arrangement units in which the groups are arranged adjacent to each other are sequentially arranged. Interleaved with. In this case, the group interleaver 122 may use Table 24 described above.

Accordingly, groups located adjacent to each other in LDPC codewords interleaved in group units may be written in the same column of the block interleaver 124, and bits written in the same column may be It is mapped to two bits.

For example, it is assumed that the block interleaver 124 includes as many columns as the number of bits constituting the modulation symbol, that is, includes 6 columns. In this case, as shown in Table 28 or Table 32, each column of the block interleaver 124 may be divided into a first part including 2520 rows and a second part including 180 rows.

Accordingly, the group interleaver 122 is an array unit consisting of 7 groups of 2520/360=7 groups that are written to the first part of each column of the block interleaver 124 among the plurality of groups, and are adjacent to each other. Group interleaving is performed so that are sequentially arranged. Accordingly, the block interleaver 124 may write seven groups to the first part of each column, divide bits included in the remaining three groups, and write to the second part of each column.

Thereafter, the block interleaver 124 may read bits written in each row of a first part of a plurality of columns in a row direction, and read bits written in each row of a second part of a plurality of columns in a row direction.

That is, the block interleaver 124 sets the bits written to each row of a plurality of columns in the order of bits written to the first row of the sixth column from the bit written to the first row of the first column (q ₀ ,q ₁ ,q ₂ ,q ₃ ,q ₄ ,q ₅ ,q ₆ ,q ₇ ,q ₈ ,q ₉ ,q ₁₀ ,q ₁₁ ,...).

In this case, when the demultiplexer (not shown) is not used, or when the demultiplexer (not shown) sequentially outputs the input bits without changing the order, the LDPC codeword bits output from the block interleaver 124 (q ₀ , q ₁ ,q ₂ ,q ₃ ,q ₄ ,q ₅ ), (q ₆ ,q ₇ ,q ₈ ,q ₉ ,q ₁₀ ,q ₁₁ ),... are modulated by the modulator 130. That is, LDPC codeword bits output from the block interleaver 124 (q ₀ ,q ₁ ,q ₂ ,q ₃ ,q ₄ ,q ₅ ), (q ₆ ,q ₇ ,q ₈ ,q ₉ ,q ₁₀ ,q ₁₁ ),... These cells (y _{0 ,0} ,y _{1 ,0} ,…,y _{5 ,0} ), (y _{0 ,1} ,y _{1 ,1} ,…,y _{5 ,1} ), respectively. .., and the modulator 130 may generate a modulation symbol by mapping cells to constellation points.

Accordingly, the modulator 130 may map bits output from the same column of the block interleaver 124 to one specific bit among bits constituting the modulation symbol. For example, the modulator 130 maps bits included in the group that were written to the first column in the block interleaver 124, that is, (q ₀ ,q ₆ ,...) to the first bit in the modulation symbol. The bits written in the first column may be bits determined to be mapped to the first bit of each modulation symbol according to codeword characteristics of LDPC codeword bits and reliability of bits constituting the modulation symbol.

In this way, the group interleaver 122 divides a plurality of groups constituting the LDPC codeword into a group unit so that groups including bits to be mapped to one bit at a specific position in the modulation symbol are written to a specific column of the block interleaver 124. Can be interleaved.

On the other hand, it is assumed that the block interleaver 124 includes half the columns of the number of bits constituting the modulation symbol, that is, includes 3 columns. In this case, as shown in Table 31, parts of each column of the block interleaver 124 are not divided, and 5400 bits may be written to each column.

Accordingly, the group interleaver 122 interleaves groups so that 5400/360=15 groups written to each column of the block interleaver 124 are adjacent to each other, and array units consisting of 15 groups are sequentially arranged. Perform. Accordingly, the block interleaver 124 may write 15 groups to each column.

Thereafter, the block interleaver 124 may read bits written in each row of a plurality of columns in a row direction.

That is, the block interleaver 124 sets the bits written to each row of the plurality of columns in the order of bits written to the first row of the first column to the first row of the third column (q ₀ ,q ₁ ,q ₂ ,q ₃ ,q ₄ ,q ₅ ,q ₆ ,q ₇ ,q ₈ ,q ₉ ,q ₁₀ ,q ₁₁ ,...).

In this case, the demultiplexer (not shown) demultiplexes the LDPC codeword bits output from the block interleaver 124 based on Table 34 to (y _{0 ,0} ,y _{1 ,0} ,...,y _{5 ,0} )=( q ₀ ,q ₂ ,q ₄ ,q ₁ ,q ₃ ,q ₅ ), (y _{0 ,1} ,y _{1 ,1} ,…,y _{5 ,1} )=(q ₆ ,q ₈ ,q ₁₀ ,q ₇ Cells such as ,q ₉ ,q ₁₁ )... are output, and the modulator 130 may generate a modulation symbol by mapping the cells to a constellation point.

Accordingly, the modulator 130 may map bits output from the same column of the block interleaver 124 to two specific bits among bits constituting a modulation symbol. For example, the modulator 130 is the bits contained in the first column that was light group in the block interleaver 124, the _{(q 0, q 3, q} 6, q 9, ...) from (q _0, q ₆ ,...) can be mapped to the first bit in the modulation symbol and (q ₃ ,q ₉ ,...) can be mapped to the fifth bit in the modulation symbol, and the bits written in the first column are LDPC codewords. The bits may be determined to be mapped to the first bit and the fifth bit of each modulation symbol according to the codeword characteristics of the bits and the reliability of the bits constituting the modulation symbol. Here, the first bit in the modulation symbol is _{a bit that determines the sign of the real component Re(z q} ) of the constellation point to which the modulation symbol is mapped, and the fifth bit in the modulation symbol is relative to the constellation point to which the modulation symbol is mapped. It is the bit that determines the small size.

In this way, the group interleaver 122 divides a plurality of groups constituting the LDPC codeword into a group unit so that groups including bits to be mapped to two bits at a specific position in the modulation symbol are written to a specific column of the block interleaver 124. Can be interleaved.

In the following, the encoder 110 performs LDPC encoding at a code rate of 10/15, 11/15, 12/15, and 13/15 _{to generate an LDPC codeword consisting of 16200 bits (N ldpc} = 16200), and modulates The unit 130 assumes a case of using a non-uniform 16-QAM modulation scheme corresponding to a code rate based on Table 43.

The present invention will be described in more detail through specific embodiments.

As an example, the encoder 110 performs LDPC encoding at a code rate of 10/15, 11/15, 12/15, and 13/15 _{to generate an LDPC codeword consisting of 16200 bits (N ldpc} = 16200), It is assumed that the modulator 130 uses a non-uniform 16-QAM modulation scheme corresponding to a code rate based on Table 43.

In this case, the group interleaver 122 may perform group interleaving using Equation 11 and Table 23. Meanwhile, according to Table 28 or Table 32, the number of columns is 4, the number of rows of the first part is 3960 (=360 × 11), and the number of rows of the second part is 90. I can.

Accordingly, 11 groups (X ₃₅ , X ₃₁ , X ₃₉ , X ₁₉ , X ₂₉ , X ₂₀ , X ₃₆ , X ₀ , X ₉ , X ₁₃ , X ₅ ) constituting the LDPC codeword 124) in the first part of the first column, and 11 groups (X ₃₇ , X ₁₇ , X ₄₃ , X ₂₁ , X ₄₁ , X ₂₅ , X ₁ , X ₃₃ , X ₂₄ , X ₁₂ , X ₃₀ ) It is input to the first part of the second column of the block interleaver 124, and 11 groups (X ₁₆ , X ₃₂ , X ₁₀ , X ₂₈ , X ₄ , X ₂₆ , X ₈ , X ₄₀ , X ₄₂ , X ₃ , X ₆ ) is input to the first part of the third column of the block interleaver 124, and 11 groups (X ₂ , X ₃₈ , X ₁₄ , X ₃₄ , X ₂₂ , X ₁₈ , X ₂₇ , X ₂₃ , X ₇ , X ₁₁ , X ₁₅ ) are input to the first part of the fourth column of the block interleaver 124.

Then, the group X ₄₄ is input to the second part of the block interleaver 124. Specifically, _{the bits constituting group X 44} are sequentially input to the row of the first column of the second part, then sequentially input to the row of the second column, and then sequentially input to the row of the third column, and finally the fourth It is entered sequentially in the row of the column. In this case, since the group X ₄₄ is composed of 360 bits, 90 bits may be input to the second part of each column.

In addition, the block interleaver 124 may sequentially output bits input to the first row to the last row of each column, and bits output from the block interleaver 124 may be sequentially input to the modulator 130. . In this case, the demultiplexer (not shown) may be omitted, or the demultiplexer (not shown) may sequentially output the input bits without changing the order of the input bits.

Accordingly, one bit included in each of the _{group X 35} , the group X ₃₇ , the group X _16, and the group X _{2 constitutes one modulation symbol.}

The present invention includes, for example, that one bit included in each of the _{groups X 35} , the group X ₃₇ , the group X ₁₆ and the group X _{2 constitutes one modulation symbol based on group interleaving and block interleaving.} , In addition to the above-described method, _{other methods in which one bit included in each of the group X 35} , the group X ₃₇ , the group X ₁₆ and the group X ₂ constitute one modulation symbol may also be included within the scope of the present invention.

Meanwhile, the transmission device 100 may modulate the signal mapped to the constellation and transmit it to the reception device (eg, 2700 of FIG. 24 ). For example, the transmitting device 100 may map a signal mapped to a constellation to an OFMD frame using an Orthogonal Frequency Division Multiplexing (OFDM) scheme, and may transmit the mapped signal to the receiving device 2700 through an allocated channel.

To this end, the transmission device 100 includes a frame mapper (not shown) for mapping a signal mapped to a constellation to an OFDM frame, and a transmission unit (not shown) for transmitting a signal in the form of an OFDM frame to the reception device 2700. It may further include.

block- low Interleaver When to use

In another embodiment of the present invention, the interleaver 120 interleaves the LDPC codeword through a method other than the above-described method, so that a bit included in a preset group among a plurality of groups constituting the interleaved LDPC codeword is included in the modulation symbol. It can be mapped to a preset bit. Refer to FIG. 20 for a detailed description.

According to FIG. 20, the interleaver 120 includes a parity interleaver 121, a group interleaver (or, a group-wise interleaver, 122), a group twist interleaver 123, and a block-row interleaver 125. do. Here, since the parity interleaver 121 and the group twist interleaver 123 perform the same functions as described above in the first embodiment, detailed descriptions of these components will be omitted.

The group interleaver 122 may divide the parity-interleaved LDPC codeword into a plurality of groups, and rearrange the order of the plurality of groups in a group unit.

In this case, since the operation of dividing the parity-interleaved LDPC codeword into a plurality of groups is the same as in the above-described embodiment, a detailed description will be omitted.

Meanwhile, the group interleaver 122 interleaves the LDPC codeword in a group unit. That is, the group interleaver 122 may rearrange the order of the plurality of groups in the LDPC codeword in groups by changing positions of the plurality of groups constituting the LDPC codeword.

Here, the group interleaver 122 may rearrange the order of the plurality of groups in groups so that groups including bits mapped to the same modulation symbol among the plurality of groups are sequentially arranged.

In this case, the group interleaver 122 maps to the same modulation symbol in consideration of the number of rows and columns constituting the block-row interleaver 124, the number of groups constituting the LDPC codeword, and the number of bits included in each group. The order of the plurality of groups may be rearranged in units of groups so that the groups including the bits are sequentially arranged.

To this end, the group interleaver 122 may interleave the LDPC codeword in group units using Equation 12 below.

Here, X _j denotes the j-th group before group interleaving, and Y _j denotes the j-th group after group interleaving. In addition, π(j) is a parameter indicating an interleaving order, and may be determined by at least one of a length, a code rate, and a modulation method of the LDPC codeword.

Accordingly, X _π(j) represents the π(j)-th group before group interleaving, and Equation 13 means that the π(j)-th group before interleaving is interleaved into the j-th group after interleaving.

Meanwhile, a specific example of π(j) according to an embodiment of the present invention may be defined as shown in Tables 50 to 54 below.

In this case, π(j) is defined according to the length and code rate of the LDPC codeword, and the parity check matrix is also defined according to the length and code rate of the LDPC codeword. Therefore, when LDPC coding is performed based on a specific parity check matrix according to the length and code rate of the LDPC codeword, the LDPC codeword is group-wise based on π(j) that satisfies the length and code rate of the LDPC codeword. Can be interleaved with.

For example, when the encoder 110 performs LDPC encoding at a code rate of 10/15 to generate an LDPC codeword having a length of 16200, the group interleaver 122 is selected from among Tables 50 to 54 below. Interleaving may be performed using π(j) defined in the LDPC codeword having a length of 16200 and a code rate of 10/15.

For example, when the length of the LDPC codeword is 16200, the code rate is 10/15, and the modulation method is 16-QAM, the group interleaver 122 performs interleaving using π(j) defined as in Table 50. can do.

Meanwhile, a specific example of π(j) is as follows.

For example, when the length N _ldpc of the LDPC codeword is 16200, the code rate is 10/15, 11/15, 12/15, 13/15, and the modulation method is 16-QAM, π(j) is shown in Table 50 below. It can be defined as

In the case of Table 50, Equation 12 is X ₀ =Y _π(0) =Y ₁₁ , X ₁ =Y _π(1) =Y ₃₈ , X ₂ =Y _π(2) =Y ₂₇ ,..., X ₄₃ =Y _π(43) =Y ₁₇ , X ₄₄ =Y _π(44) =Y ₄₄ . Accordingly, the group interleaver 122 is the 0th group as the 11th, the 1st group as the 38th, the second group as the 27th, ..., the 43th group as the 17th, and the 44th group as the 44th The order of the plurality of groups may be rearranged in units of groups by changing the order.

As another example, when the length N _ldpc of the LDPC codeword is 16200, the code rate is 6/15, 7/15, 8/15, 9/15, and the modulation method is 64-QAM, π(j) is shown in Table 51 below. It can be defined as

In the case of Table 51, Equation 12 is X ₀ =Y _π(0) =Y ₂₆ , X ₁ =Y _π(1) =Y ₂₂ , X ₂ =Y _π(2) =Y ₄₁ ,..., X ₄₃ =Y _π(43) =Y ₄₃ , X ₄₄ =Y _π(44) =Y ₄₄ . Accordingly, the group interleaver 122 is the 0th group as the 26th, the 1st group as the 22nd, the 2nd group as the 41st, ..., the 43rd group as the 43rd, and the 44th group as the 44th The order of the plurality of groups may be rearranged in units of groups by changing the order.

As another example, when the length N _ldpc of the LDPC codeword is 16200, the code rate is 10/15, 11/15, 12/15, 13/15, and the modulation method is 256-QAM, π(j) is shown in Table 52 below. It can be defined as

For Table 52, Equation 12 is X ₀ =Y _π(0) =Y ₃₂ , X ₁ =Y _π(1) =Y ₂₆ , X ₂ =Y _π(2) =Y ₁₄ ,..., X ₄₃ =Y _π(43) =Y ₄₃ , X ₄₄ =Y _π(44) =Y ₄₄ . Accordingly, the group interleaver 122 is the 0th group as the 32nd, the 1st group as the 26th, the 2nd group as the 14th, ..., the 43rd group as the 43rd, and the 44th group as the 44th The order of the plurality of groups may be rearranged in units of groups by changing the order.

As another example, when the length N _ldpc of the LDPC codeword is 16200, the code rates are 6/15, 7/15, 8/15, 9/15, and the modulation method is 1024-QAM, π(j) is shown in Table 53 below. It can be defined as

In the case of Table 53, Equation 12 is X ₀ =Y _π(0) =Y ₂₂ , X ₁ =Y _π(1) =Y ₂₀ , X ₂ =Y _π(2) =Y ₇ ,..., X ₄₃ =Y _π(43) =Y ₄₃ , X ₄₄ =Y _π(44) =Y ₄₄ . Accordingly, the group interleaver 122 is the 0th group as the 22nd, the 1st group as the 20th, the 2nd group as the 7th, ..., the 43rd group as the 43rd, and the 44th group as the 44th The order of the plurality of groups may be rearranged in units of groups by changing the order.

As another example, when the length N _ldpc of the LDPC codeword is 64800, the code rate is 6/15, 7/15, 8/15, 9/15, and the modulation method is 256-QAM, π(j) is shown in Table 54 below. It can be defined as

For Table 54, Equation 12 is X ₀ =Y _π(0) =Y ₇₂ , X ₁ =Y _π(1) =Y ₄₈ , X ₂ =Y _π(2) =Y ₅₅ ,..., X _It can be expressed as 178 =Y _π(178) =Y ₁₇₈ , X ₁₇₉ =Y _π(179) =Y _179. Accordingly, the group interleaver 122 sets the 0th group to the 72nd, the 1st group to the 48th, the 2nd group to the 55th, ..., the 178th group to the 178th, and the 179th group to the 179th The order of the plurality of groups may be rearranged in units of groups by changing the order.

In this way, the group interleaver 122 may rearrange the order of a plurality of groups in group units using Equation 12 and Tables 50 to 54.

On the other hand, in that the groups constituting the LDPC codeword are rearranged in group units by the group interleaver 122 and then block interleaved by the block interleaver 124 to be described later, π(j ) In relation to "Order of bits group to be block interleaved".

When performing group interleaving based on Tables 50 to 54, the order of groups constituting the group-interleaved LDPC codeword is different from the group constituting the group-interleaved LDPC codeword based on Tables 23 to 27. do.

This is because the block-row interleaver 125 is used instead of the block interleaver 124 in this embodiment. That is, since the interleaving method used in the block interleaver 124 and the interleaving method used in the block-row interleaver 125 are different from each other, the group interleaver 122 in this embodiment is based on Tables 50 to 54. The order of a plurality of groups constituting a codeword is rearranged.

Specifically, the group interleaver 122 may rearrange the order of a plurality of groups in a group unit so that an arrangement unit in which at least one group including bits mapped to the same modulation symbol is sequentially arranged in a group unit is repeated.

That is, the group interleaver 122 is one of a plurality of first groups including a bit mapped to a specific first position of a modulation symbol, and one of a plurality of second groups including a bit mapped to a specific second position of a modulation symbol. One,..., one of a plurality of n-th groups including bits mapped to a specific n-th position of a modulation symbol may be sequentially disposed, and the remaining groups may be repeatedly disposed in the same manner.

The block-row interleaver 125 interleaves a plurality of groups in which the order is rearranged. In this case, the block-row interleaver 125 may interleave a plurality of groups in which the order is rearranged using at least one row consisting of a plurality of columns. For a more detailed description, refer to FIGS. 21 to 23.

21 to 23 are diagrams illustrating a structure of a block-row interleaver and a method of performing interleaving according to an embodiment of the present invention.

First, when N _group /m is an integer, the block-row interleaver 125 includes an interleaver 125-1 consisting of m rows each including M columns as shown in FIG. 21, and a block-row interleaver ( _{125) may perform interleaving using N group} /m interleavers 125-1 having the structure shown in FIG. 21.

Here, N _group is the total number of groups constituting the LDPC codeword. And, M is the number of bits included in one group, for example, may be 360, and m may be equal to the number of bits constituting the modulation symbol or 1/2 of the number of bits constituting the modulation symbol. have. For example, in the case of using non-uniform QAM, since the performance of the bits constituting the modulation symbol are all different, the m value is configured equal to the number of bits constituting the modulation symbol, so that one group constitutes the modulation symbol. So that it can be mapped to one bit.

Specifically, the block-row interleaver 125 writes each of a plurality of groups constituting the LDPC codeword in a row direction to each row in a group unit, and writes each column of a plurality of rows in which the plurality of groups are written in a group unit. Interleaving can be performed by reading in the column direction.

For example, as shown in FIG. 21, the block-row interleaver 125 writes m consecutive m groups among a plurality of groups in a row direction to each of m rows constituting the interleaver 125-1, and writes bits. Each column of the m rows can be read in the column direction. In this case, the quotient obtained by dividing the number of groups by the number of rows, that is, N _groups /m interleavers 125-1 may be used.

As described above, when the number of groups constituting the LDPC codeword is an integer multiple of the number of rows, the block-row interleaver 125 may perform interleaving by sequentially writing as many groups as the number of rows among a plurality of groups. .

On the other hand, when the number of groups constituting the LDPC codeword is not an integer multiple of the number of rows, the block-row interleaver 125 uses N (N is an integer of 2 or more) interleavers including different numbers of columns. Interleaving can be performed by using.

×m이고,

는 N_group/m 이하의 가장 큰 정수를 나타낸다.For example, as shown in FIGS. 22 and 23, the block-row interleaver 125 includes a first interleaver 125-2 composed of m rows each including M columns and a×M/m columns each. Interleaving may be performed using the second interleaver 125-3 consisting of m rows. Where a is N _group-

×m,

_Represents the largest integer of N group /m or less.

개가 이용될 수 있고, 제2 인터리버(125-3)는 1 개가 이용될 수 있다. In this case, the first interleaver 125-2

Dogs may be used, and one second interleaver 125-3 may be used.

×m 개 그룹 각각을 그룹 단위로 각 행에 행 방향으로 라이트하고,

×m 개 그룹이 그룹 단위로 라이트된 복수의 행의 각 열을 열 방향으로 리드하여 인터리빙을 수행할 수 있다.Specifically, the block-row interleaver 125 is among a plurality of groups constituting the LDPC codeword.

Write each of ×m groups in the row direction to each row as a group unit,

Interleaving may be performed by reading each column of a plurality of rows in which ×m groups are written in a group unit in a column direction.

×m 개 그룹 중에서 행의 개수와 동일한 개수의 연속된 m 개의 그룹을 제1 인터리버(125-2)의 각 행에 행 방향으로 라이트하고, m 개의 그룹이 라이트된 제1 인터리버(125-2)의 복수의 행의 각 열을 열 방향으로 리드할 수 있다. 이 경우, 도 22 및 도 23과 같은 구조를 갖는 제1 인터리버(125-2)가

개만큼 이용될 수 있다.For example, as shown in FIGS. 22 and 23, the block-row interleaver 125 is

The first interleaver 125-2 in which m consecutive m groups of the same number as the number of rows among ×m groups are written in the row direction to each row of the first interleaver 125-2, and m groups are written. Each column of a plurality of rows of can be lead in the column direction. In this case, the first interleaver 125-2 having the structure shown in FIGS. 22 and 23

Can be used as much as dogs.

In addition, m may be a product of the number of bits constituting the modulation scheme and the number of antennas in a system using multiple antennas.

Thereafter, the block-row interleaver 125 divides the bits included in the other groups except for the group written to the first interleaver 125-2, and writes the bits to each row of the second interleaver 125-3 in the row direction. I can. In this case, the same number of bits may be written to each row of the second interleaver 125-3. That is, one bit group may be input to a plurality of rows of the second interleaver 125-3.

For example, as shown in FIG. 22, the block-row interleaver 125 uses the bits included in the other groups except for the group written to the first interleaver 125-2 to form the second interleaver 125-3. Each of the m rows may be written in a row direction by a×M/m, and each column of the m rows of the second interleaver 125-3 to which bits are written may be read in the column direction. In this case, one second interleaver 125-3 having the structure as shown in FIG. 22 may be used.

However, according to another embodiment of the present invention, as shown in FIG. 23, the block-row interleaver 125 writes bits to the first interleaver 125-2 in the same manner as described in FIG. , For the second interleaver 125-3, bits may be written in a manner different from the method described in FIG. 22.

That is, the block-row interleaver 125 may write bits to the second interleaver 125-3 in the column direction.

For example, as shown in FIG. 23, the block-row interleaver 125 includes bits included in the remaining groups except for the group written to the first interleaver 125-2, respectively constituting the second interleaver 125-3. Bits may be written in a column direction in each column of m rows composed of a×M/m columns, and each column of m rows of the second interleaver 125-3 to which the bits are written may be read in the column direction. In this case, one second interleaver 125-3 having a structure as shown in FIG. 23 may be used.

Meanwhile, in the case of the method shown in FIG. 23, the block-row interleaver 125 performs interleaving by writing bits to the second interleaver in the column direction and then reading them in the column direction. Accordingly, bits included in the group interleaved by the second interleaver are read in the order in which they are written and output to the modulator 130. Accordingly, bits included in a group belonging to the second interleaver may not be rearranged by the block-row interleaver 125 and may be sequentially mapped to the modulation symbols. In this way, the block-row interleaver 125 may perform interleaving for at least some of the plurality of groups, and may not perform interleaving for the remaining groups. Specifically, the block-row interleaver 125 performs interleaving by sequentially writing LDPC codewords constituting at least some of the plurality of groups to a plurality of rows and reading them in the column direction, but interleaving the remaining groups. I can't. That is, since the block-row interleaver 125 writes and reads bits included in the remaining groups in the same direction, bits included in the remaining groups may be output as they are without changing the order.

In addition, in the above-described example, it has been described that bits included in the remaining groups are written and read in the column direction, but this is only an example. That is, the block-row interleaver 125 may write and read bits included in the remaining groups in the row direction, and even in this case, the bits included in the remaining groups may be output as they are without changing the order.

In this way, the block-row interleaver 125 may interleave a plurality of groups using the method described with reference to FIGS. 21 to 23.

In this manner, the output of the block-row interleaver 125 may be the same as the output of the block interleaver 124. Specifically, when the block-row interleaver 125 performs interleaving as shown in FIG. 21, the same value as the block interleaver 124 performing interleaving as shown in FIG. 8 is output, and the block-row interleaver 125 is shown in FIG. 22 When interleaving is performed as shown in FIG. 9, the same value as the block interleaver 124 performing interleaving is output, and when the block-row interleaver 125 performs interleaving as shown in FIG. 23, interleaving is performed as shown in FIG. The same value as the block interleaver 124 to be executed may be output.

Specifically, when using the group interleaver 122 and the block interleaver 124 based on Equation 11, the output groups of the group interleaver 122 are referred to as Y _i (0≦j<N _group ), and Equation 12 When the group interleaver 122 is used and the block-row interleaver 125 is used, the output groups of the _{group interleaver 122 are Z i} (0≤j<N _group ), the output group after group interleaving The relationship between Z _i and Y _i may be expressed as Equation 13 and Equation 14 below, and as a result, the same value may be output from the block interleaver 124.

로, 블록 인터리버(124)를 사용할 경우 제 1 파트의 하나의 열에 입력되는 그룹의 개수를 의미하며,

는 N_group/m 이하의 가장 큰 정수이다. 그리고, m은 변조 심볼을 구성하는 비트의 개수와 동일하거나, 변조 심볼을 구성하는 비트의 절반일 수 있다. 또한, m은 블록 인터리버(124)의 열의 개수를 의미하고, m은 블록-로우 인터리버(125)의 행의 개수를 의미한다.Where, α=

As, when the block interleaver 124 is used, it means the number of groups input to one column of the first part,

Is the largest integer less than _{N group /m.} In addition, m may be equal to the number of bits constituting the modulation symbol, or may be half of the bits constituting the modulation symbol. Further, m denotes the number of columns of the block interleaver 124, and m denotes the number of rows of the block-row interleaver 125.

Accordingly, the modulator 130 may map bits output from the block-row interleaver 125 to the modulation symbols in the same manner as in the case of using the block interleaver 124.

Meanwhile, the bit interleaving scheme proposed in the present invention is composed of a parity interleaver 121, a group interleaver 122, a group twist interleaver 123, and a block interleaver 124, as shown in FIG. , The parity interleaver 121 or the group twist interleaver 123 may be omitted), which is only an example, and there is no need to limit it to being composed of three modules or four modules as described above.

For example, in the present invention, when a block interleaver is used and a group interleaving method expressed as Equation 11 is used, bit groups X _j (0≦j<N _group ) defined as Equations 9 and 10 For, m bit groups such as {X _π(i) , X _π(α+i) ,...,X _{π((m-1)×α+i)} } (0≤i<α) Bits belonging to are configured to constitute one modulation symbol.

이다. 그리고, m은 블록 인터리버의 열의 개수를 의미하며, 이는 변조 심볼을 구성하는 비트의 개수 또는 변조 심볼을 구성하는 비트의 개수의 절반일 수 있다.Here, α is the number of bit groups constituting the first part of the block interleaver, α=

to be. In addition, m denotes the number of columns of the block interleaver, which may be half of the number of bits constituting the modulation symbol or the number of bits constituting the modulation symbol.

Therefore, as an example, for parity interleaved bits u _i , {u _π(i)+j , u _π(α+i)+j ,...,u _{π((m-1)×α+i )+j} } (0<i≤m, 0<j≤M) may constitute one modulation symbol. As described above, there may be various methods of configuring one modulation symbol.

In addition, the bit interleaving scheme proposed in the present invention is composed of a parity interleaver 121, a group interleaver 122, and a group twist interleaver 123 and a block-row interleaver 125 as shown in FIG. Accordingly, the group twist interleaver 123 may be omitted), which is only an example, and there is no need to limit it to being composed of three modules or four modules as described above.

For example, in the present invention, when a block-row interleaver is used and a group interleaving method expressed as Equation 12 is used, bit groups X _j (0≦j<N _group ), m bit groups such as {X _π(m×i) , X _π(m×i+1) ,...,X _{π(m×i+(m-1))} } (0 Bits belonging to ?i<α) constitute one modulation symbol.

이다. 그리고, m은 블록 인터리버의 열의 개수를 의미하며, 이는 변조 심볼을 구성하는 비트의 개수 또는 변조 심볼을 구성하는 비트의 개수의 절반일 수 있다.Here, α is the number of bit groups constituting the first part of the block interleaver, α=

to be. In addition, m denotes the number of columns of the block interleaver, which may be half of the number of bits constituting the modulation symbol or the number of bits constituting the modulation symbol.

Therefore, as an example, for parity interleaved bits u _i , (u _π(m×i)+j , u _π(m×i+1)+j ,...,u _{π(m×i+(m -1))+j} } (0<i≤m, 0<j≤M) may constitute one modulation symbol. As described above, there may be various methods of configuring one modulation symbol.

Meanwhile, in the present invention, the transmission device 100 may use an interleaving method differently according to a set including at least one of a code rate, a length of an LDPC codeword, and a modulation method.

For example, the transmission device 100 may perform interleaving using a block interleaver 124 in a first set including a specific code rate, a length of an LDPC codeword, and a modulation method, and different from the first set. In the second set including a specific code rate, LDPC codeword length, and modulation method, interleaving may be performed using the block-row interleaver 125.

24 is a block diagram illustrating a configuration of a receiving device according to an embodiment of the present invention. Referring to FIG. 24, a reception device 2700 includes a demodulation unit 2710, a multiplexer 2720, a deinterleaver 2730, and a decoding unit 2740.

The demodulation unit 2710 receives and demodulates the signal transmitted from the transmission device 100. Specifically, the demodulation unit 2710 demodulates the received signal to generate a value corresponding to the LDPC codeword, and outputs it to the multiplexer 2720. In this case, the demodulation unit 2710 may perform demodulation to correspond to the modulation method used in the transmission device 100.

To this end, the transmission device 100 may transmit information on the modulation method to the reception device 2700, or the transmission device 100 modulates using a predefined modulation method between the reception device 2700 and the reception device 2700. You can do it.

Here, the value corresponding to the LDPC codeword may be expressed as a channel value for the received signal. There may be various methods of determining the channel value, for example, a method of determining a Log Likelihood Ratio (LLR) value.

The LLR value may be expressed as a value obtained by taking a log in a ratio of a probability that a bit transmitted from the transmission device 100 is 0 and a probability of 1. Alternatively, the LLR value may be a bit value itself determined according to a hard decision, and the LLR value is a representative value determined according to a section to which the probability that the bit transmitted from the transmitting device 100 is 0 or 1 belongs. It could be.

The multiplexer 2720 multiplexes the output values of the demodulation unit 2710 and outputs them to the deinterleaver 2730.

Specifically, the multiplexer 2720 is a component corresponding to a demultiplexer (not shown) provided in the transmission device 100 and performs an operation corresponding to a demultiplexer (not shown). Accordingly, when the demultiplexer (not shown) is omitted in the transmitting device 100, the multiplexer 2720 of the receiving device 2700 may be omitted.

That is, the multiplexer 2720 may convert the output value of the demodulator 2710 cell-to-bit to output an LLR value in bit units.

In this case, when the demultiplexer (not shown) does not change the order of the LDPC codeword bits as shown in FIG. 13, the multiplexer 2720 does not change the order of LLR values corresponding to the bits constituting the cell, LLR values can be output sequentially. Alternatively, the multiplexer 2720 may rearrange the order of the LLR values corresponding to the bits constituting the cell so that the demultiplexing operation performed by the demultiplexer (not shown) is reversed based on Table 34. Meanwhile, information on whether to perform the demultiplexing operation may be provided from the transmitting device 100 or previously stored between the transmitting device 100 and the receiving device 2700.

The deinterleaver 2730 deinterleaves the output value of the multiplexer 2720 and outputs it to the decoder 2740.

Specifically, the deinterleaver 2730 is a component corresponding to the interleaver 120 of the transmission device 100 and performs an operation corresponding to the interleaver 120. That is, the deinterleaver 2730 reversely performs the interleaving operation performed by the interleaver 120 to deinterleave the LLR value.

To this end, the deinterleaver 2730 may include components as shown in FIGS. 25 and 27.

First, as shown in FIG. 25, the deinterleaver 2730 may include a block deinterleaver 2731, a group twist deinterleaver 2732, a group deinterleaver 2733, and a parity deinterleaver 2734.

The block deinterleaver 2731 deinterleaves the output of the multiplexer 2720 and outputs it to the group twist deinterleaver 2732.

Specifically, the block deinterleaver 2731 is a component corresponding to the block interleaver 124 provided in the transmission device 100 and may reversely perform an interleaving operation performed by the block interleaver 124.

That is, the block deinterleaver 271 writes the LLR values output from the multiplexer 2720 in the row direction to each row using at least one row consisting of a plurality of columns, and writes the LLR values to each of the plurality of rows written. Deinterleaving can be performed by leading the column in the column direction.

In this case, when interleaving is performed by dividing a column into two parts in the block interleaver 124, the block deinterleaver 271 may perform deinterleaving by dividing a row into two parts.

In addition, when the block interleaver 124 writes and reads a group not belonging to the first part in the row direction, the block deinterleaver 271 writes and reads a value corresponding to the group not belonging to the first part in the row direction. Deinterleaving can also be performed by reading.

Hereinafter, the block deinterleaver 273 will be described with reference to FIG. 26. However, this is only an example, and it goes without saying that the block deinterleaver 273 may be implemented in other ways.

,

이다.The input LLR v _{i (0≦} i<N ldpc) is written to _{the r i} row and c _i column of the block deinterleaver 2431. From here,

,

to be.

,

이다.On the other hand, the output LLR q _i (0≦i<N _c ×N _r1 ) is read from _{the c i} column and r _i row of the first part of the block deinterleaver 2431. From here,

,

to be.

,

이다.The output _{LLR q i (N c × N} r1 ≤i <N ldpc) is lead from the second part of the column c _i, r _i the row of the block deinterleaver (2431). From here,

,

to be.

The group twist deinterleaver 2732 deinterleaves the output value of the block deinterleaver 2431 and outputs it to the group deinterleaver 2733.

Specifically, the group twist deinterleaver 2732 is a component corresponding to the group twist interleaver 123 provided in the transmission device 100, and may reversely perform an interleaving operation performed by the group twist interleaver 123. .

That is, the group twist deinterleaver 2732 may rearrange the LLR values in the same group by changing the order of the LLR values existing in the same group. Meanwhile, when the group twist operation is not performed in the transmission device 100, the group twist deinterleaver 2732 may be omitted.

The group deinterleaver 2733 (or group-wise deinterleaver) deinterleaves the output value of the group twist deinterleaver 2732 and outputs it to the parity deinterleaver 2734.

Specifically, the group deinterleaver 2733 is a component corresponding to the group interleaver 122 provided in the transmission device 100 and may reversely perform an interleaving operation performed by the group interleaver 122.

That is, the group deinterleaver 2733 may rearrange the order of a plurality of groups in groups. In this case, the group deinterleaver 2733 may rearrange the order of a plurality of groups in groups by inversely applying the interleaving method of Tables 23 to 27 according to the length, modulation method, and code rate of the LDPC codeword.

Meanwhile, as described above, in the parity check matrix having the form of FIGS. 2 and 3, the order of column groups can be changed, and the column groups correspond to bit groups. Accordingly, when the order of the column groups of the parity check matrix is changed, the order of the bit groups may also be changed to correspond thereto, and the group deinterleaver 2733 may refer to this and rearrange the order of the plurality of groups in group units.

The parity deinterleaver 2734 performs parity deinterleaving on the output value of the group deinterleaver 2733 and outputs the parity deinterleaving to the decoder 2740.

Specifically, the parity deinterleaver 2734 is a component corresponding to the parity interleaver 121 provided in the transmission device 100 and may reversely perform an interleaving operation performed by the parity interleaver 121. That is, the parity deinterleaver 2734 may deinterleave LLR values corresponding to parity bits among LLR values output from the group deinterleaver 2733. In this case, the parity deinterleaver 2734 may deinterleave LLR values corresponding to parity bits in the reverse of the parity interleaving method of Equation (8). However, the parity deinterleaver 2734 may be omitted depending on the decoding method and implementation of the decoder 2740.

Meanwhile, the deinterleaver 2730 of FIG. 24 may be composed of three or four components as shown in FIG. 25, but operations of the components may be performed as one component. For example, when one bit belonging to each bit group for bit groups _{X a} , X _b , X _c , and X _{d constitutes one modulation symbol, the deinterleaver 2730} Deinterleaving may be performed to positions corresponding to bit groups based on the modulation symbol.

For example, when the code rate is 12/15 and the modulation method is 16-QAM, the group deinterleaver 2733 may perform deinterleaving based on Table 21.

In this case, one bit included in each of the _{bit groups X 35} , X ₃₇ , X ₁₆ , and X _{2 constitutes one modulation symbol.} Since each bit in bit groups X ₃₅ , X ₃₇ , X ₁₆ , and X ₂ constitutes one modulation symbol, the deinterleaver 2730 consists of bit groups X ₃₅ and X _{37 based on one received modulation symbol.} , X ₁₆ , and X ₂ may be mapped to initial decoding values.

Meanwhile, as shown in FIG. 27, the deinterleaver 2730 may include a block-row deinterleaver 2735, a group twist deinterleaver 2732, a group deinterleaver 2733, and a parity deinterleaver 2734. In this case, since the group twist deinterleaver 2732 and the parity deinterleaver 2734 perform the same function as in FIG. 25, detailed descriptions of overlapping portions will be omitted.

The block-row deinterleaver 2735 deinterleaves the output value of the multiplexer 2720 and outputs it to the group twist deinterleaver 2732.

Specifically, the block-row deinterleaver 2735 is a component corresponding to the block-low interleaver 125 provided in the transmission device 100, and performs an interleaving operation performed by the block-row interleaver 125 in reverse. can do.

That is, the block-row deinterleaver 2735 writes the LLR values output from the multiplexer 2720 in the column direction to each column using at least one column consisting of a plurality of rows, and Deinterleaving can be performed by reading each row in the column direction.

However, when the block-row interleaver 125 writes and reads a group that does not belong to the first part in the column direction, the block-row deinterleaver 2735 indicates a value corresponding to a group not belonging to the first part. Deinterleaving can also be performed by writing and reading in the direction.

The group deinterleaver 2733 deinterleaves the output value of the group twist deinterleaver 2732 and outputs this to the parity deinterleaver 2734.

Specifically, the group deinterleaver 2733 is a component corresponding to the group interleaver 122 provided in the transmission device 100 and may reversely perform an interleaving operation performed by the group interleaver 122.

That is, the group deinterleaver 2733 may rearrange the order of a plurality of groups in groups. In this case, the group deinterleaver 2733 may rearrange the order of a plurality of groups in groups by inversely applying the interleaving method of Tables 49 to 53 according to the length, modulation method, and code rate of the LDPC codeword.

Meanwhile, the deinterleaver 2730 of FIG. 24 may be composed of three or four components as shown in FIG. 27, but operations of the components may be performed as one component. For example, when one bit belonging to each bit group for bit groups _{X a} , X _b , X _c , and X _{d constitutes one modulation symbol, the deinterleaver 2730} Deinterleaving may be performed to positions corresponding to bit groups based on the modulation symbol.

To this end, the transmitting device 100 transmits various types of information used for interleaving by the interleaver 120 to the receiving device 2700, or the transmitting device 100 is a predefined method between the receiving device 2700 and the receiving device 2700. Interleaving can be performed using.

The decoder 2740 may perform LDPC decoding using an output value of the deinterleaver 2730. To this end, the decoder 2740 may include an LDPC decoder (not shown) for performing LDPC decoding.

Specifically, the decoding unit 2740 is a component corresponding to the encoding unit 110 of the transmission device 100, and can correct an error by performing LDPC decoding using the LLR value output from the deinterleaver 2730. have

For example, the decoder 2740 may perform LDPC decoding using an iterative decoding method based on a sum-product algorithm. Here, the summation algorithm is a kind of message passing algorithm, and the message passing algorithm is to exchange messages (e.g., LLR values) through edges on a bipartite graph, and to variable nodes or check nodes. Represents an algorithm that calculates and updates an output message from input messages.

Meanwhile, the decoder 2740 may use a parity check matrix during LDPC decoding. In this case, the information word partial matrix in the parity check matrix is defined as shown in Tables 4 to 21 according to the code rate and the length of the LDPC codeword, and the parity partial matrix may have a double diagonal structure.

In addition, information on a parity check matrix used in LDPC decoding and information on a code rate may be pre-stored in the reception device 2700 or may be provided from the transmission device 100.

28 is a flowchart illustrating a signal processing method of a transmission device according to an embodiment of the present invention.

First, LDPC encoding is performed to generate an LDPC codeword (S3010).

Thereafter, the LDPC codeword is interleaved (S3020), and the interleaved LDPC codeword is modulated according to a modulation method to generate a modulation symbol (S3030).

In operation S3020, the LDPC codewords may be interleaved by dividing each of a plurality of columns each including a plurality of rows into a first part and a second part according to the number of columns and the number of bit groups.

Here, the number of the plurality of columns has the same value as the modulation order according to the modulation method, and each of the plurality of columns may consist of rows equal to a value obtained by dividing the number of bits constituting the LDPC codeword by the number of columns.

In each of the plurality of columns, the first part is a bit group in each of a plurality of columns among a plurality of bit groups constituting the LDPC codeword according to the number of columns, the number of bit groups, and the number of bits constituting each bit group. Consists of as many rows as the number of bits included in at least some bit groups that can be written as a unit, and the second part is written in each of a plurality of columns in each of a plurality of columns in a row constituting each of a plurality of columns. It may be composed of rows excluding as many rows as the number of bits included in at least some possible bit groups.

In this case, the number of rows of the second part may have the same value as a quotient obtained by dividing the number of bits included in all bit groups except for the bit group corresponding to the first part by the number of columns.

Meanwhile, in step S3020, bits included in at least some bit groups that can be written in bit group units are sequentially written to each of a plurality of columns constituting the first part, and the rest of the plurality of bit groups excluding at least some bit groups The bits included in the bit group may be divided based on the number of columns and sequentially written to each of the plurality of columns constituting the second part.

In step S3020, the bits included in the remaining bit group are divided into a plurality of columns, each of the divided bits is written in a column direction to each of a plurality of columns constituting a second part, and the first part and the first part Interleaving may be performed by reading a plurality of columns constituting two parts in a row direction.

Meanwhile, the modulation order may be 2,4,6,8,10,12 when the modulation scheme is QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, or 4096-QAM.

Meanwhile, a non-transitory computer readable medium in which a program sequentially performing a signal processing method according to the present invention is stored may be provided.

The non-transitory readable medium refers to a medium that stores data semi-permanently and can be read by a device, rather than a medium that stores data for a short moment, such as a register, a cache, and a memory. Specifically, various applications or programs may be provided by being stored in a non-transitory readable medium such as a CD, DVD, hard disk, Blu-ray disk, USB, memory card, ROM, or the like.

In addition, although a bus is not shown in the above-described block diagram showing the transmitting device and the receiving device, communication between components in each device may be performed through a bus. In addition, each device may further include a processor such as a CPU or a microprocessor that performs the various steps described above.

In addition, although the preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the specific embodiments described above, and the technical field to which the present invention belongs without departing from the gist of the present invention claimed in the claims. In addition, various modifications are possible by those of ordinary skill in the art, and these modifications should not be understood individually from the technical spirit or prospect of the present invention.

100: transmitting device 110: encoding unit
120: interleaver 130: modulator

Claims (14)

In the transmission device,
An encoder for generating parity bits by encoding input bits based on a low density parity check (LDPC) code;
An interleaver for interleaving a codeword including the input bits and the parity bits; And
Includes; a modulator for mapping bits of the codeword to constellation points based on 256-QAM (quadrature amplitude modulation),
The interleaver,
A group interleaver for dividing the codeword into a plurality of groups and interleaving the plurality of groups; And
Including; a block interleaver for interleaving the bits of the interleaved plurality of groups using a plurality of columns,
Each of the plurality of columns includes a first part and a second part,
If the code length of the LDPC code is 64800, the number of bits written to the first part of each column is 7920, and the number of bits written to the second part of each column is 180,
If the code length of the LDPC code is 16200, the number of bits written to the first part of each column is 1800 and the number of bits written to the second part of each column is 225. The method of claim 1,
Each of the plurality of groups includes 360 bits. The method of claim 1,
The interleaver,
A parity interleaver for interleaving the parity bits; further comprising,
The group interleaver divides the codeword including the input bits and the interleaved parity bits into the plurality of groups.
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