JP2012015688A - Data processing device and data processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance durability to errors.SOLUTION: LDPC codes having a code length of 4320 bits are written in a column direction of a memory 31, and read out in a row direction. A code bit of 2, 4 or 6 bits read out from the memory 31 is set as 1 symbol, and mapped at signal points of 2, 2or 2. A column twist interleaver performs column twist interleave of changing the writing start position for writing code bits in the column direction of the memory 31 every column of the memory 31 as rearrangement processing of rearranging the code bits of the LDPC code so that plural code bits corresponding to 1 on any raw of an inspection matrix of the LDPC code are not contained in 1 symbol. The present invention is applicable for transmitting the LDPC code.

Description

  The present invention relates to a data processing apparatus and a data processing method, and more particularly, to a data processing apparatus and a data processing method capable of improving, for example, tolerance against data errors.

  LDPC (Low Density Parity Check) code has a high error correction capability, and recently, for example, widely used in transmission systems including satellite digital broadcasting such as DVB (Digital Video Broadcasting) -S.2 performed in Europe. It has begun to be adopted (for example, see Non-Patent Document 1). LDPC codes are also being considered for next-generation terrestrial digital broadcasting.

  Recent studies have shown that LDPC codes can achieve performance close to the Shannon limit as the code length is increased, similar to turbo codes and the like. In addition, since the LDPC code has the property that the minimum distance is proportional to the code length, its characteristic is that the block error probability characteristic is good, and furthermore, the so-called error floor phenomenon observed in the decoding characteristic such as turbo code is observed. An advantage is that it hardly occurs.

  Hereinafter, such an LDPC code will be specifically described. Note that the LDPC code is a linear code and does not necessarily need to be binary, but will be described here as being binary.

  The LDPC code is characterized in that the parity check matrix defining the LDPC code is sparse. Here, a sparse matrix is a matrix in which the number of “1” s in the matrix is very small (a matrix in which most elements are 0).

  FIG. 1 shows an example of a parity check matrix H of an LDPC code.

  In the parity check matrix H in FIG. 1, the weight of each column (column weight) (the number of “1”) (weight) is “3”, and the weight of each row (row weight) is “6”. .

  In the encoding by LDPC code (LDPC encoding), for example, a generator matrix G is generated based on the check matrix H, and the generator matrix G is multiplied by binary information bits to generate a codeword (LDPC code). ) Is generated.

Specifically, an encoding apparatus that performs LDPC encoding first calculates a generator matrix G that satisfies the expression GH ^T = 0 between the transposed matrix H ^T of the parity check matrix H. Here, when the generator matrix G is a K × N matrix, the encoding device multiplies the generator matrix G by a bit string (vector u) of information bits made up of K bits to generate a code made up of N bits. Generate the word c (= uG). The code word (LDPC code) generated by this encoding device is received on the receiving side via a predetermined communication path.

  LDPC code decoding is an algorithm proposed by Gallager called probabilistic decoding (Probabilistic Decoding), which consists of a variable node (also called a message node) and a check node. This can be done by a message passing algorithm based on belief propagation on a so-called Tanner graph. Here, hereinafter, the variable node and the check node are also simply referred to as nodes as appropriate.

  FIG. 2 shows a procedure for decoding the LDPC code.

In the following, a real value (reception LLR) expressing the “0” likelihood of the value of the i-th code bit of the LDPC code (1 codeword) received on the receiving side as a log likelihood ratio as appropriate. ) _Is also referred to as a received value u _0i . Further, a message output from the check node is u _j and a message output from the variable node is v _i .

First, in the decoding of the LDPC code, as shown in FIG. 2, in step S11, the LDPC code is received, the message (check node message) u _j is initialized to “0”, and the counter of the iterative process is used. The variable k taking the integer of is initialized to “0”, and the process proceeds to step S12. In step S12, a message (variable node message) v _i is obtained by performing the calculation (variable node calculation) shown in Expression (1) based on the received value u _0i obtained by receiving the LDPC code. Based on the message v _i , the message u _j is obtained by performing the calculation (check node calculation) shown in Expression (2).

・・・（１）

... (1)

・・・（２）

... (2)

Here, d _v and d _c in Equation (1) and Equation (2) can be arbitrarily selected to indicate the number of “1” s in the vertical direction (column) and horizontal direction (row) of the parity check matrix H, respectively. For example, in the case of a (3, 6) code, d _v = 3 and d _c = 6.

It should be noted that in the variable node calculation of Expression (1) and the check node calculation of (2), the message input from the edge (line connecting the variable node and the check node) to which the message is to be output, respectively. Are not subject to computation, the computation range is 1 to d _v -1 or 1 to d _c -1. In addition, the check node calculation of equation (2) actually creates a table of function R (v ₁ , v ₂ ) shown in equation (3) defined by one output for two inputs v ₁ and v ₂ in advance. In addition, this is performed by using it continuously (recursively) as shown in Equation (4).

・・・（３）

... (3)

・・・（４）

... (4)

  In step S12, the variable k is further incremented by “1”, and the process proceeds to step S13. In step S13, it is determined whether or not the variable k is larger than a predetermined iterative decoding count C. If it is determined in step S13 that the variable k is not greater than C, the process returns to step S12, and thereafter the same processing is repeated.

On the other hand, if it is determined in step S13 that the variable k is larger than C, the process proceeds to step S14, and a message v _i as a decoding result to be finally output is obtained by performing the calculation shown in equation (5). And the LDPC code decoding process ends.

・・・（５）

... (5)

Here, unlike the variable node calculation of equation (1), the calculation of equation (5) is performed using messages u _j from all branches connected to the variable node.

  FIG. 3 shows an example of a parity check matrix H of a (3, 6) LDPC code (coding rate 1/2, code length 12).

  In the parity check matrix H in FIG. 3, the column weight is 3 and the row weight is 6, as in FIG. 1.

  FIG. 4 shows a Tanner graph of the parity check matrix H of FIG.

  In FIG. 4, a check node is represented by plus “+”, and a variable node is represented by equal “=”. Check nodes and variable nodes correspond to the rows and columns of the parity check matrix H, respectively. The connection between the check node and the variable node is an edge, and corresponds to “1” of the check matrix element.

  That is, if the element in the j-th row and i-th column of the parity check matrix is 1, the i-th variable node ("=" node) from the top and the j-th check node ("from the top) in FIG. + "Node") are connected by a branch. The branch represents that the sign bit corresponding to the variable node has a constraint condition corresponding to the check node.

  In a sum product algorithm, which is a decoding method of an LDPC code, a variable node operation and a check node operation are repeatedly performed.

  FIG. 5 shows a variable node calculation performed in the variable node.

In the variable node, the message v _i corresponding to the branch to be calculated is the variable node of the formula (1) using the messages u ₁ and u ₂ from the remaining branches connected to the variable node and the received value u _0i. It is obtained by calculation. Messages corresponding to other branches are obtained in the same manner.

  FIG. 6 shows a check node operation performed at the check node.

  Here, the check node operation of the expression (2) uses the relationship of the expression a × b = exp {ln (| a |) + ln (| b |)} × sign (a) × sign (b), Equation (6) can be rewritten. However, sign (x) is 1 when x ≧ 0, and −1 when x <0.

・・・（６）

... (6)

If the function φ (x) is defined as the equation φ (x) = ln (tanh (x / 2)) when x ≧ 0, the equation φ ⁻¹ (x) = 2 tanh ⁻¹ (e ^−x ) holds. Equation (6) can be transformed into Equation (7).

・・・（７）

... (7)

  In the check node, the check node calculation of Expression (2) is performed according to Expression (7).

That is, in the check node, as shown in FIG. 6, the message u _j corresponding to the branch to be calculated is the messages v ₁ , v ₂ , v ₃ , v ₄ , v from the remaining branches connected to the check node. _It is obtained by the check node calculation of Equation (7) using ₅ . Messages corresponding to other branches are obtained in the same manner.

Note that the function φ (x) in the equation (7) can be expressed by the equation φ (x) = ln ((e ^x +1) / (e ^x −1)), and when x> 0, φ (x ) = φ ⁻¹ (x). When the functions φ (x) and φ ⁻¹ (x) are mounted on hardware, they may be mounted using a LUT (Look Up Table), but both are the same LUT.

DVB-S.2: ETSI EN 302 307 V1.1.2 (2006-06)

  LDPC codes are used in DVB-S.2 which is a standard for satellite digital broadcasting and DVB-T.2 which is a standard for next-generation terrestrial digital broadcasting. The LDPC code is planned to be used in DVB-C.2, the next-generation CATV (Cable Television) digital broadcasting standard.

  In digital broadcasting compliant with DVB standards such as DVB-S.2, LDPC codes are converted into symbols (or symbolized) for quadrature modulation (digital modulation) such as QPSK (Quadrature Phase Shift Keying), and these symbols are signals. It is mapped to a point and transmitted.

  In the symbolization of the LDPC code, the code bits of the LDPC code are exchanged in units of two or more code bits, and the code bit after the exchange is used as a symbol bit.

  Various methods for exchanging code bits for symbolizing an LDPC code have been proposed in various methods, for example, DVB-T.2.

  By the way, DVB-T.2 is a standard for digital broadcasting for fixed terminals such as television receivers installed in homes and the like, and may not be appropriate for digital broadcasting for portable terminals.

  In other words, the mobile terminal needs to have a smaller circuit scale than the fixed terminal, and it is necessary to reduce power consumption. Therefore, in digital broadcasting for portable terminals, in order to reduce the load necessary for processing such as decoding of LDPC codes in portable terminals, for example, the number of repetitions of LDPC code decoding (repetition decoding number C), LDPC code May be more limited than in the case of digital broadcasting for fixed terminals.

  However, even under such limitations, tolerance to errors needs to be maintained to some extent.

  The present invention has been made in view of such a situation, and is intended to improve resistance to errors in data such as LDPC codes.

The data processing apparatus or the data processing method according to the first aspect of the present invention is written in the column direction of a storage means for storing code bits of an LDPC (Low Density Parity Check) code in the row direction and the column direction, When the code bit of the LDPC code read in the row direction is a symbol, and m code bits of 2 bits or more of the LDPC code are transmitted as one symbol, the column direction of the storage means is Reordering means for performing column twist interleaving for changing the writing start position when the code bits of the LDPC code are written for each column of the storage means as a reordering process for reordering the code bits of the LDPC code, or A reordering step, where the code means of the LDPC code is represented by N bits, and a predetermined positive integer is represented by b, respectively, the storage means, When mb bits are stored in the row direction, N / (mb) bits are stored in the column direction, and the sign bits of the mb bits read in the row direction of the storage means are b symbols The LDPC code has a coding rate of 1/4, 1/3, 5/12, 1/2, 7/12, 2/3, or 3/4, and a code length N of 4320 bits. the sign, the m bits are 2 bits and the integer b is 1, the sign bit of the 2 bits of the LDPC code, which of the 2 ² signal points prescribed in a predetermined modulation scheme The storage means has two columns for storing 2 × 1 bits in the row direction, and the rearrangement means or the rearrangement step is a head position in the column direction of the storage means. When the address of each position in the column direction of the storage means is expressed by an integer in ascending order, the address of the storage means The write start position of the first column of the two columns is the position where the address is 0, and the write start position of the second column of the two columns of the storage means is the position where the address is 60 A data processing apparatus or a data processing method.

The data processing apparatus or the data processing method according to the second aspect of the present invention is written in the column direction of the storage means for storing the code bits of the LDPC (Low Density Parity Check) code in the row direction and the column direction, When the code bit of the LDPC code read in the row direction is a symbol, and m code bits of 2 bits or more of the LDPC code are transmitted as one symbol, the column direction of the storage means is Reordering means for performing column twist interleaving for changing the writing start position when the code bits of the LDPC code are written for each column of the storage means as a reordering process for reordering the code bits of the LDPC code, or A reordering step, where the code means of the LDPC code is represented by N bits, and a predetermined positive integer is represented by b, respectively, the storage means, When mb bits are stored in the row direction, N / (mb) bits are stored in the column direction, and the sign bits of the mb bits read in the row direction of the storage means are b symbols The LDPC code has a coding rate of 1/4, 1/3, 5/12, 1/2, 7/12, 2/3, or 3/4, and a code length N of 4320 bits. the sign, the m bits are 2 bits and the integer b is 2, the sign bit of the 2 bits of the LDPC code, which of the 2 ² signal points prescribed in a predetermined modulation scheme The storage means has four columns for storing 2 × 2 bits in the row direction, and the rearrangement means or the rearrangement step is a head position in the column direction of the storage means. When the address of each position in the column direction of the storage means is expressed by an integer in ascending order, the address of the storage means The write start position of the first column of the four columns is the position where the address is 0, and the write start position of the second column of the four columns of the storage means is the address of 62 The write start position of the third column of the four columns of the storage means is the position where the address is 36, and the write of the fourth column of the four columns of the storage means This is a data processing apparatus or data processing method in which the first position is the position where the address is 3.

The data processing apparatus or the data processing method according to the third aspect of the present invention is written in the column direction of a storage means for storing code bits of an LDPC (Low Density Parity Check) code in the row direction and the column direction, When the code bit of the LDPC code read in the row direction is a symbol, and m code bits of 2 bits or more of the LDPC code are transmitted as one symbol, the column direction of the storage means is Reordering means for performing column twist interleaving for changing the writing start position when the code bits of the LDPC code are written for each column of the storage means as a reordering process for reordering the code bits of the LDPC code, or A reordering step, where the code means of the LDPC code is represented by N bits, and a predetermined positive integer is represented by b, respectively, the storage means, When mb bits are stored in the row direction, N / (mb) bits are stored in the column direction, and the sign bits of the mb bits read in the row direction of the storage means are b symbols The LDPC code has a coding rate of 1/4, 1/3, 5/12, 1/2, 7/12, 2/3, or 3/4, and a code length N of 4320 bits. the sign, the m bits are 4 bits and the integer b is 1, the sign bit of the 4 bits of the LDPC code, which of the 2 ⁴ signal points prescribed in a predetermined modulation scheme The storage means has four columns for storing 4 × 1 bits in the row direction, and the rearrangement means or the rearrangement step is a head position in the column direction of the storage means. When the address of each position in the column direction of the storage means is expressed by an integer in ascending order, the address of the storage means The write start position of the first column of the four columns is the position where the address is 0, and the write start position of the second column of the four columns of the storage means is the address of 62 The write start position of the third column of the four columns of the storage means is the position where the address is 36, and the write of the fourth column of the four columns of the storage means This is a data processing apparatus or data processing method in which the first position is the position where the address is 3.

The data processing apparatus or the data processing method according to the fourth aspect of the present invention is written in the column direction of the storage means for storing the code bits of the LDPC (Low Density Parity Check) code in the row direction and the column direction, When the code bit of the LDPC code read in the row direction is a symbol, and m code bits of 2 bits or more of the LDPC code are transmitted as one symbol, the column direction of the storage means is Reordering means for performing column twist interleaving for changing the writing start position when the code bits of the LDPC code are written for each column of the storage means as a reordering process for reordering the code bits of the LDPC code, or A reordering step, where the code means of the LDPC code is represented by N bits, and a predetermined positive integer is represented by b, respectively, the storage means, When mb bits are stored in the row direction, N / (mb) bits are stored in the column direction, and the sign bits of the mb bits read in the row direction of the storage means are b symbols The LDPC code has a coding rate of 1/4, 1/3, 5/12, 1/2, 7/12, 2/3, or 3/4, and a code length N of 4320 bits. The m bits are 6 bits, the integer b is 1, and the 6-bit code bits of the LDPC code are any of ²⁶ signal points determined by a predetermined modulation scheme. The storage means has six columns for storing 6 × 1 bits in the row direction, and the rearrangement means or the rearrangement step is a head position in the column direction of the storage means. When the address of each position in the column direction of the storage means is expressed by an integer in ascending order, the address of the storage means The writing start position of the first column of the six columns is the position where the address is 0, and the writing start position of the second column of the six columns of the storage means is the address of 3 And the write start position of the third column of the six columns of the storage means is the position of address 68, and the write of the fourth column of the six columns of the storage means The starting position is the position where the address is 24, the writing start position of the fifth column of the six columns of the storage means is the position of the address 47, and the six columns of the storage means This is a data processing apparatus or data processing method in which the writing start position of the sixth column is the position where the address is 4.

The data processing apparatus or the data processing method according to the fifth aspect of the present invention is written in the column direction of the storage means for storing the code bits of the LDPC (Low Density Parity Check) code in the row direction and the column direction, When the code bit of the LDPC code read in the row direction is a symbol, and m code bits of 2 bits or more of the LDPC code are transmitted as one symbol, the column direction of the storage means is Reordering means for performing column twist interleaving for changing the writing start position when the code bits of the LDPC code are written for each column of the storage means as a reordering process for reordering the code bits of the LDPC code, or A reordering step, where the code means of the LDPC code is represented by N bits, and a predetermined positive integer is represented by b, respectively, the storage means, When mb bits are stored in the row direction, N / (mb) bits are stored in the column direction, and the sign bits of the mb bits read in the row direction of the storage means are b symbols The LDPC code has a coding rate of 1/4, 1/3, 5/12, 1/2, 7/12, 2/3, or 3/4, and a code length N of 4320 bits. the sign, the m bits are 4 bits and the integer b is 2, the sign bit of the 4 bits of the LDPC code, which of the 2 ⁴ signal points prescribed in a predetermined modulation scheme The storage means has 8 columns for storing 4 × 2 bits in the row direction, and the rearrangement means or the rearrangement step is a head position in the column direction of the storage means. When the address of each position in the column direction of the storage means is expressed by an integer in ascending order, the address of the storage means The write start position of the first column of the eight columns is the position where the address is 0, and the write start position of the second column of the eight columns of the storage means is the address of 2 The write start position of the third column of the eight columns of the storage means is the position of the address 46, and the write of the fourth column of the eight columns of the storage means The starting position is the position of address 79, the writing start position of the fifth column of the eight columns of the storage means is the position of address 291, and the eight columns of the storage means The writing start position of the sixth column is the position where the address is 146, the writing start position of the seventh column of the eight columns of the storage means is the position where the address is 3, The beginning of the 8th column of the 8 columns of storage means The data processing device according to the position whose address is 13, or a data processing method.

The data processing apparatus or the data processing method according to the sixth aspect of the present invention is written in the column direction of a storage means for storing code bits of an LDPC (Low Density Parity Check) code in the row direction and the column direction, When the code bit of the LDPC code read in the row direction is a symbol, and m code bits of 2 bits or more of the LDPC code are transmitted as one symbol, the column direction of the storage means is Reordering means for performing column twist interleaving for changing the writing start position when the code bits of the LDPC code are written for each column of the storage means as a reordering process for reordering the code bits of the LDPC code, or A reordering step, where the code means of the LDPC code is represented by N bits, and a predetermined positive integer is represented by b, respectively, the storage means, When mb bits are stored in the row direction, N / (mb) bits are stored in the column direction, and the sign bits of the mb bits read in the row direction of the storage means are b symbols The LDPC code has a coding rate of 1/4, 1/3, 5/12, 1/2, 7/12, 2/3, or 3/4, and a code length N of 4320 bits. The m bits are 6 bits, the integer b is 2, and the 6-bit code bits of the LDPC code are any of ²⁶ signal points determined by a predetermined modulation scheme. The storage means has 12 columns storing 6 × 2 bits in the row direction, and the rearrangement means or the rearrangement step is a head position in the column direction of the storage means. When the address of each position in the column direction of the storage means is expressed by an integer in ascending order, the storage means The writing start position of the first column of the 12 columns is the position where the address is 0, and the writing start position of the second column of the 12 columns of the storage means is the position where the address is 0. And the write start position of the third column of the 12 columns of the storage means is the position of the address 3 and the write of the fourth column of the 12 columns of the storage means. The starting position is the position where the address is 15, the writing start position of the fifth column of the 12 columns of the storage means is the position of the address 119, and the 12 columns of the storage means Of the 12 columns of the storage means, the writing start position of the sixth column is the position of the address 32, the writing start position of the seventh column of the 12 columns of the storage means is the position of the address 24, and Start writing 8th column of 12 columns of storage The address of 169 is the address of 169, the write start position of the ninth column of the 12 columns of the storage means is the position of the address 84, and the position of the 12 columns of the storage means The 10th column write start position is the address 3 position, and the 11th column write start position of the 12 columns of the storage means is the address 12 position. A data processing apparatus or a data processing method in which the writing start position of the twelfth column of the twelve columns of the means is the position where the address is 3.

Note that the parity check matrix of the LDPC code is a parity check matrix initial value representing the position of one element of the information matrix corresponding to the code length of the parity check matrix and the information length according to the coding rate for every 60 columns. 1 element of the information matrix determined by the table is arranged with a period of every 60 columns in the column direction,
The parity check matrix initial value table of an LDPC code with a coding rate of 1/4 is
111 115 245 809 815 864 1015 1050 2008 2077 2090 2277 2357 2382 2413 2455 2546 2598 2608 2664 2805 2981 3089
35 180 216 251 257 266 297 427 571 596 963 1252 1449 1588 1938 2069 2202 2404 2587 2652 2787 2855 3109
36 74 98 169 177 223 381 677 684 748 874 1308 1349 1436 1480 1786 2077 2551 2620 2905 3058 3194 3226
52 361 441 459 672 779 916 942 1189 1335 1725 1829 1932 1957 2055 2111 2378 2451 2572 2800 2847 2894 2934
146 344 392 427 639 853 1022 1070 1466 1488 1511 1564 1632 1730 1754 1921 1963 2122 2442 2634 2955 3092 3162
135 886 2142 2647
719 868 1316 1600
1067 1606 2385 2823
287 911 1506 2242
337 1192 2075 2268
163 1778 2314 2738
192 1401 1589 2046
648 1664 3039 3169
173 1160 1894 2000
73 770 1420 2687
1271 1706 2325 2917
73 1869 2883 3137
249 1012 1160 2721
Consists of
The parity check matrix initial value table of an LDPC code having a coding rate of 1/3 is:
91 115 152 392 509 892 985 1337 1542 1672 1820 2158 2330 2432 2660 2667 2831
364 524 557 1022 1201 1252 1300 1311 1357 1959 2114 2122 2130 2198 2311 2427 2539
245 458 664 869 1063 1164 1236 1398 1497 1669 1874 1955 1981 1989 2125 2349 2874
134 210 315 798 833 1232 1491 1841 1877 1957 1980 2057 2140 2275 2335 2436 2563
66 223 826 1044 1137 1253 1290 1570 1827 1847 1983 2429 2449 2455 2463 2722 2753
159 379 635 744 882 912 934 1086 1174 1545 1585 2225 2356 2747 2765 2807 2848
412 646 1187 2606
361 2212 2349 2505
1317 1442 2076 2611
1312 1940 2211 2295
1200 1581 2063 2410
8 951 1094 2384
102 362 802 2110
175 493 1344 2588
549 1113 1582 2311
1038 1830 2018 2507
880 1177 2078 2241
116 1174 2197 2282
152 1210 1464 2784
936 1185 1740 2087
590 1139 2280 2372
431 839 2281 2363
99 905 1633 2512
213 1050 1288 1707
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 5/12 is:
168 346 446 527 585 747 1129 1159 1276 1283 1361 1512 1527 1532 1537 1782 1794 1956 2133 2369
111 196 301 319 342 354 475 507 712 1026 1444 1454 1459 1553 1813 2024 2053 2162 2245 2479
69 286 372 399 741 759 1224 1515 1682 1685 1781 1843 1870 1984 2015 2045 2232 2236 2285 2411
92 518 550 565 631 643 825 834 987 1072 1108 1136 1227 1255 1341 1418 1430 1836 1880 2020
28 102 149 160 219 287 313 666 671 928 952 1438 1510 2055 2081 2119 2296 2342 2358 2445
147 194 351 460 509 641 748 755 970 1160 1337 1360 1410 1559 1650 1924 2072 2177 2266 2468
47 292 375 1912
957 1430 1717 2072
458 1607 1761 2489
290 805 1122 1189
324 1122 1293 2447
668 1317 2018 2437
507 803 819 1362
471 1952 2027 2359
88 1233 1543 1650
146 314 890 2419
410 1207 1638 2376
80 1302 1442 2166
1064 1263 1531 1696
180 535 1979 2017
910 924 1373 1693
91 1293 1647 1816
1121 1146 1264 2070
321 885 1630 1926
703 821 1155 1163
715 1198 1436 1576
393 758 950 2377
1337 1639 1674 2024
714 1088 1525 1547
1056 1410 1667 1973
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 1/2 is
135 300 342 383 482 543 641 662 798 1058 1125 1187 1398 1472 1582 1651 1716 1796 1799 1836
48 191 227 264 571 613 623 661 664 748 827 1052 1270 1366 1376 1494 1698 1718 1781 1886
75 233 317 382 605 623 656 768 846 1090 1161 1189 1245 1275 1347 1446 1616 1701 1735 1838
236 325 530 552 589 620 637 658 793 800 807 960 1049 1481 1554 1740 1841 1989 1991 2156
79 88 268 541 645 691 773 932 1077 1162 1516 1522 1540 1741 1781 1834 1862 1977 2020 2032
135 235 379 683 724 841 871 963 1014 1020 1241 1353 1533 1624 1643 1700 1957 2073 2107 2113
106 1706 2037 2074
2 131 448 553
138 1198 1690 1911
326 994 1213 1902
207 951 1491 1710
288 676 952 1561
310 579 792 1064
75 150 277 1104
280 971 1515 2015
1714 1876 2107 2126
198 394 551 2145
51 1145 1613 1766
793 1034 1082 1603
390 1423 1486 2010
676 850 1424 1676
706 767 888 1364
499 779 843 2108
317 1045 1497 1507
224 458 609 1933
219 400 689 1591
164 808 895 1902
629 1431 1552 1892
151 338 600 2097
189 1103 1392 1626
33 365 835 1215
573 1022 1576 1877
239 1169 1766 2061
607 846 990 2093
396 612 1427 1999
180 252 566 817
Consists of
The parity check matrix initial value table of an LDPC code having a coding rate of 7/12 is as follows:
182 275 329 391 518 548 588 595 669 672 787 820 967 1016 1023 1056 1088 1108 1170 1573 1639 1784
112 156 251 316 359 451 457 590 635 867 924 970 982 985 1028 1371 1439 1485 1571 1766 1784 1790
0 47 77 143 200 289 425 454 482 531 721 750 763 859 982 1037 1044 1068 1208 1517 1664 1772
28 116 127 142 184 255 279 395 413 453 570 629 676 717 750 842 1371 1599 1606 1653 1675 1764
81 129 142 267 285 471 498 632 680 893 945 994 1059 1105 1316 1326 1364 1616 1635 1715 1720 1747
25 53 69 263 520 553 556 573 920 976 1000 1043 1129 1141 1195 1319 1359 1391 1513 1680 1711 1736
1443 1572 1693 1754
82 470 732 738
1056 1079 1287 1656
85 798 951 1240
795 1208 1481 1703
638 660 935 1069
40 398 538 991
401 773 1187 1752
227 560 690 1741
378 675 881 1511
207 257 636 889
366 654 1041 1279
1079 1121 1434 1515
80 267 564 996
505 948 1271 1545
794 824 1226 1466
822 1021 1032 1474
304 771 1690 1740
69 932 974 1722
575 682 906 1377
418 1134 1633 1674
93 213 613 792
613 749 1264 1368
95 624 646 1107
1561 1592 1736 1774
322 603 1504 1683
52 478 497 1726
307 604 1202 1663
327 607 749 1456
107 510 1624 1708
381 1278 1330 1433
238 637 751 1315
698 1726 1742 1759
319 453 478 1537
642 815 1175 1558
722 939 974 1040
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 2/3 is:
66 80 110 250 268 296 342 502 564 631 845 934 998 1071 1090 1268 1282 1308 1428
3 23 44 212 368 616 681 778 800 844 856 889 949 967 1060 1292 1319 1398 1431
55 144 185 253 266 329 361 424 436 570 699 952 963 1012 1033 1254 1302 1304 1420
28 278 384 598 741 791 809 931 976 1084 1106 1183 1198 1212 1259 1263 1265 1337 1386
7 112 119 147 149 240 268 470 498 534 662 761 813 859 885 1097 1130 1226 1386
120 155 320 345 367 374 395 419 426 535 671 687 793 930 967 1035 1162 1300 1356
622 755 766 950
514 631 757 1073
489 541 614 691
660 786 1162 1216
219 447 635 787
29 572 578 758
170 634 1112 1291
608 892 1320 1345
444 693 1320 1358
358 448 842 1153
695 792 841 894
567 678 777 981
69 341 717 999
405 990 1171 1401
37 130 471 554
850 959 999 1208
464 624 970 1369
757 870 909 1072
45 168 1078 1203
592 735 1344 1401
32 215 445 915
120 1068 1350 1409
701 1062 1205 1319
103 793 1220 1303
579 651 738 757
444 1014 1251 1363
693 947 952 1176
278 499 1261 1325
49 485 1171 1233
238 559 650 947
865 980 1044 1401
50 83 310 500
186 644 1256 1387
340 434 869 1249
644 770 877 1076
299 315 849 1233
299 307 1085 1290
159 324 1091 1313
137 184 863 1404
398 431 478 1069
13 173 993 1133
129 329 730 1143
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 3/4 is:
27 103 130 135 146 249 432 446 501 618 706 795 843 988
80 295 372 403 585 642 719 740 805 904 908 958 999 1033
136 139 230 325 364 385 434 558 605 611 619 771 795 874
143 318 342 347 422 468 489 576 755 767 798 802 952 1014
35 40 187 241 310 458 590 687 698 719 739 765 786 1059
196 457 499 676 729 752 809 818 857 880 917 987 1050 1071
23 141 190 236 381 477 523 594 789 799 919 995 1012 1079
586 636 703 970
205 353 534 940
276 440 495 852
100 138 211 932
114 589 855 946
686 715 844 952
58 239 248 460
351 438 517 1049
245 467 847 867
54 629 698 743
79 490 628 714
138 586 778 861
42 410 485 921
61 882 884 1028
422 444 695 1032
333 385 506 698
83 137 397 534
37 387 489 1073
728 804 836 878
203 374 874 876
373 516 738 766
322 405 477 898
58 451 540 784
311 440 696 900
141 327 818 828
94 205 887 975
437 829 904 1066
3 152 712 889
452 504 689 975
450 651 808 820
425 681 721 845
77 319 330 901
553 769 865 870
168 825 831 938
43 183 771 782
41 325 491 1074
296 452 913 1075
416 728 964 1044
267 477 894 920
193 484 756 986
348 839 861 938
35 233 577 852
355 386 573 721
146 545 644 934
623 779 803 898
560 590 803 1073
219 428 713 1060
Consists of.

  In the first to sixth aspects as described above, the code bits of the LDPC (Low Density Parity Check) code are written in the column direction of the storage means for storing in the row direction and the column direction, and are read out in the row direction. When the code bit of the LDPC code is a symbol, and m code bits of 2 bits or more of the LDPC code are transmitted as one symbol, the code of the LDPC code in the column direction of the storage means Column twist interleaving for changing the writing start position when bits are written for each column of the storage means is performed as a rearrangement process for rearranging the code bits of the LDPC code. Further, when the code length of the LDPC code is represented as N bits and the predetermined positive integer is represented as b, the storage means stores mb bits in the row direction and N / in the column direction. (mb) bits are stored, and the mb code bits read out in the row direction of the storage means are made into b symbols.

Then, the m bits are 2 bits and the integer b is 1, the sign bit of the 2 bits of the LDPC code, to one of 2 ² signal points prescribed in a predetermined modulation scheme In the case of mapping, the storage means has two columns for storing 2 × 1 bits in the row direction, the address of the head position in the column direction of the storage means is set to 0, and When the address of each position in the direction is represented by an integer in ascending order, the write start position of the first column of the two columns of the storage means is the position where the address is 0, The start position of the second column of the columns is the position where the address is 60.

Further, the m bits are 2 bits and the integer b is 2, the sign bit of the 2 bits of the LDPC code, to one of 2 ² signal points prescribed in a predetermined modulation scheme In the case of mapping, the storage means has four columns for storing 2 × 2 bits in the row direction, the address of the head position in the column direction of the storage means is set to 0, and the column of the storage means When the address of each position in the direction is represented by an integer in ascending order, the write start position of the first column among the four columns of the storage means is the position where the address is 0, and the 4 of the storage means The start position of the second column of the columns is the position of the address 62, and the start position of the third column of the four columns of the storage means is the position of the address 36. And the fourth of the four columns of the storage means The starting position of the column is the position where the address is 3.

Further, the m bits are 4 bits and the integer b is 1, the sign bit of the 4 bits of the LDPC code, to one of 2 ⁴ signal points prescribed in a predetermined modulation scheme When mapped, the storage means has four columns for storing 4 × 1 bits in the row direction, the address of the head position in the column direction of the storage means is set to 0, and the column of the storage means When the address of each position in the direction is represented by an integer in ascending order, the write start position of the first column among the four columns of the storage means is the position where the address is 0, and the 4 of the storage means The start position of the second column of the columns is the position of the address 62, and the start position of the third column of the four columns of the storage means is the position of the address 36. 4 of the 4 columns of the storage means The start position of the eye column is the position where the address is 3.

Further, the m bits are 6 bits, the integer b is 1, and the 6-bit code bits of the LDPC code are any one of ²⁶ signal points determined by a predetermined modulation method. In the case of mapping, the storage means has 6 columns for storing 6 × 1 bits in the row direction, the address of the head position in the column direction of the storage means is set to 0, and the column of the storage means When the address of each position in the direction is represented by an integer in ascending order, the write start position of the first column among the six columns of the storage means is the position where the address is 0. The write start position of the second column of the columns is the position of the address 3, and the write start position of the third column of the six columns of the storage means is the address 68. The fourth of the six columns of the storage means The column write start position is the address 24, and the write start position of the fifth column of the six columns of the storage means is the address 47, and the storage means The start position of the 6th column among the 6 columns is the position where the address is 4.

Further, the m bits are 4 bits and the integer b is 2, the sign bit of the 4 bits of the LDPC code, to one of 2 ⁴ signal points prescribed in a predetermined modulation scheme In the case of mapping, the storage means has 8 columns for storing 4 × 2 bits in the row direction, the address of the head position in the column direction of the storage means is set to 0, and the column of the storage means When the address of each position in the direction is represented by an integer in ascending order, the write start position of the first column among the eight columns of the storage means is the position where the address is 0, and the storage means 8 The start position of the second column of the columns is the position of the address 2, and the start position of the third column of the eight columns of the storage means is the address 46. 4 of the 8 columns of the storage means The write start position of the column is the position of address 79, the write start position of the fifth column of the eight columns of the storage means is the position of address 291, and the storage means Of the 8 columns, the write start position of the 6th column is the position of the address 146, and the write start position of the 7th column of the 8 columns of the storage means is the address Is the position of 3, and the write start position of the eighth column among the eight columns of the storage means is the position of the address 13.

Further, the m bits are 6 bits, the integer b is 2, and the 6-bit code bits of the LDPC code are any one of ²⁶ signal points determined by a predetermined modulation method. In the case of mapping, the storage means has 12 columns storing 6 × 2 bits in the row direction, the address of the head position in the column direction of the storage means is set to 0, and the column of the storage means When the address of each position in the direction is represented by an integer in ascending order, the position where the first column of the 12 columns of the storage means starts to be written is the position where the address is 0. The start position of the second column of the columns is the position where the address is 0, and the start position of the third column of the 12 columns of the storage means is the position where the address is 3. 4 of the 12 columns of the storage means The starting position of writing the column of the eye is the position of the address 15, the writing start position of the fifth column of the 12 columns of the storage means is the position of the address 119, the memory The writing start position of the sixth column of the 12 columns of the means is the address 32, and the writing start position of the seventh column of the 12 columns of the storage means is The address is a position of 24, the write start position of the eighth column of the 12 columns of the storage means is the position of the address 169, and the position of 9 of the 12 columns of the storage means The write start position of the th column is the position of the address 84, the write start position of the tenth column of the 12 columns of the storage means is the position of the address 3, and the storage The first position of the eleventh column out of the twelve columns of the instrument There, the address is the location of the 12, 12-th writing starting position for the columns of the 12 columns of said storage means, the address is the position of 3.

Here, the LDPC code has a coding rate of 1/4, 1/3, 5/12, 1/2, 7/12, 2/3, or 3/4, and a code length N of 4320 bits. LDPC code. Further, the parity check matrix of the LDPC code is a parity check matrix initial value representing the position of one element of the information matrix corresponding to the code length of the parity check matrix and the information length corresponding to the coding rate for every 60 columns. One element of the information matrix determined by the table is arranged in a column direction with a period of every 60 columns. And, the parity check matrix initial value table of the LDPC code having a coding rate of 1/4 is
111 115 245 809 815 864 1015 1050 2008 2077 2090 2277 2357 2382 2413 2455 2546 2598 2608 2664 2805 2981 3089
35 180 216 251 257 266 297 427 571 596 963 1252 1449 1588 1938 2069 2202 2404 2587 2652 2787 2855 3109
36 74 98 169 177 223 381 677 684 748 874 1308 1349 1436 1480 1786 2077 2551 2620 2905 3058 3194 3226
52 361 441 459 672 779 916 942 1189 1335 1725 1829 1932 1957 2055 2111 2378 2451 2572 2800 2847 2894 2934
146 344 392 427 639 853 1022 1070 1466 1488 1511 1564 1632 1730 1754 1921 1963 2122 2442 2634 2955 3092 3162
135 886 2142 2647
719 868 1316 1600
1067 1606 2385 2823
287 911 1506 2242
337 1192 2075 2268
163 1778 2314 2738
192 1401 1589 2046
648 1664 3039 3169
173 1160 1894 2000
73 770 1420 2687
1271 1706 2325 2917
73 1869 2883 3137
249 1012 1160 2721
The parity check matrix initial value table of an LDPC code having a coding rate of 1/3 is:
91 115 152 392 509 892 985 1337 1542 1672 1820 2158 2330 2432 2660 2667 2831
364 524 557 1022 1201 1252 1300 1311 1357 1959 2114 2122 2130 2198 2311 2427 2539
245 458 664 869 1063 1164 1236 1398 1497 1669 1874 1955 1981 1989 2125 2349 2874
134 210 315 798 833 1232 1491 1841 1877 1957 1980 2057 2140 2275 2335 2436 2563
66 223 826 1044 1137 1253 1290 1570 1827 1847 1983 2429 2449 2455 2463 2722 2753
159 379 635 744 882 912 934 1086 1174 1545 1585 2225 2356 2747 2765 2807 2848
412 646 1187 2606
361 2212 2349 2505
1317 1442 2076 2611
1312 1940 2211 2295
1200 1581 2063 2410
8 951 1094 2384
102 362 802 2110
175 493 1344 2588
549 1113 1582 2311
1038 1830 2018 2507
880 1177 2078 2241
116 1174 2197 2282
152 1210 1464 2784
936 1185 1740 2087
590 1139 2280 2372
431 839 2281 2363
99 905 1633 2512
213 1050 1288 1707
The parity check matrix initial value table of an LDPC code with a coding rate of 5/12 is:
168 346 446 527 585 747 1129 1159 1276 1283 1361 1512 1527 1532 1537 1782 1794 1956 2133 2369
111 196 301 319 342 354 475 507 712 1026 1444 1454 1459 1553 1813 2024 2053 2162 2245 2479
69 286 372 399 741 759 1224 1515 1682 1685 1781 1843 1870 1984 2015 2045 2232 2236 2285 2411
92 518 550 565 631 643 825 834 987 1072 1108 1136 1227 1255 1341 1418 1430 1836 1880 2020
28 102 149 160 219 287 313 666 671 928 952 1438 1510 2055 2081 2119 2296 2342 2358 2445
147 194 351 460 509 641 748 755 970 1160 1337 1360 1410 1559 1650 1924 2072 2177 2266 2468
47 292 375 1912
957 1430 1717 2072
458 1607 1761 2489
290 805 1122 1189
324 1122 1293 2447
668 1317 2018 2437
507 803 819 1362
471 1952 2027 2359
88 1233 1543 1650
146 314 890 2419
410 1207 1638 2376
80 1302 1442 2166
1064 1263 1531 1696
180 535 1979 2017
910 924 1373 1693
91 1293 1647 1816
1121 1146 1264 2070
321 885 1630 1926
703 821 1155 1163
715 1198 1436 1576
393 758 950 2377
1337 1639 1674 2024
714 1088 1525 1547
1056 1410 1667 1973
The parity check matrix initial value table of an LDPC code having a coding rate of 1/2 is
135 300 342 383 482 543 641 662 798 1058 1125 1187 1398 1472 1582 1651 1716 1796 1799 1836
48 191 227 264 571 613 623 661 664 748 827 1052 1270 1366 1376 1494 1698 1718 1781 1886
75 233 317 382 605 623 656 768 846 1090 1161 1189 1245 1275 1347 1446 1616 1701 1735 1838
236 325 530 552 589 620 637 658 793 800 807 960 1049 1481 1554 1740 1841 1989 1991 2156
79 88 268 541 645 691 773 932 1077 1162 1516 1522 1540 1741 1781 1834 1862 1977 2020 2032
135 235 379 683 724 841 871 963 1014 1020 1241 1353 1533 1624 1643 1700 1957 2073 2107 2113
106 1706 2037 2074
2 131 448 553
138 1198 1690 1911
326 994 1213 1902
207 951 1491 1710
288 676 952 1561
310 579 792 1064
75 150 277 1104
280 971 1515 2015
1714 1876 2107 2126
198 394 551 2145
51 1145 1613 1766
793 1034 1082 1603
390 1423 1486 2010
676 850 1424 1676
706 767 888 1364
499 779 843 2108
317 1045 1497 1507
224 458 609 1933
219 400 689 1591
164 808 895 1902
629 1431 1552 1892
151 338 600 2097
189 1103 1392 1626
33 365 835 1215
573 1022 1576 1877
239 1169 1766 2061
607 846 990 2093
396 612 1427 1999
180 252 566 817
The parity check matrix initial value table of an LDPC code with a coding rate of 7/12 is:
182 275 329 391 518 548 588 595 669 672 787 820 967 1016 1023 1056 1088 1108 1170 1573 1639 1784
112 156 251 316 359 451 457 590 635 867 924 970 982 985 1028 1371 1439 1485 1571 1766 1784 1790
0 47 77 143 200 289 425 454 482 531 721 750 763 859 982 1037 1044 1068 1208 1517 1664 1772
28 116 127 142 184 255 279 395 413 453 570 629 676 717 750 842 1371 1599 1606 1653 1675 1764
81 129 142 267 285 471 498 632 680 893 945 994 1059 1105 1316 1326 1364 1616 1635 1715 1720 1747
25 53 69 263 520 553 556 573 920 976 1000 1043 1129 1141 1195 1319 1359 1391 1513 1680 1711 1736
1443 1572 1693 1754
82 470 732 738
1056 1079 1287 1656
85 798 951 1240
795 1208 1481 1703
638 660 935 1069
40 398 538 991
401 773 1187 1752
227 560 690 1741
378 675 881 1511
207 257 636 889
366 654 1041 1279
1079 1121 1434 1515
80 267 564 996
505 948 1271 1545
794 824 1226 1466
822 1021 1032 1474
304 771 1690 1740
69 932 974 1722
575 682 906 1377
418 1134 1633 1674
93 213 613 792
613 749 1264 1368
95 624 646 1107
1561 1592 1736 1774
322 603 1504 1683
52 478 497 1726
307 604 1202 1663
327 607 749 1456
107 510 1624 1708
381 1278 1330 1433
238 637 751 1315
698 1726 1742 1759
319 453 478 1537
642 815 1175 1558
722 939 974 1040
The parity check matrix initial value table of an LDPC code having a coding rate of 2/3 is
66 80 110 250 268 296 342 502 564 631 845 934 998 1071 1090 1268 1282 1308 1428
3 23 44 212 368 616 681 778 800 844 856 889 949 967 1060 1292 1319 1398 1431
55 144 185 253 266 329 361 424 436 570 699 952 963 1012 1033 1254 1302 1304 1420
28 278 384 598 741 791 809 931 976 1084 1106 1183 1198 1212 1259 1263 1265 1337 1386
7 112 119 147 149 240 268 470 498 534 662 761 813 859 885 1097 1130 1226 1386
120 155 320 345 367 374 395 419 426 535 671 687 793 930 967 1035 1162 1300 1356
622 755 766 950
514 631 757 1073
489 541 614 691
660 786 1162 1216
219 447 635 787
29 572 578 758
170 634 1112 1291
608 892 1320 1345
444 693 1320 1358
358 448 842 1153
695 792 841 894
567 678 777 981
69 341 717 999
405 990 1171 1401
37 130 471 554
850 959 999 1208
464 624 970 1369
757 870 909 1072
45 168 1078 1203
592 735 1344 1401
32 215 445 915
120 1068 1350 1409
701 1062 1205 1319
103 793 1220 1303
579 651 738 757
444 1014 1251 1363
693 947 952 1176
278 499 1261 1325
49 485 1171 1233
238 559 650 947
865 980 1044 1401
50 83 310 500
186 644 1256 1387
340 434 869 1249
644 770 877 1076
299 315 849 1233
299 307 1085 1290
159 324 1091 1313
137 184 863 1404
398 431 478 1069
13 173 993 1133
129 329 730 1143
The parity check matrix initial value table of an LDPC code with a coding rate of 3/4 is:
27 103 130 135 146 249 432 446 501 618 706 795 843 988
80 295 372 403 585 642 719 740 805 904 908 958 999 1033
136 139 230 325 364 385 434 558 605 611 619 771 795 874
143 318 342 347 422 468 489 576 755 767 798 802 952 1014
35 40 187 241 310 458 590 687 698 719 739 765 786 1059
196 457 499 676 729 752 809 818 857 880 917 987 1050 1071
23 141 190 236 381 477 523 594 789 799 919 995 1012 1079
586 636 703 970
205 353 534 940
276 440 495 852
100 138 211 932
114 589 855 946
686 715 844 952
58 239 248 460
351 438 517 1049
245 467 847 867
54 629 698 743
79 490 628 714
138 586 778 861
42 410 485 921
61 882 884 1028
422 444 695 1032
333 385 506 698
83 137 397 534
37 387 489 1073
728 804 836 878
203 374 874 876
373 516 738 766
322 405 477 898
58 451 540 784
311 440 696 900
141 327 818 828
94 205 887 975
437 829 904 1066
3 152 712 889
452 504 689 975
450 651 808 820
425 681 721 845
77 319 330 901
553 769 865 870
168 825 831 938
43 183 771 782
41 325 491 1074
296 452 913 1075
416 728 964 1044
267 477 894 920
193 484 756 986
348 839 861 938
35 233 577 852
355 386 573 721
146 545 644 934
623 779 803 898
560 590 803 1073
219 428 713 1060
Consists of.

  According to the first to sixth aspects of the present invention, it is possible to improve resistance to errors.

It is a figure explaining the check matrix H of an LDPC code. It is a flowchart explaining the decoding procedure of an LDPC code. It is a figure which shows the example of the check matrix of a LDPC code. It is a figure which shows the Tanner graph of a check matrix. It is a figure which shows a variable node. It is a figure which shows a check node. It is a figure which shows the structural example of one Embodiment of the transmission system to which this invention is applied. 3 is a block diagram illustrating a configuration example of a transmission device 11. FIG. 3 is a block diagram illustrating a configuration example of a bit interleaver 116. FIG. It is a figure which shows a check matrix. It is a figure which shows a parity matrix. It is a figure explaining the check matrix of the LDPC code prescribed | regulated to the DVB-S.2 standard. It is a figure explaining the check matrix of the LDPC code prescribed | regulated to the DVB-S.2 standard. It is a figure which shows the signal point arrangement | positioning of 16QAM. It is a figure which shows the signal point arrangement | positioning of 64QAM. It is a figure which shows the signal point arrangement | positioning of 64QAM. It is a figure which shows the signal point arrangement | positioning of 64QAM. FIG. 6 is a diagram for explaining processing of a demultiplexer 25. FIG. 6 is a diagram for explaining processing of a demultiplexer 25. It is a figure which shows the Tanner graph about decoding of an LDPC code. And the parity matrix H _T having a staircase structure, a diagram illustrating a Tanner graph corresponding to the parity matrix H _T. It is a diagram illustrating a parity matrix H _T of the parity check matrix H corresponding to the LDPC code after parity interleave. It is a figure which shows a conversion test matrix. It is a figure explaining the process of the column twist interleaver. It is a figure which shows the number of columns of the memory 31 required for column twist interleaving, and the address of the write start position. It is a figure which shows the number of columns of the memory 31 required for column twist interleaving, and the address of the write start position. 10 is a flowchart for explaining processing performed by a bit interleaver 116 and a QAM encoder 117. It is a figure which shows the model of the communication path employ | adopted by simulation. An error rate obtained by the simulation is a diagram showing the relationship between the Doppler frequency f _d of the flutter. An error rate obtained by the simulation is a diagram showing the relationship between the Doppler frequency f _d of the flutter. 3 is a block diagram illustrating a configuration example of an LDPC encoder 115. FIG. 5 is a flowchart for explaining processing of an LDPC encoder 115. [Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 1/4 and the code length 16200. It is a figure explaining the method of calculating | requiring the check matrix H from a check matrix initial value table. [Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 1/4 and the code length 4320. [Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with an encoding rate of 1/3 and a code length of 4320. [Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 5/12 and the code length 4320. [Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 1/2 and the code length 4320. [Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 7/12 and the code length 4320. [Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 2/3 and the code length 4320. [Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 3/4 and the code length 4320. [Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 5/6 and the code length 4320. [Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 11/12 and the code length 4320. It is a figure which shows the example of the Tanner graph of the ensemble of a degree sequence that column weight is 3 and row weight is 6. FIG. It is a figure which shows the example of the Tanner graph of a multi-edge type ensemble. [Fig. 38] Fig. 38 is a diagram illustrating a minimum cycle length and a performance threshold value of a parity check matrix of an LDPC code having a code length 4320. [Fig. 38] Fig. 38 is a diagram illustrating a parity check matrix of an LDPC code having a code length of 4320. [Fig. 38] Fig. 38 is a diagram illustrating a parity check matrix of an LDPC code having a code length of 4320. It is a figure which shows the number of columns of the memory 31 required for column twist interleaving, and the address of the write start position. It is a figure which shows the simulation result of BER at the time of performing column twist interleaving. It is a figure explaining the exchange process of the present system. It is a figure explaining the exchange process of the present system. FIG. 4 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length of 4k and a coding rate of 1/4 is modulated by 64QAM and a multiple b is 2. FIG. 11 is a diagram illustrating an allocation rule when an LDPC code having a code length of 4k and a coding rate of 1/4 is modulated by 64QAM, and a multiple b is 2. [Fig. 10] Fig. 10 is a diagram illustrating code bit replacement according to an allocation rule when an LDPC code having a code length of 4k and a coding rate of 1/4 is modulated by 64QAM and a multiple b is 2. FIG. 4 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length of 4k and a coding rate of 1/3 is modulated by 64QAM and a multiple b is 2. FIG. 10 is a diagram showing an allocation rule when an LDPC code having a code length of 4k and a coding rate of 1/3 is modulated by 64QAM, and a multiple b is 2. [Fig. 12] Fig. 12 is a diagram illustrating code bit replacement according to an allocation rule when an LDPC code having a code length of 4k and a coding rate of 1/3 is modulated by 64QAM and a multiple b is 2. [Fig. 11] Fig. 11 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length of 4k and a coding rate of 5/12 is modulated by 64QAM and the multiple b is 2. FIG. 11 is a diagram illustrating an allocation rule when an LDPC code having a code length of 4k and a coding rate of 5/12 is modulated by 64QAM, and a multiple b is 2. [Fig. 10] Fig. 10 is a diagram illustrating code bit replacement according to an allocation rule when an LDPC code having a code length of 4k and an encoding rate of 5/12 is modulated by 64QAM and a multiple b is 2. [Fig. 11] Fig. 11 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length of 4k and a coding rate of 1/2 is modulated by 64QAM and a multiple b is 2. FIG. 10 is a diagram illustrating an allocation rule when an LDPC code having a code length of 4k and a coding rate of 1/2 is modulated by 64QAM, and a multiple b is 2. [Fig. 12] Fig. 12 is a diagram illustrating code bit replacement according to an allocation rule when an LDPC code having a code length of 4k and a coding rate of 1/2 is modulated by 64QAM and a multiple b is 2. [Fig. 12] Fig. 12 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length of 4k and a coding rate of 7/12 is modulated by 64QAM, and a multiple b is 2. [Fig. 12] Fig. 12 is a diagram illustrating an allocation rule when an LDPC code having a code length of 4k and a coding rate of 7/12 is modulated by 64QAM, and a multiple b is 2. [Fig. 11] Fig. 11 is a diagram illustrating code bit replacement according to an allocation rule when an LDPC code having a code length of 4k and a coding rate of 7/12 is modulated by 64QAM and a multiple b is 2. [Fig. 12] Fig. 12 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length of 4k and a coding rate of 2/3 is modulated by 64QAM and a multiple b is 2. FIG. 10 is a diagram showing an allocation rule when an LDPC code having a code length of 4k and a coding rate of 2/3 is modulated by 64QAM, and a multiple b is 2. [Fig. 10] Fig. 10 is a diagram illustrating code bit replacement according to an allocation rule when an LDPC code having a code length of 4k and an encoding rate of 2/3 is modulated by 64QAM and a multiple b is 2. FIG. 6 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length of 4k and a coding rate of 3/4 is modulated by 64QAM, and a multiple b is 2. FIG. 11 is a diagram showing an allocation rule when an LDPC code having a code length of 4k and a coding rate of 3/4 is modulated by 64QAM, and a multiple b is 2. [Fig. 10] Fig. 10 is a diagram illustrating code bit replacement according to an allocation rule when an LDPC code having a code length of 4k and an encoding rate of 3/4 is modulated by 64QAM and a multiple b is 2. [Fig. 10] Fig. 10 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length of 4k and a coding rate of 5/6 is modulated by 64QAM and a multiple b is 2. FIG. 11 is a diagram illustrating an allocation rule when an LDPC code having a code length of 4k and a coding rate of 5/6 is modulated by 64QAM, and a multiple b is 2. [Fig. 12] Fig. 12 is a diagram illustrating code bit replacement according to an allocation rule when an LDPC code having a code length of 4k and a coding rate of 5/6 is modulated by 64QAM and a multiple b is 2. [Fig. 10] Fig. 10 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length of 4k and a coding rate of 11/12 is modulated by 64QAM and a multiple b is 2. FIG. 11 is a diagram illustrating an allocation rule when an LDPC code having a code length of 4k and a coding rate of 11/12 is modulated by 64QAM, and a multiple b is 2. [Fig. 10] Fig. 10 is a diagram illustrating code bit replacement according to an allocation rule when an LDPC code having a code length of 4k and a coding rate of 11/12 is modulated by 64QAM and a multiple b is 2. FIG. 5 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length of 4k and a coding rate of 1/4 is modulated by 16QAM and a multiple b is 2. FIG. 11 is a diagram illustrating an allocation rule when an LDPC code having a code length of 4k and a coding rate of 1/4 is modulated by 16QAM, and a multiple b is 2. [Fig. 12] Fig. 12 is a diagram illustrating code bit replacement according to an allocation rule when an LDPC code having a code length of 4k and a coding rate of 1/4 is modulated by 16QAM and a multiple b is 2. FIG. 4 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length of 4k and a coding rate of 1/3 is modulated by 16QAM and a multiple b is 2. FIG. 11 is a diagram showing an allocation rule when an LDPC code having a code length of 4k and a coding rate of 1/3 is modulated by 16QAM, and a multiple b is 2. [Fig. 10] Fig. 10 is a diagram illustrating code bit replacement according to an allocation rule when an LDPC code having a code length of 4k and a coding rate of 1/3 is modulated by 16QAM and a multiple b is 2. FIG. 4 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length of 4k and a coding rate of 5/12 is modulated by 16QAM and a multiple b is 2. FIG. 11 is a diagram illustrating an allocation rule when an LDPC code having a code length of 4k and a coding rate of 5/12 is modulated by 16QAM, and a multiple b is 2. [Fig. 12] Fig. 12 is a diagram illustrating code bit replacement according to an allocation rule when an LDPC code having a code length of 4k and a coding rate of 5/12 is modulated by 16QAM and a multiple b is 2. [Fig. 10] Fig. 10 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length of 4k and a coding rate of 1/2 is modulated by 16QAM and a multiple b is 2. FIG. 11 is a diagram showing an allocation rule when an LDPC code having a code length of 4k and a coding rate of 1/2 is modulated by 16QAM, and a multiple b is 2. [Fig. 10] Fig. 10 is a diagram illustrating code bit replacement according to an allocation rule when an LDPC code having a code length of 4k and an encoding rate of 1/2 is modulated by 16QAM and a multiple b is 2. [Fig. 10] Fig. 10 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length of 4k and a coding rate of 7/12 is modulated by 16QAM and a multiple b is 2. FIG. 11 is a diagram illustrating an allocation rule when an LDPC code having a code length of 4k and a coding rate of 7/12 is modulated by 16QAM, and a multiple b is 2. [Fig. 10] Fig. 10 is a diagram illustrating code bit replacement according to an allocation rule when an LDPC code having a code length of 4k and a coding rate of 7/12 is modulated by 16QAM and a multiple b is 2. FIG. 4 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length of 4k and a coding rate of 2/3 is modulated by 16QAM and a multiple b is 2. FIG. 11 is a diagram showing an allocation rule when an LDPC code having a code length of 4k and a coding rate of 2/3 is modulated by 16QAM, and a multiple b is 2. [Fig. 10] Fig. 10 is a diagram illustrating code bit replacement according to an allocation rule when an LDPC code having a code length of 4k and an encoding rate of 2/3 is modulated by 16QAM and a multiple b is 2. FIG. 3 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length of 4k and a coding rate of 3/4 is modulated by 16QAM and a multiple b is 2. FIG. 11 is a diagram showing an allocation rule when an LDPC code having a code length of 4k and a coding rate of 3/4 is modulated by 16QAM, and a multiple b is 2. [Fig. 10] Fig. 10 is a diagram illustrating code bit replacement according to an allocation rule when an LDPC code having a code length of 4k and a coding rate of 3/4 is modulated by 16QAM and a multiple b is 2. FIG. 7 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length of 4k and a coding rate of 5/6 is modulated by 16QAM and the multiple b is 2. FIG. 11 is a diagram illustrating an allocation rule when an LDPC code having a code length of 4k and a coding rate of 5/6 is modulated by 16QAM, and a multiple b is 2. [Fig. 10] Fig. 10 is a diagram illustrating code bit replacement according to an allocation rule when an LDPC code having a code length of 4k and a coding rate of 5/6 is modulated by 16QAM and a multiple b is 2. FIG. 4 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length of 4k and a coding rate of 11/12 is modulated by 16QAM and a multiple b is 2. FIG. 11 is a diagram showing an allocation rule when an LDPC code having a code length of 4k and a coding rate of 11/12 is modulated by 16QAM, and a multiple b is 2. [Fig. 10] Fig. 10 is a diagram illustrating code bit replacement according to an allocation rule when an LDPC code having a code length of 4k and a coding rate of 11/12 is modulated by 16QAM and a multiple b is 2. FIG. 7 is a diagram illustrating a BER simulation result when an LDPC code having a code length of 4k and a coding rate of 1/4 is modulated by 64QAM, and a multiple b is 2. FIG. 7 is a diagram illustrating a BER simulation result when an LDPC code having a code length of 4k and a coding rate of 1/3 is modulated by 64QAM, and a multiple b is 2. FIG. 11 is a diagram illustrating a BER simulation result when an LDPC code having a code length of 4k and a coding rate of 5/12 is modulated by 64QAM, and a multiple b is 2. FIG. 10 is a diagram illustrating a BER simulation result when an LDPC code having a code length of 4k and a coding rate of 1/2 is modulated by 64QAM, and a multiple b is 2. FIG. 7 is a diagram illustrating a BER simulation result when an LDPC code having a code length of 4k and a coding rate of 7/12 is modulated by 64QAM, and a multiple b is 2. FIG. 10 is a diagram illustrating a BER simulation result when an LDPC code having a code length of 4k and a coding rate of 2/3 is modulated by 64QAM, and a multiple b is 2. FIG. 10 is a diagram illustrating a BER simulation result when an LDPC code having a code length of 4k and a coding rate of 3/4 is modulated by 64QAM, and a multiple b is 2. [Fig. 10] Fig. 10 is a diagram illustrating a BER simulation result when an LDPC code having a code length of 4k and a coding rate of 5/6 is modulated by 64QAM, and a multiple b is 2. FIG. 11 is a diagram illustrating a BER simulation result when an LDPC code having a code length of 4k and a coding rate of 11/12 is modulated by 64QAM, and a multiple b is 2. FIG. 10 is a diagram illustrating a BER simulation result when an LDPC code having a code length of 4k and a coding rate of 1/4 is modulated by 16QAM, and a multiple b is 2. FIG. 10 is a diagram illustrating a BER simulation result when an LDPC code having a code length of 4k and a coding rate of 1/3 is modulated by 16QAM, and a multiple b is 2. FIG. 11 is a diagram illustrating a BER simulation result when an LDPC code having a code length of 4k and a coding rate of 5/12 is modulated by 16QAM, and a multiple b is 2. FIG. 10 is a diagram illustrating a BER simulation result when an LDPC code having a code length of 4k and a coding rate of 1/2 is modulated by 16QAM, and a multiple b is 2. FIG. 11 is a diagram illustrating a BER simulation result when an LDPC code having a code length of 4k and a coding rate of 7/12 is modulated by 16QAM, and a multiple b is 2. FIG. 11 is a diagram illustrating a BER simulation result when an LDPC code having a code length of 4k and a coding rate of 2/3 is modulated by 16QAM, and a multiple b is 2. FIG. 11 is a diagram illustrating a BER simulation result when an LDPC code having a code length of 4k and a coding rate of 3/4 is modulated by 16QAM, and a multiple b is 2. FIG. 6 is a diagram illustrating a BER simulation result when an LDPC code having a code length of 4k and a coding rate of 5/6 is modulated by 16QAM, and a multiple b is 2. FIG. 11 is a diagram illustrating a BER simulation result when an LDPC code having a code length of 4k and a coding rate of 11/12 is modulated by 16QAM, and a multiple b is 2. [Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 1/4 and the code length 4320. [Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with an encoding rate of 1/3 and a code length of 4320. [Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 5/12 and the code length 4320. [Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 1/2 and the code length 4320. [Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 7/12 and the code length 4320. [Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 2/3 and the code length 4320. [Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 3/4 and the code length 4320. [Fig. 38] Fig. 38 is a diagram illustrating a minimum cycle length and a performance threshold value of a parity check matrix of an LDPC code having a code length 4320. [Fig. 38] Fig. 38 is a diagram illustrating a parity check matrix of an LDPC code having a code length of 4320. It is a figure which shows the number of columns of the memory 31 required for column twist interleaving, and the address of the write start position. It is a figure which shows the simulation result of BER. 3 is a block diagram illustrating a configuration example of a receiving device 12. FIG. It is a block diagram which shows the structural example of the bit deinterleaver 165. FIG. 12 is a flowchart for describing processing performed by a QAM decoder 164, a bit deinterleaver 165, and an LDPC decoder 166. It is a figure which shows the example of the check matrix of a LDPC code. It is a figure which shows the matrix (conversion test matrix) which performed row substitution and column substitution to the check matrix. It is a figure which shows the conversion test matrix divided | segmented into 5x5 unit. It is a block diagram which shows the structural example of the decoding apparatus which performs P node operation collectively. 3 is a block diagram illustrating a configuration example of an LDPC decoder 166. FIG. It is a figure explaining the process of the multiplexer 54 which comprises the bit deinterleaver 165. FIG. It is a figure explaining the process of the column twist deinterleaver. It is a block diagram which shows the other structural example of the bit deinterleaver 165. FIG. It is a block diagram which shows the 1st structural example of the receiving system which can apply the receiving device. It is a block diagram which shows the 2nd structural example of the receiving system which can apply the receiving device. It is a block diagram which shows the 3rd structural example of the receiving system which can apply the receiving device. It is a block diagram which shows the structural example of one Embodiment of the computer to which this invention is applied.

  [Configuration example of transmission system to which the present invention is applied]

  FIG. 7 is a diagram of a transmission system to which the present invention is applied (a system refers to a logical collection of a plurality of devices, regardless of whether or not each configuration device is in the same housing). The structural example of embodiment is shown.

  In FIG. 7, the transmission system includes a transmission device 11 and a reception device 12.

  The transmission device 11 transmits (broadcasts) (transmits) a program for a fixed terminal or a portable terminal. That is, the transmission device 11 encodes target data to be transmitted, such as image data and audio data as a program for a fixed terminal or a portable terminal, into an LDPC code, for example, a communication channel that is a terrestrial wave 13 to transmit.

  The receiving device 12 is, for example, a mobile terminal, receives an LDPC code transmitted from the transmitting device 11 via the communication path 13, decodes it into target data, and outputs it.

  Here, it is known that the LDPC code used in the transmission system of FIG. 7 exhibits extremely high capability in an AWGN (Additive White Gaussian Noise) communication channel.

  However, a burst error or erasure may occur in the communication path 13 such as terrestrial waves. For example, in an Orthogonal Frequency Division Multiplexing (OFDM) system, echo (echo) (echo) in a multipath environment where D / U (Desired to Undesired Ratio) is 0 dB (Undesired = echo power equals Desired = main path power). Depending on the delay of a path other than the main path, the power of a specific symbol may be erasured.

  Also, even if flutter (channel with delay of 0 and doppler frequency applied echo) is added, if D / U is 0 dB, depending on the Doppler frequency, OFDM at a specific time There are cases where the power of the entire symbol becomes zero (erasure).

  Furthermore, a burst error may occur due to the state of the wiring from the receiving unit (not shown) such as an antenna that receives a signal from the transmitting device 11 to the receiving device 12 on the receiving device 12 side or the instability of the power supply of the receiving device 12. May occur.

On the other hand, in the decoding of the LDPC code, as shown in FIG. 5 described above, the code bit (received value u _0i of the LDPC code) at the variable node corresponding to the column of the parity check matrix H and thus the code bit of the LDPC code. Since the variable node operation of the expression (1) with the addition of) is performed, if an error occurs in the sign bit used for the variable node operation, the accuracy of the required message is reduced.

  In the decoding of the LDPC code, the check node performs the check node calculation of Expression (7) using the message obtained by the variable node connected to the check node, so that a plurality of connected variable nodes ( When the number of check nodes in which the error (including erasure) of the code bits of the LDPC code corresponding to) simultaneously increases, the decoding performance deteriorates.

  That is, for example, if two or more of the variable nodes connected to the check node become erasures simultaneously, the check node sends a message with an equal probability of a probability of 0 and a probability of 1 to all the variable nodes. return. In this case, a check node that returns an equiprobable message does not contribute to one decoding process (one set of variable node calculation and check node calculation), and as a result, requires a large number of repetitions of the decoding process. As a result, the decoding performance deteriorates, and the power consumption of the receiving apparatus 12 that decodes the LDPC code increases.

  Therefore, in the transmission system of FIG. 7, the tolerance to burst errors and erasures is improved while maintaining the performance on the AWGN communication path.

  [Configuration Example of Transmitting Device 11]

  FIG. 8 is a block diagram illustrating a configuration example of the transmission device 11 of FIG.

  In the transmission apparatus 11, one or more input streams (Input Streams) as target data are supplied to a mode adaptation / multiplexer (Mode Adaptation / Multiplexer) 111.

  The mode adaptation / multiplexer 111 performs mode selection and multiplexing of one or more input streams supplied thereto, and supplies the resulting data to a padder 112.

  The padder 112 performs necessary zero padding (Null insertion) on the data from the mode adaptation / multiplexer 111 and supplies the resulting data to a BB scrambler 113.

  The BB scrambler 113 performs energy spreading on the data from the padder 112 and supplies the resulting data to a BCH encoder 114.

  The BCH encoder 114 BCH-encodes the data from the BB scrambler 113, and supplies the data obtained as a result to an LDPC encoder 115 as LDPC target data that is a target of LDPC encoding.

  The LDPC encoder 115 performs LDPC encoding on the LDPC target data from the BCH encoder 114 according to a parity check matrix in which a parity matrix that is a part corresponding to the parity bits of the LDPC code has a staircase structure. Output LDPC code as information bits.

  That is, the LDPC encoder 115 performs LDPC encoding for encoding LDPC target data into an LDPC code such as an LDPC code defined in the DVB-T.2 standard, and outputs the resulting LDPC code. To do.

  Here, in the DVB-T.2 standard, the LDPC code defined in the DVB-S.2 standard is adopted except when the code length is 16200 bits and the coding rate is 3/5. . The LDPC code defined in the DVB-T.2 standard is an IRA (Irregular Repeat Accumulate) code, and the parity matrix in the parity check matrix of the LDPC code has a staircase structure. The parity matrix and the staircase structure will be described later. Regarding IRA codes, for example, “Irregular Repeat-Accumulate Codes,” H. Jin, A. Khandekar, and RJ McEliece, in Proceedings of 2nd International Symposium on Turbo codes and Related Topics, pp. 1-8, Sept. 2000.

  The LDPC code output from the LDPC encoder 115 is supplied to the bit interleaver 116.

  The bit interleaver 116 performs bit interleaving, which will be described later, on the LDPC code from the LDPC encoder 115 and supplies the LDPC code after the bit interleaving to a QAM encoder (QAM encoder) 117.

  The QAM encoder 117 maps the LDPC code from the bit interleaver 116 to a signal point representing one symbol of orthogonal modulation in units of one or more code bits (symbol unit) of the LDPC code and performs orthogonal modulation ( Multilevel modulation).

  That is, the QAM encoder 117 converts the LDPC code from the bit interleaver 116 into an IQ plane (IQ constellation) defined by an I axis representing an I component in phase with the carrier and a Q axis representing a Q component orthogonal to the carrier. ) Perform the quadrature modulation by mapping to the signal points determined by the modulation method that performs the quadrature modulation of the LDPC code.

  Here, as a modulation method of the quadrature modulation performed by the QAM encoder 117, for example, a modulation method including a modulation method defined in the DVB-T standard, for example, QPSK (Quadrature Phase Shift Keying), 16QAM, etc. (Quadrature Amplitude Modulation), 64QAM, 256QAM, 1024QAM, 4096QAM, etc. Which modulation method is used to perform quadrature modulation in the QAM encoder 117 is set in advance, for example, according to the operation of the operator of the transmission device 11. The QAM encoder 117 can perform other quadrature modulation, such as 4PAM (Pulse Amplitude Modulation).

  Data (symbols mapped to signal points) obtained by processing in the QAM encoder 117 is supplied to a time interleaver 118.

  The time interleaver 118 performs time interleaving for each symbol on the data (symbol) from the QAM encoder 117, and supplies the resulting data to a MISO / MIMO encoder (MISO / MIMO encoder) 119.

  The MISO / MIMO encoder 119 performs space-time coding on the data (symbol) from the time interleaver 118 and supplies it to a frequency interleaver 120.

  The frequency interleaver 120 performs frequency interleaving for each symbol for the data (symbol) from the MISO / MIMO encoder 119 and supplies the data to a frame builder / resource allocation unit 131.

  On the other hand, the BCH encoder 121 is supplied with control data (signalling) for transmission control such as a preamble called L1, for example.

  The BCH encoder 121 performs BCH encoding on the control data supplied thereto in the same manner as the BCH encoder 114, and supplies the resulting data to the LDPC encoder 122.

  The LDPC encoder 122 performs LDPC encoding on the data from the BCH encoder 121 as LDPC target data in the same manner as the LDPC encoder 115, and supplies the resulting LDPC code to the QAM encoder 123.

  Similarly to the QAM encoder 117, the QAM encoder 123 converts the LDPC code from the LDPC encoder 122 into a signal point representing one symbol of orthogonal modulation in units of one or more code bits (symbol unit) of the LDPC code. The orthogonal modulation is performed by mapping, and data (symbol) obtained as a result is supplied to the frequency interleaver 124.

  Similarly to the frequency interleaver 120, the frequency interleaver 124 performs frequency interleaving for each symbol on the data (symbol) from the QAM encoder 123 and supplies the data to the frame builder / resource allocation unit 131.

  The frame builder / resource allocation unit 131 inserts pilot symbols at necessary positions of the data (symbols) from the frequency interleavers 120 and 124, and from the resulting data (symbols), a predetermined number A frame composed of a number of symbols is formed and supplied to an OFDM generation unit 132.

  The OFDM generation unit 132 generates an OFDM signal corresponding to the frame from the frame from the frame builder / resource allocation unit 131, and transmits the OFDM signal via the communication path 13 (FIG. 7).

  FIG. 9 shows a configuration example of the bit interleaver 116 of FIG.

  The bit interleaver 116 is a data processing device that interleaves data, and includes a parity interleaver 23, a column twist interleaver 24, and a demultiplexer (DEMUX) 25.

  The parity interleaver 23 performs parity interleaving for interleaving the parity bits of the LDPC code from the LDPC encoder 115 to the positions of other parity bits, and supplies the LDPC code after the parity interleaving to the column twist interleaver 24.

  The column twist interleaver 24 performs column twist interleaving on the LDPC code from the parity interleaver 23 and supplies the LDPC code after the column twist interleaving to the demultiplexer 25.

  That is, the LDPC code is transmitted in the QAM encoder 117 of FIG. 8 by mapping one or more code bits of the LDPC code to signal points representing one symbol of orthogonal modulation.

  The column twist interleaver 24 uses a parity interleaver 23 so that a plurality of code bits of the LDPC code corresponding to 1 in any one row of the parity check matrix used in the LDPC encoder 115 are not included in one symbol. As rearrangement processing for rearranging the code bits of the LDPC code, for example, column twist interleaving as described later is performed.

  The demultiplexer 25 performs an exchange process for exchanging positions of two or more code bits of the LDPC code as a symbol for the LDPC code from the column twist interleaver 24, thereby obtaining an LDPC code with enhanced resistance to AWGN. Then, the demultiplexer 25 supplies two or more code bits of the LDPC code obtained by the replacement process to the QAM encoder 117 (FIG. 8) as a symbol.

  Next, FIG. 10 shows a parity check matrix H used for LDPC encoding by the LDPC encoder 115 of FIG.

The parity check matrix H has an LDGM (Low-Density Generation Matrix) structure, and among the code bits of the LDPC code, an information matrix H _A corresponding to an information bit and a parity matrix H _T corresponding to a parity bit And can be expressed by the formula H = [H _A | H _T ] (a matrix having the information matrix H _A as the left element and the parity matrix H _T as the right element).

  Here, the number of information bits and the number of parity bits in the code bits of one LDPC code (one code word) are referred to as information length K and parity length M, respectively, and one LDPC. The number of code bits of the code is called a code length N (= K + M).

The information length K and the parity length M for an LDPC code having a certain code length N are determined by the coding rate. Also, the parity check matrix H is an M × N matrix with rows × columns. Then, the information matrix H _A, becomes the matrix of M × K, the parity matrix H _T is a matrix of M × M.

Figure 11 illustrates a parity matrix H _T of the parity DVB-T.2 (and DVB-S.2) check matrix H of an LDPC code prescribed in the standard of.

Parity matrix H _T of the parity check matrix H of an LDPC code prescribed in the standard of DVB-T.2, as shown in FIG. 11, 1 elements, so to speak a staircase structure arranged in a stepwise manner. The row weight of the parity matrix H _T is 1 for the first row and 2 for all the remaining rows. The column weight is 1 for the last column and 2 for all the remaining columns.

As described above, LDPC codes of the check matrix H the parity matrix H _T has a staircase structure can be using the check matrix H, readily produced.

That is, an LDPC code (one codeword), together represented by a row vector c, and column vector obtained by transposing the row vector is represented as c ^T. Further, in the row vector c which is an LDPC code, the information bit portion is represented by the row vector A, and the parity bit portion is represented by the row vector T.

  In this case, the row vector c is expressed by the expression c = [A | T] (the element of the row vector A is the left element, and the row vector T is represented by the row vector A as information bits and the row vector T as parity bits. Can be represented by a row vector with the right element as the right element.

And the check matrix H, the row vector c = as LDPC codes | and [A T], it is necessary to satisfy the expression Hc ^T = 0, = such expression Hc ^T = 0 to satisfy the row vector c [A | T] to the row vector T as parity bits which constitute check matrix H = | when [H _a H _T] parity matrix H _T of the parity has a staircase structure shown in FIG. 11, in the formula Hc ^T = 0 By sequentially setting the elements in each row to 0 from the element in the first row of the column vector Hc ^T , it can be obtained sequentially (in order).

  FIG. 12 is a diagram for explaining the parity check matrix H of the LDPC code defined in the DVB-T.2 standard.

  For the KX column from the first column of the LDPC code parity check matrix H defined in the DVB-T.2 standard, the column weight is X, the subsequent K3 column is the column weight 3, and the subsequent The column weight is 2 for the M-1 column, and the column weight is 1 for the last column.

  Here, KX + K3 + M-1 + 1 is equal to the code length N.

  FIG. 13 is a diagram illustrating the number of columns KX, K3, and M and the column weight X for each coding rate r of the LDPC code defined in the DVB-T.2 standard.

  The DVB-T.2 standard defines LDPC codes with a code length N of 64,800 bits and 16,200 bits.

  For an LDPC code having a code length N of 64,800 bits, 11 code rates (nominal rates) 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3 / 4, 4/5, 5/6, 8/9, and 9/10 are defined, and for an LDPC code having a code length N of 16200 bits, 10 coding rates 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, and 8/9 are specified.

  Hereafter, the code length N of 64800 bits is also referred to as 64k bits, and the code length N of 16200 bits is also referred to as 16k bits.

  Regarding the LDPC code, it is known that the code bit corresponding to the column having the larger column weight of the check matrix H has a lower error rate.

  In the parity check matrix H defined in the DVB-T.2 standard shown in FIG. 12 and FIG. 13, the column weight on the head side (left side) tends to be large. As for the LDPC code corresponding to, there is a tendency that the first code bit is more resistant to errors (is more resistant to errors), and the last code bit is more vulnerable to errors.

  Next, FIG. 14 shows an arrangement on the IQ plane of 16 symbols (corresponding signal points) when 16QAM is performed by the QAM encoder 117 of FIG.

  That is, FIG. 14A shows DVQ-T.2 16QAM symbols.

In 16QAM, one symbol is represented by 4 bits, and there are 16 (= 2 ⁴ ) symbols. The 16 symbols are arranged so that the I direction × Q direction is a 4 × 4 square shape with the origin of the IQ plane as the center.

Assuming that the bit of i + 1 bit from the most significant bit in the bit string represented by one symbol is represented as bit y _i , the four bits represented by one symbol of 16QAM are bit y _{0 in} order from the most significant bit. , y ₁ , y ₂ , y ₃ . When the modulation method is 16QAM, 4 code bits of the LDPC code is (symbolized) into 4-bit y ₀ to y ₃ symbol (symbol value).

FIG. 14B shows bit boundaries for each of 4 bits (hereinafter also referred to as symbol bits) y ₀ to y ₃ represented by a 16QAM symbol.

Here, the bit boundary for symbol bit y _i (i = 0, 1, 2, 3 in FIG. 14) is a symbol whose symbol bit y _i is 0, a symbol that is 1 Means the boundary.

As shown in FIG. 14B, for the most significant symbol bit y ₀ of the 4 symbol bits y ₀ to y ₃ represented by the 16QAM symbol, only one location on the Q axis in the IQ plane becomes a bit boundary. For the second symbol bit y ₁ (from the most significant bit), only one location on the I axis on the IQ plane is the bit boundary.

For the third symbol bit y ₂ , _two positions of the 4 × 4 symbols are located between the first and second columns from the left and between the third and fourth columns. A bit boundary.

Further, for the fourth symbol bit y ₃ , two locations of the 4 × 4 symbols are located between the first row and the second row and between the third row and the fourth row from the top. A bit boundary.

The symbol bit y _i represented by a symbol is more likely to be erroneous (lower error probability) the more symbols are away from the bit boundary, and more likely to be error (higher error probability) as there are more symbols near the bit boundary.

Assuming that a bit that is hard to error (strong to errors) is called a “strong bit” and a bit that is easy to error (weak to errors) is called a “weak bit”, 4 symbol bits y ₀ to y _{3 of} a 16QAM symbol , The most significant symbol bit y ₀ and the second symbol bit y ₁ are strong bits, and the third symbol bit y ₂ and the fourth symbol bit y ₃ are weak bits. .

  15 to 17 show the arrangement of 64 symbols (corresponding signal points) on the IQ plane when 64QAM is performed by the QAM encoder 117 of FIG. 8, that is, DVB-T.2 16QAM symbols. Is shown.

In 64QAM, one symbol represents 6 bits, and there are 64 (= 2 ⁶ ) symbols. Then, the 64 symbols are arranged so that the I direction × Q direction has a square shape of 8 × 8 with the origin of the IQ plane as the center.

One symbol bit of 64QAM can be expressed as bits y ₀ , y ₁ , y ₂ , y ₃ , y ₄ , y _{5 in} order from the most significant bit. When the modulation method is 64QAM, the 6 code bits of the LDPC code are the symbol bit y ₀ no 6-bit to the symbol y _5.

Here, FIG. 15 shows bit boundaries for the most significant symbol bit y ₀ and the second symbol bit y ₁ among the symbol bits y ₀ to y ₅ of the 64QAM symbol, and FIG. th symbol bit y _2, the bit boundaries for the fourth symbol bit y _3, respectively, FIG. 17, the fifth symbol bit y _4, the bit boundaries for the sixth symbol bit y _5, respectively, each Show.

As shown in FIG. 15, the symbol bits y ₀ of the uppermost bit boundaries for the second symbol bit y _1, respectively, has at one place. Also, as shown in FIG. 16, there are two bit boundaries for each of the third symbol bit y ₂ and the fourth symbol bit y ₃ , and as shown in FIG. 17, the fifth symbol bit There are four bit boundaries for bit y ₄ and sixth symbol bit y ₅ .

Therefore, for the symbol bits y ₀ to y ₅ of the 64QAM symbol, the most significant symbol bit y ₀ and the second symbol bit y ₁ are strong bits, and the third symbol bits y ₂ and 4 th symbol bit y ₃ has become a strong bit to the next. The fifth symbol bit y ₄ and the sixth symbol bit y ₅ are weak bits.

  14 and FIG. 15 through FIG. 17, it can be seen that the symbol bits of the orthogonal modulation symbols tend to be higher bits in the upper bits and weak bits in the lower bits.

  Here, as described in FIGS. 12 and 13, the LDPC code output from the LDPC encoder 115 (FIG. 8) includes a code bit that is resistant to errors and a code bit that is vulnerable to errors.

  As described with reference to FIGS. 14 to 17, the symbol bits of the orthogonal modulation symbols performed by the QAM encoder 117 include strong bits and weak bits.

  Therefore, if a code bit vulnerable to an error of an LDPC code is assigned to a weak symbol bit of an orthogonal modulation symbol, the overall tolerance to the error is reduced.

  Therefore, an interleaver that interleaves the code bits of the LDPC code in a tendency to assign the code bits vulnerable to errors of the LDPC code to the strong bits (symbol bits) of the orthogonal modulation symbol has been proposed.

  The demultiplexer 25 in FIG. 9 can perform the processing of the interleaver.

  FIG. 18 is a diagram for explaining the processing of the demultiplexer 25 of FIG.

  That is, A in FIG. 18 shows a functional configuration example of the demultiplexer 25.

  The demultiplexer 25 includes a memory 31 and a replacement unit 32.

  The memory 31 is supplied with the LDPC code from the LDPC encoder 115.

  The memory 31 has a storage capacity for storing mb bits in the row (horizontal) direction and N / (mb) bits in the column (vertical) direction, and the LDPC supplied thereto The sign bit of the code is written in the column direction, read in the row direction, and supplied to the switching unit 32.

  Here, N (= information length K + parity length M) represents the code length of the LDPC code as described above.

  Also, m represents the number of code bits of the LDPC code that is one symbol, b is a predetermined positive integer, and is a multiple used to multiply m by an integer. As described above, the demultiplexer 25 uses the sign bit of the LDPC code as a symbol (symbolizes), and the multiple b represents the number of symbols that the demultiplexer 25 obtains by so-called symbolization.

  FIG. 18A shows a configuration example of the demultiplexer 25 when the modulation scheme is 64QAM. Therefore, the number m of code bits of the LDPC code that is one symbol is 6 bits.

  In FIG. 18A, the multiple b is 1, and therefore the memory 31 has a storage capacity of N / (6 × 1) × (6 × 1) bits in the column direction × row direction.

  Here, the storage area of the memory 31 extending in the column direction and having 1 bit in the row direction is hereinafter referred to as a column as appropriate. In FIG. 18A, the memory 31 is composed of 6 (= 6 × 1) columns.

  In the demultiplexer 25, the code bits of the LDPC code are written from the top to the bottom (column direction) of the columns constituting the memory 31 from the left to the right columns.

  When writing of the sign bit is completed to the bottom of the rightmost column, the sign bit is changed in units of 6 bits (mb bits) in the row direction from the first row of all the columns constituting the memory 31. It is read out and supplied to the replacement unit 32.

The exchanging unit 32 performs an exchanging process of exchanging the positions of the 6-bit code bits from the memory 31, and the 6 bits obtained as a result are replaced with 6 symbol bits y ₀ , y ₁ , y ₂ , y representing one symbol of 64QAM. Output as ₃ , y ₄ , y ₅ .

That is, mb bits (6 bits in this case) of code bits are read from the memory 31 in the row direction, and the i-th bit from the most significant bit of the mb bits of code bits read from the memory 31 is read out. (i = 0,1,..., mb−1), and bit b _i , the 6-bit code bits read out from the memory 31 in the row direction are bits b ₀ , It can be expressed as b ₁ , b ₂ , b ₃ , b ₄ , b ₅ .

The sign bit in the direction of bit b ₀ is a sign bit that is resistant to errors in the relationship of the column weights described in FIGS. 12 and 13, and the sign bit in the direction of bit b ₅ is a sign that is vulnerable to errors. It is a bit.

In the replacement unit 32, the 6-bit code bits b ₀ to b ₅ from the memory 31 are assigned the error-sensitive code bits to the strong bits of the 64QAM 1-symbol symbol bits y ₀ to y _5. As shown in the figure, it is possible to perform an exchange process for exchanging the positions of the 6-bit code bits b ₀ to b ₅ from the memory 31.

Here, as a replacement method for changing the 6-bit code bits b ₀ to b ₅ from the memory 31 and allocating them to each of the 6 symbol bits y ₀ to y ₅ representing one symbol of 64QAM, each company Therefore, various methods have been proposed.

  18B shows the first replacement method, FIG. 18C shows the second replacement method, and FIG. 18D shows the third replacement method.

In B of FIG. 18 to D of FIG. 18 (the same applies to FIG. 19 described later), the line segment connecting bits b _i and y _j assigns code bit b _i to symbol bit y _j of the symbol (symbol bit) y _j ).

  As the first replacement method of B in FIG. 18, it has been proposed to employ any one of the three types of replacement methods, and as the second replacement method of FIG. It has been proposed to employ any one of the replacement methods.

  As the third replacement method in FIG. 18D, it has been proposed to select and use six types of replacement methods in order.

  FIG. 19 shows a case where the modulation scheme is 64QAM (therefore, the number m of code bits of the LDPC code mapped to one symbol is 6 bits as in FIG. 18) and the multiple b is 2. A configuration example of the demultiplexer 25 and a fourth replacement method are shown.

  When the multiple b is 2, the memory 31 has a storage capacity of N / (6 × 2) × (6 × 2) bits in the column direction × row direction, and from 12 (= 6 × 2) columns. Composed.

  19A shows the order of writing LDPC codes to the memory 31. FIG.

  In the demultiplexer 25, as described with reference to FIG. 18, the code bits of the LDPC code are written from the upper side to the lower side (column direction) of the columns constituting the memory 31. Is called.

  When the writing of the sign bit is completed to the bottom of the rightmost column, the sign bit is set in units of 12 bits (mb bits) in the row direction from the first row of all the columns constituting the memory 31. It is read out and supplied to the replacement unit 32.

The exchanging unit 32 performs an exchanging process of exchanging the positions of the 12-bit code bits from the memory 31 by the fourth exchanging method, and the 12 bits obtained as a result represent 2 symbols (b symbols) of 64QAM. 12 bits, that is, 6 symbol bit y ₀ representing a symbol of _{64QAM, y 1, y 2,} y 3, y 4, and y _5, 6 symbol bits y ₀ representing the next one symbol, y _1, y ₂ , y ₃ , y ₄ , y ₅

  Here, B of FIG. 19 shows a fourth replacement method of the replacement processing by the replacement unit 32 of A of FIG.

When the multiple b is 2 (the same applies when the multiple b is 3 or more), in the replacement process, mb code bits are allocated to mb symbol bits of b consecutive symbols. In the following, including FIG. 19, for convenience of explanation, the i + 1-th bit from the most significant bit of the mb bits of b consecutive symbols is represented as bit (symbol bit) y _i .

  In addition, what type of replacement is appropriate, that is, whether the error rate in the AWGN channel is further improved depends on the coding rate, code length, modulation method, and the like of the LDPC code.

  [Parity interleave]

  Next, parity interleaving by the parity interleaver 23 in FIG. 9 will be described with reference to FIGS.

  FIG. 20 shows (part of) a Tanner graph of a parity check matrix of an LDPC code.

  As shown in FIG. 20, when two or more of the variable nodes (corresponding code bits) connected to the check node simultaneously become errors such as erasures, all the check nodes are connected to the check node. A message having a probability that the value is 0 and the probability that the value is 1 is returned to the variable node. For this reason, if a plurality of variable nodes connected to the same check node simultaneously become erasures or the like, the decoding performance deteriorates.

Incidentally, LDPC encoder 115 of FIG. 8 outputs, LDPC code prescribed in the standard of DVB-T.2 is the IRA code, parity matrix H _T of the parity check matrix H, as shown in FIG. 11 It has a staircase structure.

FIG. 21 shows a parity matrix H _T having a staircase structure and a Tanner graph corresponding to the parity matrix H _T.

That is, A of FIG. 21 shows a parity matrix H _T having a staircase structure, and B of FIG. 21 shows a Tanner graph corresponding to the parity matrix H _T of A of FIG.

In parity matrix H _T has a staircase structure, in each row (except the first row) first element is adjacent. Therefore, in the Tanner graph of the parity matrix H _T, the value of the parity matrix H _T corresponding to the columns of two adjacent elements are set to 1, the two variable nodes adjacent, connected to the same check node Yes.

  Therefore, if a parity error corresponding to the two adjacent variable nodes mentioned above simultaneously becomes an error due to a burst error, an erasure, or the like, two variable nodes (using the parity bit) corresponding to the two parity bits that are in error. Since the check node connected to the variable node that seeks the message returns the message having the same probability of 0 and 1 to the variable node connected to the check node, the decoding performance is improved. to degrade. When the burst length (the number of parity bits that continuously cause an error) increases, the number of check nodes that return messages with equal probability increases, and the decoding performance further deteriorates.

  Therefore, the parity interleaver 23 (FIG. 9) performs parity interleaving for interleaving the parity bits of the LDPC code from the LDPC encoder 115 to the positions of other parity bits in order to prevent the above-described degradation in decoding performance. .

Figure 22 illustrates a parity matrix H _T of the parity check matrix H corresponding to the LDPC code after parity interleave to the parity interleaver 23 of FIG. 9 is performed.

Here, the information matrix H _A of the parity check matrix H corresponding to the LDPC code defined in the DVB-T.2 standard and output from the LDPC encoder 115 has a cyclic structure.

  A cyclic structure is a structure in which a column matches a cyclic shift of another column.For example, for each P column, the position of 1 in each row of the P column is the first of the P column. A structure in which the column is cyclically shifted in the column direction by a value proportional to the value q obtained by dividing the parity length M is also included. Hereinafter, the P column in the cyclic structure is referred to as the number of columns in the cyclic structure unit as appropriate.

  As described in FIGS. 12 and 13, the LDPC code defined in the DVB-T.2 standard includes two types of LDPC codes having a code length N of 64800 bits and 16200 bits. For all types of LDPC codes, the number P of columns in the unit of the cyclic structure is defined as 360 which is one of the divisors excluding 1 and M among the divisors of the parity length M.

  Further, the parity length M is a value other than a prime number represented by the equation M = q × P = q × 360 using a value q that varies depending on the coding rate. Therefore, the value q is also one of the divisors other than 1 and M among the divisors of the parity length M, similarly to the column number P of the cyclic structure unit, and the parity length M is set to the cyclic structure. (The product of P and q, which is a divisor of the parity length M, becomes the parity length M).

  As described above, the parity interleaver 23 sets the information length to K, sets x to an integer between 0 and less than P, and sets y to an integer between 0 and less than q. Of the code bits of the code, the K + qx + y + 1-th code bit is interleaved at the position of the K + Py + x + 1-th code bit.

  The K + qx + y + 1-th code bit and the K + Py + x + 1-th code bit are both the K + 1-th code bit and the subsequent parity bits, and are therefore parity bits. According to interleaving, the position of the parity bit of the LDPC code is moved.

  According to such parity interleaving, the variable nodes connected to the same check node (corresponding parity bits) are separated by the number of columns P of the cyclic structure unit, that is, 360 bits here, so the burst length is In the case of less than 360 bits, it is possible to avoid a situation in which a plurality of variable nodes connected to the same check node cause an error at the same time, and as a result, it is possible to improve resistance to burst errors.

  Note that the LDPC code after parity interleaving that interleaves the K + qx + y + 1-th code bit at the position of the K + Py + x + 1-th code bit is K + qx + of the original parity check matrix H. This coincides with the LDPC code of a parity check matrix (hereinafter also referred to as a transform parity check matrix) obtained by performing column replacement for replacing the y + 1th column with the K + Py + x + 1th column.

  Further, as shown in FIG. 22, a pseudo cyclic structure having P columns (360 columns in FIG. 22) as a unit appears in the parity matrix of the conversion check matrix.

  Here, the pseudo cyclic structure means a structure in which a part except a part has a cyclic structure. The parity check matrix obtained by performing column replacement equivalent to parity interleaving on the parity check matrix of the LDPC code specified in the DVB-T.2 standard is a 360-row x 360-column portion at the right corner. In the shift matrix (to be described later), there is only one element of 1 (it is an element of 0), and in that respect, it is not a (complete) cyclic structure but a pseudo cyclic structure.

  In addition to the column replacement corresponding to parity interleaving with respect to the original check matrix H, the conversion check matrix in FIG. 22 replaces rows so that the conversion check matrix is configured with a configuration matrix described later. (Row replacement) is also applied to the matrix.

  [Column twist interleaving]

  Next, column twist interleaving as rearrangement processing by the column twist interleaver 24 of FIG. 9 will be described with reference to FIGS.

  8 transmits one or more bits of the LDPC code as one symbol. That is, for example, when 2 bits of code bits are used as one symbol, QPSK is used as a modulation system, for example. When 4 bits of code bits are used as 1 symbol, a modulation system is used. For example, 16QAM is used.

  When two or more bits of a code bit are transmitted as one symbol, if an erasure or the like occurs in a certain symbol, all the code bits of the symbol become an error (erasure).

  Therefore, in order to improve the decoding performance, in order to reduce the probability that a plurality of variable nodes (corresponding code bits) connected to the same check node simultaneously become erasures, the code bits of one symbol are changed. It is necessary to avoid that the corresponding variable node is connected to the same check node.

On the other hand, as described above, LDPC encoder 115 is output, the parity check matrix H of an LDPC code prescribed in the standard of DVB-T.2, the information matrix H _A has a cyclic structure and the parity matrix H _T is Has a staircase structure. As described with reference to FIG. 22, in the transform parity check matrix that is the parity check matrix of the LDPC code after parity interleaving, a cyclic structure (more precisely, a pseudo cyclic structure as described above) also appears in the parity matrix.

  FIG. 23 shows a conversion parity check matrix.

  That is, A of FIG. 23 shows a conversion parity check matrix of a parity check matrix H of an LDPC code having a code length N of 64,800 bits and a coding rate (r) of 3/4.

  In A of FIG. 23, the position of the element whose value is 1 in the conversion check matrix is indicated by a point (·).

  FIG. 23B shows processing performed by the demultiplexer 25 (FIG. 9) for the LDPC code of the conversion check matrix of A in FIG. 23, that is, the LDPC code after parity interleaving.

  In B of FIG. 23, the modulation method is 16QAM, and the code bits of the LDPC code after parity interleaving are written in the column direction in four columns constituting the memory 31 of the demultiplexer 25.

  Code bits written in the column direction in the four columns constituting the memory 31 are read out in units of 4 bits in the row direction to become one symbol.

In this case, 4-bit code bits B ₀ , B ₁ , B ₂ , and B ₃ that are one symbol are code bits corresponding to 1 in any one row of the conversion check matrix of A in FIG. In this case, the variable nodes corresponding to the sign bits B ₀ , B ₁ , B ₂ , and B ₃ are connected to the same check node.

Therefore, if the 4 sign bits B ₀ , B ₁ , B ₂ , B ₃ of one symbol are sign bits corresponding to 1 in any one row of the conversion check matrix, When an erasure occurs, an appropriate message cannot be obtained at the same check node connected to the variable nodes corresponding to the sign bits B ₀ , B ₁ , B ₂ , and B ₃ , and as a result, Performance deteriorates.

  Similarly, for coding rates other than 3/4, a plurality of code bits corresponding to a plurality of variable nodes connected to the same check node may be one symbol of 16QAM. is there.

  Therefore, the column twist interleaver 24 performs a process after parity interleaving from the parity interleaver 23 so that a plurality of code bits corresponding to 1 in any one row of the conversion check matrix are not included in one symbol. Column twist interleaving is performed to interleave the code bits of the LDPC code.

  FIG. 24 is a diagram for explaining column twist interleaving.

  That is, FIG. 24 shows the memory 31 (FIGS. 18 and 19) of the demultiplexer 25.

  As described with reference to FIG. 18, the memory 31 stores mb bits in the column (vertical) direction and has a storage capacity for storing N / (mb) bits in the row (horizontal) direction. Consists of The column twist interleaver 24 performs column twist interleaving by controlling the write start position when writing the code bits of the LDPC code in the column direction and reading in the row direction to the memory 31.

  That is, in the column twist interleaver 24, a plurality of code bits, which are read as one symbol, are read out in the row direction by appropriately changing the write start position at which code bit writing is started for each of a plurality of columns. The sign bit corresponding to 1 in any one row of the conversion parity check matrix is prevented (a plurality of code bits corresponding to 1 in any one row of the parity check matrix are not included in the same symbol. The code bits of the LDPC code are rearranged).

  Here, FIG. 24 illustrates a configuration example of the memory 31 when the modulation scheme is 16QAM and the multiple b described in FIG. 18 is 1. Therefore, the number m of code bits of the LDPC code made into one symbol is 4 bits, and the memory 31 is composed of 4 (= mb) columns.

  The column twist interleaver 24 writes the code bits of the LDPC code from the top to the bottom (column direction) of the four columns constituting the memory 31 (instead of the demultiplexer 25 in FIG. 18) from left to right. Towards the direction column.

  When the writing of the sign bit is completed up to the rightmost column, the column twist interleaver 24 starts from the first row of all the columns constituting the memory 31 in the row direction in units of 4 bits (mb bits). The code bit is read out and output to the switching unit 32 (FIGS. 18 and 19) of the demultiplexer 25 as the LDPC code after column twist interleaving.

  However, in the column twist interleaver 24, if the address at the top (top) position of each column is 0 and the address at each position in the column direction is expressed as an integer in ascending order, The starting position of writing is the position where the address is 0, the second column (from the left) is the starting position of writing, the address is the position 2, and the third column is the starting position of writing. The address is at position 4, and for the fourth column, the write start position is the position at address 7.

  For columns where the writing start position is other than the position where the address is 0, after writing the sign bit to the lowest position, it returns to the beginning (position where the address is 0), and the writing start position. Writing up to the position immediately before is performed. Thereafter, writing to the next (right) column is performed.

  By performing column twist interleaving as described above, with respect to the LDPC code defined in the DVB-T.2 standard, a plurality of code bits corresponding to a plurality of variable nodes connected to the same check node are converted into 16QAM. Can be avoided (contained in the same symbol), and as a result, decoding performance on a communication path with an erasure can be improved.

  FIG. 25 shows the number of columns of the memory 31 required for column twist interleaving and the writing of LDPC codes for 11 coding rates with a code length N of 64,800 as defined in the DVB-T.2 standard. The address of the starting position is shown for each modulation method.

  When the multiple b is 1 and the bit number m of one symbol is 2 bits by adopting, for example, QPSK as the modulation method, the memory 31 is arranged in the row direction according to FIG. It has two columns for storing 2 × 1 (= mb) bits and stores 64800 / (2 × 1) bits in the column direction.

  Then, the write start position of the first column of the two columns of the memory 31 is the position where the address is 0, and the write start position of the second column is the position where the address is 2. The

  For example, when any one of the first to third replacement methods in FIG. 18 is adopted as the replacement method of the replacement process of the demultiplexer 25 (FIG. 9), the multiple b is 1.

  When the multiple b is 2 and the bit number m of one symbol is 2 bits by adopting, for example, QPSK as the modulation method, the memory 31 is arranged in the row direction according to FIG. It has 4 columns for storing 2 × 2 bits and stores 64800 / (2 × 2) bits in the column direction.

  Of the four columns in the memory 31, the first column write start position is the address 0 position, the second column write start position is the address 2 position, and the third column The start position of writing in the column is the position where the address is 4, and the start position of writing in the fourth column is the position where the address is 7.

  For example, when the fourth replacement method of FIG. 19 is adopted as the replacement method of the replacement process of the demultiplexer 25 (FIG. 9), the multiple b is 2.

  When the multiple b is 1 and 16QAM is used as a modulation method, for example, when the bit number m of one symbol is 4 bits, the memory 31 is arranged in the row direction according to FIG. It has four columns for storing 4 × 1 bits, and stores 64800 / (4 × 1) bits in the column direction.

  Of the four columns of the memory 31, the first column write start position is the address 0 position, the second column write start position is the address 2 position, 3 The write start position of the second column is the position where the address is 4, and the write start position of the fourth column is the position where the address is 7.

  When the multiple b is 2 and 16QAM is adopted as a modulation method, for example, when the bit number m of one symbol is 4 bits, the memory 31 is arranged in the row direction according to FIG. It has 8 columns for storing 4 × 2 bits and stores 64800 / (4 × 2) bits in the column direction.

  Of the eight columns of the memory 31, the first column write start position is the address 0 position, the second column write start position is the address 0 position, 3 The start position of the second column is the position where the address is 2, the start position of the fourth column is the position where the address is 4, and the start position of the fifth column is the position where the address is 4. The position and the start position of writing in the sixth column are the position where the address is 5, the start position of writing in the seventh column is the position where the address is 7, and the starting position of the eighth column is The address is made with 7 positions, respectively.

  When the multiple b is 1 and 64QAM is used as a modulation method, for example, when the bit number m of one symbol is 6 bits, the memory 31 is arranged in the row direction according to FIG. It has 6 columns for storing 6 × 1 bits, and stores 64800 / (6 × 1) bits in the column direction.

  Of the six columns in the memory 31, the first column write start position is the address 0 position, the second column write start position is the address 2 position, 3 The first column write position is the address 5 position, the fourth column write start position is the address 9 position, and the fifth column write start position is the address 10. The position and the position at the beginning of writing in the sixth column are the position where the address is 13, respectively.

  When multiple b is 2 and 64QAM is adopted as a modulation method, for example, when the number of bits m of one symbol is 6 bits, according to FIG. 25, the memory 31 is arranged in the row direction. It has 12 columns for storing 6 × 2 bits, and stores 64800 / (6 × 2) bits in the column direction.

  Of the 12 columns of the memory 31, the first column write start position is the address 0 position, the second column write start position is the address 0 position, 3 The start position of the second column is the position where the address is 2, the start position of the fourth column is the position where the address is 2, and the start position of the fifth column is the position where the address is 3. The position and the start position of the 6th column are the position where the address is 4, the start position of the 7th column is the position where the address is 4 and the start position of the 8th column is The position where the address is 5 and the start position of writing in the ninth column are the position where the address is 5, and the start position of writing in the 10th column is the position where the address is 7 and the start position of writing in the 11th column. The position of is the position of address 8 and the 12th column Position of the writing start is set to the position whose address is 9, are respectively.

  When the multiple b is 1 and, for example, 256QAM is adopted as the modulation method, and the bit number m of one symbol is 8 bits, the memory 31 is arranged in the row direction according to FIG. It has 8 columns for storing 8 × 1 bits and stores 64800 / (8 × 1) bits in the column direction.

  Of the eight columns of the memory 31, the first column write start position is the address 0 position, the second column write start position is the address 0 position, 3 The start position of the second column is the position where the address is 2, the start position of the fourth column is the position where the address is 4, and the start position of the fifth column is the position where the address is 4. The position and the start position of writing in the sixth column are the position where the address is 5, the start position of writing in the seventh column is the position where the address is 7, and the starting position of the eighth column is The address is made with 7 positions, respectively.

  When the multiple b is 2 and 256QAM is used as the modulation method, for example, when the bit number m of one symbol is 8 bits, the memory 31 is arranged in the row direction according to FIG. It has 16 columns for storing 8 × 2 bits, and stores 64800 / (8 × 2) bits in the column direction.

  Of the 16 columns in the memory 31, the first column write start position is the address 0 position, the second column write start position is the address 2 position, 3 The start position of the second column is the position where the address is 2, the start position of the fourth column is the position where the address is 2, and the start position of the fifth column is the address where the address is 2. The position and the start position of writing the sixth column are the position where the address is 3, the start position of the seventh column is the position where the address is 7, and the start position of the eighth column is The position where the address is 15 and the start position of the 9th column are the position where the address is 16 and the start position where the 10th column is written are the position where the address is 20 and the start position of the 11th column. The position of is the position of address 22 and the 12th color The writing start position is the position where the address is 22, the writing start position of the 13th column is the position of address 27, the writing start position of the 14th column is the position of address 27, The write start position of the 15th column is the position where the address is 28, and the write start position of the 16th column is the position where the address is 32.

  When the multiple b is 1 and the bit number m of one symbol is 10 bits by adopting, for example, 1024QAM as a modulation method, the memory 31 is arranged in the row direction according to FIG. It has 10 columns for storing 10 × 1 bits, and stores 64800 / (10 × 1) bits in the column direction.

  Of the ten columns of the memory 31, the first column write start position is the address 0 position, the second column write start position is the address 3 position, 3 The first column write position is the address 6 position, the fourth column write start position is the address 8 position, the fifth column start position is the address 11 The position and the start position of the 6th column are the position of the address 13, the start position of the 7th column is the position of the address 15 and the start position of the 8th column is The address 17 position, the 9th column write start position, the address 18 position, and the 10th column write start position, the address 20 position, respectively.

  When the multiple b is 2 and the bit number m of one symbol is 10 bits by adopting, for example, 1024QAM as the modulation method, the memory 31 is arranged in the row direction according to FIG. It has 20 columns for storing 10 × 2 bits and stores 64800 / (10 × 2) bits in the column direction.

  Of the 20 columns of the memory 31, the first column write start position is the address 0 position, the second column write start position is the address 1 position, 3 The start position of the second column is the position where the address is 3, the start position of the fourth column is the position where the address is 4, and the start position of the fifth column is the position where the address is 5. The position and the start position of writing in the sixth column are the position where the address is 6, the start position of writing in the seventh column is the position where the address is 6, and the starting position of the eighth column is The position where the address is 9 and the start position of writing the ninth column are the position where the address is 13, and the start position of writing the tenth column is the position where the address is 14 and the start of writing the eleventh column. The position of is the position of address 14 and the 12th color The write start position of the address is position 16, the write start position of the 13th column is the position of address 21, the write start position of the 14th column is the position of address 21, The writing start position of the 15th column is the position where the address is 23, the writing start position of the 16th column is the position of address 25, and the writing start position of the 17th column is address 25. The 18th column write start position is the address 26 position, the 19th column write start position is the address 28 position, and the 20th column write start position is The address is 30 positions, respectively.

  When the multiple b is 1 and, for example, 4096QAM is adopted as the modulation method, and the bit number m of one symbol is 12 bits, the memory 31 is arranged in the row direction according to FIG. It has 12 columns for storing 12 × 1 bits, and stores 64800 / (12 × 1) bits in the column direction.

  Of the 12 columns of the memory 31, the first column write start position is the address 0 position, the second column write start position is the address 0 position, 3 The start position of the second column is the position where the address is 2, the start position of the fourth column is the position where the address is 2, and the start position of the fifth column is the position where the address is 3. The position and the start position of the 6th column are the position where the address is 4, the start position of the 7th column is the position where the address is 4 and the start position of the 8th column is The position where the address is 5 and the start position of writing in the ninth column are the position where the address is 5, and the start position of writing in the 10th column is the position where the address is 7 and the start position of writing in the 11th column. The position of is the position of address 8 and the 12th column Position of the writing start is set to the position whose address is 9, are respectively.

  When the multiple b is 2 and, for example, 4096QAM is adopted as the modulation method, and the bit number m of one symbol is 12 bits, the memory 31 is arranged in the row direction according to FIG. It has 24 columns for storing 12 × 2 bits, and stores 64800 / (12 × 2) bits in the column direction.

  Of the 24 columns in the memory 31, the first column write start position is the address 0 position, the second column write start position is the address 5 position, 3 The start position of the second column is the position where the address is 8, the start position of the fourth column is the position where the address is 8, and the start position of the fifth column is the position where the address is 8. The position and the writing start position of the sixth column are the position where the address is 8, the writing start position of the seventh column is the position of the address 10 and the writing start position of the eighth column is The position where the address is 10 and the start position of the 9th column are the position where the address is 10 and the start position where the 10th column is written are the position where the address is 12 and the start position of the 11th column. The position of is the position of address 13 and the 12th color The start position of the program is the position where the address is 16, the start position of the 13th column is the position where the address is 17, the start position of the 14th column is the position where the address is 19 The 15th column write start position is the address 21 position, the 16th column write start position is the address 22 position, and the 17th column write start position is the address The position of 23 and the start position of writing of the 18th column are the position of address 26, and the start position of writing of the 19th column is the position of address 37 and the start position of writing of the 20th column. The position of the address 39 and the start position of the 21st column are the position of the address 40 and the start position of the 22nd column is the position of the address 41 and the position of the 23rd column. The starting position is the address 41 And location, writing starting the 24th column position is set to the position whose address is 41, are respectively.

  FIG. 26 shows the number of columns of the memory 31 required for column twist interleaving and the writing for each LDPC code of 10 coding rates defined in the DVB-T.2 standard and having a code length N of 16200. The address of the starting position is shown for each modulation method.

  When the multiple b is 1 and the bit number m of one symbol is 2 bits by adopting, for example, QPSK as the modulation method, the memory 31 is arranged in the row direction according to FIG. It has two columns that store 2 × 1 bits and stores 16200 / (2 × 1) bits in the column direction.

  Of the two columns of the memory 31, the first column write start position is the address 0 position, and the second column write start position is the address 0 position. Is done.

  When the multiple b is 2 and the number of bits m of one symbol is 2 bits by adopting, for example, QPSK as the modulation method, the memory 31 is arranged in the row direction according to FIG. It has four columns for storing 2 × 2 bits, and stores 16200 / (2 × 2) bits in the column direction.

  Of the four columns of the memory 31, the first column write start position is the address 0 position, the second column write start position is the address 2 position, 3 The writing start position of the second column is the position where the address is 3, and the writing start position of the fourth column is the position where the address is 3.

  When the multiple b is 1 and 16QAM is used as the modulation method, for example, when the number of bits m of one symbol is 4 bits, the memory 31 is arranged in the row direction according to FIG. It has four columns for storing 4 × 1 bits, and stores 16200 / (4 × 1) bits in the column direction.

  Of the four columns of the memory 31, the first column write start position is the address 0 position, the second column write start position is the address 2 position, 3 The writing start position of the second column is the position where the address is 3, and the writing start position of the fourth column is the position where the address is 3.

  When the multiple b is 2 and 16QAM is used as a modulation method, for example, when the number of bits m of one symbol is 4 bits, the memory 31 is arranged in the row direction according to FIG. It has 8 columns that store 4 × 2 bits, and stores 16200 / (4 × 2) bits in the column direction.

  Of the eight columns of the memory 31, the first column write start position is the address 0 position, the second column write start position is the address 0 position, 3 The first column write start position is the address 0, the fourth column write start position is the address 1 position, and the fifth column write start position is the address 7. The position and the start position of writing the sixth column are the position where the address is 20, the start position of the seventh column is the position where the address is 20, and the start position of the eighth column is Addresses are made with 21 positions, respectively.

  When the multiple b is 1 and 64QAM is adopted as a modulation method, for example, when the bit number m of one symbol is 6 bits, the memory 31 is arranged in the row direction according to FIG. It has 6 columns for storing 6 × 1 bits, and stores 16200 / (6 × 1) bits in the column direction.

  Of the six columns of the memory 31, the first column write start position is the address 0 position, the second column write start position is the address 0 position, 3 The start position of the second column is the position where the address is 2, the start position of the fourth column is the position where the address is 3, and the start position of the fifth column is the position where the address is 7. The position and the position at the beginning of writing in the sixth column are set to the position where the address is 7, respectively.

  When the multiple b is 2 and the bit number m of one symbol is 6 bits by adopting, for example, 64QAM as the modulation method, the memory 31 is arranged in the row direction according to FIG. It has 12 columns for storing 6 × 2 bits, and stores 16200 / (6 × 2) bits in the column direction.

  Of the 12 columns of the memory 31, the first column write start position is the address 0 position, the second column write start position is the address 0 position, 3 The start position of the second column is the position where the address is 0, the start position of the fourth column is the position where the address is 2, and the start position of the fifth column is the position where the address is 2. The position of the start position of the 6th column is the position where the address is 2, the start position of the 7th column is the position of the address 3 and the start position of the 8th column is The position where the address is 3 and the start position of the 9th column are the position where the address is 3 and the start position of the 10th column is the position where the address is 6 and the start of writing the 11th column. The position of is the position of address 7 and the 12th column Position of the writing start is set to the position whose address is 7, are respectively.

  When the multiple b is 1 and 256QAM is used as the modulation method, for example, when the bit number m of one symbol is 8 bits, the memory 31 is arranged in the row direction according to FIG. It has 8 columns for storing 8 × 1 bits, and stores 16200 / (8 × 1) bits in the column direction.

  Of the eight columns of the memory 31, the first column write start position is the address 0 position, the second column write start position is the address 0 position, 3 The first column write start position is the address 0, the fourth column write start position is the address 1 position, and the fifth column write start position is the address 7. The position and the start position of writing the sixth column are the position where the address is 20, the start position of the seventh column is the position where the address is 20, and the start position of the eighth column is Addresses are made with 21 positions, respectively.

  When the multiple b is 1 and the bit number m of one symbol is 10 bits by adopting, for example, 1024QAM as a modulation method, the memory 31 is arranged in the row direction according to FIG. It has 10 columns for storing 10 × 1 bits, and stores 16200 / (10 × 1) bits in the column direction.

  Of the ten columns in the memory 31, the first column write start position is the address 0 position, the second column write start position is the address 1 position, 3 The start position of the second column is the position where the address is 2, the start position of the fourth column is the position where the address is 2, and the start position of the fifth column is the position where the address is 3. The position and the start position of the 6th column are the position where the address is 3, the start position of the 7th column is the position where the address is 4 and the start position of the 8th column is The address 4 position, the 9th column write start position are the address 5 position, and the 10th column write start position are the address 7 position.

  When the multiple b is 2 and the number of bits m of one symbol is 10 bits by adopting, for example, 1024QAM as a modulation method, the memory 31 is arranged in the row direction according to FIG. It has 20 columns for storing 10 × 2 bits, and stores 16200 / (10 × 2) bits in the column direction.

  Of the 20 columns in the memory 31, the first column write start position is the address 0 position, the second column write start position is the address 0 position, 3 The start position of the second column is the position where the address is 0, the start position of the fourth column is the position where the address is 2, and the start position of the fifth column is the position where the address is 2. The position and the start position of writing in the sixth column are the position where the address is 2, the start position of writing in the seventh column is the position of address 2 and the starting position of the eighth column is The position where the address is 2 and the start position of writing the ninth column are the position where the address is 5, and the start position of writing the tenth column is the position where the address is 5 and the start of writing the eleventh column. The position of is the position of address 5 and the 12th column The write start position is the position where the address is 5, the write start position of the 13th column is the position where the address is 5, the write start position of the 14th column is the position where the address is 7 and 15 The write start position of the seventh column is the position where the address is 7, the write start position of the 16th column is the position of address 7, and the write start position of the 17th column is the address of 7. The position and the write start position of the 18th column are the position where the address is 8, the write start position of the 19th column is the position of the address 8 and the write start position of the 20th column is Each address is made with 10 positions.

  When the multiple b is 1 and the bit number m of one symbol is 12 bits by adopting 4096QAM as a modulation method, for example, according to FIG. 26, the memory 31 is arranged in the row direction. It has 12 columns for storing 12 × 1 bits, and stores 16200 / (12 × 1) bits in the column direction.

  Of the 12 columns of the memory 31, the first column write start position is the address 0 position, the second column write start position is the address 0 position, 3 The start position of the second column is the position where the address is 0, the start position of the fourth column is the position where the address is 2, and the start position of the fifth column is the position where the address is 2. The position of the start position of the 6th column is the position where the address is 2, the start position of the 7th column is the position of the address 3 and the start position of the 8th column is The position where the address is 3 and the start position of the 9th column are the position where the address is 3 and the start position of the 10th column is the position where the address is 6 and the start of writing the 11th column. The position of is the position of address 7 and the 12th column Position of the writing start is set to the position whose address is 7, are respectively.

  When the multiple b is 2 and, for example, 4096QAM is adopted as the modulation method, and the bit number m of one symbol is 12 bits, the memory 31 is arranged in the row direction according to FIG. It has 24 columns for storing 12 × 2 bits, and stores 16200 / (12 × 2) bits in the column direction.

  Of the 24 columns of the memory 31, the first column write start position is the address 0 position, the second column write start position is the address 0 position, 3 The start position of the second column is the position where the address is 0, the start position of the fourth column is the position where the address is 0, and the start position of the fifth column is the position where the address is 0. The position of the start position of the 6th column is the position where the address is 0, the start position of the 7th column is the position where the address is 0, and the start position of the 8th column is The position where the address is 1 and the start position of writing the ninth column are the position where the address is 1, and the start position of writing the tenth column is the position where the address is 1 and the start of writing the eleventh column. The position of is the position of address 2 and the 12th column The writing start position is the position where the address is 2, the writing start position of the 13th column is the position of address 2, the writing start position of the 14th column is the position of address 3 and 15 The write start position of the 19th column is the position of address 7, the write start position of the 16th column is the position of address 9, and the start position of the 17th column is the address of 9 The position of the 18th column and the start position of the 18th column are the position where the address is 9, the start position of the 19th column is the position of the address 10 and the start position of the 20th column is The position where the address is 10 and the start position of writing in the 21st column are the positions where the address is 10 and the start position of writing in the 22nd column are the positions where the address is 10 and the start of writing in the 23rd column. The position of is the position where the address is 10, The writing starting position for the fourth column is set to the position whose address is 11, are respectively.

  FIG. 27 is a flowchart for explaining processing performed by the LDPC encoder 115, the bit interleaver 116, and the QAM encoder 117 of FIG.

  The LDPC encoder 115 waits for the LDPC target data to be supplied from the BCH encoder 114, encodes the LDPC target data into an LDPC code in step S101, and supplies the LDPC code to the bit interleaver 116. The process proceeds to step S102.

  In step S102, the bit interleaver 116 performs bit interleaving on the LDPC code from the LDPC encoder 115, supplies a symbol obtained by symbolizing the LDPC code after the bit interleaving to the QAM encoder 117, and performs processing. The process proceeds to step S103.

  That is, in step S102, in the bit interleaver 116 (FIG. 9), the parity interleaver 23 performs parity interleaving for the LDPC code from the LDPC encoder 115, and converts the LDPC code after the parity interleaving into the column twist interleave. Supplied to Lever 24.

  The column twist interleaver 24 performs column twist interleaving on the LDPC code from the parity interleaver 23 and supplies it to the demultiplexer 25.

  The demultiplexer 25 replaces the code bits of the LDPC code after the column twist interleaving by the column twist interleaver 24, and performs a replacement process in which the replaced code bits are used as symbol bits of the symbol (bits representing symbols).

  Here, the replacement process by the demultiplexer 25 can be performed according to the first to fourth replacement methods shown in FIGS. 18 and 19 and according to the allocation rule. The allocation rule is a rule for allocating code bits of LDPC codes to symbol bits representing symbols, and details thereof will be described later.

  The symbols obtained by the replacement process by the demultiplexer 25 are supplied from the demultiplexer 25 to the QAM encoder 117.

  In step S103, the QAM encoder 117 maps the symbol from the demultiplexer 25 to a signal point determined by the modulation method of the orthogonal modulation performed by the QAM encoder 117 and performs orthogonal modulation, and the resulting data is converted into a time interleaver. 118.

  As described above, by performing parity interleaving and column twist interleaving, it is possible to improve resistance to erasure and burst errors when transmitting a plurality of code bits of an LDPC code as one symbol.

  Here, in FIG. 9, for convenience of explanation, the parity interleaver 23 that is a block that performs parity interleaving and the column twist interleaver 24 that is a block that performs column twist interleaving are configured separately. The parity interleaver 23 and the column twist interleaver 24 can be integrally configured.

  That is, both parity interleaving and column twist interleaving can be performed by writing and reading code bits to and from the memory, and an address (write address) for writing code bits is an address for reading code bits. It can be represented by a matrix to be converted into (read address).

  Therefore, if a matrix obtained by multiplying a matrix representing parity interleaving and a matrix representing column twist interleaving is obtained, parity interleaving is performed by converting the sign bit by the matrix, and further, the parity. The result of column twist interleaving of the interleaved LDPC code can be obtained.

  In addition to the parity interleaver 23 and the column twist interleaver 24, the demultiplexer 25 can also be configured integrally.

  That is, the replacement process performed by the demultiplexer 25 can also be represented by a matrix that converts the write address of the memory 31 that stores the LDPC code into a read address.

  Therefore, if a matrix obtained by multiplying a matrix representing parity interleaving, a matrix representing column twist interleaving, and a matrix representing replacement processing is obtained, parity interleaving, column twist interleaving, and replacement processing are performed according to the matrix. Can be performed collectively.

  Note that only one of parity interleaving and column twist interleaving can be performed, or neither can be performed.

  Next, simulation for measuring an error rate (bit error rate) performed for the transmission device 11 of FIG. 8 will be described with reference to FIGS.

  The simulation was conducted using a communication path with flutter with a D / U of 0 dB.

  FIG. 28 shows a model of the communication path employed in the simulation.

  That is, FIG. 28A shows a flutter model employed in the simulation.

  Further, B in FIG. 28 shows a model of a communication path with a flutter represented by the model in A in FIG.

In FIG. 28B, H represents the flutter model of A in FIG. In FIG. 28B, N represents ICI (Inter Carrier Interference). In the simulation, the expected value E [N ² ] of the power is approximated by AWGN.

29 and 30, an error rate obtained by the simulation shows the relationship between the Doppler frequency f _d of the flutter.

FIG. 29 shows the relationship between the error rate and the Doppler frequency f _d when the modulation method is 16QAM, the coding rate (r) is (3/4), and the replacement method is the first replacement method. Show. FIG. 30 shows the relationship between the error rate and the Doppler frequency f _d when the modulation method is 64QAM, the coding rate (r) is (5/6), and the replacement method is the first replacement method. Show.

Further, in FIG. 29 and FIG. 30, the thick line indicates the relationship between the error rate and the Doppler frequency f _d when the parity interleaving, the column twist interleaving, and the replacement process are all performed, and the thin line indicates the parity. interleave, column twist interleave and of the replacement process, in the case of performing only the replacement process, shows the relationship between the error rate and the Doppler frequency f _d.

  In any of FIG. 29 and FIG. 30, the error rate is improved (smaller) when parity interleaving, column twist interleaving, and replacement processing are all performed than when only replacement processing is performed. I understand that.

  [Configuration example of LDPC encoder 115]

  FIG. 31 is a block diagram illustrating a configuration example of the LDPC encoder 115 of FIG.

  Note that the LDPC encoder 122 of FIG. 8 is similarly configured.

  As described with reference to FIGS. 12 and 13, the DVB-T.2 standard defines two types of LDPC codes with a code length N of 64800 bits and 16200 bits.

  For LDPC codes having a code length N of 64,800 bits, eleven coding rates 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4 / 5, 5/6, 8/9, and 9/10 are defined, and for LDPC codes with a code length N of 16200 bits, 10 coding rates 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, and 8/9 are defined (FIGS. 12 and 13).

  For example, the LDPC encoder 115 performs encoding (error correction coding) using an LDPC code having a code length N of 64,800 bits or 16200 bits for each code length N and each code rate. This can be performed according to the prepared check matrix H.

  The LDPC encoder 115 includes an encoding processing unit 601 and a storage unit 602.

  The encoding processing unit 601 includes an encoding rate setting unit 611, an initial value table reading unit 612, a parity check matrix generation unit 613, an information bit reading unit 614, an encoded parity calculation unit 615, and a control unit 616, and an LDPC encoder The LDPC encoding of the LDPC target data supplied to 115 is performed, and the resulting LDPC code is supplied to the bit interleaver 116 (FIG. 8).

  That is, the coding rate setting unit 611 sets the code length N and coding rate of the LDPC code in accordance with, for example, an operator operation.

  The initial value table reading unit 612 reads a parity check matrix initial value table, which will be described later, corresponding to the code length N and the coding rate set by the coding rate setting unit 611 from the storage unit 602.

Based on the parity check matrix initial value table read out by the initial value table reading unit 612, the parity check matrix generation unit 613 uses the code length N set by the coding rate setting unit 611 and the information length K (= code) corresponding to the coding rate. 1 element of the information matrix _HA corresponding to the length N-parity length M) is arranged in the column direction at a period of 360 columns (the number of columns P of the unit of the cyclic structure) to generate the check matrix H, and the storage unit Stored in 602.

  The information bit reading unit 614 reads (extracts) information bits for the information length K from the LDPC target data supplied to the LDPC encoder 115.

  The encoded parity calculation unit 615 reads the parity check matrix H generated by the parity check matrix generation unit 613 from the storage unit 602, and uses the parity check matrix H to calculate a parity bit for the information bits read by the information bit reading unit 614, A codeword (LDPC code) is generated by calculating based on the formula.

  The control unit 616 controls each block configuring the encoding processing unit 601.

  The storage unit 602 stores, for example, a plurality of parity check matrix initial value tables corresponding to a plurality of coding rates and the like shown in FIGS. 12 and 13 for code lengths N such as 64800 bits and 16200 bits, respectively. Has been. The storage unit 602 temporarily stores data necessary for the processing of the encoding processing unit 601.

  FIG. 32 is a flowchart for explaining processing of the LDPC encoder 115 of FIG.

  In step S201, the coding rate setting unit 611 determines (sets) a code length N and a coding rate r for performing LDPC coding.

  In step S202, the initial value table reading unit 612 reads, from the storage unit 602, a predetermined parity check matrix initial value table corresponding to the code length N and the coding rate r determined by the coding rate setting unit 611. .

  In step S203, the parity check matrix generation unit 613 uses the parity check matrix initial value table read from the storage unit 602 by the initial value table reading unit 612, and the code length N and the coding rate determined by the coding rate setting unit 611. The parity check matrix H of the LDPC code of r is obtained (generated), supplied to the storage unit 602 and stored.

  In step S204, the information bit reading unit 614 uses the information length K (= N) corresponding to the code length N and the coding rate r determined by the coding rate setting unit 611 from the LDPC target data supplied to the LDPC encoder 115. Xr) information bits are read, and the check matrix H obtained by the check matrix generation unit 613 is read from the storage unit 602 and supplied to the encoded parity calculation unit 615.

  In step S205, the encoded parity calculation unit 615 sequentially calculates the parity bits of the code word c that satisfies Expression (8).

Hc ^T = 0
... (8)

In Expression (8), c represents a row vector as a code word (LDPC code), and c ^T represents transposition of the row vector c.

  Here, as described above, in the row vector c as the LDPC code (one code word), the information bit portion is represented by the row vector A and the parity bit portion is represented by the row vector T. The row vector c can be expressed by the equation c = [A | T] by a row vector A as information bits and a row vector T as parity bits.

And the check matrix H, the row vector c = as LDPC codes | and [A T], it is necessary to satisfy the expression Hc ^T = 0, = such expression Hc ^T = 0 to satisfy the row vector c [A | T] to the row vector T as parity bits which constitute check matrix H = | when [H _a H _T] parity matrix H _T of the parity has a staircase structure shown in FIG. 11, in the formula Hc ^T = 0 By sequentially setting the elements in each row to 0 from the element in the first row of the column vector Hc ^T , it can be obtained sequentially.

  When the encoded parity calculation unit 615 obtains the parity bit T for the information bit A, the coded parity calculation unit 615 converts the code word c = [A | T] represented by the information bit A and the parity bit T to the information bit A. Output as LDPC encoding result.

  Thereafter, in step S206, the control unit 616 determines whether or not to end LDPC encoding. If it is determined in step S206 that the LDPC encoding is not terminated, that is, for example, if there is still LDPC target data to be LDPC encoded, the process returns to step S201 (or step S204). The processing from S201 (or step S204) to S206 is repeated.

  In addition, when it is determined in step S206 that LDPC encoding is to be ended, that is, for example, when there is no LDPC target data to be LDPC encoded, the LDPC encoder 115 ends the processing.

  As described above, a parity check matrix initial value table corresponding to each code length N and each coding rate r is prepared, and the LDPC encoder 115 has a predetermined code length N and a predetermined coding rate r. LDPC encoding is performed using a parity check matrix H generated from a parity check matrix initial value table corresponding to the predetermined code length N and the predetermined coding rate r.

  [Example of parity check matrix initial value table]

The parity check matrix initial value table includes an information matrix H _A corresponding to the code length N of the LDPC code (LDPC code defined by the parity check matrix H) and the information length K of the parity check matrix H (FIG. 10). ) Is a table that represents the position of one element for each 360 columns (number of columns P of cyclic structure units), and is created in advance for each check matrix H of each code length N and each coding rate r.

  FIG. 33 is a diagram illustrating an example of a parity check matrix initial value table.

  That is, FIG. 33 illustrates a parity check matrix initial value table for a parity check matrix H defined in the DVB-T.2 standard and having a code length N of 16200 bits and a coding rate r of 1/4.

  The parity check matrix generation unit 613 (FIG. 31) uses the parity check matrix initial value table to obtain the parity check matrix H as follows.

  That is, FIG. 34 shows a method for obtaining the parity check matrix H from the parity check matrix initial value table.

  Note that the parity check matrix initial value table in FIG. 34 is the parity check matrix initial value for the parity check matrix H defined in the DVB-T.2 standard and having a code length N of 16200 bits and a code rate r of 2/3. Shows the table.

As described above, the parity check matrix initial value table indicates the position of one element of the information matrix H _A (FIG. 10) corresponding to the information length K corresponding to the code length N of the LDPC code and the coding rate r, as 360 columns. This is a table expressed for each (number of columns P of the unit of the cyclic structure), and in the i-th row, the row number of the 1 element of the 1 + 360 × (i−1) -th column of the check matrix H (check matrix H (The row number where the row number of the first row is 0) is arranged by the number of column weights of the 1 + 360 × (i−1) th column.

Here, since the parity matrix H _T (FIG. 10) corresponding to the parity length M of the parity check matrix H is determined as shown in FIG. 21, according to the parity check matrix initial value table, An information matrix H _A (FIG. 10) corresponding to the information length K is obtained.

  The number of rows k + 1 in the parity check matrix initial value table differs depending on the information length K.

  The relationship of Expression (9) is established between the information length K and the number of rows k + 1 in the parity check matrix initial value table.

K = (k + 1) × 360
... (9)

  Here, 360 in Equation (9) is the number of columns P of the unit of the cyclic structure described in FIG.

  In the parity check matrix initial value table of FIG. 34, 13 numerical values are arranged from the first line to the third line, and three values are arranged from the fourth line to the k + 1 line (the 30th line in FIG. 34). Are lined up.

  Therefore, the column weights of the parity check matrix H obtained from the parity check matrix initial value table of FIG. 34 are 13 from the first column to the 1 + 360 × (3-1) −1 column, and 1 + 360 × (3-1) It is 3 from the column to the Kth column.

  The first row of the parity check matrix initial value table in FIG. 34 is 0,2084,1613,1548,1286,1460,3196,4297,2481,3369,3451,4620,2622, which is the parity check matrix H In the first column, the row number is 0,2084,1613,1548,1286,1460,3196,4297,2481,3369,3451,4620,2622, and the element of the row is 1 (and other elements) Is 0).

  34 is 1,122,1516,3448,2880,1407,1847,3799,3529,373,971,4358,3108, which is 361 of the parity check matrix H. In the (= 1 + 360 × (2-1)) column, the row number is 1,122,1516,3448,2880,1407,1847,3799,3529,373,971,4358,3108, indicating that the element is 1 ing.

As described above, the parity check matrix initial value table represents the position of one element of the information matrix _HA of the parity check matrix H for every 360 columns.

  Columns other than the 1 + 360 × (i-1) -th column of the parity check matrix H, that is, each column from the 2 + 360 × (i-1) -th column to the 360 × i-th column is a parity check matrix initial value table. The 1 element in the 1 + 360 × (i−1) th column determined by is arranged cyclically and cyclically downward (downward in the column) according to the parity length M.

  That is, for example, the 2 + 360 × (i-1) column is the 1 + 360 × (i-1) column cyclically shifted downward by M / 360 (= q). The next 3 + 360 × (i-1) column is the 1 + 360 × (i-1) column cyclically shifted downward by 2 × M / 360 (= 2 × q) ( 2 + 360 × (i-1) column is cyclically shifted downward by M / 360 (= q)).

The numerical value of the i-th row (i-th from the top) and j-th column (j-th from the left) of the parity check matrix initial value table is represented as h _{i, j} and j items in the w-th column of the parity check matrix H. If the row number of the first element is represented as H _wj , the row number H of the first element in the w column, which is a column other than the 1 + 360 × (i−1) column of the parity check matrix H _wj can be obtained by Expression (10).

H _wj = mod {h _{i, j} + mod ((w-1), P) × q, M)
... (10)

  Here, mod (x, y) means a remainder obtained by dividing x by y.

  Further, P is the number of columns in the unit of the cyclic structure described above. For example, in the DVB-T.2 standard, P is 360 as described above. Further, q is a value M / 360 obtained by dividing the parity length M by the number of columns P (= 360) in the unit of the cyclic structure.

  The parity check matrix generation unit 613 (FIG. 31) specifies the row number of the 1 element in the 1 + 360 × (i−1) column of the parity check matrix H by using the parity check matrix initial value table.

Further, the parity check matrix generation unit 613 (FIG. 31) _calculates the row number H _wj of the first element of the w column that is a column other than the 1 + 360 × (i−1) column of the parity check matrix H by the formula ( 10) to generate a parity check matrix H in which the element of the row number obtained as described above is 1.

  [LDPC code with code length N of 4320 bits]

  By the way, if digital broadcasting for mobile terminals can be performed without changing the specifications of transmitters and receivers compliant with DVB-T.2 which is a standard for digital broadcasting for fixed terminals, it will be cost effective. This is advantageous.

  However, in DVB-T.2, LDPC codes having a code length N of 64 k bits and 16 k bits are defined, but LDPC codes having a code length shorter than that are not defined.

  On the other hand, since the LDPC code with a short code length can reduce the memory and delay required when decoding the LDPC code, compared with the LDPC code with a long code length, in digital broadcasting for mobile terminals, May be effective.

  Therefore, in the transmission apparatus 11 (FIG. 7), an LDPC code having a code length shorter than the LDPC code (code length N is 64 kbit and 16 kbit LDPC code) stipulated in DVB-T.2 is used for portable terminals. Digital broadcasting for portable terminals can be performed using the LDPC code for digital broadcasting (hereinafter also referred to as portable LDPC code).

For portable LDPC codes, the parity of parity check matrix H is the same as for LDPC codes specified in DVB-T.2, from the viewpoint of maintaining compatibility with DVB-T.2 as much as possible. The matrix H _T has a staircase structure (FIG. 11).

Furthermore, for portable LDPC codes, the information matrix _HA of the parity check matrix H has a cyclic structure, and the number of columns P of the cyclic structure unit is 360 as in the LDPC code defined in DVB-T.2. And

  In addition, the code length N of the portable LDPC code is shorter than the LDPC code specified in DVB-T.2, and is cyclic (similar to the LDPC code specified in DVB-T.2). For example, 4320 bits (hereinafter also referred to as 4k bits), which is a multiple of the number of columns P of the unit of the structure, is adopted.

  FIGS. 35 to 43 are diagrams illustrating examples of the parity check matrix initial value table of the (portable) LDPC code having the code length N of 4k bits as described above.

  35 shows a parity check matrix initial value table for a parity check matrix H having a code length N of 4k bits and a coding rate r of 1/4.

  FIG. 36 illustrates a parity check matrix initial value table for a parity check matrix H having a code length N of 4k bits and a code rate r of 1/3.

  FIG. 37 illustrates a parity check matrix initial value table for a parity check matrix H having a code length N of 4k bits and a code rate r of 5/12.

  FIG. 38 shows a parity check matrix initial value table for a parity check matrix H having a code length N of 4k bits and a code rate r of 1/2.

  FIG. 39 illustrates a parity check matrix initial value table for a parity check matrix H having a code length N of 4k bits and a code rate r of 7/12.

  FIG. 40 illustrates a parity check matrix initial value table for a parity check matrix H having a code length N of 4k bits and a code rate r of 2/3.

  FIG. 41 illustrates a parity check matrix initial value table for a parity check matrix H having a code length N of 4k bits and a code rate r of 3/4.

  FIG. 42 illustrates a parity check matrix initial value table for a parity check matrix H having a code length N of 4k bits and a code rate r of 5/6.

  FIG. 43 shows a parity check matrix initial value table for a parity check matrix H having a code length N of 4k bits and an encoding rate r of 11/12.

  The LDPC encoder 115 (FIGS. 8 and 31) uses a parity check matrix H obtained from the parity check matrix initial value table shown in FIGS. 35 to 43 for digital broadcasting for mobile terminals, and a code length N is 4k bits. The coding rate r is 1/4, 1/3, 5/12, 1/2, 7/12, 2/3, 3/4, 5/6, and 11/12 Encode to any LDPC code.

  The LDPC code obtained by using the parity check matrix H obtained from the parity check matrix initial value table of FIGS. 35 to 43 is a high-performance LDPC code.

  Here, a high-performance LDPC code is an LDPC code obtained from an appropriate parity check matrix H.

Also, an appropriate parity check matrix H is an LDPC code obtained from the parity check matrix H with a low E _s / N ₀ (signal power to noise power ratio per symbol) or E _b / N _o (per bit). This is a parity check matrix that satisfies a predetermined condition for making BER (Bit Error Rate) smaller when transmitted at a signal power to noise power ratio.

An appropriate parity check matrix H can be obtained, for example, by performing a simulation for measuring the BER when LDPC codes obtained from various parity check matrices satisfying a predetermined condition are transmitted at low E _s / N _o .

  The predetermined conditions that the appropriate check matrix H should satisfy are, for example, that the analysis result obtained by the code performance analysis method called Density Evolution is good, and that one element called cycle 4 There are no loops, etc.

Here, in the information matrix H _A , it is known that if one element is dense as in the cycle 4, the decoding performance of the LDPC code is deteriorated. Therefore, the appropriate check matrix H is satisfied. It is required that cycle 4 does not exist as a predetermined condition.

  Note that the predetermined condition to be satisfied by an appropriate parity check matrix H can be appropriately determined from the viewpoint of improving the decoding performance of the LDPC code, facilitating (simplifying) the decoding process of the LDPC code, and the like.

  44 and 45 are diagrams for explaining density evolution that provides an analysis result as a predetermined condition that should be satisfied by an appropriate check matrix H. FIG.

  Density evolution is a code analysis method that calculates the expected value of the error probability for the entire LDPC code (ensemble) whose code length N is ∞ characterized by the degree sequence described later. It is.

  For example, on an AWGN channel, when the noise variance is increased from 0, the expected value of the error probability of a certain ensemble is initially 0, but the noise variance is greater than a certain threshold. Then, it is not 0.

  According to Density Evolution, the expected value of the error probability is not zero, and the threshold of noise variance (hereinafter also referred to as performance threshold) is compared to determine whether the ensemble performance (appropriateness of the check matrix) is good or bad. Can be decided.

  Note that if an ensemble to which the LDPC code belongs is determined for a specific LDPC code and density evolution is performed on the ensemble, the rough performance of the LDPC code can be predicted.

  Accordingly, if an LDPC code having good performance is found, an ensemble having good performance can be found from among LDPC codes belonging to the ensemble.

  Here, the above-described degree sequence represents the ratio of variable nodes and check nodes having weights of each value to the code length N of the LDPC code.

  For example, a regular (3,6) LDPC code with a coding rate of 1/2 is a degree in which the weights (column weights) of all variable nodes are 3 and the weights (row weights) of all check nodes are 6. Belongs to an ensemble characterized by a sequence.

  FIG. 44 shows a Tanner graph of such an ensemble.

  In the Tanner Bluff of FIG. 44, there are only N variable nodes indicated by circles (◯) in the figure, which are equal to the code length N, and check nodes indicated by squares (□) in the figure are encoded at the code length N. There are only N / 2 equal to the product of multiplication by 1/2.

  Each variable node is connected with three edges equal to the column weight. Therefore, there are only 3N branches connected to the N variable nodes.

  Each check node is connected with 6 branches equal to the row weight. Therefore, there are only 3N branches connected to N / 2 check nodes.

  Furthermore, in the Tanner graph of FIG. 44, there is one interleaver.

  The interleaver randomly reorders 3N branches connected to N variable nodes, and reorders each of the rearranged branches into 3N branches connected to N / 2 check nodes. Connect to one of them.

  There are (3N)! (= (3N) × (3N-1) × ・ ・ ・ × 1) rearrangement patterns for rearranging 3N branches connected to N variable nodes in the interleaver. There are only. Therefore, an ensemble characterized by a degree sequence where all variable nodes have a weight of 3 and all check nodes have a weight of 6 is a set of (3N)! LDPC codes.

  In the simulation for obtaining a high-performance LDPC code (appropriate parity check matrix), a multi-edge type ensemble was used in the density evolution.

  In the multi-edge type, the interleaver through which the branch connected to the variable node and the branch connected to the check node pass is divided into multiple edges, which makes the ensemble more characterized. Strictly done.

  FIG. 45 shows an example of a Tanner graph of a multi-edge type ensemble.

  In the Tanner graph of FIG. 45, there are two interleavers, a first interleaver and a second interleaver.

  In the Tanner graph of FIG. 45, there is one branch connected to the first interleaver, only one v1 variable node having zero branches connected to the second interleaver, and one branch connected to the first interleaver. , There are only 2 variable nodes with 2 branches connected to the second interleaver, 0 branches with the 1st interleaver, v3 branches with 2 branches connected to the 2nd interleaver, Exists.

  Furthermore, in the Tanner graph of FIG. 45, there are two branches connected to the first interleaver, c1 check nodes with 0 branches connected to the second interleaver, and two branches connected to the first interleaver. The number of branches connected to the second interleaver is c2 check nodes, the number of branches connected to the first interleaver is 0, and the number of branches connected to the second interleaver is c3. Exists.

  Here, for density evolution and its implementation, for example, "On the Design of Low-Density Parity-Check Codes within 0.0045 dB of the Shannon Limit", SYChung, GDForney, TJRichardson, R.Urbanke, IEEE Communications Leggers, VOL.5, NO.2, Feb 2001.

In the simulation for obtaining the portable LDPC code (its check matrix initial value table) of FIGS. 35 to 43, the performance threshold value is E _b / N ₀ where the BER begins to drop (becomes smaller) due to multi-edge type density evolution. Finds an ensemble that falls below a predetermined value, and from among the LDPC codes belonging to that ensemble, the performance of an LDPC code that reduces the BER in multiple modulation schemes used in digital broadcasting for mobile terminals, such as 16QAM and 64QAM, Selected as a good LDPC code.

  Here, as described above, in digital broadcasting for mobile terminals, 4k bits whose code length N is shorter than the LDPC code (LDPC code whose code length N is 16k and 64k bits) defined in DVB-T.2. This LDPC code is less resistant to errors in the communication channel 13 (FIG. 7) than an LDPC code having a long code length N defined in DVB-T.2.

  Therefore, in digital broadcasting for portable terminals, in order to improve tolerance to errors, a modulation method with a relatively small number of signal points, such as QPSK, 16QAM, and 64QAM, is employed.

  35 to 43 described above are parity check matrix initial value tables of LDPC codes having a code length N of 4k bits, which are obtained by the above simulation.

  46, the code length N of FIGS. 35 to 43 is 4k bits, and the coding rate r is 1/4, 1/3, 5/12, 1/2, 7/12, 2/3, 3 /. It is a figure which shows the minimum cycle length and performance threshold value of the parity check matrix H calculated | required from the parity check matrix initial value table of nine types of LDPC codes of 4, 5/6, and 11/12.

  Of the parity check matrix H obtained from the parity check matrix initial value table of FIG. 35 to FIG. 43, the minimum cycle length of the parity check matrix H whose coding rate r is 1/4 and 1/3 is 8 cycles. The minimum cycle length of the parity check matrix H with r = 5/12, 1/2, 7/12, 2/3, 3/4, 5/6, and 11/12 is 6 cycles.

  Therefore, cycle 4 does not exist in parity check matrix H obtained from the parity check matrix initial value tables of FIGS.

  Further, since the redundancy of the LDPC code increases as the encoding rate r decreases, the performance threshold increases (becomes smaller) as the encoding rate r decreases.

  FIG. 47 is a diagram for explaining the parity check matrix H (obtained from the parity check matrix initial value table) of FIGS. 35 to 43 (hereinafter also referred to as the parity check matrix H of the portable LDPC code).

  For the KX column from the first column of the check matrix H of the portable LDPC code, the column weight is X, the column weight is Y for the subsequent KY column, and the column weight is M for the subsequent M-1 column. For the last one column, the column weight is 1, respectively.

  Here, KX + KY + M-1 + 1 is equal to the code length N = 4320 bits.

  FIG. 48 shows each coding rate r (= 1/4, 1/3, 5/12, 1/2, 7/12, 2/3, 3/4, 5/6, 11 / of the portable LDPC code. It is a figure which shows the column numbers KX, KY, and M and column weight X and Y about 12).

  For a parity check matrix H of a portable LDPC code having a code length N of 4k, as in the parity check matrix defined in DVB-T.2 described in FIGS. The column weight tends to be large, and therefore, the first code bit of the portable LDPC code tends to be more resistant to errors (resistant to errors).

  [Column twist interleaving of LDPC code with code length N of 4320 bits]

  In LDPC encoder 115 (FIG. 8, FIG. 31), when performing LDPC encoding to a portable LDPC code using parity check matrix H (determined from the parity check matrix initial value table) shown in FIGS. In the column twist interleave as the rearrangement process performed by the column twist interleaver 24 (FIG. 9), the write start position of each column (FIG. 24) of the memory 31 is defined in DVB-T.2. This is different from the writing start position in the case of the existing LDPC code (FIGS. 25 and 26).

  FIG. 49 is a diagram showing the number of columns of the memory 31 necessary for column twist interleaving and the address of the writing start position for the portable LDPC code.

  That is, in FIG. 49, the code length N of FIGS. 35 to 43 is 4k bits, and the coding rate r is 1/4, 1/3, 5/12, 1/2, 7/12, 2/3, Number of columns in memory 31 required for column twist interleaving for 9 types of portable LDPC codes (obtained from parity check matrix H obtained from parity check matrix initial value table) of 9/4, 5/6, and 11/12 And the address of the writing start position are shown for each modulation method.

  For portable LDPC codes, as described above, QPSK, 16QAM, and 64QAM, which have a relatively small number of signal points, are employed as modulation schemes.

  When the multiple b is 1 and QPSK is adopted as the modulation method, when the bit number m of one symbol is 2 bits, the memory 31 stores 2 × 1 bits in the row direction 2 It has N columns, and stores N / (mb) = 4320 / (2 × 1) bits in the column direction.

  Of the two columns in the memory 31, the write start position of the first column is the position where the address is 0, and the write start position of the second column is the position where the address is 2. Is done.

  When the multiple b is 2 and QPSK is adopted as the modulation method, when the bit number m of one symbol is 2 bits, the memory 31 stores 2 × 2 bits in the row direction 4 It has N columns and stores N / (mb) = 4320 / (2 × 2) bits in the column direction.

  Of the four columns in the memory 31, the first column write start position is the address 0 position, the second column write start position is the address 0 position, 3 The write start position of the second column is the position where the address is 1, and the write start position of the fourth column is the position where the address is 0.

  When the multiple b is 1 and 16QAM is adopted as the modulation method, when the bit number m of one symbol is 4 bits, the memory 31 stores 4 × 1 bits in the row direction 4 It has N columns and stores N / (mb) = 4320 / (4 × 1) bits in the column direction.

  The write start position of each of the four columns in the memory 31 is the same as when the multiple b is 2 and QPSK is adopted as the modulation method.

  That is, of the four columns of the memory 31, the first column write start position is the address 0 position, the second column write start position is the address 0 position, 3 The write start position of the second column is the position where the address is 1, and the write start position of the fourth column is the position where the address is 0.

  When the multiple b is 2 and 16QAM is adopted as the modulation method, when the bit number m of one symbol is 4 bits, the memory 31 stores 4 × 2 bits in the row direction 8 It has N columns and stores N / (mb) = 4320 / (4 × 2) bits in the column direction.

  Of the eight columns of the memory 31, the first column write start position is the address 0 position, the second column write start position is the address 8 position, 3 The first column write position is the address 10 position, the fourth column write start position is the address 10 position, and the fifth column write start position is the address 25. The position and the start position of writing the sixth column are the position where the address is 54, the start position of the seventh column is the position where the address is 62, and the start position of the eighth column is Each address is made 69 positions.

  When the multiple b is 1 and 64QAM is adopted as the modulation method, when the bit number m of one symbol is 6 bits, the memory 31 stores 6 × 1 bits in the row direction 6 It has N columns, and stores N / (mb) = 4320 / (6 × 1) bits in the column direction.

  Of the six columns of the memory 31, the first column write start position is the address 0 position, the second column write start position is the address 0 position, 3 The start position of the first column is the position where the address is 1, the start position of the fourth column is the position where the address is 1, and the start position of the fifth column is the address where the address is 0. The position and the position at the beginning of writing in the sixth column are set as the position where the address is 0, respectively.

  When the multiple b is 2 and 64QAM is used as a modulation method, for example, when the bit number m of one symbol is 6 bits, the memory 31 is arranged in the row direction according to FIG. It has 12 columns for storing 6 × 2 bits, and stores 4320 / (6 × 2) bits in the column direction.

  Of the twelve columns in the memory 31, the first column write start position is the address 0 position, the second column write start position is the address 2 position, 3 The first column write position is the address 10 position, the fourth column write start position is the address 12 position, the fifth column start position is the address 15 The position and the start position of writing in the sixth column are the position where the address is 17, the start position of writing in the seventh column is the position where the address is 20, and the starting position of the eighth column is The position of address 21 and the start position of writing the ninth column are the position of address 23 and the start position of the tenth column are the position of address 25 and the start of writing the eleventh column. The position of the address is 26 and the 12th position The writing starting position for the ram is set to the position whose address is 30, are respectively.

  For the portable LDPC code having a code length N of 4k bits in FIGS. 35 to 43, by performing column twist interleaving as described above, a plurality of variables corresponding to a plurality of variable nodes connected to the same check node are performed. It is possible to avoid the sign bit from being one symbol of QPSK, 16QAM, or 64QAM (contained in the same symbol), and as a result, the decoding performance in a channel with an erasure can be improved. Can be improved.

  FIG. 50 is a diagram illustrating a BER simulation result when column twist interleaving is performed on a portable LDPC code.

  The simulation assumes a communication channel (channel) in which Rayleigh fading with an erasure probability of symbol loss of 0.167 is assumed, and a portable LDPC code has a code length N of 4k bits and a coding rate of 2/3 LDPC code (FIG. 40) and QPSK as a modulation method.

In FIG. 50, the horizontal axis represents E _s / N ₀ (signal power to noise power ratio per symbol), and the vertical axis represents BER.

  In FIG. 50, the solid line represents the BER when both parity interleaving and column twist interleaving are performed, and the dotted line represents the BER when parity interleaving is performed and column twist interleaving is not performed.

  According to FIG. 50, when column twist interleaving is performed, the overall BER is improved as compared with the case where column twist interleaving is not performed, and therefore, the tolerance to errors is improved. I understand.

  [Replacement processing of LDPC code with code length N of 4320 bits]

  In digital broadcasting for portable terminals, when a portable LDPC code having a short code length N, that is, an LDPC code having a code length N of 4k bits as described above, is used, an error occurs in the communication path 13 (FIG. 7). Resistance to is reduced.

  Therefore, in digital broadcasting for portable terminals, it is desirable to take measures to improve resistance to errors.

  As measures for improving the tolerance against errors, as described above, in addition to a method employing a modulation method with a relatively small number of signal points, such as 16QAM or 64QAM, for example, a demultiplexer 25 (FIG. 9). There is a replacement process performed in.

  In the replacement process, for example, the above-described first to fourth replacement methods, DVB-T.2 and the like can be used as the replacement method for replacing the code bits of the LDPC code defined in the DVB-T.2 standard. There is a replacement method defined in the standard, but when digital broadcasting for mobile terminals is performed by the above-described LDPC code (portable LDPC code) with a code length N of 4k bits, the code length N is 4k. It is necessary to adopt a replacement process suitable for the LDPC code of bits.

  Furthermore, it is desirable to employ a replacement process of a method that further improves tolerance to errors as the replacement process employed for an LDPC code having a code length N of 4k bits.

  Therefore, as described with reference to FIG. 27, the demultiplexer 25 (FIG. 9) can perform the replacement process according to the assignment rule.

  Hereinafter, the replacement process according to the allocation rule will be described, but before that, the replacement process by the already proposed replacement method (hereinafter also referred to as the current method) will be described.

  Referring to FIG. 51 and FIG. 52, it is assumed that the demultiplexer 25 performs a replacement process on the LDPC code defined in DVB-T.2 etc. (hereinafter also referred to as a defined code) in the current method. In this case, the replacement process will be described.

  FIG. 51 shows an example of replacement processing of the current method when the LDPC code is an LDPC code defined in DVB-T.2 and having a code length N of 64,800 bits and a coding rate of 3/5. Show.

  That is, A in FIG. 51 is an LDPC code in which the code length N is 64800 bits, the coding rate is 3/5, the modulation method is 16QAM, and the multiple b is 2. An example of the replacement process of the current method is shown.

  When the modulation scheme is 16QAM, 4 (= m) bits of the code bit are mapped as one symbol to any one of 16 signal points defined by 16QAM.

  Furthermore, when the code length N is 64800 bits and the multiple b is 2, the memory 31 (FIGS. 18 and 19) of the demultiplexer 25 stores 8 × 4 (= mb) bits in the row direction. It has a column and stores 64800 / (4 × 2) bits in the column direction.

  In the demultiplexer 25, the code bit of the LDPC code is written in the column direction of the memory 31, and when the writing of the 64800-bit code bit (one code word) is completed, the code bit written in the memory 31 is changed in the row direction. , 4 × 2 (= mb) bits, and supplied to the replacement unit 32 (FIGS. 18 and 19).

The exchanging unit 32 converts the 4 × 2 (= mb) code bits b ₀ , b ₁ , b ₂ , b ₃ , b ₄ , b ₅ , b ₆ , b ₇ read from the memory 31 into, for example, FIG. 4 × 2 (= mb) symbol bits y ₀ , y ₁ , y ₂ , y ₃ , y ₄ , y ₅ , y ₆ , of 2 (= b) consecutive symbols The code bits b ₀ to b ₇ of 4 × 2 (= mb) bits are switched so as to be assigned to y ₇ .

That is, the replacement unit 32
Sign bit b ₀ to symbol bit y ₇
Sign bit b ₁ to symbol bit y ₁
Sign bit b ₂ to symbol bit y ₄
Sign bit b ₃ to symbol bit y ₂
Sign bit b ₄ to symbol bit y ₅
Sign bit b ₅ to symbol bit y ₃
Sign bit b ₆ into symbol bit y ₆
The sign bit b ₇ to the symbol bit y ₀
Replace each assigned.

  51B shows the current scheme when the LDPC code is a defined code with a code length N of 64,800 bits and a coding rate of 3/5, and the modulation scheme is 64QAM and the multiple b is 2. Shows an example of the replacement process.

  When the modulation scheme is 64QAM, 6 (= m) bits of code bits are mapped as one symbol to any one of 64 signal points defined by 64QAM.

  Further, when the code length N is 64800 bits and the multiple b is 2, the memory 31 (FIGS. 18 and 19) of the demultiplexer 25 stores 12 × 6 (= mb) bits in the row direction. It has a column and stores 64800 / (6 × 2) bits in the column direction.

  In the demultiplexer 25, the code bit of the LDPC code is written in the column direction of the memory 31, and when the writing of the 64800-bit code bit (one code word) is completed, the code bit written in the memory 31 is changed in the row direction. , 6 × 2 (= mb) bits, and supplied to the replacement unit 32 (FIGS. 18 and 19).

The replacement unit 32 reads 6 × 2 (= mb) code bits b ₀ , b ₁ , b ₂ , b ₃ , b ₄ , b ₅ , b ₆ , b ₇ , b ₈ , b ₉ read from the memory 31. , b ₁₀ , b ₁₁ are, for example, 6 × 2 (= mb) symbol bits y ₀ , y ₁ , y ₂ , of 2 (= b) consecutive symbols as shown in FIG. The code bits b ₀ to b ₁₁ of 6 × 2 (= mb) bits are switched so as to be assigned to y ₃ , y ₄ , y ₅ , y ₆ , y ₇ , y ₈ , y ₉ , y ₁₀ , y ₁₁ .

That is, the replacement unit 32
Sign bit b ₀ to symbol bit y ₁₁
Sign bit b ₁ to symbol bit y ₇
Sign bit b ₂ to symbol bit y ₃
Sign bit b ₃ to symbol bit y ₁₀
Sign bit b ₄ to symbol bit y ₆
Sign bit b ₅ to symbol bit y ₂
Sign bit b ₆ to symbol bit y ₉
Sign bit b ₇ to symbol bit y ₅
Sign bit b ₈ to symbol bit y ₁
Sign bit b ₉ to symbol bit y ₈
Sign bit b ₁₀ to symbol bit y ₄
The sign bit b ₁₁ to the symbol bit y ₀
Replace each assigned.

  51C shows the current scheme when the LDPC code is a defined code with a code length N of 64,800 bits and a coding rate of 3/5, and the modulation scheme is 256QAM and the multiple b is 2. Shows an example of the replacement process.

  When the modulation scheme is 256QAM, 8 (= m) bits of code bits are mapped as one symbol to any one of 256 signal points defined by 256QAM.

  Furthermore, when the code length N is 64800 bits and the multiple b is 2, the memory 31 (FIGS. 18 and 19) of the demultiplexer 25 stores 16 × 8 (= mb) bits in the row direction. It has a column and stores 64800 / (8 × 2) bits in the column direction.

  In the demultiplexer 25, the code bit of the LDPC code is written in the column direction of the memory 31, and when the writing of the 64800-bit code bit (one code word) is completed, the code bit written in the memory 31 is changed in the row direction. , 8 × 2 (= mb) bits, and supplied to the replacement unit 32 (FIGS. 18 and 19).

The replacement unit 32 reads 8 × 2 (= mb) bits of code bits b ₀ , b ₁ , b ₂ , b ₃ , b ₄ , b ₅ , b ₆ , b ₇ , b ₈ , b ₉ read from the memory 31. , b ₁₀ , b ₁₁ , b ₁₂ , b ₁₃ , b ₁₄ , b ₁₅ , for example, as shown in C of FIG. 51, 8 × 2 (= mb) bits of 2 (= b) consecutive symbols symbol bit y _{0 of, y 1, y 2, y} 3, y 4, y 5, y 6, y 7, y 8, y 9, y 10, y 11, y 12, y 13, y 14, y 15 The code bits b ₀ to b ₁₅ of 8 × 2 (= mb) bits are switched so as to be assigned to.

That is, the replacement unit 32
Sign bit b ₀ to symbol bit y ₁₅
Sign bit b ₁ to symbol bit y ₁
Sign bit b ₂ into symbol bit y ₁₃
Sign bit b ₃ to symbol bit y ₃
Sign bit b ₄ to symbol bit y ₈
Sign bit b ₅ to symbol bit y ₁₁
Sign bit b ₆ to symbol bit y ₉
Sign bit b ₇ to symbol bit y ₅
Sign bit b ₈ to symbol bit y ₁₀
Sign bit b ₉ to symbol bit y ₆
Sign bit b ₁₀ to symbol bit y ₄
Sign bit b ₁₁ to symbol bit y ₇
Sign bit b ₁₂ into symbol bit y ₁₂
The sign bit b ₁₃ into the symbol bit y ₂
Sign bit b ₁₄ into symbol bit y ₁₄
The sign bit b ₁₅ to the symbol bit y ₀
Replace each assigned.

  FIG. 52 shows an example of the current system replacement process when the LDPC code is a defined code having a code length N of 16200 bits and an encoding rate of 3/5.

  That is, A in FIG. 52 is an LDPC code in which the LDPC code is an LDPC code having a code length N of 16200 bits and a coding rate of 3/5, and further, the modulation scheme is 16QAM and the multiple b is 2. An example of the replacement process of the current method is shown.

  When the modulation scheme is 16QAM, 4 (= m) bits of the code bit are mapped as one symbol to any one of 16 signal points defined by 16QAM.

  Further, when the code length N is 16200 bits and the multiple b is 2, the memory 31 (FIGS. 18 and 19) of the demultiplexer 25 stores 8 × 4 (= mb) bits in the row direction. It has a column and stores 16200 / (4 × 2) bits in the column direction.

  In the demultiplexer 25, the code bit of the LDPC code is written in the column direction of the memory 31, and when the writing of the 16200-bit code bit (one code word) is completed, the code bit written in the memory 31 is changed in the row direction. , 4 × 2 (= mb) bits, and supplied to the replacement unit 32 (FIGS. 18 and 19).

The replacement unit 32 converts the 4 × 2 (= mb) code bits b ₀ , b ₁ , b ₂ , b ₃ , b ₄ , b ₅ , b ₆ , b ₇ read from the memory 31 into, for example, FIG. 4 × 2 (= mb) symbol bits y ₀ , y ₁ , y ₂ , y ₃ , y ₄ , y ₅ , y ₆ , of 2 (= b) consecutive symbols The code bits b ₀ to b ₇ of 4 × 2 (= mb) bits are switched so as to be assigned to y ₇ .

That is, the replacement unit 32 performs replacement to assign the code bits b ₀ to b ₇ to the symbol bits y ₀ to y ₇ as in the case of A in FIG.

  52B shows an LDPC code in which the code length N is 16200 bits, the code rate is 3/5, the code is 3/5, the modulation method is 64QAM, and the multiple b is 2. Shows an example of the replacement process.

  When the modulation scheme is 64QAM, 6 (= m) bits of code bits are mapped as one symbol to any one of 64 signal points defined by 64QAM.

  Further, when the code length N is 16200 bits and the multiple b is 2, the memory 31 (FIGS. 18 and 19) of the demultiplexer 25 stores 12 × 6 (= mb) bits in the row direction. It has a column and stores 16200 / (6 × 2) bits in the column direction.

  In the demultiplexer 25, the code bit of the LDPC code is written in the column direction of the memory 31, and when the writing of the 16200-bit code bit (one code word) is completed, the code bit written in the memory 31 is changed in the row direction. , 6 × 2 (= mb) bits, and supplied to the replacement unit 32 (FIGS. 18 and 19).

The replacement unit 32 reads 6 × 2 (= mb) code bits b ₀ , b ₁ , b ₂ , b ₃ , b ₄ , b ₅ , b ₆ , b ₇ , b ₈ , b ₉ read from the memory 31. , b ₁₀ , b ₁₁ are represented by 6 × 2 (= mb) symbol bits y ₀ , y ₁ , y ₂ , of 2 (= b) consecutive symbols, for example, as shown in FIG. The code bits b ₀ to b ₁₁ of 6 × 2 (= mb) bits are switched so as to be assigned to y ₃ , y ₄ , y ₅ , y ₆ , y ₇ , y ₈ , y ₉ , y ₁₀ , y ₁₁ .

That is, the replacement unit 32 performs the replacement for assigning the code bits b ₀ to b ₁₁ to the symbol bits y ₀ to y ₁₁ as in the case of B in FIG. 51 described above.

  52C shows an LDPC code in which the code length N is 16200 bits and the coding rate is 3/5, the modulation method is 256QAM, and the multiple b is 1. An example of a replacement process is shown.

  When the modulation scheme is 256QAM, 8 (= m) bits of code bits are mapped as one symbol to any one of 256 signal points defined by 256QAM.

  Further, when the code length N is 16200 bits and the multiple b is 1, the memory 31 (FIGS. 18 and 19) of the demultiplexer 25 stores 8 × 1 (= mb) bits in the row direction. It has a column and stores 16200 / (8 × 1) bits in the column direction.

  In the demultiplexer 25, the code bit of the LDPC code is written in the column direction of the memory 31, and when the writing of the 16200-bit code bit (one code word) is completed, the code bit written in the memory 31 is changed in the row direction. , 8 × 1 (= mb) bits, and supplied to the replacement unit 32 (FIGS. 18 and 19).

The exchanging unit 32 converts the 8 × 1 (= mb) code bits b ₀ , b ₁ , b ₂ , b ₃ , b ₄ , b ₅ , b ₆ , b ₇ read from the memory 31 into, for example, FIG. As shown in C, 8 × 1 (= mb) symbol bits y ₀ , y ₁ , y ₂ , y ₃ , y ₄ , y ₅ , y ₆ , y _{7 of} 1 (= b) symbols The code bits b ₀ to b ₇ of 8 × 1 (= mb) bits are switched so as to be assigned to.

That is, the replacement unit 32
Sign bit b ₀ to symbol bit y ₇
Sign bit b ₁ to symbol bit y ₃
Sign bit b ₂ to symbol bit y ₁
Sign bit b ₃ to symbol bit y ₅
Sign bit b ₄ to symbol bit y ₂
Sign bit b ₅ to symbol bit y ₆
Sign bit b ₆ to symbol bit y ₄
The sign bit b ₇ to the symbol bit y ₀
Replace each assigned.

  Next, a replacement process according to the allocation rule (hereinafter also referred to as a replacement process in the new replacement method) will be described.

  In digital broadcasting for mobile terminals, modulation schemes such as QPSK with fewer signal points, 16QAM, 64QAM, etc. are adopted. Here, each of the modulation schemes is 16QAM and 64QAM. The new replacement method will be described.

When the modulation method is QPSK, the 2-bit symbol bits y ₀ and y ₁ representing the four symbols (signal points) of QPSK do not have superiority or inferiority to the error described with reference to FIGS. Therefore, it is not necessary to perform the replacement process (the resistance to errors does not change even if the replacement process is performed).

  53 to 55 are diagrams for explaining the new replacement method.

  In the new replacement method, the replacement unit 32 of the demultiplexer 25 performs replacement of code bits of mb bits according to a predetermined allocation rule.

  The allocation rule is a rule for allocating code bits of LDPC codes to symbol bits. In the allocation rule, a group set that is a combination of a code bit group of a code bit and a symbol bit group of a symbol bit to which a code bit of the code bit group is allocated, and each of the code bit group and the symbol bit group of the group set The number of code bits and the number of symbol bits (hereinafter also referred to as the number of group bits) are defined.

  Here, as described above, the code bit has a difference in error probability, and the symbol bit also has a difference in error probability. The code bit group is a group that groups the code bits according to the error probability, and the symbol bit group is a group that groups the symbol bits according to the error probability.

  FIG. 53 shows a code bit when the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 1/4, and further having a modulation scheme of 64QAM and a multiple b of 2. A group and a symbol bit group are shown.

  In this case, 6 × 2 (= mb) code bits read from the memory 31 are divided into three code bit groups Gb1, Gb2, and Gb3 as shown in FIG. Can be grouped.

  Here, the code bit group Gb # i is a group having a good (small) error probability of code bits belonging to the code bit group Gb # i as the suffix #i is smaller.

  In the following description, the # i + 1 bit from the most significant bit of the mb code bit read out from the memory 31 in the row direction is also expressed as bit b # i, and mb of consecutive b symbols. The # i + 1 bit from the most significant bit of the bit symbols is also expressed as bit y # i.

  In A of FIG. 53, the sign bit group Gb1 includes the sign bit b0, the sign bit group Gb2 includes the sign bits b1 and b2, and the sign bit group Gb3 includes the sign bits b3, b4, b5, b6, b7. , b8, b9, b10, b11 belong respectively.

  When the modulation scheme is 64QAM and the multiple b is 2, symbol bits of 6 × 2 (= mb) bits are divided into three symbol bit groups as shown in FIG. 53B according to the difference in error probability. Can be grouped into Gy1, Gy2, Gy3.

  Here, similarly to the code bit group, the symbol bit group Gy # i is a group having a better error probability of the symbol bits belonging to the symbol bit group Gy # i as the suffix #i is smaller.

  In B of FIG. 53, symbol bit group Gy1 includes symbol bits y0, y1, y6, and y7, symbol bit group Gy2 includes symbol bits y2, y3, y8, and y9, and symbol bit group Gy3 includes symbols. Bits y4, y5, y10, and y11 belong to each.

  FIG. 54 shows an allocation rule when the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 1/4, and further, the modulation method is 64QAM and the multiple b is 2. Is shown.

  54, the combination of the code bit group Gb1 and the symbol bit group Gy3 is defined as one group set. The number of group bits of the group set is defined as 1 bit.

  Hereinafter, the group set and the number of group bits are collectively referred to as group set information. Then, for example, the group set of the sign bit group Gb1 and the symbol bit group Gy3 and 1 bit that is the number of group bits of the group set are described as group set information (Gb1, Gy3, 1).

  54, in addition to group set information (Gb1, Gy3, 1), group set information (Gb2, Gy3, 2), (Gb3, Gy3, 1), (Gb3, Gy2, 4), (Gb3, Gy1,4) is specified.

  For example, the group set information (Gb1, Gy3, 1) means that one bit of the code bit belonging to the code bit group Gb1 is assigned to one bit of the symbol bit belonging to the symbol bit group Gy3.

Therefore, in the assignment rule of FIG.
According to the group set information (Gb1, Gy3, 1), 1 bit of the code bit of the code bit group Gb1 having the highest error probability is assigned to 1 bit of the symbol bit of the symbol bit group Gy3 having the third highest error probability. thing,
According to the group set information (Gb2, Gy3, 2), 2 bits of the code bit group Gb2 having the second highest error probability are allocated to 2 bits of the symbol bit group Gy3 having the third highest error probability. thing,
According to the group set information (Gb3, Gy3, 1), one bit of the sign bit of the code bit group Gb3 having the third highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy3 having the third highest error probability. thing,
According to the group set information (Gb3, Gy2, 4), 4 bits of the code bit of the code bit group Gb3 having the third highest error probability are allocated to 4 bits of the symbol bit of the symbol bit group Gy2 having the second highest error probability. thing,
And, according to the group set information (Gb3, Gy1, 4), the 4 bits of the sign bit of the code bit group Gb3 with the third highest error probability and the 4 bits of the symbol bits of the symbol bit group Gy1 with the best error probability It is stipulated to be assigned to

  As described above, the code bit group is a group that groups the code bits according to the error probability, and the symbol bit group is a group that groups the symbol bits according to the error probability. Therefore, it can be said that the allocation rule defines a combination of an error probability of a code bit and an error probability of a symbol bit to which the code bit is allocated.

  As described above, the allocation rule that defines the combination of the error probability of the code bit and the error probability of the symbol bit to which the code bit is assigned is, for example, an error resistance (resistance to noise) by simulation or the like that measures BER. Determined to be better.

  Note that even if the code bit allocation destination of a certain code bit group is changed in the bits of the same symbol bit group, the tolerance against errors is not (almost) affected.

  Therefore, in order to improve tolerance to errors, the group set information that minimizes the BER (Bit Error Rate), that is, the code bit group of the code bit and the symbol bit group of the symbol bit to which the code bit of the code bit group is assigned And the number of sign bits and the number of symbol bits (number of group bits) of each group bit set (group set) and the symbol bit group of the group set are defined as allocation rules. The code bits may be exchanged so that the code bits are assigned to the symbol bits.

  However, it is necessary to determine in advance between the transmission device 11 and the reception device 12 (FIG. 7) how to assign which code bit to which symbol bit according to the allocation rule.

  FIG. 55 shows an example of exchanging code bits according to the assignment rule of FIG.

  That is, A in FIG. 55 is a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 1/4, and the modulation method is 64QAM and the multiple b is 2. 54 shows a first example of code bit replacement according to the allocation rule of FIG.

  When the LDPC code is a portable LDPC code with a code length N of 4320 bits and a coding rate of 1/4, and further when the modulation method is 64QAM and the multiple b is 2, the demultiplexer 25 uses the column direction × The sign bit written in the memory 31 with (4320 / (6 × 2)) × (6 × 2) bits in the row direction is read in 6 × 2 (= mb) bits and replaced in the row direction It is supplied to the unit 32 (FIGS. 18 and 19).

  The replacement unit 32, according to the allocation rule of FIG. 54, generates 2 (= b) code bits b0 to b11 of 6 × 2 (= mb) bits read from the memory 31, for example, as shown in A of FIG. The 6 × 2 (= mb) code bits b0 to b11 are switched so as to be assigned to 6 × 2 (= mb) symbol bits y0 to y11.

That is, the replacement unit 32
Sign bit b0 to symbol bit y11
Sign bit b1 to symbol bit y10,
Sign bit b2 to symbol bit y4,
Sign bit b3 into symbol bit y5
Sign bit b4 to symbol bit y2
Sign bit b5 to symbol bit y3,
Sign bit b6 to symbol bit y8
Sign bit b7 to symbol bit y9,
Sign bit b8 to symbol bit y6,
Sign bit b9 into symbol bit y7
Sign bit b10 to symbol bit y1
Sign bit b11 to symbol bit y0,
Replace each assigned.

  FIG. 55B shows a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 1/4, and further, when the modulation scheme is 64QAM and the multiple b is 2. 54 shows a second example of code bit replacement according to the assignment rule of FIG.

According to B of FIG. 55, the replacement unit 32 follows the allocation rules of FIG. 54 for the 6 × 2 (= mb) bits of code bits b0 to b11 read from the memory 31.
Sign bit b0 to symbol bit y11
Sign bit b1 to symbol bit y10,
Sign bit b2 to symbol bit y4,
Sign bit b3 into symbol bit y5
Sign bit b4 to symbol bit y9,
Sign bit b5 to symbol bit y8
Sign bit b6 to symbol bit y3,
Sign bit b7 to symbol bit y2
Sign bit b8 to symbol bit y0,
Sign bit b9 to symbol bit y1,
Sign bit b10 into symbol bit y6,
Sign bit b11 to symbol bit y7
Replace each assigned.

  Here, the method of allocating the sign bit b # i to the symbol bit y # i shown in A of FIG. 55 and B of FIG. 55 follows the allocation rule of FIG. 54 (observing the allocation rule). ing).

  FIG. 56 shows a code bit when the LDPC code is a portable LDPC code having a code length N of 4320 bits and an encoding rate of 1/3, and further having a modulation scheme of 64QAM and a multiple b of 2. A group and a symbol bit group are shown.

  In this case, 6 × 2 (= mb) code bits read from the memory 31 are divided into three code bit groups Gb1, Gb2, and Gb3 as shown in FIG. 56A according to the difference in error probability. Can be grouped.

  In FIG. 56A, code bit b0 belongs to code bit group Gb1, code bits b1 to b3 belong to code bit group Gb2, and code bits b4 to b11 belong to code bit group Gb3.

  When the modulation method is 64QAM and the multiple b is 2, symbol bits of 6 × 2 (= mb) bits are divided into three symbol bit groups as shown in FIG. 56B according to the difference in error probability. Can be grouped into Gy1, Gy2, Gy3.

  In B of FIG. 56, similarly to B of FIG. 53, symbol bit group Gy1 includes symbol bits y0, y1, y6, and y7, and symbol bit group Gy2 includes symbol bits y2, y3, y8, and y9. Symbol bits y4, y5, y10, and y11 belong to the symbol bit group Gy3, respectively.

  FIG. 57 shows an allocation rule when the LDPC code is a portable LDPC code having a code length N of 4320 bits and an encoding rate of 1/3, and further, when the modulation scheme is 64QAM and the multiple b is 2. Is shown.

  57, the group set information (Gb1, Gy1, 1), (Gb2, Gy3, 2), (Gb2, Gy1, 1), (Gb3, Gy3, 2), (Gb3, Gy2, 4), (Gb3, Gy1, 2) is specified.

That is, in the allocation rule of FIG.
According to the group set information (Gb1, Gy1, 1), one bit of the code bit of the code bit group Gb1 having the highest error probability is allocated to one bit of the symbol bit of the symbol bit group Gy1 having the highest error probability. about,
According to the group set information (Gb2, Gy3, 2), 2 bits of the code bit group Gb2 having the second highest error probability are allocated to 2 bits of the symbol bit group Gy3 having the third highest error probability. thing,
According to the group set information (Gb2, Gy1, 1), one bit of the sign bit of the code bit group Gb2 having the second highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy1 having the best error probability. thing,
According to the group set information (Gb3, Gy3, 2), 2 bits of the sign bit group Gb3 having the third highest error probability are allocated to 2 bits of the symbol bit group Gy3 having the third highest error probability. thing,
According to the group set information (Gb3, Gy2, 4), 4 bits of the code bit of the code bit group Gb3 having the third highest error probability are allocated to 4 bits of the symbol bit of the symbol bit group Gy2 having the second highest error probability. thing,
And, according to the group set information (Gb3, Gy1, 2), 2 bits of the sign bit of the code bit group Gb3 having the third highest error probability, and 2 bits of the symbol bits of the symbol bit group Gy1 having the best error probability It is stipulated to be assigned to

  FIG. 58 shows an example of exchanging code bits according to the assignment rule of FIG.

  That is, A in FIG. 58 is a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and an encoding rate of 1/3, and further, the modulation method is 64QAM and the multiple b is 2. 57 shows a first example of exchanging code bits in accordance with the allocation rule of FIG.

  When the LDPC code is a portable LDPC code having a code length N of 4320 bits and an encoding rate of 1/3, and further when the modulation method is 64QAM and the multiple b is 2, the demultiplexer 25 uses the column direction × The sign bit written in the memory 31 with (4320 / (6 × 2)) × (6 × 2) bits in the row direction is read in 6 × 2 (= mb) bits and replaced in the row direction It is supplied to the unit 32 (FIGS. 18 and 19).

  In accordance with the allocation rule of FIG. 57, the replacement unit 32 generates 2 (= b) code bits b0 to b11 of 6 × 2 (= mb) bits read from the memory 31, for example, as shown in A of FIG. The 6 × 2 (= mb) code bits b0 to b11 are switched so as to be assigned to 6 × 2 (= mb) symbol bits y0 to y11.

That is, the replacement unit 32
Sign bit b0 to symbol bit y0,
The sign bit b1 is changed to the symbol bit y11.
Sign bit b2 to symbol bit y1,
Sign bit b3 into symbol bit y10,
Sign bit b4 to symbol bit y4,
Sign bit b5 to symbol bit y8
Sign bit b6 to symbol bit y2
Sign bit b7 to symbol bit y9,
Sign bit b8 to symbol bit y3,
Sign bit b9 into symbol bit y7
Sign bit b10 to symbol bit y5
Sign bit b11 to symbol bit y6,
Replace each assigned.

  58B shows a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 1/3, and further when the modulation method is 64QAM and the multiple b is 2. 57 shows a second example of code bit replacement according to the allocation rule of FIG.

According to B of FIG. 58, the replacement unit 32 follows the allocation rule of FIG. 57 for the code bits b0 to b11 of 6 × 2 (= mb) bits read from the memory 31.
Sign bit b0 to symbol bit y0,
Sign bit b1 to symbol bit y10,
Sign bit b2 to symbol bit y1,
Sign bit b3 to symbol bit y11,
Sign bit b4 to symbol bit y5
Sign bit b5 to symbol bit y3,
Sign bit b6 to symbol bit y9,
Sign bit b7 to symbol bit y2
Sign bit b8 to symbol bit y8,
Sign bit b9 to symbol bit y6,
Sign bit b10 into symbol bit y4,
Sign bit b11 to symbol bit y7
Replace each assigned.

  FIG. 59 shows a code bit when the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 5/12, and further having a modulation scheme of 64QAM and a multiple b of 2. A group and a symbol bit group are shown.

  In this case, 6 × 2 (= mb) code bits read from the memory 31 are divided into three code bit groups Gb1, Gb2, and Gb3 as shown in FIG. 59A according to the difference in error probability. Can be grouped.

  In FIG. 59A, code bit b0 belongs to code bit group Gb1, code bits b1 to b4 belong to code bit group Gb2, and code bits b5 to b11 belong to code bit group Gb3.

  When the modulation scheme is 64QAM and the multiple b is 2, 6 × 2 (= mb) bit symbol bits are divided into three symbol bit groups as shown in FIG. 59B according to the difference in error probability. Can be grouped into Gy1, Gy2, Gy3.

  In B of FIG. 59, similarly to B of FIG. 53, the symbol bit group Gy1 includes symbol bits y0, y1, y6, and y7, and the symbol bit group Gy2 includes symbol bits y2, y3, y8, and y9. Symbol bits y4, y5, y10, and y11 belong to the symbol bit group Gy3, respectively.

  FIG. 60 shows an allocation rule when the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 5/12, and further, the modulation method is 64QAM and the multiple b is 2. Is shown.

  In the allocation rule of FIG. 60, group set information (Gb1, Gy1, 1), (Gb2, Gy3, 3), (Gb2, Gy1, 1), (Gb3, Gy2, 4), (Gb3, Gy1, 2), (Gb3, Gy3, 1) is defined.

That is, in the allocation rule of FIG.
According to the group set information (Gb1, Gy1, 1), one bit of the code bit of the code bit group Gb1 having the highest error probability is allocated to one bit of the symbol bit of the symbol bit group Gy1 having the highest error probability. about,
According to the group set information (Gb2, Gy3, 3), 3 bits of the code bit of the code bit group Gb2 having the second highest error probability are allocated to 3 bits of the symbol bit of the symbol bit group Gy3 having the third highest error probability. thing,
According to the group set information (Gb2, Gy1, 1), one bit of the sign bit of the code bit group Gb2 having the second highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy1 having the best error probability. thing,
According to the group set information (Gb3, Gy2, 4), 4 bits of the code bit of the code bit group Gb3 having the third highest error probability are allocated to 4 bits of the symbol bit of the symbol bit group Gy2 having the second highest error probability. thing,
According to the group set information (Gb3, Gy1, 2), 2 bits of the code bit of the code bit group Gb3 having the third highest error probability are allocated to 2 bits of the symbol bit of the symbol bit group Gy1 having the best error probability. thing,
Also, according to the group set information (Gb3, Gy3, 1), 1 bit of the sign bit of the code bit group Gb3 having the third highest error probability and 1 bit of the symbol bit of the symbol bit group Gy3 having the third highest error probability It is stipulated to be assigned to

  FIG. 61 shows an example of exchanging code bits according to the allocation rule of FIG.

  That is, A in FIG. 61 is a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 5/12, and further, the modulation method is 64QAM and the multiple b is 2. 60 shows a first example of code bit replacement according to the allocation rule of FIG.

  When the LDPC code is a portable LDPC code having a code length N of 4320 bits and an encoding rate of 5/12, and further when the modulation method is 64QAM and the multiple b is 2, the demultiplexer 25 uses the column direction × The sign bit written in the memory 31 with (4320 / (6 × 2)) × (6 × 2) bits in the row direction is read in 6 × 2 (= mb) bits and replaced in the row direction It is supplied to the unit 32 (FIGS. 18 and 19).

  In accordance with the allocation rule of FIG. 60, the replacement unit 32 generates 2 (= b) code bits b0 to b11 of 6 × 2 (= mb) bits read from the memory 31, for example, as shown in A of FIG. The 6 × 2 (= mb) code bits b0 to b11 are switched so as to be assigned to 6 × 2 (= mb) symbol bits y0 to y11.

That is, the replacement unit 32
Sign bit b0 to symbol bit y0,
The sign bit b1 is changed to the symbol bit y11.
Sign bit b2 to symbol bit y1,
Sign bit b3 into symbol bit y10,
Sign bit b4 to symbol bit y4,
Sign bit b5 to symbol bit y8
Sign bit b6 to symbol bit y2
Sign bit b7 to symbol bit y9,
Sign bit b8 to symbol bit y3,
Sign bit b9 into symbol bit y7
Sign bit b10 to symbol bit y5
Sign bit b11 to symbol bit y6,
Replace each assigned.

  FIG. 61B shows a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 5/12, and further, when the modulation scheme is 64QAM and the multiple b is 2. 60 shows a second example of code bit replacement according to the allocation rule of FIG.

According to B of FIG. 61, the replacement unit 32 follows the allocation rules of FIG. 60 for the 6 × 2 (= mb) bit code bits b0 to b11 read from the memory 31.
Sign bit b0 to symbol bit y0,
Sign bit b1 into symbol bit y4
Sign bit b2 to symbol bit y1,
Sign bit b3 to symbol bit y11,
Sign bit b4 to symbol bit y10,
Sign bit b5 to symbol bit y3,
Sign bit b6 to symbol bit y9,
Sign bit b7 to symbol bit y2
Sign bit b8 to symbol bit y8,
Sign bit b9 to symbol bit y6,
Sign bit b10 to symbol bit y5
Sign bit b11 to symbol bit y7
Replace each assigned.

  FIG. 62 shows a code bit when the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 1/2, and a modulation scheme of 64QAM and a multiple b of 2. A group and a symbol bit group are shown.

  In this case, 6 × 2 (= mb) code bits read from the memory 31 are divided into three code bit groups Gb1, Gb2, Gb3 as shown in FIG. Can be grouped.

  In FIG. 62A, code bit group Gb1 includes code bit b0, code bit group Gb2 includes code bits b1 to b5, and code bit group Gb3 includes code bits b6 to b11.

  When the modulation scheme is 64QAM and the multiple b is 2, 6 × 2 (= mb) bit symbol bits are divided into three symbol bit groups as shown in FIG. Can be grouped into Gy1, Gy2, Gy3.

  In B of FIG. 62, symbol bits y0, y1, y6, and y7 are included in symbol bit group Gy1, and symbol bits y2, y3, y8, and y9 are included in symbol bit group Gy2, as in B of FIG. Symbol bits y4, y5, y10, and y11 belong to the symbol bit group Gy3, respectively.

  FIG. 63 shows an allocation rule when the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 1/2, and further, when the modulation scheme is 64QAM and the multiple b is 2. Is shown.

  63, group set information (Gb1, Gy1, 1), (Gb2, Gy1, 3), (Gb2, Gy1, 1), (Gb2, Gy2, 1), (Gb3, Gy2, 3), (Gb3, Gy1, 2) and (Gb3, Gy3, 1) are defined.

That is, in the allocation rule of FIG.
According to the group set information (Gb1, Gy1, 1), one bit of the code bit of the code bit group Gb1 having the highest error probability is allocated to one bit of the symbol bit of the symbol bit group Gy1 having the highest error probability. about,
According to the group set information (Gb2, Gy3, 3), 3 bits of the code bit of the code bit group Gb2 having the second highest error probability are allocated to 3 bits of the symbol bit of the symbol bit group Gy3 having the third highest error probability. thing,
According to the group set information (Gb2, Gy1, 1), one bit of the sign bit of the code bit group Gb2 having the second highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy1 having the best error probability. thing,
According to the group set information (Gb2, Gy2, 1), one bit of the sign bit of the code bit group Gb2 having the second highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy2 having the second highest error probability. thing,
According to the group set information (Gb3, Gy2, 3), 3 bits of the code bit of the code bit group Gb3 having the third highest error probability are allocated to 3 bits of the symbol bit of the symbol bit group Gy2 having the second highest error probability. thing,
According to the group set information (Gb3, Gy1, 2), 2 bits of the code bit of the code bit group Gb3 having the third highest error probability are allocated to 2 bits of the symbol bit of the symbol bit group Gy1 having the best error probability. thing,
Also, according to the group set information (Gb3, Gy3, 1), 1 bit of the sign bit of the code bit group Gb3 having the third highest error probability and 1 bit of the symbol bit of the symbol bit group Gy3 having the third highest error probability It is stipulated to be assigned to

  FIG. 64 shows an example of exchanging code bits according to the allocation rule of FIG.

  That is, A in FIG. 64 is a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 1/2, and further, the modulation method is 64QAM and the multiple b is 2. 63 shows a first example of exchanging code bits in accordance with the allocation rule of FIG.

  When the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 1/2, and further when the modulation method is 64QAM and the multiple b is 2, the demultiplexer 25 uses the column direction × The sign bit written in the memory 31 with (4320 / (6 × 2)) × (6 × 2) bits in the row direction is read in 6 × 2 (= mb) bits and replaced in the row direction It is supplied to the unit 32 (FIGS. 18 and 19).

  The replacement unit 32, according to the allocation rule of FIG. 63, generates 2 (= b) code bits b0 to b11 of 6 × 2 (= mb) bits read from the memory 31, for example, as shown in A of FIG. The 6 × 2 (= mb) code bits b0 to b11 are switched so as to be assigned to 6 × 2 (= mb) symbol bits y0 to y11.

That is, the replacement unit 32
Sign bit b0 to symbol bit y0,
The sign bit b1 is changed to the symbol bit y11.
Sign bit b2 to symbol bit y1,
Sign bit b3 into symbol bit y10,
Sign bit b4 to symbol bit y4,
Sign bit b5 to symbol bit y8
Sign bit b6 to symbol bit y2
Sign bit b7 to symbol bit y9,
Sign bit b8 to symbol bit y3,
Sign bit b9 into symbol bit y7
Sign bit b10 to symbol bit y5
Sign bit b11 to symbol bit y6,
Replace each assigned.

  64B shows a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 1/2, and further, when the modulation scheme is 64QAM and the multiple b is 2. 63 shows a second example of code bit replacement according to the assignment rule of FIG.

According to B in FIG. 64, the replacement unit 32 follows the allocation rules in FIG. 63 for the 6 × 2 (= mb) bit code bits b0 to b11 read from the memory 31.
Sign bit b0 to symbol bit y0,
Sign bit b1 into symbol bit y4
Sign bit b2 to symbol bit y1,
Sign bit b3 to symbol bit y11,
Sign bit b4 to symbol bit y10,
Sign bit b5 to symbol bit y8
Sign bit b6 to symbol bit y9,
Sign bit b7 to symbol bit y2
Sign bit b8 to symbol bit y3,
Sign bit b9 into symbol bit y7
Sign bit b10 to symbol bit y5
Sign bit b11 to symbol bit y6,
Replace each assigned.

  FIG. 65 shows a code bit when the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 7/12, and further the modulation method is 64QAM and the multiple b is 2. A group and a symbol bit group are shown.

  In this case, 6 × 2 (= mb) code bits read from the memory 31 are divided into three code bit groups Gb1, Gb2, and Gb3 as shown in FIG. Can be grouped.

  In FIG. 65A, code bit group Gb1 includes code bit b0, code bit group Gb2 includes code bits b1 to b6, and code bit group Gb3 includes code bits b7 to b11.

  When the modulation scheme is 64QAM and the multiple b is 2, 6 × 2 (= mb) bit symbol bits are divided into three symbol bit groups as shown in FIG. Can be grouped into Gy1, Gy2, Gy3.

  In B of FIG. 65, similarly to B of FIG. 53, symbol bit group Gy1 includes symbol bits y0, y1, y6, and y7, and symbol bit group Gy2 includes symbol bits y2, y3, y8, and y9. Symbol bits y4, y5, y10, and y11 belong to the symbol bit group Gy3, respectively.

  FIG. 66 shows an allocation rule when the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 7/12, and further the modulation scheme is 64QAM and the multiple b is 2. Is shown.

  66, group set information (Gb1, Gy1, 1), (Gb2, Gy3, 3), (Gb2, Gy1, 1), (Gb2, Gy2, 2), (Gb3, Gy2, 2), (Gb3, Gy1, 2) and (Gb3, Gy3, 1) are defined.

That is, in the allocation rule of FIG.
According to the group set information (Gb1, Gy1, 1), one bit of the code bit of the code bit group Gb1 having the highest error probability is allocated to one bit of the symbol bit of the symbol bit group Gy1 having the highest error probability. about,
According to the group set information (Gb2, Gy3, 3), 3 bits of the code bit of the code bit group Gb2 having the second highest error probability are allocated to 3 bits of the symbol bit of the symbol bit group Gy3 having the third highest error probability. thing,
According to the group set information (Gb2, Gy1, 1), one bit of the sign bit of the code bit group Gb2 having the second highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy1 having the best error probability. thing,
According to the group set information (Gb2, Gy2, 2), 2 bits of the code bit of the code bit group Gb2 having the second highest error probability are allocated to 2 bits of the symbol bit of the symbol bit group Gy2 having the second highest error probability. thing,
According to the group set information (Gb3, Gy2, 2), 2 bits of the code bit of the code bit group Gb3 having the third highest error probability are allocated to 2 bits of the symbol bit of the symbol bit group Gy2 having the second highest error probability. thing,
According to the group set information (Gb3, Gy1, 2), 2 bits of the code bit of the code bit group Gb3 having the third highest error probability are allocated to 2 bits of the symbol bit of the symbol bit group Gy1 having the best error probability. thing,
Also, according to the group set information (Gb3, Gy3, 1), 1 bit of the sign bit of the code bit group Gb3 having the third highest error probability and 1 bit of the symbol bit of the symbol bit group Gy3 having the third highest error probability It is stipulated to be assigned to

  FIG. 67 shows an example of exchanging code bits according to the allocation rule of FIG.

  That is, A in FIG. 67 is a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 7/12, and further, the modulation method is 64QAM and the multiple b is 2. 66 shows a first example of exchanging code bits in accordance with the allocation rule of FIG.

  When the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 7/12, and further when the modulation method is 64QAM and the multiple b is 2, the demultiplexer 25 uses the column direction × The sign bit written in the memory 31 with (4320 / (6 × 2)) × (6 × 2) bits in the row direction is read in 6 × 2 (= mb) bits and replaced in the row direction It is supplied to the unit 32 (FIGS. 18 and 19).

  In accordance with the allocation rule of FIG. 66, the replacement unit 32 generates 2 (= b) code bits b0 to b11 of 6 × 2 (= mb) bits read from the memory 31, for example, as shown in A of FIG. The 6 × 2 (= mb) code bits b0 to b11 are switched so as to be assigned to 6 × 2 (= mb) symbol bits y0 to y11.

That is, the replacement unit 32
Sign bit b0 to symbol bit y0,
The sign bit b1 is changed to the symbol bit y11.
Sign bit b2 to symbol bit y1,
Sign bit b3 into symbol bit y10,
Sign bit b4 to symbol bit y4,
Sign bit b5 to symbol bit y8
Sign bit b6 to symbol bit y2
Sign bit b7 to symbol bit y9,
Sign bit b8 to symbol bit y3,
Sign bit b9 into symbol bit y7
Sign bit b10 to symbol bit y5
Sign bit b11 to symbol bit y6,
Replace each assigned.

  FIG. 67B shows a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 7/12, and further, when the modulation scheme is 64QAM and the multiple b is 2. 66 shows a second example of exchanging code bits according to the allocation rule of FIG.

According to B of FIG. 67, the replacement unit 32 follows the allocation rules of FIG. 66 for the 6 × 2 (= mb) bits of code bits b0 to b11 read from the memory 31.
Sign bit b0 to symbol bit y0,
Sign bit b1 into symbol bit y4
Sign bit b2 to symbol bit y1,
Sign bit b3 to symbol bit y11,
Sign bit b4 to symbol bit y10,
Sign bit b5 to symbol bit y2
Sign bit b6 to symbol bit y8
Sign bit b7 to symbol bit y3,
Sign bit b8 to symbol bit y9,
Sign bit b9 into symbol bit y7
Sign bit b10 to symbol bit y5
Sign bit b11 to symbol bit y6,
Replace each assigned.

  FIG. 68 shows a code bit when the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 2/3, and further, when the modulation scheme is 64QAM and the multiple b is 2. A group and a symbol bit group are shown.

  In this case, 6 × 2 (= mb) code bits read out from the memory 31 are divided into three code bit groups Gb1, Gb2, and Gb3 as shown in FIG. Can be grouped.

  In FIG. 68A, code bit b0 belongs to code bit group Gb1, code bits b1 to b7 belong to code bit group Gb2, and code bits b8 to b11 belong to code bit group Gb3.

  When the modulation scheme is 64QAM and the multiple b is 2, symbol bits of 6 × 2 (= mb) bits are divided into three symbol bit groups as shown in FIG. 68B according to the difference in error probability. Can be grouped into Gy1, Gy2, Gy3.

  In B of FIG. 68, similarly to B of FIG. 53, symbol bit group Gy1 includes symbol bits y0, y1, y6, and y7, and symbol bit group Gy2 includes symbol bits y2, y3, y8, and y9. Symbol bits y4, y5, y10, and y11 belong to the symbol bit group Gy3, respectively.

  FIG. 69 shows an allocation rule when the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 2/3, and further, the modulation scheme is 64QAM and the multiple b is 2. Is shown.

  69, group set information (Gb1, Gy2, 1), (Gb2, Gy2, 1), (Gb2, Gy3, 3), (Gb2, Gy1, 3), (Gb3, Gy3, 1), (Gb3, Gy2, 2) and (Gb3, Gy1, 1) are defined.

That is, in the allocation rule of FIG.
According to the group set information (Gb1, Gy2, 1), 1 bit of the code bit of the code bit group Gb1 having the first highest error probability is assigned to 1 bit of the symbol bit of the symbol bit group Gy2 having the second highest error probability. thing,
According to the group set information (Gb2, Gy2, 1), one bit of the sign bit of the code bit group Gb2 having the second highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy2 having the second highest error probability. thing,
According to the group set information (Gb2, Gy3, 3), 3 bits of the code bit of the code bit group Gb2 having the second highest error probability are allocated to 3 bits of the symbol bit of the symbol bit group Gy3 having the third highest error probability. thing,
According to the group set information (Gb2, Gy1, 3), 3 bits of the sign bit of the code bit group Gb2 with the second highest error probability are assigned to 3 bits of the symbol bit of the symbol bit group Gy1 with the best error probability. thing,
According to the group set information (Gb3, Gy3, 1), one bit of the sign bit of the code bit group Gb3 having the third highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy3 having the third highest error probability. thing,
According to the group set information (Gb3, Gy2, 2), 2 bits of the code bit of the code bit group Gb3 having the third highest error probability are allocated to 2 bits of the symbol bit of the symbol bit group Gy2 having the second highest error probability. thing,
Also, according to the group set information (Gb3, Gy1, 1), 1 bit of the sign bit of the code bit group Gb3 having the third highest error probability and 1 bit of the symbol bit of the symbol bit group Gy1 having the highest error probability It is stipulated to be assigned to

  FIG. 70 shows an example of exchanging code bits according to the assignment rule of FIG.

  That is, A in FIG. 70 is a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 2/3, and further, the modulation method is 64QAM and the multiple b is 2. 69 shows a first example of code bit replacement according to the allocation rule of FIG.

  When the LDPC code is a portable LDPC code having a code length N of 4320 bits and an encoding rate of 2/3, and further when the modulation method is 64QAM and the multiple b is 2, the demultiplexer 25 uses the column direction × The sign bit written in the memory 31 with (4320 / (6 × 2)) × (6 × 2) bits in the row direction is read in 6 × 2 (= mb) bits and replaced in the row direction It is supplied to the unit 32 (FIGS. 18 and 19).

  In accordance with the allocation rule of FIG. 69, the replacement unit 32 generates 2 (= b) code bits b0 to b11 of 6 × 2 (= mb) bits read from the memory 31, for example, as shown in A of FIG. The 6 × 2 (= mb) code bits b0 to b11 are switched so as to be assigned to 6 × 2 (= mb) symbol bits y0 to y11.

That is, the replacement unit 32
Sign bit b0 to symbol bit y2
Sign bit b1 into symbol bit y8
Sign bit b2 to symbol bit y5
Sign bit b3 to symbol bit y11,
Sign bit b4 to symbol bit y0,
Sign bit b5 to symbol bit y6,
Sign bit b6 to symbol bit y1
Sign bit b7 to symbol bit y10
Sign bit b8 to symbol bit y4,
Sign bit b9 to symbol bit y9,
Sign bit b10 to symbol bit y3,
Sign bit b11 to symbol bit y7
Replace each assigned.

  FIG. 70B shows a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and an encoding rate of 2/3, and further, when the modulation scheme is 64QAM and the multiple b is 2. 69 shows a second example of code bit replacement according to the allocation rule of FIG. 69.

According to B of FIG. 70, the replacement unit 32 follows the allocation rule of FIG.
Sign bit b0 to symbol bit y2
Sign bit b1 into symbol bit y8
Sign bit b2 to symbol bit y11
Sign bit b3 into symbol bit y5
Sign bit b4 to symbol bit y0,
Sign bit b5 to symbol bit y6,
Sign bit b6 to symbol bit y1
Sign bit b7 to symbol bit y10
Sign bit b8 to symbol bit y4,
Sign bit b9 to symbol bit y3,
Sign bit b10 into symbol bit y9,
Sign bit b11 to symbol bit y7
Replace each assigned.

  FIG. 71 shows a code bit when the LDPC code is a portable LDPC code with a code length N of 4320 bits and a coding rate of 3/4, and further, the modulation scheme is 64QAM and the multiple b is 2. A group and a symbol bit group are shown.

  In this case, 6 × 2 (= mb) code bits read from the memory 31 are divided into three code bit groups Gb1, Gb2, and Gb3 as shown in FIG. 71A according to the difference in error probability. Can be grouped.

  In A of FIG. 71, code bit b0 belongs to code bit group Gb1, code bits b1 to b8 belong to code bit group Gb2, and code bits b9 to b11 belong to code bit group Gb3.

  When the modulation method is 64QAM and the multiple b is 2, 6 × 2 (= mb) bit symbol bits are divided into three symbol bit groups as shown in FIG. Can be grouped into Gy1, Gy2, Gy3.

  In B of FIG. 71, similarly to B of FIG. 53, symbol bit group Gy1 includes symbol bits y0, y1, y6, and y7, and symbol bit group Gy2 includes symbol bits y2, y3, y8, and y9. Symbol bits y4, y5, y10, and y11 belong to the symbol bit group Gy3, respectively.

  FIG. 72 shows an allocation rule when the LDPC code is a portable LDPC code with a code length N of 4320 bits and a coding rate of 3/4, and further, the modulation scheme is 64QAM and the multiple b is 2. Is shown.

  72, the group set information (Gb1, Gy2, 1), (Gb2, Gy2, 1), (Gb2, Gy3,4), (Gb2, Gy1, 3), (Gb3, Gy2, 2), (Gb3, Gy1, 1) is defined.

That is, in the allocation rule of FIG.
According to the group set information (Gb1, Gy2, 1), 1 bit of the code bit of the code bit group Gb1 having the first highest error probability is assigned to 1 bit of the symbol bit of the symbol bit group Gy2 having the second highest error probability. thing,
According to the group set information (Gb2, Gy2, 1), one bit of the sign bit of the code bit group Gb2 having the second highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy2 having the second highest error probability. thing,
According to the group set information (Gb2, Gy3,4), 4 bits of code bits of the code bit group Gb2 having the second highest error probability are allocated to 4 bits of symbol bits of the symbol bit group Gy3 having the third highest error probability. thing,
According to the group set information (Gb2, Gy1, 3), 3 bits of the sign bit of the code bit group Gb2 with the second highest error probability are assigned to 3 bits of the symbol bit of the symbol bit group Gy1 with the best error probability. thing,
According to the group set information (Gb3, Gy2, 2), 2 bits of the code bit of the code bit group Gb3 having the third highest error probability are allocated to 2 bits of the symbol bit of the symbol bit group Gy2 having the second highest error probability. thing,
Also, according to the group set information (Gb3, Gy1, 1), 1 bit of the sign bit of the code bit group Gb3 having the third highest error probability and 1 bit of the symbol bit of the symbol bit group Gy1 having the highest error probability It is stipulated to be assigned to

  FIG. 73 shows an example of code bit replacement according to the assignment rule of FIG.

  That is, A in FIG. 73 is a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 3/4, and further, the modulation method is 64QAM and the multiple b is 2. 72 shows a first example of exchanging code bits according to the allocation rule of FIG.

  When the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 3/4, and further when the modulation method is 64QAM and the multiple b is 2, the demultiplexer 25 uses the column direction × The sign bit written in the memory 31 with (4320 / (6 × 2)) × (6 × 2) bits in the row direction is read in 6 × 2 (= mb) bits and replaced in the row direction It is supplied to the unit 32 (FIGS. 18 and 19).

  In accordance with the allocation rule of FIG. 72, the replacement unit 32 generates 2 (= b) code bits b0 to b11 of 6 × 2 (= mb) bits read from the memory 31, for example, as shown in A of FIG. The 6 × 2 (= mb) code bits b0 to b11 are switched so as to be assigned to 6 × 2 (= mb) symbol bits y0 to y11.

That is, the replacement unit 32
Sign bit b0 to symbol bit y2
Sign bit b1 into symbol bit y8
Sign bit b2 to symbol bit y5
Sign bit b3 to symbol bit y11,
Sign bit b4 to symbol bit y0,
Sign bit b5 to symbol bit y6,
Sign bit b6 to symbol bit y1
Sign bit b7 to symbol bit y10
Sign bit b8 to symbol bit y4,
Sign bit b9 to symbol bit y9,
Sign bit b10 to symbol bit y3,
Sign bit b11 to symbol bit y7
Replace each assigned.

  73B shows a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 3/4, and further, when the modulation scheme is 64QAM and the multiple b is 2. 72 shows a second example of code bit replacement in accordance with the allocation rule of FIG.

According to B in FIG. 73, the replacement unit 32 follows the allocation rules in FIG. 72 for the 6 × 2 (= mb) -bit code bits b0 to b11 read from the memory 31.
Sign bit b0 to symbol bit y2
Sign bit b1 into symbol bit y8
Sign bit b2 to symbol bit y4,
Sign bit b3 into symbol bit y10,
Sign bit b4 to symbol bit y1,
Sign bit b5 to symbol bit y0,
Sign bit b6 to symbol bit y6,
Sign bit b7 to symbol bit y11,
Sign bit b8 to symbol bit y5
Sign bit b9 to symbol bit y3,
Sign bit b10 into symbol bit y9,
Sign bit b11 to symbol bit y7
Replace each assigned.

  FIG. 74 shows a code bit when the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 5/6, and further having a modulation scheme of 64QAM and a multiple b of 2. A group and a symbol bit group are shown.

  In this case, 6 × 2 (= mb) code bits read from the memory 31 are divided into three code bit groups Gb1, Gb2, and Gb3 as shown in FIG. Can be grouped.

  In FIG. 74A, code bits b0 and b1 belong to code bit group Gb1, code bits b2 to b9 belong to code bit group Gb2, and code bits b10 and b11 belong to code bit group Gb3, respectively. .

  When the modulation scheme is 64QAM and the multiple b is 2, 6 × 2 (= mb) bit symbol bits are divided into three symbol bit groups as shown in FIG. Can be grouped into Gy1, Gy2, Gy3.

  In B of FIG. 74, similarly to B of FIG. 53, symbol bit group Gy1 includes symbol bits y0, y1, y6, y7, and symbol bit group Gy2 includes symbol bits y2, y3, y8, y9. Symbol bits y4, y5, y10, and y11 belong to the symbol bit group Gy3, respectively.

  FIG. 75 shows an allocation rule when the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 5/6, and further having a modulation scheme of 64QAM and a multiple b of 2. Is shown.

  75, group set information (Gb1, Gy2, 2), (Gb2, Gy3,4), (Gb2, Gy1, 3), (Gb2, Gy2, 1), (Gb3, Gy2, 1), (Gb3, Gy1, 1) is defined.

That is, in the allocation rule of FIG.
According to the group set information (Gb1, Gy2, 2), 2 bits of the code bit of the code bit group Gb1 having the first highest error probability are allocated to 2 bits of the symbol bit of the symbol bit group Gy2 having the second highest error probability. thing,
According to the group set information (Gb2, Gy3,4), 4 bits of code bits of the code bit group Gb2 having the second highest error probability are allocated to 4 bits of symbol bits of the symbol bit group Gy3 having the third highest error probability. thing,
According to the group set information (Gb2, Gy1, 3), 3 bits of the sign bit of the code bit group Gb2 with the second highest error probability are assigned to 3 bits of the symbol bit of the symbol bit group Gy1 with the best error probability. thing,
According to the group set information (Gb2, Gy2, 1), one bit of the sign bit of the code bit group Gb2 having the second highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy2 having the second highest error probability. thing,
According to the group set information (Gb3, Gy2, 1), one bit of the code bit of the code bit group Gb3 having the third highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy2 having the second highest error probability. thing,
Also, according to the group set information (Gb3, Gy1, 1), 1 bit of the sign bit of the code bit group Gb3 having the third highest error probability and 1 bit of the symbol bit of the symbol bit group Gy1 having the highest error probability It is stipulated to be assigned to

  FIG. 76 shows an example of code bit replacement according to the assignment rule of FIG.

  That is, A in FIG. 76 is a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 5/6, and further, the modulation method is 64QAM and the multiple b is 2. 75 shows a first example of exchanging code bits according to the allocation rule of FIG.

  When the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 5/6, and further having a modulation scheme of 64QAM and a multiple b of 2, the demultiplexer 25 uses the column direction × The sign bit written in the memory 31 with (4320 / (6 × 2)) × (6 × 2) bits in the row direction is read in 6 × 2 (= mb) bits and replaced in the row direction It is supplied to the unit 32 (FIGS. 18 and 19).

  The replacement unit 32 follows the allocation rule of FIG. 75, and 2 (= b) code bits b0 to b11 of 6 × 2 (= mb) bits read from the memory 31, for example, as shown in A of FIG. The 6 × 2 (= mb) code bits b0 to b11 are switched so as to be assigned to 6 × 2 (= mb) symbol bits y0 to y11.

That is, the replacement unit 32
Sign bit b0 to symbol bit y2
Sign bit b1 into symbol bit y8
Sign bit b2 to symbol bit y5
Sign bit b3 to symbol bit y11,
Sign bit b4 to symbol bit y0,
Sign bit b5 to symbol bit y6,
Sign bit b6 to symbol bit y1
Sign bit b7 to symbol bit y10
Sign bit b8 to symbol bit y4,
Sign bit b9 to symbol bit y9,
Sign bit b10 to symbol bit y3,
Sign bit b11 to symbol bit y7
Replace each assigned.

  76B shows a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 5/6, and further when the modulation scheme is 64QAM and the multiple b is 2. 75 shows a second example of code bit replacement according to the assignment rule of FIG.

According to B of FIG. 76, the replacement unit 32 follows the allocation rule of FIG. 75 for the 6 × 2 (= mb) bit code bits b0 to b11 read from the memory 31.
Sign bit b0 to symbol bit y8
Sign bit b1 to symbol bit y2
Sign bit b2 to symbol bit y4,
Sign bit b3 into symbol bit y10,
Sign bit b4 to symbol bit y6,
Sign bit b5 to symbol bit y0,
Sign bit b6 to symbol bit y1
Sign bit b7 to symbol bit y11,
Sign bit b8 to symbol bit y5
Sign bit b9 to symbol bit y9,
Sign bit b10 to symbol bit y3,
Sign bit b11 to symbol bit y7
Replace each assigned.

  FIG. 77 shows a code bit when the LDPC code is a portable LDPC code having a code length N of 4320 bits and an encoding rate of 11/12, and further, the modulation method is 64QAM and the multiple b is 2. A group and a symbol bit group are shown.

  In this case, 6 × 2 (= mb) code bits read from the memory 31 are divided into three code bit groups Gb1, Gb2, Gb3 as shown in A of FIG. 77 according to the difference in error probability. Can be grouped.

  In A of FIG. 77, code bit b0 belongs to code bit group Gb1, code bits b1 to b10 belong to code bit group Gb2, and code bit b11 belongs to code bit group Gb3.

  When the modulation scheme is 64QAM and the multiple b is 2, 6 × 2 (= mb) bit symbol bits are divided into three symbol bit groups as shown in FIG. 77B according to the difference in error probability. Can be grouped into Gy1, Gy2, Gy3.

  In B of FIG. 77, symbol bits y0, y1, y6, and y7 are included in symbol bit group Gy1, and symbol bits y2, y3, y8, and y9 are included in symbol bit group Gy2, as in B of FIG. Symbol bits y4, y5, y10, and y11 belong to the symbol bit group Gy3, respectively.

  FIG. 78 shows an allocation rule when the LDPC code is a portable LDPC code having a code length N of 4320 bits and an encoding rate of 11/12, and further the modulation scheme is 64QAM and the multiple b is 2. Is shown.

  78, group set information (Gb1, Gy2, 1), (Gb2, Gy2, 3), (Gb2, Gy3,4) (Gb2, Gy1, 3), (Gb3, Gy1, 1) are defined. Has been.

That is, in the allocation rule of FIG.
According to the group set information (Gb1, Gy2, 1), 1 bit of the code bit of the code bit group Gb1 having the first highest error probability is assigned to 1 bit of the symbol bit of the symbol bit group Gy2 having the second highest error probability. thing,
According to the group set information (Gb2, Gy2, 3), 3 bits of the code bit of the code bit group Gb2 having the second highest error probability are allocated to 3 bits of the symbol bit of the symbol bit group Gy2 having the second highest error probability. thing,
According to the group set information (Gb2, Gy3,4), 4 bits of code bits of the code bit group Gb2 having the second highest error probability are allocated to 4 bits of symbol bits of the symbol bit group Gy3 having the third highest error probability. thing,
According to the group set information (Gb2, Gy1, 3), 3 bits of the sign bit of the code bit group Gb2 with the second highest error probability are assigned to 3 bits of the symbol bit of the symbol bit group Gy1 with the best error probability. thing,
Also, according to the group set information (Gb3, Gy1, 1), 1 bit of the sign bit of the code bit group Gb3 having the third highest error probability and 1 bit of the symbol bit of the symbol bit group Gy1 having the highest error probability It is stipulated to be assigned to

  FIG. 79 shows an example of exchanging code bits according to the assignment rule of FIG.

  That is, A in FIG. 79 is a portable LDPC code whose LDPC code has a code length N of 4320 bits and a coding rate of 11/12, and further, the modulation method is 64QAM and the multiple b is 2. 78 shows a first example of exchanging code bits according to the allocation rule of FIG.

  When the LDPC code is a portable LDPC code having a code length N of 4320 bits and an encoding rate of 11/12, and further when the modulation method is 64QAM and the multiple b is 2, the demultiplexer 25 uses the column direction × The sign bit written in the memory 31 with (4320 / (6 × 2)) × (6 × 2) bits in the row direction is read in 6 × 2 (= mb) bits and replaced in the row direction It is supplied to the unit 32 (FIGS. 18 and 19).

  In accordance with the allocation rule of FIG. 78, the replacement unit 32 generates 2 (= b) code bits b0 to b11 of 6 × 2 (= mb) bits read from the memory 31, for example, as shown in A of FIG. The 6 × 2 (= mb) code bits b0 to b11 are switched so as to be assigned to 6 × 2 (= mb) symbol bits y0 to y11.

That is, the replacement unit 32
Sign bit b0 to symbol bit y2
Sign bit b1 into symbol bit y8
Sign bit b2 to symbol bit y5
Sign bit b3 to symbol bit y11,
Sign bit b4 to symbol bit y0,
Sign bit b5 to symbol bit y6,
Sign bit b6 to symbol bit y1
Sign bit b7 to symbol bit y10
Sign bit b8 to symbol bit y4,
Sign bit b9 to symbol bit y9,
Sign bit b10 to symbol bit y3,
Sign bit b11 to symbol bit y7
Replace each assigned.

  79B shows a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and an encoding rate of 11/12, and further, when the modulation scheme is 64QAM and the multiple b is 2. 78 shows a second example of code bit replacement in accordance with the assignment rule of FIG.

According to B in FIG. 79, the replacement unit 32 follows the allocation rules in FIG. 78 for 6 × 2 (= mb) bits of code bits b0 to b11 read from the memory 31.
Sign bit b0 to symbol bit y2
Sign bit b1 to symbol bit y3,
Sign bit b2 into symbol bit y10
Sign bit b3 to symbol bit y4,
Sign bit b4 to symbol bit y6,
Sign bit b5 to symbol bit y1,
Sign bit b6 to symbol bit y0,
Sign bit b7 to symbol bit y11,
Sign bit b8 to symbol bit y5
Sign bit b9 to symbol bit y8
Sign bit b10 into symbol bit y9,
Sign bit b11 to symbol bit y7
Replace each assigned.

  FIG. 80 shows a code bit when the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 1/4, and further having a modulation scheme of 16QAM and a multiple b of 2. A group and a symbol bit group are shown.

  In this case, 4 × 2 (= mb) code bits read from the memory 31 are divided into three code bit groups Gb1, Gb2, and Gb3 as shown in FIG. Can be grouped.

  In A of FIG. 80, code bit b0 belongs to code bit group Gb1, code bit b1 belongs to code bit group Gb2, and code bits b2 to b7 belong to code bit group Gb3.

  When the modulation scheme is 16QAM and the multiple b is 2, the symbol bit of 4 × 2 (= mb) bits can be divided into two symbol bit groups as shown in FIG. Can be grouped into Gy1 and Gy2.

  In B of FIG. 80, symbol bit group Gy1 includes symbol bits y0, y1, y4, and y5, and symbol bit group Gy2 includes symbol bits y2, y3, y6, and y7, respectively.

  FIG. 81 shows an allocation rule when the LDPC code is a portable LDPC code with a code length N of 4320 bits and a coding rate of 1/4, and further the modulation scheme is 16QAM and the multiple b is 2. Is shown.

  81, group set information (Gb1, Gy2, 1), (Gb2, Gy2, 1), (Gb3, Gy2, 2), (Gb3, Gy1, 4) are defined.

That is, in the allocation rule of FIG.
According to the group set information (Gb1, Gy2, 1), 1 bit of the code bit of the code bit group Gb1 having the first highest error probability is assigned to 1 bit of the symbol bit of the symbol bit group Gy2 having the second highest error probability. thing,
According to the group set information (Gb2, Gy2, 1), one bit of the sign bit of the code bit group Gb2 having the second highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy2 having the second highest error probability. thing,
According to the group set information (Gb3, Gy2, 2), 2 bits of the code bit of the code bit group Gb3 having the third highest error probability are allocated to 2 bits of the symbol bit of the symbol bit group Gy2 having the second highest error probability. thing,
And, according to the group set information (Gb3, Gy1, 4), the 4 bits of the sign bit of the code bit group Gb3 with the third highest error probability and the 4 bits of the symbol bits of the symbol bit group Gy1 with the best error probability It is stipulated to be assigned to

  FIG. 82 shows an example of exchanging code bits according to the allocation rule of FIG.

  That is, A in FIG. 82 is a case where the LDPC code is a portable LDPC code with a code length N of 4320 bits and a coding rate of 1/4, and the modulation scheme is 16QAM and the multiple b is 2. 81 shows a first example of code bit replacement according to the allocation rule of FIG.

  When the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 1/4, and further when the modulation method is 16QAM and the multiple b is 2, the demultiplexer 25 uses the column direction × The sign bit written in the memory 31 whose row direction is (4320 / (4 × 2)) × (4 × 2) bits is read and replaced in the row direction in units of 4 × 2 (= mb) It is supplied to the unit 32 (FIGS. 18 and 19).

  In accordance with the allocation rule of FIG. 81, the replacement unit 32 generates 2 (= b) code bits b0 to b7 of 4 × 2 (= mb) bits read from the memory 31, for example, as shown in A of FIG. The 4 × 2 (= mb) code bits b0 to b7 are switched so as to be assigned to 4 × 2 (= mb) symbol bits y0 to y7.

That is, the replacement unit 32
Sign bit b0 to symbol bit y7
Sign bit b1 to symbol bit y6,
Sign bit b2 to symbol bit y4,
Sign bit b3 into symbol bit y3
Sign bit b4 to symbol bit y2
Sign bit b5 to symbol bit y5
Sign bit b6 to symbol bit y1
Sign bit b7 to symbol bit y0,
Replace each assigned.

  B in FIG. 82 is a portable LDPC code with an LDPC code having a code length N of 4320 bits and an encoding rate of 1/4, and further, when the modulation scheme is 16QAM and the multiple b is 2. 81 shows a second example of code bit replacement according to the allocation rule of FIG.

According to B of FIG. 82, the replacement unit 32 follows the allocation rule of FIG. 81 for the 4 × 2 (= mb) bit code bits b0 to b7 read from the memory 31.
Sign bit b0 to symbol bit y7
Sign bit b1 to symbol bit y6,
Sign bit b2 to symbol bit y1,
Sign bit b3 to symbol bit y2
Sign bit b4 to symbol bit y3,
Sign bit b5 to symbol bit y4,
Sign bit b6 to symbol bit y0,
Sign bit b7 to symbol bit y5,
Replace each assigned.

  FIG. 83 shows a code bit when the LDPC code is a portable LDPC code having a code length N of 4320 bits and an encoding rate of 1/3, and further when the modulation method is 16QAM and the multiple b is 2. A group and a symbol bit group are shown.

  In this case, 4 × 2 (= mb) code bits read from the memory 31 are divided into four code bit groups Gb1, Gb2, Gb3, Can be grouped into Gb4.

  In FIG. 83A, the sign bit group Gb1 includes the sign bit b0, the sign bit group Gb2 includes the sign bit b1, the sign bit group Gb3 includes the sign bit b2, and the sign bit group Gb4 includes the sign bit. Bits b3 to b7 belong to each.

  When the modulation scheme is 16QAM and the multiple b is 2, the symbol bit of 4 × 2 (= mb) bits is divided into two symbol bit groups as shown in FIG. 83B according to the difference in error probability. Can be grouped into Gy1 and Gy2.

  83B, similarly to the case of B of FIG. 80, symbol bit group Gy1 includes symbol bits y0, y1, y4, and y5, and symbol bit group Gy2 includes symbol bits y2, y3, y6, and y7. Belong to each.

  FIG. 84 shows an allocation rule when the LDPC code is a portable LDPC code having a code length N of 4320 bits and an encoding rate of 1/3, and further, when the modulation scheme is 16QAM and the multiple b is 2. Is shown.

  In the allocation rule of FIG. 84, group set information (Gb1, Gy2, 1), (Gb2, Gy2, 1), (Gb3, Gy1, 1), (Gb4, Gy2, 2), (Gb4, Gy1, 3) It is prescribed.

That is, in the allocation rule of FIG.
According to the group set information (Gb1, Gy2, 1), 1 bit of the code bit of the code bit group Gb1 having the first highest error probability is assigned to 1 bit of the symbol bit of the symbol bit group Gy2 having the second highest error probability. thing,
According to the group set information (Gb2, Gy2, 1), one bit of the sign bit of the code bit group Gb2 having the second highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy2 having the second highest error probability. thing,
According to the group set information (Gb3, Gy1, 1), one bit of the code bit of the code bit group Gb3 having the third highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy1 having the highest error probability. thing,
According to the group set information (Gb4, Gy2, 2), 2 bits of the code bit of the code bit group Gb4 having the fourth highest error probability are allocated to 2 bits of the symbol bit of the symbol bit group Gy2 having the second highest error probability. thing,
And, according to the group set information (Gb4, Gy1, 3), 3 bits of the code bit of the code bit group Gb4 having the fourth highest error probability and 3 bits of the symbol bits of the symbol bit group Gy1 having the highest error probability It is stipulated to be assigned to

  FIG. 85 shows an example of exchanging code bits according to the assignment rule of FIG.

  That is, A in FIG. 85 is a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and an encoding rate of 1/3, and further, the modulation method is 16QAM and the multiple b is 2. 84 shows a first example of exchanging code bits according to the allocation rule of FIG.

  When the LDPC code is a portable LDPC code having a code length N of 4320 bits and an encoding rate of 1/3, and further when the modulation method is 16QAM and the multiple b is 2, the demultiplexer 25 uses the column direction × The sign bit written in the memory 31 whose row direction is (4320 / (4 × 2)) × (4 × 2) bits is read and replaced in the row direction in units of 4 × 2 (= mb) It is supplied to the unit 32 (FIGS. 18 and 19).

  The replacement unit 32, according to the allocation rule of FIG. 84, generates 2 (= b) code bits b0 to b7 of 4 × 2 (= mb) bits read from the memory 31, for example, as shown in A of FIG. The 4 × 2 (= mb) code bits b0 to b7 are switched so as to be assigned to 4 × 2 (= mb) symbol bits y0 to y7.

That is, the replacement unit 32
Sign bit b0 to symbol bit y7
Sign bit b1 to symbol bit y6,
Sign bit b2 to symbol bit y4,
Sign bit b3 into symbol bit y3
Sign bit b4 to symbol bit y2
Sign bit b5 to symbol bit y5
Sign bit b6 to symbol bit y1
Sign bit b7 to symbol bit y0,
Replace each assigned.

  B in FIG. 85 is a portable LDPC code in which the LDPC code has a code length N of 4320 bits and a coding rate of 1/3, and the modulation scheme is 16QAM, and the multiple b is 2. 84 shows a second example of code bit replacement according to the allocation rule of FIG.

According to B of FIG. 85, the replacement unit 32 follows the allocation rule of FIG. 84 for the 4 × 2 (= mb) bit code bits b0 to b7 read from the memory 31.
Sign bit b0 to symbol bit y7
Sign bit b1 to symbol bit y6,
Sign bit b2 to symbol bit y4,
Sign bit b3 to symbol bit y2
Sign bit b4 to symbol bit y3,
Sign bit b5 to symbol bit y0,
Sign bit b6 to symbol bit y5
Sign bit b7 to symbol bit y1
Replace each assigned.

  FIG. 86 shows a code bit when the LDPC code is a portable LDPC code with a code length N of 4320 bits and a coding rate of 5/12, and further when the modulation method is 16QAM and the multiple b is 2. A group and a symbol bit group are shown.

  In this case, 4 × 2 (= mb) code bits read from the memory 31 are divided into four code bit groups Gb1, Gb2, Gb3, Gb1, as shown in FIG. Can be grouped into Gb4.

  In A of FIG. 86, the sign bit group Gb1 includes the sign bit b0, the sign bit group Gb2 includes the sign bits b1 and b2, the sign bit group Gb3 includes the sign bit b3, and the sign bit group Gb4 includes the sign bit b3. The code bits b4 to b7 belong respectively.

  When the modulation scheme is 16QAM and the multiple b is 2, the symbol bit of 4 × 2 (= mb) bits is divided into two symbol bit groups as shown in FIG. 86B according to the difference in error probability. Can be grouped into Gy1 and Gy2.

  In B of FIG. 86, as in the case of B of FIG. 80, symbol bit group Gy1 includes symbol bits y0, y1, y4, and y5, and symbol bit group Gy2 includes symbol bits y2, y3, y6, and y7. Belong to each.

  FIG. 87 shows an allocation rule when the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 5/12, and further has a modulation scheme of 16QAM and a multiple b of 2. Is shown.

  87, the group set information (Gb1, Gy1, 1), (Gb2, Gy1, 1), (Gb2, Gy2, 1), (Gb3, Gy2, 1), (Gb4, Gy1, 2), (Gb4, Gy2, 2) is specified.

That is, in the allocation rule of FIG.
According to the group set information (Gb1, Gy1, 1), one bit of the code bit of the code bit group Gb1 having the highest error probability is allocated to one bit of the symbol bit of the symbol bit group Gy1 having the highest error probability. about,
According to the group set information (Gb2, Gy1, 1), one bit of the sign bit of the code bit group Gb2 having the second highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy1 having the best error probability. thing,
According to the group set information (Gb2, Gy2, 1), one bit of the sign bit of the code bit group Gb2 having the second highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy2 having the second highest error probability. thing,
According to the group set information (Gb3, Gy2, 1), one bit of the code bit of the code bit group Gb3 having the third highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy2 having the second highest error probability. thing,
According to the group set information (Gb4, Gy1, 2), 2 bits of the code bit of the code bit group Gb4 having the fourth highest error probability are allocated to 2 bits of the symbol bit of the symbol bit group Gy1 having the best error probability. thing,
And, according to the group set information (Gb4, Gy2, 2), 2 bits of the sign bit of the code bit group Gb4 having the fourth highest error probability and 2 bits of the symbol bits of the symbol bit group Gy2 having the second highest error probability It is stipulated to be assigned to

  FIG. 88 shows an example of exchanging code bits according to the assignment rule of FIG.

  88A shows a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 5/12, and further, the modulation method is 16QAM and the multiple b is 2. 87 shows a first example of exchanging code bits according to the allocation rule of FIG.

  When the LDPC code is a portable LDPC code having a code length N of 4320 bits and an encoding rate of 5/12, and further when the modulation method is 16QAM and the multiple b is 2, the demultiplexer 25 uses the column direction × The sign bit written in the memory 31 whose row direction is (4320 / (4 × 2)) × (4 × 2) bits is read and replaced in the row direction in units of 4 × 2 (= mb) It is supplied to the unit 32 (FIGS. 18 and 19).

  In accordance with the allocation rule of FIG. 87, the replacement unit 32 generates 2 (= b) code bits b0 to b7 of 4 × 2 (= mb) bits read from the memory 31, for example, as shown in A of FIG. The 4 × 2 (= mb) code bits b0 to b7 are switched so as to be assigned to 4 × 2 (= mb) symbol bits y0 to y7.

That is, the replacement unit 32
Sign bit b0 to symbol bit y0,
Sign bit b1 into symbol bit y4
Sign bit b2 to symbol bit y2
Sign bit b3 into symbol bit y6
Sign bit b4 to symbol bit y1,
Sign bit b5 to symbol bit y5
Sign bit b6 to symbol bit y3,
Sign bit b7 into symbol bit y7
Replace each assigned.

  88B shows a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 5/12, and further when the modulation method is 16QAM and the multiple b is 2. 87 shows a second example of code bit replacement according to the assignment rule of FIG.

According to B in FIG. 88, the replacement unit 32 follows the allocation rules in FIG. 87 for the 4 × 2 (= mb) bits of code bits b0 to b7 read from the memory 31.
Sign bit b0 to symbol bit y0,
Sign bit b1 into symbol bit y4
Sign bit b2 to symbol bit y2
Sign bit b3 into symbol bit y6
Sign bit b4 to symbol bit y5
Sign bit b5 to symbol bit y1,
Sign bit b6 to symbol bit y3,
Sign bit b7 into symbol bit y7
Replace each assigned.

  FIG. 89 shows a code bit when the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 1/2, and further, when the modulation scheme is 16QAM and the multiple b is 2. A group and a symbol bit group are shown.

  In this case, 4 × 2 (= mb) code bits read from the memory 31 are divided into three code bit groups Gb1, Gb2, and Gb3 as shown in FIG. 89A according to the difference in error probability. Can be grouped.

  In A of FIG. 89, code bit b0 belongs to code bit group Gb1, code bits b1 to b3 belong to code bit group Gb2, and code bits b4 to b7 belong to code bit group Gb3.

  When the modulation scheme is 16QAM and the multiple b is 2, symbol bits of 4 × 2 (= mb) bits are divided into two symbol bit groups as shown in FIG. 89B according to the difference in error probability. Can be grouped into Gy1 and Gy2.

  In B of FIG. 89, similarly to the case of B of FIG. 80, symbol bit group Gy1 includes symbol bits y0, y1, y4, and y5, and symbol bit group Gy2 includes symbol bits y2, y3, y6, and y7. Belong to each.

  FIG. 90 shows an allocation rule when the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 1/2, and further, when the modulation scheme is 16QAM and the multiple b is 2. Is shown.

  90, the group set information (Gb1, Gy2, 1), (Gb2, Gy2, 2), (Gb2, Gy1, 1), (Gb3, Gy2, 1), (Gb3, Gy1, 3) It is prescribed.

That is, in the assignment rule of FIG.
According to the group set information (Gb1, Gy2, 1), 1 bit of the code bit of the code bit group Gb1 having the first highest error probability is assigned to 1 bit of the symbol bit of the symbol bit group Gy2 having the second highest error probability. thing,
According to the group set information (Gb2, Gy2, 2), 2 bits of the code bit of the code bit group Gb2 having the second highest error probability are allocated to 2 bits of the symbol bit of the symbol bit group Gy2 having the second highest error probability. thing,
According to the group set information (Gb2, Gy1, 1), one bit of the sign bit of the code bit group Gb2 having the second highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy1 having the best error probability. thing,
According to the group set information (Gb3, Gy2, 1), one bit of the code bit of the code bit group Gb3 having the third highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy2 having the second highest error probability. thing,
And, according to the group set information (Gb3, Gy1, 3), 3 bits of the code bit of the code bit group Gb3 having the third highest error probability, and 3 bits of the symbol bits of the symbol bit group Gy1 having the highest error probability It is stipulated to be assigned to

  FIG. 91 shows an example of exchanging code bits according to the assignment rule of FIG.

  That is, A in FIG. 91 is a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 1/2, and further, the modulation method is 16QAM and the multiple b is 2. 90 shows a first example of code bit replacement in accordance with the allocation rule of FIG.

  When the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 1/2, and further when the modulation method is 16QAM and the multiple b is 2, the demultiplexer 25 uses the column direction × The sign bit written in the memory 31 whose row direction is (4320 / (4 × 2)) × (4 × 2) bits is read and replaced in the row direction in units of 4 × 2 (= mb) It is supplied to the unit 32 (FIGS. 18 and 19).

  The replacement unit 32 follows the allocation rule of FIG. 90, for example, 2 (= b) code bits b0 to b7 of 4 × 2 (= mb) bits read from the memory 31 as shown in A of FIG. The 4 × 2 (= mb) code bits b0 to b7 are switched so as to be assigned to 4 × 2 (= mb) symbol bits y0 to y7.

That is, the replacement unit 32
Sign bit b0 to symbol bit y7
Sign bit b1 to symbol bit y6,
Sign bit b2 to symbol bit y4,
Sign bit b3 into symbol bit y3
Sign bit b4 to symbol bit y2
Sign bit b5 to symbol bit y5
Sign bit b6 to symbol bit y1
Sign bit b7 to symbol bit y0,
Replace each assigned.

  91B shows a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 1/2, and further, when the modulation scheme is 16QAM and the multiple b is 2. 90 shows a second example of code bit replacement according to the assignment rule of FIG.

According to B of FIG. 91, the replacement unit 32 follows the allocation rules of FIG. 90 for 4 × 2 (= mb) bits of code bits b0 to b7 read from the memory 31.
Sign bit b0 to symbol bit y7
Sign bit b1 to symbol bit y3,
Sign bit b2 to symbol bit y4,
Sign bit b3 into symbol bit y6
Sign bit b4 to symbol bit y2
Sign bit b5 to symbol bit y0,
Sign bit b6 to symbol bit y5
Sign bit b7 to symbol bit y1
Replace each assigned.

  FIG. 92 shows a code bit when the LDPC code is a portable LDPC code with a code length N of 4320 bits and an encoding rate of 7/12, and further when the modulation method is 16QAM and the multiple b is 2. A group and a symbol bit group are shown.

  In this case, 4 × 2 (= mb) code bits read from the memory 31 are divided into four code bit groups Gb1, Gb2, Gb3, Can be grouped into Gb4.

  In A of FIG. 92, the sign bit group Gb1 includes the sign bit b0, the sign bit group Gb2 includes the sign bits b1 to b3, the sign bit group Gb3 includes the sign bit b4, and the sign bit group Gb4 includes the sign bit b4. The code bits b5 to b7 belong respectively.

  When the modulation method is 16QAM and the multiple b is 2, the symbol bit of 4 × 2 (= mb) bits is divided into two symbol bit groups as shown in FIG. 92B according to the difference in error probability. Can be grouped into Gy1 and Gy2.

  In B of FIG. 92, as in the case of B of FIG. 80, symbol bit group Gy1 includes symbol bits y0, y1, y4, and y5, and symbol bit group Gy2 includes symbol bits y2, y3, y6, and y7. Belong to each.

  FIG. 93 shows an allocation rule when the LDPC code is a portable LDPC code having a code length N of 4320 bits and an encoding rate of 7/12, and further, when the modulation scheme is 16QAM and the multiple b is 2. Is shown.

  93, the group set information (Gb1, Gy1, 1), (Gb2, Gy1, 1), (Gb2, Gy2, 2), (Gb3, Gy1, 1), (Gb4, Gy1, 1), (Gb4, Gy2, 2) is specified.

That is, in the assignment rule of FIG.
According to the group set information (Gb1, Gy1, 1), one bit of the code bit of the code bit group Gb1 having the highest error probability is allocated to one bit of the symbol bit of the symbol bit group Gy1 having the highest error probability. about,
According to the group set information (Gb2, Gy1, 1), one bit of the sign bit of the code bit group Gb2 having the second highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy1 having the best error probability. thing,
According to the group set information (Gb2, Gy2, 2), 2 bits of the code bit of the code bit group Gb2 having the second highest error probability are allocated to 2 bits of the symbol bit of the symbol bit group Gy2 having the second highest error probability. thing,
According to the group set information (Gb3, Gy1, 1), one bit of the code bit of the code bit group Gb3 having the third highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy1 having the highest error probability. thing,
According to the group set information (Gb4, Gy1, 1), one bit of the code bit of the code bit group Gb4 having the fourth highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy1 having the highest error probability. thing,
And, according to the group set information (Gb4, Gy2, 2), 2 bits of the sign bit of the code bit group Gb4 having the fourth highest error probability and 2 bits of the symbol bits of the symbol bit group Gy2 having the second highest error probability It is stipulated to be assigned to

  FIG. 94 shows an example of exchanging code bits in accordance with the assignment rule of FIG.

  That is, A in FIG. 94 is a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 7/12, and further the modulation method is 16QAM and the multiple b is 2. 93 shows a first example of exchanging code bits in accordance with the allocation rule of FIG.

  When the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 7/12, and further when the modulation method is 16QAM and the multiple b is 2, the demultiplexer 25 uses the column direction × The sign bit written in the memory 31 whose row direction is (4320 / (4 × 2)) × (4 × 2) bits is read and replaced in the row direction in units of 4 × 2 (= mb) It is supplied to the unit 32 (FIGS. 18 and 19).

  The exchanging unit 32 follows the allocation rule of FIG. 93, for example, 2 (= b) code bits b0 to b7 of 4 × 2 (= mb) bits read from the memory 31 as shown in A of FIG. The 4 × 2 (= mb) code bits b0 to b7 are switched so as to be assigned to 4 × 2 (= mb) symbol bits y0 to y7.

That is, the replacement unit 32
Sign bit b0 to symbol bit y0,
Sign bit b1 into symbol bit y4
Sign bit b2 to symbol bit y2
Sign bit b3 into symbol bit y6
Sign bit b4 to symbol bit y1,
Sign bit b5 to symbol bit y5
Sign bit b6 to symbol bit y3,
Sign bit b7 into symbol bit y7
Replace each assigned.

  FIG. 94B shows a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 7/12, and further when the modulation method is 16QAM and the multiple b is 2. 93 shows a second example of code bit replacement according to the assignment rule of FIG.

According to B of FIG. 94, the replacement unit 32 follows the allocation rules of FIG. 93 for the 4 × 2 (= mb) bit code bits b0 to b7 read from the memory 31.
Sign bit b0 to symbol bit y0,
Sign bit b1 into symbol bit y4
Sign bit b2 to symbol bit y6,
Sign bit b3 to symbol bit y2
Sign bit b4 to symbol bit y1,
Sign bit b5 to symbol bit y5
Sign bit b6 to symbol bit y7,
Sign bit b7 to symbol bit y3,
Replace each assigned.

  FIG. 95 shows a code bit when the LDPC code is a portable LDPC code with a code length N of 4320 bits and a coding rate of 2/3, and further when the modulation method is 16QAM and the multiple b is 2. A group and a symbol bit group are shown.

  In this case, 4 × 2 (= mb) code bits read out from the memory 31 are divided into four code bit groups Gb1, Gb2, Gb3, Gb1, as shown in FIG. Can be grouped into Gb4.

  In FIG. 95A, the sign bit group Gb1 includes the sign bit b0, the sign bit group Gb2 includes the sign bits b1 to b4, the sign bit group Gb3 includes the sign bit b5, and the sign bit group Gb4 includes the sign bit b5. The code bits b6 and b7 belong respectively.

  When the modulation scheme is 16QAM and the multiple b is 2, the symbol bit of 4 × 2 (= mb) bits is divided into two symbol bit groups as shown in FIG. Can be grouped into Gy1 and Gy2.

  In B of FIG. 95, similarly to the case of B of FIG. 80, symbol bit group Gy1 includes symbol bits y0, y1, y4, and y5, and symbol bit group Gy2 includes symbol bits y2, y3, y6, and y7. Belong to each.

  FIG. 96 shows an allocation rule when the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 2/3, and further, when the modulation scheme is 16QAM and the multiple b is 2. Is shown.

  In the allocation rule of FIG. 96, group set information (Gb1, Gy1, 1), (Gb2, Gy1, 2), (Gb2, Gy2, 2), (Gb3, Gy1, 1), (Gb4, Gy2, 2) It is prescribed.

That is, in the allocation rule of FIG.
According to the group set information (Gb1, Gy1, 1), one bit of the code bit of the code bit group Gb1 having the highest error probability is allocated to one bit of the symbol bit of the symbol bit group Gy1 having the highest error probability. about,
According to the group set information (Gb2, Gy1, 2), 2 bits of the code bit of the code bit group Gb2 having the second highest error probability are allocated to 2 bits of the symbol bit of the symbol bit group Gy1 having the best error probability. thing,
According to the group set information (Gb2, Gy2, 2), 2 bits of the code bit of the code bit group Gb2 having the second highest error probability are allocated to 2 bits of the symbol bit of the symbol bit group Gy2 having the second highest error probability. thing,
According to the group set information (Gb3, Gy1, 1), one bit of the code bit of the code bit group Gb3 having the third highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy1 having the highest error probability. thing,
And, according to the group set information (Gb4, Gy2, 2), 2 bits of the sign bit of the code bit group Gb4 having the fourth highest error probability and 2 bits of the symbol bits of the symbol bit group Gy2 having the second highest error probability It is stipulated to be assigned to

  FIG. 97 shows an example of exchanging code bits according to the assignment rule of FIG.

  That is, A in FIG. 97 is a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 2/3, and further, the modulation method is 16QAM and the multiple b is 2. 96 shows a first example of exchanging code bits in accordance with the allocation rule of FIG.

  When the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 2/3, and further when the modulation method is 16QAM and the multiple b is 2, the demultiplexer 25 uses the column direction × The sign bit written in the memory 31 whose row direction is (4320 / (4 × 2)) × (4 × 2) bits is read and replaced in the row direction in units of 4 × 2 (= mb) It is supplied to the unit 32 (FIGS. 18 and 19).

  The replacement unit 32, according to the allocation rule of FIG. 96, generates 2 (= b) code bits b0 to b7 of 4 × 2 (= mb) bits read from the memory 31, for example, as shown in A of FIG. The 4 × 2 (= mb) code bits b0 to b7 are switched so as to be assigned to 4 × 2 (= mb) symbol bits y0 to y7.

That is, the replacement unit 32
Sign bit b0 to symbol bit y0,
Sign bit b1 into symbol bit y4
Sign bit b2 to symbol bit y2
Sign bit b3 into symbol bit y6
Sign bit b4 to symbol bit y1,
Sign bit b5 to symbol bit y5
Sign bit b6 to symbol bit y3,
Sign bit b7 into symbol bit y7
Replace each assigned.

  FIG. 97B shows a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 2/3, a modulation scheme of 16QAM, and a multiple b of 2. 96 shows a second example of code bit replacement according to the assignment rule of FIG.

According to B of FIG. 97, the replacement unit 32 follows the allocation rules of FIG. 96 for the 4 × 2 (= mb) bit code bits b0 to b7 read from the memory 31.
Sign bit b0 to symbol bit y0,
Sign bit b1 to symbol bit y1,
Sign bit b2 to symbol bit y6,
Sign bit b3 to symbol bit y2
Sign bit b4 to symbol bit y4,
Sign bit b5 to symbol bit y5
Sign bit b6 to symbol bit y7,
Sign bit b7 to symbol bit y3,
Replace each assigned.

  FIG. 98 shows a code bit when the LDPC code is a portable LDPC code with a code length N of 4320 bits and a coding rate of 3/4, and the modulation method is 16QAM and the multiple b is 2. A group and a symbol bit group are shown.

  In this case, 4 × 2 (= mb) code bits read from the memory 31 are divided into three code bit groups Gb1, Gb2, and Gb3 as shown in FIG. Can be grouped.

  In FIG. 98A, code bit b0 belongs to code bit group Gb1, code bits b1 to b5 belong to code bit group Gb2, and code bits b6 and b7 belong to code bit group Gb3, respectively.

  When the modulation method is 16QAM and the multiple b is 2, symbol bits of 4 × 2 (= mb) bits are divided into two symbol bit groups as shown in FIG. Can be grouped into Gy1 and Gy2.

  In B of FIG. 98, similarly to B of FIG. 80, symbol bit group Gy1 includes symbol bits y0, y1, y4, and y5, and symbol bit group Gy2 includes symbol bits y2, y3, y6, and y7. Belong to each.

  FIG. 99 shows an allocation rule when the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 3/4, and further, the modulation scheme is 16QAM and the multiple b is 2. Is shown.

  In the allocation rule of FIG. 99, group set information (Gb1, Gy1, 1), (Gb2, Gy1, 3), (Gb2, Gy2, 2), (Gb3, Gy2, 2) are defined.

That is, in the allocation rule of FIG.
According to the group set information (Gb1, Gy1, 1), one bit of the code bit of the code bit group Gb1 having the highest error probability is allocated to one bit of the symbol bit of the symbol bit group Gy1 having the highest error probability. about,
According to the group set information (Gb2, Gy1, 3), 3 bits of the sign bit of the code bit group Gb2 with the second highest error probability are assigned to 3 bits of the symbol bit of the symbol bit group Gy1 with the best error probability. thing,
According to the group set information (Gb2, Gy2, 2), 2 bits of the code bit of the code bit group Gb2 having the second highest error probability are allocated to 2 bits of the symbol bit of the symbol bit group Gy2 having the second highest error probability. thing,
And, according to the group set information (Gb3, Gy2, 2), 2 bits of the sign bit of the code bit group Gb3 having the third highest error probability and 2 bits of the symbol bits of the symbol bit group Gy2 having the second highest error probability It is stipulated to be assigned to

  FIG. 100 illustrates an example of exchanging code bits according to the allocation rule of FIG.

  That is, A in FIG. 100 is a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 3/4, and further, the modulation method is 16QAM and the multiple b is 2. FIG. 99 shows a first example of code bit replacement according to the assignment rule of FIG.

  When the LDPC code is a portable LDPC code with a code length N of 4320 bits and a coding rate of 3/4, and further when the modulation method is 16QAM and the multiple b is 2, the demultiplexer 25 uses the column direction × The sign bit written in the memory 31 whose row direction is (4320 / (4 × 2)) × (4 × 2) bits is read and replaced in the row direction in units of 4 × 2 (= mb) It is supplied to the unit 32 (FIGS. 18 and 19).

  In accordance with the allocation rule of FIG. 99, the replacement unit 32 generates 2 (= b) code bits b0 to b7 of 4 × 2 (= mb) bits read from the memory 31, for example, as shown in A of FIG. The 4 × 2 (= mb) code bits b0 to b7 are switched so as to be assigned to 4 × 2 (= mb) symbol bits y0 to y7.

That is, the replacement unit 32
Sign bit b0 to symbol bit y0,
Sign bit b1 into symbol bit y4
Sign bit b2 to symbol bit y2
Sign bit b3 into symbol bit y6
Sign bit b4 to symbol bit y1,
Sign bit b5 to symbol bit y5
Sign bit b6 to symbol bit y3,
Sign bit b7 into symbol bit y7
Replace each assigned.

  B in FIG. 100 is a portable LDPC code in which the LDPC code has a code length N of 4320 bits and a coding rate of 3/4, and the modulation scheme is 16QAM and the multiple b is 2. 99 shows a second example of code bit replacement according to the allocation rule of FIG.

According to B of FIG. 100, the replacement unit 32 follows the allocation rule of FIG. 99 for the 4 × 2 (= mb) bit code bits b0 to b7 read from the memory 31.
Sign bit b0 to symbol bit y0,
Sign bit b1 into symbol bit y5
Sign bit b2 to symbol bit y6,
Sign bit b3 to symbol bit y2
Sign bit b4 to symbol bit y4,
Sign bit b5 to symbol bit y1,
Sign bit b6 to symbol bit y7,
Sign bit b7 to symbol bit y3,
Replace each assigned.

  FIG. 101 shows a code bit when the LDPC code is a portable LDPC code with a code length N of 4320 bits and a coding rate of 5/6, and the modulation scheme is 16QAM and the multiple b is 2. A group and a symbol bit group are shown.

  In this case, 4 × 2 (= mb) code bits read out from the memory 31 are divided into five code bit groups Gb1, Gb2, Gb3, Gb1, as shown in FIG. Can be grouped into Gb4 and Gb5.

  In A of FIG. 101, the sign bit group Gb1 includes the sign bit b0, the sign bit group Gb2 includes the sign bit b1, the sign bit group Gb3 includes the sign bits b2 to b5, and the sign bit group Gb4 includes the sign bit b1. The code bit b6 belongs to the code bit group Gb5, and the code bit b7 belongs to the code bit group Gb5.

  When the modulation scheme is 16QAM and the multiple b is 2, 4 × 2 (= mb) symbol bits are divided into two symbol bit groups as shown in FIG. 101B according to the difference in error probability. Can be grouped into Gy1 and Gy2.

  In B of FIG. 101, as in the case of B of FIG. 80, symbol bit group Gy1 includes symbol bits y0, y1, y4, and y5, and symbol bit group Gy2 includes symbol bits y2, y3, y6, and y7. Belong to each.

  FIG. 102 shows an allocation rule when the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 5/6, and further having a modulation scheme of 16QAM and a multiple b of 2. Is shown.

  102, the group set information (Gb1, Gy1, 1), (Gb2, Gy1, 1), (Gb3, Gy2, 2), (Gb3, Gy1, 2), (Gb4, Gy2, 1), (Gb5, Gy2, 1) is specified.

That is, in the allocation rule of FIG.
According to the group set information (Gb1, Gy1, 1), one bit of the code bit of the code bit group Gb1 having the highest error probability is allocated to one bit of the symbol bit of the symbol bit group Gy1 having the highest error probability. about,
According to the group set information (Gb2, Gy1, 1), one bit of the sign bit of the code bit group Gb2 having the second highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy1 having the best error probability. thing,
According to the group set information (Gb3, Gy2, 2), 2 bits of the code bit of the code bit group Gb3 having the third highest error probability are allocated to 2 bits of the symbol bit of the symbol bit group Gy2 having the second highest error probability. thing,
According to the group set information (Gb3, Gy1, 2), 2 bits of the code bit of the code bit group Gb3 having the third highest error probability are allocated to 2 bits of the symbol bit of the symbol bit group Gy1 having the best error probability. thing,
According to the group set information (Gb4, Gy2, 1), 1 bit of the code bit of the code bit group Gb4 having the fourth highest error probability is assigned to 1 bit of the symbol bit of the symbol bit group Gy2 having the second highest error probability. thing,
Also, according to the group set information (Gb5, Gy2, 1), one bit of the sign bit of the code bit group Gb5 having the fifth highest error probability and one bit of the symbol bit of the symbol bit group Gy2 having the second highest error probability It is stipulated to be assigned to

  FIG. 103 shows an example of code bit replacement according to the assignment rule of FIG.

  That is, A in FIG. 103 is a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 5/6, and further, the modulation method is 16QAM and the multiple b is 2. 102 shows a first example of code bit replacement according to the allocation rule of FIG.

  When the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 5/6, and further having a modulation method of 16QAM and a multiple b of 2, the demultiplexer 25 uses the column direction × The sign bit written in the memory 31 whose row direction is (4320 / (4 × 2)) × (4 × 2) bits is read and replaced in the row direction in units of 4 × 2 (= mb) It is supplied to the unit 32 (FIGS. 18 and 19).

  The replacement unit 32, according to the allocation rule of FIG. 102, generates 2 (= b) code bits b0 to b7 of 4 × 2 (= mb) bits read from the memory 31, for example, as shown in A of FIG. The 4 × 2 (= mb) code bits b0 to b7 are switched so as to be assigned to 4 × 2 (= mb) symbol bits y0 to y7.

That is, the replacement unit 32
Sign bit b0 to symbol bit y0,
Sign bit b1 into symbol bit y4
Sign bit b2 to symbol bit y2
Sign bit b3 into symbol bit y6
Sign bit b4 to symbol bit y1,
Sign bit b5 to symbol bit y5
Sign bit b6 to symbol bit y3,
Sign bit b7 into symbol bit y7
Replace each assigned.

  FIG. 103B shows a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 5/6, and further when the modulation scheme is 16QAM and the multiple b is 2. 102 shows a second example of code bit replacement according to the assignment rule of FIG.

According to B of FIG. 103, the replacement unit 32 follows the allocation rules of FIG. 102 for the 4 × 2 (= mb) bit code bits b0 to b7 read from the memory 31.
Sign bit b0 to symbol bit y0,
Sign bit b1 into symbol bit y4
Sign bit b2 to symbol bit y6,
Sign bit b3 to symbol bit y2
Sign bit b4 to symbol bit y5
Sign bit b5 to symbol bit y1,
Sign bit b6 to symbol bit y3,
Sign bit b7 into symbol bit y7
Replace each assigned.

  FIG. 104 shows a code bit when the LDPC code is a portable LDPC code with a code length N of 4320 bits and an encoding rate of 11/12, and further when the modulation scheme is 16QAM and the multiple b is 2. A group and a symbol bit group are shown.

  In this case, 4 × 2 (= mb) code bits read from the memory 31 are divided into three code bit groups Gb1, Gb2, and Gb3 as shown in FIG. Can be grouped.

  In A of FIG. 104, code bit group Gb1 includes code bit b0, code bit group Gb2 includes code bits b1 to b6, and code bit group Gb3 includes code bit b7.

  When the modulation scheme is 16QAM and the multiple b is 2, symbol bits of 4 × 2 (= mb) bits are divided into two symbol bit groups as shown in FIG. Can be grouped into Gy1 and Gy2.

  In B of FIG. 104, similarly to the case of B of FIG. 80, symbol bit group Gy1 includes symbol bits y0, y1, y4, and y5, and symbol bit group Gy2 includes symbol bits y2, y3, y6, and y7. Belong to each.

  FIG. 105 shows an allocation rule when the LDPC code is a portable LDPC code with a code length N of 4320 bits and an encoding rate of 11/12, and further the modulation scheme is 16QAM and the multiple b is 2. Is shown.

  In the allocation rule of FIG. 105, group set information (Gb1, Gy1, 1), (Gb2, Gy2, 3), (Gb2, Gy1, 3), (Gb3, Gy2, 1) are defined.

That is, in the allocation rule of FIG.
According to the group set information (Gb1, Gy1, 1), one bit of the code bit of the code bit group Gb1 having the highest error probability is allocated to one bit of the symbol bit of the symbol bit group Gy1 having the highest error probability. about,
According to the group set information (Gb2, Gy2, 3), 3 bits of the code bit of the code bit group Gb2 having the second highest error probability are allocated to 3 bits of the symbol bit of the symbol bit group Gy2 having the second highest error probability. thing,
According to the group set information (Gb2, Gy1, 3), 3 bits of the sign bit of the code bit group Gb2 with the second highest error probability are assigned to 3 bits of the symbol bit of the symbol bit group Gy1 with the best error probability. thing,
Also, according to the group set information (Gb3, Gy2, 1), 1 bit of the sign bit of the code bit group Gb3 having the third highest error probability and 1 bit of the symbol bit of the symbol bit group Gy2 having the second highest error probability It is stipulated to be assigned to

  FIG. 106 shows an example of code bit replacement according to the assignment rule of FIG.

  That is, A in FIG. 106 is a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and an encoding rate of 11/12, and further, the modulation scheme is 16QAM and the multiple b is 2. 105 shows a first example of exchanging code bits according to the allocation rule of FIG.

  When the LDPC code is a portable LDPC code with a code length N of 4320 bits and an encoding rate of 11/12, and further when the modulation method is 16QAM and the multiple b is 2, the demultiplexer 25 uses the column direction × The sign bit written in the memory 31 whose row direction is (4320 / (4 × 2)) × (4 × 2) bits is read and replaced in the row direction in units of 4 × 2 (= mb) It is supplied to the unit 32 (FIGS. 18 and 19).

  The replacement unit 32, according to the allocation rule of FIG. 105, generates 2 (= b) code bits b0 to b7 of 4 × 2 (= mb) bits read from the memory 31, for example, as shown in A of FIG. The 4 × 2 (= mb) code bits b0 to b7 are switched so as to be assigned to 4 × 2 (= mb) symbol bits y0 to y7.

That is, the replacement unit 32
Sign bit b0 to symbol bit y0,
Sign bit b1 into symbol bit y4
Sign bit b2 to symbol bit y2
Sign bit b3 into symbol bit y6
Sign bit b4 to symbol bit y1,
Sign bit b5 to symbol bit y5
Sign bit b6 to symbol bit y3,
Sign bit b7 into symbol bit y7
Replace each assigned.

  B in FIG. 106 is an LDPC code in which the code length N is 4320 bits and the code rate is 11/12 portable LDPC code, and the modulation scheme is 16QAM and the multiple b is 2. 105 shows a second example of code bit replacement according to the assignment rule of FIG.

According to B of FIG. 106, the replacement unit 32 follows the allocation rules of FIG. 105, for 4 × 2 (= mb) bits of code bits b0 to b7 read from the memory 31.
Sign bit b0 to symbol bit y0,
Sign bit b1 into symbol bit y5
Sign bit b2 to symbol bit y3,
Sign bit b3 to symbol bit y2
Sign bit b4 to symbol bit y4,
Sign bit b5 to symbol bit y1,
Sign bit b6 to symbol bit y6,
Sign bit b7 into symbol bit y7
Replace each assigned.

  107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123 FIG. 124 shows the result of a BER (Bit Error Rate) simulation when the replacement process of the new replacement method is performed and when the replacement process is not performed.

  That is, in FIGS. 107 to 115, the code length N is 4320, and the coding rate is 1/4, 1/3, 5/12, 1/2, 7/12, 2/3, 3/4, 5 /. The BER is shown when 64QAM is adopted as a modulation method for portable LDPC codes (FIGS. 35 to 43) of 6, 11/12.

  116 to 124, the code length N is 4320, and the coding rate is 1/4, 1/3, 5/12, 1/2, 7/12, 2/3, 3/4, 5/6, The BER is shown for 11/12 portable LDPC codes and 16QAM is used as the modulation method.

  Here, in FIG. 107 to FIG. 124, the multiple b is 2.

In FIGS. 107 to 123, the horizontal axis represents E _s / N ₀ (signal power to noise power ratio per symbol), and the vertical axis represents BER. In addition, a circle (◯) represents the BER when the replacement process of the new replacement method is performed, and the asterisk represents the BER when the replacement process is not performed.

Figures 107 through Figure 124, according to the replacement process of the new replacement method, in comparison with the case of no replacement process, in whole or in E _s / N ₀ over a certain extent, it has improved the BER Therefore, it can be seen that the tolerance to errors is improved.

  Here, as a method of exchanging the code bits of the LDPC code in the exchanging process by the exchanging unit 32, that is, as an allocation pattern (hereinafter also referred to as a bit allocation pattern) between the code bits of the LDPC code and the symbol bits representing the symbol. For each LDPC code having a different coding rate, a dedicated bit allocation pattern can be employed for the LDPC code.

  However, if a dedicated bit allocation pattern is adopted for each LDPC code having a different coding rate, it is necessary to mount a large number of bit allocation patterns in the transmission apparatus 11, and the types of coding rates differing. It is necessary to change (switch) the bit allocation pattern for each LDPC code.

  On the other hand, according to the replacement process described with reference to FIGS. 53 to 106, the bit allocation pattern mounted on the transmission apparatus 11 can be reduced.

That is, when the code length N is 4320 bits and the modulation scheme is 64QAM,
For each LDPC code having a coding rate of 1/4, the code bits b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b10, b11 shown in FIG. Bit allocation pattern to be assigned to symbol bits y11, y10, y4, y5, y2, y3, y8, y9, y6, y7, y1, y0,
For LDPC codes with coding rates of 1/3, 5/12, 1/2, and 7/12, the code bit b0 shown in A of FIGS. 58, 61, 64, and 67 is used. Or bit allocation pattern to assign b11 to symbol bits y0, y11, y1, y10, y4, y8, y2, y9, y3, y7, y5, y6,
For the LDPC codes with coding rates of 2/3, 3/4, 5/6, and 11/12, the code bit b0 shown in A of FIGS. 70, 73, 76, and 79 is used. Or bit allocation pattern to assign b11 to symbol bits y2, y8, y5, y11, y0, y6, y1, y10, y4, y9, y3, y7, respectively.
By adopting each, it is only necessary to mount three bit allocation patterns in the transmission device 11.

When the code length N is 4320 bits and the modulation method is 16QAM,
For LDPC codes with coding rates of 1/4, 1/3, and 1/2, code bits b0 to b7 shown in FIG. 82, FIG. 85, and FIG. Bit assignment pattern assigned to bits y7, y6, y4, y3, y2, y5, y1, y0
For LDPC codes with coding rates of 5/12, 7/12, 2/3, 3/4, 5/6, and 11/12, FIG. 88, FIG. 94, FIG. 97, FIG. And, the bit allocation patterns shown in A of FIG. 106 to assign the code bits b0 to b7 to the symbol bits y0, y4, y2, y6, y1, y5, y3, y7, respectively.
By adopting each of them, it is only necessary to mount two patterns of bit allocation patterns in the transmission device 11.

  In the present embodiment, for convenience of explanation, in the demultiplexer 25, the replacement unit 32 performs the replacement process for the code bit read from the memory 31, but the replacement process is performed in the memory 31. This can be done by controlling the writing and reading of the sign bit for.

  That is, the replacement process can be performed, for example, by controlling the address (read address) from which the code bits are read so that the code bits are read from the memory 31 in the order of the code bits after the replacement.

  [LDPC code with a code length N of 4320 bits (second 4k code)]

  By the way, for an LDPC code having a code length of 4k bits (hereinafter, also referred to as a first 4k code) obtained using a parity check matrix obtained from the parity check matrix initial value table of FIGS. 35 to 43, DVB-T.2 From the standpoint of maintaining the affinity with the PSB as much as possible, 360 as specified in DVB-T.2 is used as the number of columns P of the unit of the cyclic structure, as in the LDPC code specified in DVB-T.2. It has been adopted.

  However, it may be required to improve the BER even if the affinity with DVB-T.2 is sacrificed to some extent.

  125 to 131 are diagrams illustrating examples of a parity check matrix initial value table of a second 4k code that is a portable LDPC code having a code length of 4k bits, which is different from the first 4k code.

  That is, FIG. 125 illustrates a parity check matrix initial value table for a parity check matrix H having a code length N of 4k bits and a coding rate r of 1/4.

  FIG. 126 illustrates a parity check matrix initial value table for a parity check matrix H having a code length N of 4k bits and an encoding rate r of 1/3.

  127 illustrates a parity check matrix initial value table for a parity check matrix H having a code length N of 4k bits and a code rate r of 5/12.

  128 illustrates a parity check matrix initial value table for a parity check matrix H having a code length N of 4k bits and a code rate r of 1/2.

  FIG. 129 illustrates a parity check matrix initial value table for a parity check matrix H having a code length N of 4k bits and a code rate r of 7/12.

  FIG. 130 illustrates a parity check matrix initial value table for a parity check matrix H having a code length N of 4k bits and a code rate r of 2/3.

  FIG. 131 illustrates a parity check matrix initial value table for a parity check matrix H having a code length N of 4k bits and a code rate r of 3/4.

  Note that the parity matrix of the parity check matrix obtained from the parity check matrix initial value table of FIGS. 125 to 131 has a staircase structure (FIG. 11).

  Furthermore, the second 4k code, which is an LDPC code having a 4k bit code length obtained using the parity check matrix obtained from the parity check matrix initial value table of FIGS. 125 to 131, is defined in DVB-T.2. Similar to the LDPC code, the information matrix of the check matrix H has a cyclic structure.

  However, for the second 4k code, the number of columns P in the cyclic structure unit is not 360, but 60, which is one of the divisors of 360.

  LDPC encoder 115 (FIGS. 8 and 31) uses a parity check matrix obtained from the parity check matrix initial value table shown in FIGS. 125 to 133, and has a code length N of 4k bits and a coding rate r of 1/4. , 1/3, 5/12, 1/2, 7/12, 2/3, and 3/4 can be subjected to LDPC encoding to any second 4k code .

  That is, the LDPC encoder 115 sets the number of columns P of the cyclic structure as 60 instead of 360, from the parity check matrix initial value table shown in FIGS. 125 to 131, as in the case described in FIG. A parity check matrix is obtained, and LDPC encoding to the second 4k code is performed using the parity check matrix.

  The second 4k code (the check matrix initial value table) in FIGS. 125 to 131 is obtained by performing a simulation similar to the simulation for obtaining the first 4k code in FIGS.

That is, in the simulation for obtaining the second 4k code, an ensemble in which the performance threshold at which _Eb / N ₀ starts to decrease (becomes smaller) due to multi-edge type density evolution is equal to or less than a predetermined value is found. From among the LDPC codes belonging to the ensemble, an LDPC code that reduces the BER in a plurality of modulation schemes used in digital broadcasting for mobile terminals, such as 16QAM and 64QAM, was selected as a high-performance LDPC code.

  In the simulation for obtaining the second 4k code, the number of signal points such as QPSK, 16QAM, 64QAM, and the like is compared in order to improve tolerance to errors, similarly to the simulation for obtaining the first 4k code. Adopted a few modulation methods.

  FIG. 132 shows seven types of coding rates r of FIGS. 125 to 131 with 1/4, 1/3, 5/12, 1/2, 7/12, 2/3, and 3/4, respectively. It is a figure which shows the minimum cycle length and performance threshold value of a check matrix calculated | required from the check matrix initial value table of a 2nd 4k code.

  The minimum cycle lengths of the parity check matrix obtained from the parity check matrix initial value tables of FIGS. 125 to 131 are all 6 cycles, and cycle 4 does not exist.

  Further, since the redundancy of the LDPC code increases as the encoding rate r decreases, the performance threshold increases (becomes smaller) as the encoding rate r decreases.

  FIG. 133 is a diagram for explaining the parity check matrix (of the second 4k code obtained from the parity check matrix initial value table) in FIGS. 125 to 131.

  In the second 4k code parity check matrix, as in the case of the first 4k code parity check matrix described with reference to FIGS. 47 and 48, the column weight of the KX column from the first column is X, and the subsequent KY The column weight of the column is Y, the column weight of the subsequent M-1 column is 2, and the column weight of the last column is 1.

  Here, KX + KY + M-1 + 1 is equal to the code length N = 4320 bits.

  Then, the number of columns KX of the second 4k code parity check matrix with coding rates r of 1/4, 1/3, 5/12, 1/2, 7/12, 2/3, and 3/4, respectively. , KY, and M, and column weights X and Y are as shown in FIG.

  The second 4k code parity check matrix is the same as the parity check matrix defined in DVB-T.2 described with reference to FIGS. 12 and 13 and the first 4k code parity check matrix. The column weight tends to be larger in the column, and therefore, the first code bit of the second 4k code tends to be more resistant to errors (tolerant to errors).

  [Column twist interleaving of the second 4k code]

  In LDPC encoder 115 (FIG. 8, FIG. 31), when performing LDPC encoding to the second 4k code using the parity check matrix shown in FIGS. 125 to 131 (obtained from the parity check matrix initial value table) In the column twist interleave as the rearrangement process performed by the column twist interleaver 24 (FIG. 9), the write start position of each column (FIG. 24) of the memory 31 is defined in DVB-T.2. This is different from the writing start position in the case of the LDPC code (FIGS. 25 and 26) and the writing start position in the case of the first 4k code (FIG. 49).

  FIG. 134 is a diagram illustrating the number of columns of the memory 31 necessary for column twist interleaving and the address of the writing start position for the second 4k code.

  That is, in FIG. 134, the code length N of FIGS. 125 to 131 is 4k bits, and the coding rate r is 1/4, 1/3, 5/12, 1/2, 7/12, 2/3, And for 7/4 of 3/4 second 4k codes (obtained from the parity check matrix obtained from the parity check matrix initial value table), the number of columns of the memory 31 required for column twist interleaving and the address of the write start position Are shown for each modulation method.

  For the second 4k code, QPSK, 16QAM, and 64QAM, which have a relatively small number of signal points, are employed as the modulation method, as in the first 4k code.

  When the multiple b is 1 and QPSK is adopted as the modulation method, when the bit number m of one symbol is 2 bits, the memory 31 stores 2 × 1 bits in the row direction 2 It has N columns, and stores N / (mb) = 4320 / (2 × 1) bits in the column direction.

  Of the two columns in the memory 31, the first column write start position is the address 0 position, and the second column write start position is the address 60 position. Is done.

  When the multiple b is 2 and QPSK is adopted as the modulation method, when the bit number m of one symbol is 2 bits, the memory 31 stores 2 × 2 bits in the row direction 4 It has N columns and stores N / (mb) = 4320 / (2 × 2) bits in the column direction.

  Of the four columns in the memory 31, the first column write start position is the address 0 position, the second column write start position is the address 62 position, 3 The write start position of the second column is the position where the address is 36, and the write start position of the fourth column is the position where the address is 3.

  When the multiple b is 1 and 16QAM is adopted as the modulation method, when the bit number m of one symbol is 4 bits, the memory 31 stores 4 × 1 bits in the row direction 4 It has N columns and stores N / (mb) = 4320 / (4 × 1) bits in the column direction.

  The write start position of each of the four columns in the memory 31 is the same as when the multiple b is 2 and QPSK is adopted as the modulation method.

  That is, of the four columns in the memory 31, the first column write start position is the address 0 position, the second column write start position is the address 62 position, 3 The write start position of the second column is the position where the address is 36, and the write start position of the fourth column is the position where the address is 3.

  When the multiple b is 2 and 16QAM is adopted as the modulation method, when the bit number m of one symbol is 4 bits, the memory 31 stores 4 × 2 bits in the row direction 8 It has N columns and stores N / (mb) = 4320 / (4 × 2) bits in the column direction.

  Of the eight columns of the memory 31, the first column write start position is the address 0 position, the second column write start position is the address 2 position, 3 The write start position of the second column is the position of the address 46, the write start position of the fourth column is the position of the address 79, and the start position of the fifth column is the address 291. The position and the writing start position of the sixth column are the position of the address 146, the writing start position of the seventh column is the position of the address 3 and the writing start position of the eighth column is The address is made with 13 positions, respectively.

  When the multiple b is 1 and 64QAM is adopted as the modulation method, when the bit number m of one symbol is 6 bits, the memory 31 stores 6 × 1 bits in the row direction 6 It has N columns, and stores N / (mb) = 4320 / (6 × 1) bits in the column direction.

  Of the six columns of the memory 31, the first column write start position is the address 0 position, the second column write start position is the address 3 position, 3 The first column write position is the address 68, the fourth column write start position is the address 24 position, and the fifth column start position is the address 47. The position and the position at the beginning of writing in the sixth column are set to the position where the address is 4, respectively.

  When multiple b is 2 and 64QAM is adopted as a modulation method, for example, when the number of bits m of one symbol is 6 bits, the memory 31 stores 6 × 2 bits in the row direction. 12 columns and 4320 / (6 × 2) bits are stored in the column direction.

  Of the 12 columns of the memory 31, the first column write start position is the address 0 position, the second column write start position is the address 0 position, 3 The first column write position is the address 3 position, the fourth column write start position is the address 15 position, and the fifth column start position is the address 119. The position and the start position of writing the sixth column are the position where the address is 32, the start position of the seventh column is the position where the address is 24, and the start position of the eighth column is The position of address 169 and the start position of writing the ninth column are the position of address 84, and the start position of the tenth column is the position of address 3 and the start of writing the eleventh column. The position of is the position of the address 12 and the 12th The writing starting position for the ram is set to the position whose address is 3, are respectively.

  With respect to the second 4k code in FIGS. 125 to 131, by performing column twist interleaving as described above, a plurality of code bits corresponding to a plurality of variable nodes connected to the same check node are converted into QPSK, 16QAM. Alternatively, it is possible to avoid a single symbol of 64QAM (contained in the same symbol), and as a result, it is possible to improve the decoding performance in a communication path with an erasure.

  FIG. 135 is a diagram illustrating a result of BER simulation performed on the second 4k code.

  In the simulation, assuming an AWGN communication channel (channel), BPSK was adopted as the modulation method, and 50 iterations were adopted as the number of iterations C.

In FIG. 135, the horizontal axis represents E _s / N ₀ (signal power to noise power ratio per symbol), and the vertical axis represents BER.

  In FIG. 135, the solid line indicates the second 4k codes with coding rates r of 1/4, 1/3, 5/12, 1/2, 7/12, 2/3, and 3/4, respectively. The BER of (new) is represented, and the dotted line indicates the first code rate r of 1/4, 1/3, 5/12, 1/2, 7/12, 2/3, and 3/4, respectively. Represents BER of 4k code (old).

  According to FIG. 135, the first 4k code is used for any coding rate r of 1/4, 1/3, 5/12, 1/2, 7/12, 2/3, and 3/4. Thus, it can be seen that the second 4k code has an improved BER, and therefore an improved tolerance to errors.

  [Configuration Example of Receiving Device 12]

  136 is a block diagram illustrating a configuration example of the reception device 12 of FIG.

  An OFDM processing unit (OFDM operation) 151 receives an OFDM signal from the transmission device 11 (FIG. 7) and performs signal processing on the OFDM signal. Data (symbols) obtained by performing signal processing by the OFDM processing unit 151 is supplied to a frame management unit 152.

  The frame management unit 152 performs processing (frame interpretation) of a frame including symbols supplied from the OFDM processing unit 151, and converts the symbol of the target data and the control data symbol obtained as a result thereof into a frequency deinterleaver. (Frequency Deinterleaver) 161 and 153, respectively.

  The frequency deinterleaver 153 performs frequency deinterleaving for each symbol on the symbol from the frame management unit 152 and supplies the symbol to the QAM decoder 154.

  The QAM decoder 154 performs demapping (signal point constellation decoding) on the symbol (symbol arranged at the signal point) from the frequency deinterleaver 153 to perform orthogonal demodulation, and the resulting data (LDPC code) is converted into the LDPC decoder. (LDPC decoder) 155.

  The LDPC decoder 155 performs LDPC decoding of the LDPC code from the QAM decoder 154 and supplies LDPC target data (here, BCH code) obtained as a result to a BCH decoder 156.

  The BCH decoder 156 performs BCH decoding of the LDPC target data from the LDPC decoder 155 and outputs control data (signaling) obtained as a result.

  On the other hand, the frequency deinterleaver 161 performs frequency deinterleaving for each symbol on the symbol from the frame management unit 152 and supplies the symbol to the MISO / MIMO decoder 162.

  The MISO / MIMO decoder 162 performs space-time decoding of data (symbols) from the frequency deinterleaver 161 and supplies it to a time deinterleaver 163.

  The time deinterleaver 163 performs time deinterleaving for each symbol on the data (symbol) from the MISO / MIMO decoder 162 and supplies the data to a QAM decoder 164.

  The QAM decoder 164 performs demapping (signal point arrangement decoding) on the symbol (symbol arranged at the signal point) from the time deinterleaver 163 to perform orthogonal demodulation, and the resulting data (symbol) is subjected to bit deinterlacing. The data is supplied to a leaver (Bit Deinterleaver) 165.

  The bit deinterleaver 165 performs bit deinterleaving on the data (symbol) from the QAM decoder 164 and supplies the LDPC code obtained as a result to the LDPC decoder 166.

  The LDPC decoder 166 performs LDPC decoding of the LDPC code from the bit deinterleaver 165 and supplies LDPC target data (here, BCH code) obtained as a result to the BCH decoder 167.

  The BCH decoder 167 performs BCH decoding of the LDPC target data from the LDPC decoder 155, and supplies data obtained as a result to a BB descrambler (BB DeScrambler) 168.

  The BB descrambler 168 performs energy despreading processing on the data from the BCH decoder 167 and supplies the data obtained as a result to a null deletion unit (Null Deletion) 169.

  The null deletion unit 169 deletes the null inserted by the padder 112 in FIG. 8 from the data from the BB descrambler 168 and supplies the null to the demultiplexer 170.

  The demultiplexer 170 separates each of one or more streams (target data) multiplexed in the data from the null deletion unit 169, and outputs the result as an output stream (Output stream).

  FIG. 137 is a block diagram illustrating a configuration example of the bit deinterleaver 165 in FIG. 136.

  The bit deinterleaver 165 includes a multiplexer (MUX) 54 and a column twist deinterleaver 55, and performs (bit) deinterleaving of the symbol bits of the symbols from the QAM decoder 164 (FIG. 136).

  That is, the multiplexer 54 replaces the symbol bit of the symbol from the QAM decoder 164 by the reverse replacement process (reverse process of the replacement process) corresponding to the replacement process performed by the demultiplexer 25 of FIG. A reverse permutation process is performed to return the position of the code bit (symbol bit) of the LDPC code to the original position, and the resulting LDPC code is supplied to the column twist deinterleaver 55.

  The column twist deinterleaver 55 targets the LDPC code from the multiplexer 54, and corresponds to the column twist interleave as the rearrangement process performed by the column twist interleaver 24 of FIG. Processing), that is, column twist deinterleaving, for example, as reverse rearrangement processing for returning the code bits of LDPC codes whose rearrangement has been changed by column twist interleaving as rearrangement processing.

  Specifically, the column twist deinterleaver 55 writes the code bit of the LDPC code to the memory for deinterleaving configured similarly to the memory 31 shown in FIG. Perform column twist deinterleaving.

  However, in the column twist deinterleaver 55, the code bit is written in the row direction of the deinterleave memory using the read address at the time of reading the code bit from the memory 31 as the write address. The sign bit is read out in the column direction of the deinterleave memory using the write address at the time of writing the sign bit to the memory 31 as the read address.

  The LDPC code obtained as a result of the column twist deinterleave is supplied from the column twist deinterleaver 55 to the LDPC decoder 166.

  Here, the LDPC code supplied from the QAM decoder 164 to the bit deinterleaver 165 is subjected to parity interleaving, column twist interleaving, and replacement processing in that order. In the bit deinterleaver 165, however, Only reverse permutation processing corresponding to permutation processing and column twist deinterleaving corresponding to column twist interleaving are performed, and therefore, parity deinterleaving corresponding to parity interleaving (reverse processing of parity interleaving), ie, parity interleaving is performed. Parity deinterleaving is not performed to return the code bits of the LDPC code whose code has been changed to the original order.

  Therefore, from the bit deinterleaver 165 (the column twist deinterleaver 55) to the LDPC decoder 166, the reverse permutation process and the column twist deinterleave are performed, and the LDPC code not subjected to the parity deinterleave Is supplied.

  The LDPC decoder 166 performs LDPC decoding of the LDPC code from the bit deinterleaver 165, and at least performs column replacement corresponding to parity interleaving on the parity check matrix H used by the LDPC encoder 115 in FIG. 8 for LDPC encoding. The conversion check matrix obtained is used, and the resulting data is output as the decoding result of the LDPC target data.

  FIG. 138 is a flowchart for describing processing performed by the QAM decoder 164, the bit deinterleaver 165, and the LDPC decoder 166 of FIG.

  In step S111, the QAM decoder 164 demaps and orthogonally demodulates symbols (symbols mapped to signal points) from the time deinterleaver 163, and supplies them to the bit deinterleaver 165. Proceed to

  In step S112, the bit deinterleaver 165 performs deinterleaving (bit deinterleaving) of the symbol bits of the symbols from the QAM decoder 164, and the process proceeds to step S113.

  That is, in step S112, in the bit deinterleaver 165, the multiplexer 54 performs a reverse permutation process on the symbol bits of the symbols from the QAM decoder 164, and converts the code bits of the LDPC code obtained as a result of This is supplied to the interleaver 55.

  The column twist deinterleaver 55 performs column twist deinterleaving on the LDPC code from the multiplexer 54 and supplies the LDPC code obtained as a result to the LDPC decoder 166.

  In step S113, the LDPC decoder 166 performs LDPC decoding of the LDPC code from the column twist deinterleaver 55, and a column corresponding to parity interleaving with respect to the parity check matrix H used by the LDPC encoder 115 in FIG. 8 for LDPC encoding. The conversion check matrix obtained by performing at least the replacement is performed, and the data obtained as a result is output to the BCH decoder 167 as the decoding result of the LDPC target data.

  In FIG. 137, as in the case of FIG. 9, for convenience of explanation, the multiplexer 54 that performs reverse permutation processing and the column twist deinterleaver 55 that performs column twist deinterleaving are configured separately. However, the multiplexer 54 and the column twist deinterleaver 55 can be configured integrally.

  Further, in the case where column twist interleaving is not performed in the bit interleaver 116 in FIG. 9, the column twist deinterleaver 55 need not be provided in the bit deinterleaver 165 in FIG. 137.

  Next, LDPC decoding performed by the LDPC decoder 166 of FIG. 136 will be further described.

  In the LDPC decoder 166 of FIG. 136, as described above, the reverse permutation process and the column twist deinterleave from the column twist deinterleaver 55 are performed, and the LDPC code of the LDPC code not subjected to the parity deinterleave is performed. Decoding is performed using a transform parity check matrix obtained by performing at least column replacement corresponding to parity interleaving on parity check matrix H for parity check matrix H used by LDPC encoder 115 in FIG.

  Here, by performing LDPC decoding using a transform parity check matrix, LDPC decoding that can suppress the operating frequency to a sufficiently realizable range while suppressing the circuit scale has been proposed (for example, , See Patent No. 4224777).

  First, LDPC decoding using a transform parity check matrix, which has been proposed previously, will be described with reference to FIGS. 139 to 142.

  FIG. 139 illustrates an example of a parity check matrix H of an LDPC code having a code length N of 90 and an encoding rate of 2/3.

  In FIG. 139 (also in FIGS. 140 and 141 described later), 0 is represented by a period (.).

  In parity check matrix H in FIG. 139, the parity matrix has a staircase structure.

  FIG. 140 shows a parity check matrix H ′ obtained by subjecting the parity check matrix H of FIG. 139 to row replacement of equation (11) and column replacement of equation (12).

Line replacement: 6s + t + 1 line → 5t + s + 1 line
(11)

Column replacement: 6x + y + 61st column → 5y + x + 61th column
(12)

  However, in the formulas (11) and (12), s, t, x, and y are integers in the range of 0 ≦ s <5, 0 ≦ t <6, 0 ≦ x <5, 0 ≦ t <6, respectively. It is.

  According to the row permutation of equation (11), the first, seventh, thirteenth, nineteenth and twenty-fifth rows, which are divided by six and the remainder is 1, The second, eighth, eighth, ninth, and tenth lines that are divided by the remainder of 2 are replaced with the sixth, seventh, eighth, ninth, and tenth lines, respectively.

  Further, according to the column replacement of the equation (12), the 61st column, the 61st column (parity matrix) and the 61st column, the 67th column, the 73rd column, the 79th column, and the 85th column whose remainder is 1 are divided by 61, respectively. , 62, 63, 64, and 65, the 62, 68, 74, 80, and 86 columns, which are divided by 6 and have a remainder of 2, are called 66, 67, 68, 69, and 70 columns, respectively. The replacement is performed accordingly.

  In this way, the matrix obtained by performing row and column replacement on the parity check matrix H in FIG. 139 is the parity check matrix H ′ in FIG.

  Here, even if row replacement of parity check matrix H is performed, the arrangement of code bits of the LDPC code is not affected.

  Also, the column replacement in equation (12) is the above-described information length K of parity interleaving for interleaving the K + qx + y + 1-th code bit at the position of the K + Py + x + 1-th code bit. , 60, the number of columns P of the cyclic structure unit is 5, and the divisor q (= M / P) of the parity length M (here, 30) is 6, which corresponds to parity interleaving.

140 is the same as Equation (12) for the LDPC code of the check matrix (hereinafter, appropriately referred to as the original check matrix) H in FIG. When multiplied by the permuted one, a zero vector is output. That is, if the row vector obtained by performing column substitution of Expression (12) on the row vector c as the LDPC code (one codeword) of the original check matrix H is expressed as c ′, the property of the check matrix , Hc ^T is a 0 vector, and H'c ' ^T is naturally a 0 vector.

  From the above, the conversion parity check matrix H ′ of FIG. 140 is a parity check matrix of the LDPC code c ′ obtained by performing the column replacement of the equation (12) on the LDPC code c of the original parity check matrix H.

  Therefore, the column replacement of Equation (12) is performed on the LDPC code c of the original parity check matrix H, and the LDPC code c ′ after the column replacement is decoded using the transform parity check matrix H ′ of FIG. 140 (LDPC decoding). Then, the decoding result similar to the case of decoding the LDPC code of the original parity check matrix H using the parity check matrix H is obtained by performing the inverse permutation of the column permutation of the equation (12) on the decoding result. Can do.

  FIG. 141 shows the transform parity check matrix H ′ of FIG. 140 with an interval in 5 × 5 matrix units.

  In FIG. 141, the transform parity check matrix H ′ is a 5 × 5 unit matrix, a matrix in which one or more of the unit matrices are 0 (hereinafter referred to as a quasi-unit matrix as appropriate), a unit matrix or a quasi A sum of two or more of a unit matrix, a quasi-unit matrix, and a shift matrix (hereinafter referred to as sum matrix as appropriate), which is a cyclic shift of the unit matrix (hereinafter referred to as shift matrix), 5 It is represented by a combination of × 5 zero matrices.

  141 can be said to be composed of a 5 × 5 unit matrix, quasi-unit matrix, shift matrix, sum matrix, and zero matrix. Therefore, these 5 × 5 matrices constituting the conversion check matrix H ′ are hereinafter referred to as “configuration matrices” as appropriate.

  For decoding an LDPC code represented by a parity check matrix represented by a P × P configuration matrix, an architecture that simultaneously performs P check node operations and P variable node operations can be used.

  FIG. 142 is a block diagram illustrating a configuration example of a decoding device that performs such decoding.

  That is, FIG. 142 performs decoding of an LDPC code using at least the transformed parity check matrix H ′ of FIG. 141 obtained by performing column replacement of Equation (12) on the original parity check matrix H of FIG. 2 shows a configuration example of a decoding device.

Decoding device in FIG. 142, six FIFO 300 ₁ to the edge data storage memory 300 consisting of 300 _6, FIFO 300 ₁ to the selector 301 for selecting 300 _6, a check node calculation section 302,2 one cyclic shift circuit 303 and 308, 18 FIFOs 304 ₁ to 304 ₁₈ the edge data storage memory 304 consisting of, FIFOs 304 ₁ to 304 ₁₈ to select the selector 305, the reception data memory 306 for storing received data, a variable node calculation section 307, a decoded word calculation section 309 The received data rearrangement unit 310 and the decoded data rearrangement unit 311.

  First, a method for storing data in the branch data storage memories 300 and 304 will be described.

The branch data storage memory 300 is composed of six FIFOs 300 ₁ to 300 ₆ that are numbers obtained by dividing the number of rows 30 of the conversion check matrix H ′ of FIG. 141 by the number of rows 5 of the configuration matrix. The FIFO 300 _y (y = 1, 2,..., 6) includes a plurality of stages of storage areas, and the storage areas of each stage correspond to five branches that are the number of rows and the number of columns of the configuration matrix. Messages can be read and written simultaneously. Further, the number of stages of the storage area of the FIFO 300 _y is 9, which is the maximum number of 1s (Humming weights) in the row direction of the conversion parity check matrix in FIG.

The FIFO300 _1, data corresponding to a position of the first row of the conversion parity check matrix H of FIG. 141 'to the fifth row (messages v _i from variable nodes) were packed in each line both in the lateral direction Stored in the form (ignoring 0). That is, if the j-th row and the i-th column are represented as (j, i), the storage area of the first stage of the FIFO 300 ₁ includes (1, 1) to (5, 5) of the conversion parity check matrix H ′. The data corresponding to the position of 1 in the 5 × 5 unit matrix is stored. In the second storage area, the shift check matrix H '(1,21) to (5,25) shift matrix (shift matrix obtained by cyclically shifting three 5 × 5 unit matrices to the right by 3) The data corresponding to the 1 position is stored. Similarly, the third to eighth storage areas store data in association with the conversion parity check matrix H ′. In the storage area of the ninth stage, 1 in the first row of the 5 × 5 unit matrix is replaced with 0 in the shift matrix from (1,86) to (5,90) of the conversion check matrix H ′. Data corresponding to one position of the shift matrix that has been shifted by one to the left.

The FIFO300 _2, the data corresponding to the first position from the sixth row of the conversion parity check matrix H of FIG. 141 'until line 10 is stored. In other words, the storage area of the first stage of the FIFO 300 ₂ has a sum matrix of (6,1) to (10,5) of the conversion check matrix H ′ (5 × 5 unit matrix cyclically shifted by one to the right) The data corresponding to the position of 1 of the first shift matrix constituting the first shift matrix and the sum matrix which is the sum of the second shift matrix cyclically shifted by two to the right is stored. The second storage area stores data corresponding to position 1 of the second shift matrix constituting the sum matrix of (6,1) to (10,5) of the conversion check matrix H ′. The

That is, for a constituent matrix having a weight of 2 or more, the constituent matrix is a P × P unit matrix having a weight of 1, a quasi-unit matrix in which one or more of the elements of the unit matrix are 0, or Data corresponding to the unit matrix, quasi-unit matrix, or 1 position of the shift matrix when the unit matrix or quasi-unit matrix is expressed in the form of a plurality of shift matrices obtained by cyclically shifting the unit matrix or quasi-unit matrix (Messages corresponding to branches belonging to the unit matrix, quasi-unit matrix, or shift matrix) are stored in the same address (the same FIFO among the FIFOs 300 ₁ to 300 ₆ ).

  Hereinafter, the third to ninth storage areas are also stored in association with the conversion parity check matrix H ′.

Similarly, the FIFOs 300 ₃ to 300 ₆ store data in association with the conversion check matrix H ′.

The branch data storage memory 304 includes 18 FIFOs 304 ₁ to 304 ₁₈ obtained by dividing the number of columns 90 of the conversion check matrix H ′ by 5 that is the number of columns of the configuration matrix. The FIFO 304 _x (x = 1, 2,..., 18) is composed of a plurality of stages of storage areas. For each stage of storage area, five branches that are the number of rows and the number of columns of the transformation configuration matrix H ′. The messages corresponding to can be simultaneously read and written.

The FIFO304 _1, the data corresponding to the first position from the first row of the conversion parity check matrix H of FIG. 141 'to the fifth column (messages u _j from the check nodes) are packed vertically in each column both Stored in the form (ignoring 0). That is, data corresponding to the position of 1 in the 5 × 5 unit matrix of (1, 1) to (5, 5) of the conversion parity check matrix H ′ is stored in the first-stage storage area of the FIFO 304 ₁ . . In the second storage area, the sum matrix of (6,1) to (10,5) of the conversion check matrix H ′ (the first shift obtained by cyclically shifting one 5 × 5 unit matrix to the right by one) The data corresponding to the position of 1 of the first shift matrix constituting the matrix and the sum matrix that is the sum of the matrix and the second shift matrix cyclically shifted by two to the right is stored. The third storage area stores data corresponding to position 1 of the second shift matrix constituting the sum matrix of (6,1) to (10,5) of the conversion check matrix H ′. The

That is, for a constituent matrix having a weight of 2 or more, the constituent matrix is a P × P unit matrix having a weight of 1, a quasi-unit matrix in which one or more of the elements of the unit matrix are 0, or Data corresponding to the unit matrix, quasi-unit matrix, or 1 position of the shift matrix when the unit matrix or quasi-unit matrix is expressed in the form of a plurality of shift matrices obtained by cyclically shifting the unit matrix or quasi-unit matrix (identity matrix, the message corresponding to the branch belonging to quasi unit matrix or shift matrix) are stored in the same address (same FIFO from among the FIFOs 304 ₁ to 304 _18).

Hereinafter, data is also stored in the storage areas of the fourth and fifth stages in association with the conversion parity check matrix H ′. The number of stages in the storage area of the FIFO 304 ₁ is 5, which is the maximum number of 1s (Hamming weights) in the row direction in the first to fifth columns of the conversion parity check matrix H ′.

Similarly, the FIFOs 304 ₂ and 304 ₃ store data in association with the conversion parity check matrix H ′, and each has a length (number of stages) of 5. Similarly, the FIFOs 304 ₄ to 304 ₁₂ store data in association with the conversion check matrix H ′, and each has a length of 3. Similarly, the FIFOs 304 ₁₃ to 304 ₁₈ store data in association with the conversion check matrix H ′, and each has a length of 2.

  Next, the operation of the decoding apparatus in FIG. 142 will be described.

The branch data storage memory 300 includes six FIFOs 300 ₁ to 300 ₆ , and information (Matrix) indicating to which row of the conversion check matrix H ′ the five messages D 311 supplied from the preceding cyclic shift circuit 308 belong. according to the data) D312, a FIFO to store the data, select from among the FIFO300 ₁ to 300 _6, will be stored in the order together five messages D311 to the selected FIFO. Also, the edge data storage memory 300, when reading data, sequentially reads five messages D300 ₁ from FIFO 300 _1, supplied to the next stage of the selector 301. The branch data storage memory 300 reads the messages in order from the FIFOs 300 ₂ to 300 ₆ after reading the messages from the FIFO 300 ₁ and supplies them to the selector 301.

The selector 301 selects five messages from the FIFO from which the current data is read out of the FIFOs 300 ₁ to 300 ₆ according to the select signal D301, and supplies the selected message to the check node calculation unit 302 as a message D302.

Check node calculation section 302, 302 ₁ five check node calculator to consist 302 _5, messages D302 (D302 ₁ to D302 ₅₎ supplied through the selector 301 using (messages v _i of the expression (7)), A check node operation is performed according to Equation (7), and five messages D303 (D303 ₁ to D303 ₅ ) (message u _{j in} Equation (7)) obtained as a result of the check node operation are supplied to the cyclic shift circuit 303.

The cyclic shift circuit 303 is obtained by cyclically shifting the five unit messages D303 ₁ to D303 ₅ obtained by the check node calculation unit 302 from the unit matrix whose corresponding branch is the original in the conversion check matrix H ′. Based on such information (Matrix data) D305, a cyclic shift is performed, and the result is supplied as message D304 to branch data storage memory 304.

The branch data storage memory 304 includes 18 FIFOs 304 ₁ to 304 ₁₈ , and according to information D 305 indicating which row of the conversion check matrix H ′ the five messages D 304 supplied from the preceding cyclic shift circuit 303 belong to. The FIFO for storing data is selected from the FIFOs 304 ₁ to 304 ₁₈ , and the five messages D 304 are collectively stored in the selected FIFO in order. Also, the edge data storage memory 304, when reading data, sequentially reads five messages D306 ₁ from FIFOs 304 _1, supplied to the next stage of the selector 305. Edge data storage memory 304, after completion of the data read from the FIFOs 304 _1, from FIFOs 304 ₂ to 304 _18, sequentially reads out a message, to the selector 305.

The selector 305 selects five messages from the FIFO from which the current data is read out of the FIFOs 304 ₁ to 304 ₁₈ in accordance with the select signal D307, and as the message D308, the variable node calculation unit 307 and the decoded word calculation unit 309.

  On the other hand, the received data rearrangement unit 310 rearranges the LDPC codes D313 received through the communication path by performing column replacement of Expression (12), and supplies the rearranged data to the received data memory 306 as received data D314. The reception data memory 306 calculates and stores reception LLRs (log likelihood ratios) from the reception data D314 supplied from the reception data rearrangement unit 310, and collects the reception LLRs by five as reception values D309. The variable node calculation unit 307 and the decoded word calculation unit 309 are supplied.

The variable node calculation unit 307 includes five variable node calculators 307 ₁ to 307 ₅ , a message D308 (D308 ₁ to D308 ₅ ) (message u _{j in} Expression (1)) supplied through the selector 305, and received data. using five reception values supplied from use memory 306 D309 (formula (reception values u _0i 1)), the variable node operation according to equation (1), to the message D310 (D310 ₁ not obtained as a result of the calculation D310 ₅ ) (message v _{i in} equation (1)) is supplied to the cyclic shift circuit 308.

The cyclic shift circuit 308 determines how many times the messages D310 ₁ to D310 ₅ calculated by the variable node calculation unit 307 are cyclically shifted from the original unit matrix in the transformation check matrix H ′. A cyclic shift is performed based on the information, and the result is supplied to the branch data storage memory 300 as a message D311.

  One round of the above operation makes it possible to perform one decoding of the LDPC code. 142 decodes the LDPC code a predetermined number of times, and then obtains and outputs a final decoding result in the decoded word calculation unit 309 and the decoded data rearrangement unit 311.

That is, the decoded word calculation unit 309 includes five decoded word calculators 309 ₁ to 309 ₅ , and five messages D308 (D308 ₁ to D308 ₅ ) (message u _{j in} Expression (5)) output from the selector 305 and Using the five reception values D309 (the reception value u _{0i in} equation (5)) supplied from the reception data memory 306, the decoding result (decoding) based on equation (5) is used as the final stage of multiple times of decoding. And the decoded data D315 obtained as a result is supplied to the decoded data rearranging unit 311.

  The decoded data rearranging unit 311 rearranges the order of the decoded data D315 supplied from the decoded word calculation unit 309 by performing the column replacement in the formula (12), and obtains the final decoding result. Output as D316.

  As described above, one or both of row permutation and column permutation is applied to the parity check matrix (original parity check matrix), and one or more of the P × P unit matrix and one of its elements is set to 0. A quasi-unit matrix, a unit matrix or a shift matrix obtained by cyclically shifting a quasi-unit matrix, a unit matrix, a quasi-unit matrix, a sum matrix that is a sum of shift matrices, or a combination of P × P 0 matrices, By converting to a parity check matrix (conversion parity check matrix) that can be represented by a combination of component matrices, it is possible to adopt an architecture that decodes LDPC codes and performs P check node operations and variable node operations simultaneously. Thus, a large number of iterative decoding can be performed while suppressing the operation frequency to a range that can be realized by performing P node operations simultaneously.

  The LDPC decoder 166 constituting the receiving device 12 in FIG. 136 performs LDPC decoding by simultaneously performing P check node operations and P variable node operations, as in the decoding device in FIG. 142.

  That is, for simplicity of explanation, the parity check matrix of the LDPC code output from the LDPC encoder 115 constituting the transmission apparatus 11 of FIG. 8 is, for example, the parity matrix shown in FIG. , The parity interleaver 23 of the transmission apparatus 11 interleaves the K + qx + y + 1-th code bit at the position of the K + Py + x + 1-th code bit. However, the information length K is set to 60, the column number P of the cyclic structure unit is set to 5, and the divisor q (= M / P) of the parity length M is set to 6.

  As described above, since this parity interleaving corresponds to the column replacement of equation (12), the LDPC decoder 166 does not need to perform column replacement of equation (12).

  For this reason, in the receiving apparatus 12 of FIG. 136, as described above, the column twist deinterleaver 55 sends the LDPC code to which the parity deinterleave has not been performed, that is, the sequence of Expression (12). The LDPC code in a state where the replacement is performed is supplied, and the LDPC decoder 166 performs the same processing as that of the decoding device in FIG. 142 except that the column replacement of the equation (12) is not performed.

  That is, FIG. 143 shows a configuration example of the LDPC decoder 166 of FIG.

  In FIG. 143, the LDPC decoder 166 is configured in the same way as the decoding device of FIG. 142 except that the received data rearrangement unit 310 of FIG. 142 is not provided, and the column replacement of equation (12) is performed. Except for the above, the same processing as that of the decoding device of FIG. 142 is performed, and thus the description thereof is omitted.

  As described above, since the LDPC decoder 166 can be configured without the received data rearranging unit 310, the scale can be reduced as compared with the decoding apparatus of FIG.

  In FIG. 139 to FIG. 143, for simplicity of explanation, the code length N of the LDPC code is 90, the information length K is 60, the number of columns in the unit of the cyclic structure (the number of rows and the number of columns of the constituent matrix). ) P is 5 and the divisor q (= M / P) of the parity length M is 6, respectively, but the code length N, the information length K, the number of columns P of the cyclic structure unit, and the divisor q (= Each of (M / P) is not limited to the values described above.

  That is, in the transmission apparatus 11 of FIG. 8, the LDPC encoder 115 outputs, for example, a code length N of 64800, 16200, 4320, etc., an information length K of N-Pq (= NM), and a unit of a cyclic structure. The number of columns P is 360 or 60, and the divisor q is M / P. The LDPC decoder 166 of FIG. 143 uses the check node operation and variable node for such an LDPC code. It can also be applied to LDPC decoding by performing P operations simultaneously.

  FIG. 144 is a diagram for explaining processing of the multiplexer 54 constituting the bit deinterleaver 165 of FIG.

  That is, A in FIG. 144 shows a functional configuration example of the multiplexer 54.

  The multiplexer 54 includes a reverse switching unit 1001 and a memory 1002.

  The multiplexer 54 performs reverse replacement processing (reverse processing of replacement processing) corresponding to the replacement processing performed by the demultiplexer 25 of the transmission device 11 on the symbol bit of the symbol supplied from the preceding stage QAM decoder 164, that is, replacement. A reverse replacement process is performed to return the position of the code bit (symbol bit) of the LDPC code replaced by the process to the original position, and the resulting LDPC code is supplied to the subsequent column twist deinterleaver 55.

That is, in the multiplexer 54, the reverse switching unit 1001 includes the symbol bits y ₀ , y ₁ ,..., Y _{mb−1 of the} b symbols in units of (consecutive) b symbols. Is supplied.

The reverse permutation unit 1001 replaces the mb symbol bits y ₀ to y _mb−1 with the original mb bit code bits b ₀ , b _{1 ,.} Reverse replacement is performed to return to the order of the sign bits b ₀ to b _mb−1 before the replacement in the replacement unit 32 constituting the multiplexer 25, and the resulting mb bit code bits b ₀ to b _{mb− 1} is output.

  The memory 1002 stores mb bits in the row (horizontal) direction and N / (mb in the column (vertical) direction, similarly to the memory 31 constituting the demultiplexer 25 on the transmission device 11 side. ) It has a storage capacity for storing bits. That is, the memory 1002 includes mb columns that store N / (mb) bits.

  However, in the memory 1002, the code bits of the LDPC code output from the reverse switching unit 1001 are written in the direction in which the code bits are read from the memory 31 of the demultiplexer 25 of the transmission device 11. The sign bit written in the memory 1002 is read in the direction in which the sign bit is written.

  That is, in the multiplexer 54 of the receiving device 12, as shown in A of FIG. 144, the code bit of the LDPC code output from the reverse switching unit 1001 is written in the row direction in units of mb bits. It is performed sequentially from the eye to the lower line.

  When the writing of the code bits for one code length is completed, the multiplexer 54 reads the code bits from the memory 1002 in the column direction and supplies them to the column twist deinterleaver 55 in the subsequent stage.

  Here, FIG. 144B is a diagram illustrating reading of the sign bit from the memory 1002.

  The multiplexer 54 reads the code bits of the LDPC code from the top to the bottom (column direction) of the columns constituting the memory 1002 from the left to the right columns.

  FIG. 145 is a diagram for explaining processing of the column twist deinterleaver 55 configuring the bit deinterleaver 165 of FIG.

  That is, FIG. 145 shows a configuration example of the memory 1002 of the multiplexer 54.

  The memory 1002 stores mb bits in the column (vertical) direction and has a storage capacity for storing N / (mb) bits in the row (horizontal) direction, and includes mb columns.

  The column twist deinterleaver 55 performs column twist deinterleaving by controlling the read start position when writing the code bits of the LDPC code in the row direction and reading in the column direction to the memory 1002.

  That is, in the column twist deinterleaver 55, the code bit sequence rearranged by the column twist interleave is appropriately changed by appropriately changing the read start position where the code bit read is started for each of the plurality of columns. A reverse rearrangement process for returning the sequence is performed.

  Here, FIG. 145 illustrates a configuration example of the memory 1002 when the modulation scheme is 16QAM and the multiple b is 1 as described in FIG. Therefore, the number of bits m of one symbol is 4 bits, and the memory 1002 is composed of 4 (= mb) columns.

  The column twist deinterleaver 55 sequentially writes the code bits of the LDPC code output from the switching unit 1001 in the row direction instead of the multiplexer 54 from the first row to the lower row of the memory 1002.

  When the writing of the code bits for one code length is completed, the column twist deinterleaver 55 reads the code bits from the top to the bottom (column direction) from the top of the memory 1002 in the column from the left to the right. Do towards.

  However, the column twist deinterleaver 55 reads the code bit from the memory 1002 with the write start position where the column twist interleaver 24 on the transmission apparatus 11 side writes the code bit as the code bit read start position. .

  That is, if the address at the top (top) position of each column is 0 and the address at each position in the column direction is expressed as an ascending integer, the modulation method is 16QAM and the multiple b is 1. , The column twist deinterleaver 55 sets the read start position for the leftmost column as the position where the address is 0, and the read start position for the second column (from the left). In the third column, the read start position is the position of the address 4, and for the fourth column, the read start position is the position of the address 7.

  For the column where the read start position is other than the position where the address is 0, after reading the sign bit to the lowest position, it returns to the beginning (position where the address is 0) and starts reading. Reading up to the position immediately before the position is performed. Thereafter, reading from the next (right) column is performed.

  By performing the column twist deinterleaving as described above, the arrangement of the code bits rearranged by the column twist interleaving is returned to the original order.

  FIG. 146 is a block diagram illustrating another configuration example of the bit deinterleaver 165 in FIG. 136.

  In the figure, portions corresponding to those in FIG. 137 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  That is, the bit deinterleaver 165 in FIG. 146 is configured in the same manner as in FIG. 137 except that a parity deinterleaver 1011 is newly provided.

  In FIG. 146, the bit deinterleaver 165 includes a multiplexer (MUX) 54, a column twist deinterleaver 55, and a parity deinterleaver 1011. The bit deinterleaver 165 performs bit deinterleaving of code bits of the LDPC code from the QAM decoder 164. Do.

  That is, the multiplexer 54 replaces the LDPC code from the QAM decoder 164 by reverse replacement processing (reverse processing of the replacement processing) corresponding to the replacement processing performed by the demultiplexer 25 of the transmission device 11, that is, the replacement processing. Then, a reverse permutation process is performed to return the position of the code bit to the original position, and the resulting LDPC code is supplied to the column twist deinterleaver 55.

  The column twist deinterleaver 55 performs column twist deinterleave corresponding to the column twist interleave as the rearrangement process performed by the column twist interleaver 24 of the transmission apparatus 11 for the LDPC code from the multiplexer 54.

  The LDPC code obtained as a result of the column twist deinterleave is supplied from the column twist deinterleaver 55 to the parity deinterleaver 1011.

  The parity deinterleaver 1011 targets the code bit after the column twist deinterleave in the column twist deinterleaver 55, and performs parity deinterleave corresponding to the parity interleave performed by the parity interleaver 23 of the transmission device 11 (inverse of parity interleave). In other words, parity deinterleaving is performed to return the code bits of the LDPC code whose arrangement has been changed by parity interleaving to the original order.

  The LDPC code obtained as a result of parity deinterleaving is supplied from the parity deinterleaver 1011 to the LDPC decoder 166.

  Therefore, in the bit deinterleaver 165 of FIG. 146, the LDPC decoder 166 has the LDPC code subjected to the reverse permutation process, the column twist deinterleave, and the parity deinterleave, that is, the LDPC encoding according to the check matrix H. The LDPC code obtained by is supplied.

  The LDPC decoder 166 performs LDPC decoding of the LDPC code from the bit deinterleaver 165, parity check on the parity check matrix H used by the LDPC encoder 115 of the transmission device 11 for LDPC encoding, or the parity check interleaving H Is performed using a conversion parity check matrix obtained by performing at least column replacement corresponding to the above, and data obtained as a result is output as a decoding result of LDPC target data.

  Here, in FIG. 146, since the LDPC code obtained by LDPC encoding according to the check matrix H is supplied from the bit deinterleaver 165 (its parity deinterleaver 1011) to the LDPC decoder 166, the LDPC When the LDPC decoding of the code is performed using the parity check matrix H itself used for the LDPC encoding by the LDPC encoder 115 of the transmission apparatus 11, the LDPC decoder 166, for example, a message (check node message, variable node message) Decoding device that performs LDPC decoding by full serial decoding method that sequentially performs the operation of one node at a time, and full parallel decoding that performs message operation for all nodes simultaneously (in parallel) A decoding apparatus that performs LDPC decoding by a decoding method can be used.

  Also, LDPC decoder 166 performs LDPC decoding of an LDPC code, and a transform check obtained by performing at least column replacement corresponding to parity interleaving on parity check matrix H used by LDPC encoder 115 of transmitting apparatus 11 for LDPC encoding When performing using a matrix, the LDPC decoder 166 is an architecture decoding device that simultaneously performs P (or a divisor other than 1 of P) check node operations and variable node operations. The decoding apparatus (FIG. 142) having the received data rearrangement unit 310 that rearranges the code bits of the LDPC code by performing column replacement similar to the column replacement for obtaining the parity check matrix on the LDPC code. it can.

  In FIG. 146, for convenience of explanation, a multiplexer 54 that performs reverse permutation processing, a column twist deinterleaver 55 that performs column twist deinterleaving, and a parity deinterleaver 1011 that performs parity deinterleaving are separately illustrated. Although two or more of the multiplexer 54, the column twist deinterleaver 55, and the parity deinterleaver 1011 are configured, the parity interleaver 23, the column twist interleaver 24, and the demultiplexer 25 of the transmission device 11 Similarly, it can be configured integrally.

  [Configuration example of receiving system]

  FIG. 147 is a block diagram illustrating a first configuration example of a receiving system to which the receiving device 12 can be applied.

  In FIG. 147, the reception system includes an acquisition unit 1101, a transmission path decoding processing unit 1102, and an information source decoding processing unit 1103.

  The acquisition unit 1101 obtains a signal including an LDPC code obtained by LDPC encoding at least LDPC target data such as program image data and audio data, for example, terrestrial digital broadcasting, satellite digital broadcasting, CATV network, the Internet, and the like. Obtained via a transmission line (not shown) such as a network of the network and supplied to the transmission line decoding processing unit 1102.

  Here, when the signal acquired by the acquisition unit 1101 is broadcast from a broadcasting station via a terrestrial wave, a satellite wave, a CATV (Cable Television) network, or the like, the acquisition unit 1101 includes a tuner, Consists of STB (Set Top Box) etc. In addition, when the signal acquired by the acquisition unit 1101 is transmitted by multicast such as IPTV (Internet Protocol Television) from a web server, for example, the acquisition unit 11 includes, for example, a NIC (Network Interface Card) or the like. Network I / F (Interface).

  The transmission path decoding processing unit 1102 corresponds to the receiving device 12. The transmission path decoding processing unit 1102 performs a transmission path decoding process including at least processing for correcting an error occurring in the transmission path on the signal acquired by the acquisition unit 1101 via the transmission path, and obtains a signal obtained as a result thereof. The information is supplied to the information source decoding processing unit 1103.

  That is, the signal acquired by the acquisition unit 1101 via the transmission path is a signal obtained by performing at least error correction coding for correcting an error occurring in the transmission path. The transmission path decoding processing unit 1102 Such a signal is subjected to transmission path decoding processing such as error correction processing, for example.

  Here, examples of error correction coding include LDPC coding and BCH coding. Here, at least LDPC encoding is performed as error correction encoding.

  Also, the transmission path decoding process may include demodulation of the modulation signal.

  The information source decoding processing unit 1103 performs an information source decoding process including at least a process of expanding the compressed information into the original information on the signal subjected to the transmission path decoding process.

  That is, the signal acquired by the acquisition unit 1101 via the transmission path may be subjected to compression coding for compressing information in order to reduce the amount of data such as images and sounds as information. In this case, the information source decoding processing unit 1103 performs information source decoding processing such as processing (decompression processing) for expanding the compressed information to the original information on the signal subjected to the transmission path decoding processing.

  If the signal acquired by the acquisition unit 1101 via the transmission path is not compressed and encoded, the information source decoding processing unit 1103 performs a process of expanding the compressed information to the original information. I will not.

  Here, examples of the decompression process include MPEG decoding. The transmission path decoding process may include descrambling and the like in addition to the decompression process.

  In the reception system configured as described above, in the acquisition unit 1101, for example, compression coding such as MPEG coding is performed on data such as images and sound, and further error correction codes such as LDPC coding are performed. The processed signal is acquired via the transmission path and supplied to the transmission path decoding processing unit 1102.

  In the transmission path decoding processing unit 1102, for example, processing similar to that performed by the orthogonal demodulation unit 51, QAM decoder 164, bit deinterleaver 165, and LDPC decoder 166 (or LDPC decoder 166) is performed on the signal from the acquisition unit 1101. The signal obtained as a result of the transmission path decoding process is supplied to the information source decoding processing unit 1103.

  The information source decoding processing unit 1103 performs information source decoding processing such as MPEG decoding on the signal from the transmission path decoding processing unit 1102 and outputs the resulting image or sound.

  The reception system of FIG. 147 as described above can be applied to, for example, a television tuner that receives a television broadcast as a digital broadcast.

  The acquisition unit 1101, the transmission path decoding processing unit 1102, and the information source decoding processing unit 1103 are each configured as one independent device (hardware (IC (Integrated Circuit)) or the like) or software module). Is possible.

  Further, regarding the acquisition unit 1101, the transmission path decoding processing unit 1102, and the information source decoding processing unit 1103, the set of the acquisition unit 1101 and the transmission path decoding processing unit 1102 or the transmission path decoding processing unit 1102 and the information source decoding process The set of the unit 1103, the acquisition unit 1101, the transmission path decoding processing unit 1102, and the information source decoding processing unit 1103 can be configured as one independent device.

  FIG. 148 is a block diagram illustrating a second configuration example of the reception system to which the reception device 12 can be applied.

  In the figure, portions corresponding to those in FIG. 147 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  The reception system of FIG. 148 is common to the case of FIG. 147 in that an acquisition unit 1101, a transmission path decoding processing unit 1102, and an information source decoding processing unit 1103 are provided, and an output unit 1111 is newly provided. This is different from the case of FIG.

  The output unit 1111 is, for example, a display device that displays an image or a speaker that outputs audio, and outputs an image, audio, or the like as a signal output from the information source decoding processing unit 1103. That is, the output unit 1111 displays an image or outputs sound.

  The reception system of FIG. 148 as described above can be applied to, for example, a TV (television receiver) that receives a television broadcast as a digital broadcast, a radio receiver that receives a radio broadcast, or the like.

  If the signal acquired by the acquisition unit 1101 has not been subjected to compression coding, the signal output from the transmission path decoding processing unit 1102 is supplied to the output unit 1111.

  FIG. 149 is a block diagram illustrating a third configuration example of the reception system to which the reception device 12 can be applied.

  In the figure, portions corresponding to those in FIG. 147 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  The reception system of FIG. 149 is common to the case of FIG. 147 in that it includes an acquisition unit 1101 and a transmission path decoding processing unit 1102.

  However, the receiving system of FIG. 149 is different from the case of FIG. 147 in that the information source decoding processing unit 1103 is not provided and the recording unit 1121 is newly provided.

  The recording unit 1121 records a signal (for example, TS packet of MPEG TS) output from the transmission path decoding processing unit 1102 on a recording (storage) medium such as an optical disk, a hard disk (magnetic disk), or a flash memory (memory). )

  The reception system of FIG. 149 as described above can be applied to a recorder or the like that records a television broadcast.

  In FIG. 149, the reception system includes an information source decoding processing unit 1103, and the information source decoding processing unit 1103 performs a signal after the information source decoding processing, that is, an image obtained by decoding, Audio can be recorded by the recording unit 1121.

  [One Embodiment of Computer]

  Next, the series of processes described above can be performed by hardware or software. When a series of processing is performed by software, a program constituting the software is installed in a general-purpose computer or the like.

  Therefore, FIG. 150 shows a configuration example of an embodiment of a computer in which a program for executing the above-described series of processing is installed.

  The program can be recorded in advance in a hard disk 705 or a ROM 703 as a recording medium built in the computer.

  Alternatively, the program is stored temporarily on a removable recording medium 711 such as a flexible disk, a CD-ROM (Compact Disc Read Only Memory), an MO (Magneto Optical) disk, a DVD (Digital Versatile Disc), a magnetic disk, or a semiconductor memory. It can be stored permanently (recorded). Such a removable recording medium 711 can be provided as so-called package software.

  The program is installed on the computer from the removable recording medium 711 as described above, or transferred from the download site to the computer via a digital satellite broadcasting artificial satellite, or a LAN (Local Area Network), The program can be transferred to a computer via a network such as the Internet. The computer can receive the program transferred in this way by the communication unit 708 and install it in the built-in hard disk 705.

  The computer includes a CPU (Central Processing Unit) 702. An input / output interface 710 is connected to the CPU 702 via a bus 701, and the CPU 702 operates an input unit 707 including a keyboard, a mouse, a microphone, and the like by the user via the input / output interface 710. When a command is input by being equalized, a program stored in a ROM (Read Only Memory) 703 is executed accordingly. Alternatively, the CPU 702 may be a program stored in the hard disk 705, a program transferred from a satellite or a network, received by the communication unit 708 and installed in the hard disk 705, or a removable recording medium 711 installed in the drive 709. The program read and installed in the hard disk 705 is loaded into a RAM (Random Access Memory) 704 and executed. Thereby, the CPU 702 performs processing according to the above-described flowchart or processing performed by the configuration of the above-described block diagram. Then, the CPU 702 outputs the processing result from the output unit 706 configured with an LCD (Liquid Crystal Display), a speaker, or the like, for example, via the input / output interface 710 or the communication unit 708 as necessary. Transmission and further recording on the hard disk 705 are performed.

  Here, in this specification, the processing steps for describing a program for causing a computer to perform various types of processing do not necessarily have to be processed in time series according to the order described in the flowchart, but in parallel or individually. This includes processing to be executed (for example, parallel processing or processing by an object).

  Further, the program may be processed by a single computer, or may be processed in a distributed manner by a plurality of computers. Furthermore, the program may be transferred to a remote computer and executed.

  The embodiment of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention.

  That is, the LDPC code (its check matrix initial value table) and the like used in the above-described digital broadcasting for mobile terminals can be used in digital broadcasting for fixed terminals and the like.

DESCRIPTION OF SYMBOLS 11 Transmitter, 12 Receiver, 23 Parity interleaver, 24 Column twist interleaver, 25 Demultiplexer, 31 Memory, 32 Replacement part, 54 Multiplexer, 55 Column twist interleaver,
111 mode adaptation / multiplexer, 112 padder, 113 BB scrambler, 114 BCH encoder, 115 LDPC encoder, 116 bit interleaver, 117 QAM encoder, 118 time interleaver, 119 MISO / MIMO encoder, 120 frequency interleaver, 121 BCH encoder , 122 LDPC encoder, 123 QAM encoder, 124 frequency interleaver, 131 frame builder / resource allocation unit 132 OFDM generation unit, 151 OFDM processing unit, 152 frame management unit, 153 frequency deinterleaver, 154 QAM decoder, 155 LDPC decoder, 156 BCH decoder, 161 frequency deinterleaver, 162 MISO / MIMO decoder, 163 time deinterleaver, 164 QAM decoder, 165 bits Deinterleaver, 166 LDPC decoder, 167 BCH decoder, 168 BB descrambler, 169 Null deletion unit, 170 demultiplexer, 300 branch data storage memory, 301 selector, 302 check node calculation unit, 303 cyclic shift circuit, 304 branches Data storage memory, 305 selector, 306 received data memory, 307 variable node calculation unit, 308 cyclic shift circuit, 309 decoded word calculation unit, 310 received data rearrangement unit, 311 decoded data rearrangement unit, 601 encoding process Unit, 602 storage unit, 611 coding rate setting unit, 612 initial value table reading unit, 613 check matrix generation unit, 614 information bit reading unit, 615 coding parity calculation unit, 616 control unit, 701 bus, 702 CPU 703 ROM, 704 RAM, 705 hard disk, 706 output unit, 707 input unit, 708 communication unit, 709 drive, 710 input / output interface, 711 removable recording medium, 1001 reverse switching unit, 1002 memory, 1011 parity deinterleaver, 1101 acquisition 1101 transmission path decoding processing unit 1103 information source decoding processing unit 1111 output unit 1121 recording unit

Claims (12)

LDPC (Low Density Parity Check) code bits are written in the column direction of the storage means for storing in the row direction and the column direction, and the code bits of the LDPC code read in the row direction are used as symbols,
When m bit code bits of 2 bits or more of the LDPC code are transmitted as one symbol,
Column twist interleaving for changing the write start position when the code bits of the LDPC code are written in the column direction of the storage means for each column of the storage means, and rearranging the code bits of the LDPC code It is provided with sorting means to perform as a replacement process,
When the code length of the LDPC code is represented by N bits and the predetermined positive integer is represented by b,
The storage means stores mb bits in the row direction and stores N / (mb) bits in the column direction;
When the sign bit of the mb bits read in the row direction of the storage means is b symbols,
The LDPC code has an encoding rate of 1/4, 1/3, 5/12, 1/2, 7/12, 2/3, or 3/4, and a code length N of 4320 bits. And
The m bits is 2 bits, and the integer b is 1.
The sign bit of the 2 bits of the LDPC code are mapped to one of 2 ² signal points prescribed in a predetermined modulation scheme,
The storage means has two columns for storing 2 × 1 bits in the row direction,
The sorting means is
When the address of the head position in the column direction of the storage means is 0, and the address of each position in the column direction of the storage means is represented by an integer in ascending order,
The write start position of the first column of the two columns of the storage means is the position where the address is 0,
The write start position of the second column of the two columns of the storage means is the position where the address is 60,
The parity check matrix of the LDPC code is based on the parity check matrix initial value table that represents the position of one element of the information matrix corresponding to the information length corresponding to the code length and the coding rate of the parity check matrix every 60 columns. 1 element of the information matrix to be determined is arranged in a column direction with a period of every 60 columns,
The parity check matrix initial value table of an LDPC code with a coding rate of 1/4 is
111 115 245 809 815 864 1015 1050 2008 2077 2090 2277 2357 2382 2413 2455 2546 2598 2608 2664 2805 2981 3089
35 180 216 251 257 266 297 427 571 596 963 1252 1449 1588 1938 2069 2202 2404 2587 2652 2787 2855 3109
36 74 98 169 177 223 381 677 684 748 874 1308 1349 1436 1480 1786 2077 2551 2620 2905 3058 3194 3226
52 361 441 459 672 779 916 942 1189 1335 1725 1829 1932 1957 2055 2111 2378 2451 2572 2800 2847 2894 2934
146 344 392 427 639 853 1022 1070 1466 1488 1511 1564 1632 1730 1754 1921 1963 2122 2442 2634 2955 3092 3162
135 886 2142 2647
719 868 1316 1600
1067 1606 2385 2823
287 911 1506 2242
337 1192 2075 2268
163 1778 2314 2738
192 1401 1589 2046
648 1664 3039 3169
173 1160 1894 2000
73 770 1420 2687
1271 1706 2325 2917
73 1869 2883 3137
249 1012 1160 2721
Consists of
The parity check matrix initial value table of an LDPC code having a coding rate of 1/3 is:
91 115 152 392 509 892 985 1337 1542 1672 1820 2158 2330 2432 2660 2667 2831
364 524 557 1022 1201 1252 1300 1311 1357 1959 2114 2122 2130 2198 2311 2427 2539
245 458 664 869 1063 1164 1236 1398 1497 1669 1874 1955 1981 1989 2125 2349 2874
134 210 315 798 833 1232 1491 1841 1877 1957 1980 2057 2140 2275 2335 2436 2563
66 223 826 1044 1137 1253 1290 1570 1827 1847 1983 2429 2449 2455 2463 2722 2753
159 379 635 744 882 912 934 1086 1174 1545 1585 2225 2356 2747 2765 2807 2848
412 646 1187 2606
361 2212 2349 2505
1317 1442 2076 2611
1312 1940 2211 2295
1200 1581 2063 2410
8 951 1094 2384
102 362 802 2110
175 493 1344 2588
549 1113 1582 2311
1038 1830 2018 2507
880 1177 2078 2241
116 1174 2197 2282
152 1210 1464 2784
936 1185 1740 2087
590 1139 2280 2372
431 839 2281 2363
99 905 1633 2512
213 1050 1288 1707
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 5/12 is:
168 346 446 527 585 747 1129 1159 1276 1283 1361 1512 1527 1532 1537 1782 1794 1956 2133 2369
111 196 301 319 342 354 475 507 712 1026 1444 1454 1459 1553 1813 2024 2053 2162 2245 2479
69 286 372 399 741 759 1224 1515 1682 1685 1781 1843 1870 1984 2015 2045 2232 2236 2285 2411
92 518 550 565 631 643 825 834 987 1072 1108 1136 1227 1255 1341 1418 1430 1836 1880 2020
28 102 149 160 219 287 313 666 671 928 952 1438 1510 2055 2081 2119 2296 2342 2358 2445
147 194 351 460 509 641 748 755 970 1160 1337 1360 1410 1559 1650 1924 2072 2177 2266 2468
47 292 375 1912
957 1430 1717 2072
458 1607 1761 2489
290 805 1122 1189
324 1122 1293 2447
668 1317 2018 2437
507 803 819 1362
471 1952 2027 2359
88 1233 1543 1650
146 314 890 2419
410 1207 1638 2376
80 1302 1442 2166
1064 1263 1531 1696
180 535 1979 2017
910 924 1373 1693
91 1293 1647 1816
1121 1146 1264 2070
321 885 1630 1926
703 821 1155 1163
715 1198 1436 1576
393 758 950 2377
1337 1639 1674 2024
714 1088 1525 1547
1056 1410 1667 1973
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 1/2 is
135 300 342 383 482 543 641 662 798 1058 1125 1187 1398 1472 1582 1651 1716 1796 1799 1836
48 191 227 264 571 613 623 661 664 748 827 1052 1270 1366 1376 1494 1698 1718 1781 1886
75 233 317 382 605 623 656 768 846 1090 1161 1189 1245 1275 1347 1446 1616 1701 1735 1838
236 325 530 552 589 620 637 658 793 800 807 960 1049 1481 1554 1740 1841 1989 1991 2156
79 88 268 541 645 691 773 932 1077 1162 1516 1522 1540 1741 1781 1834 1862 1977 2020 2032
135 235 379 683 724 841 871 963 1014 1020 1241 1353 1533 1624 1643 1700 1957 2073 2107 2113
106 1706 2037 2074
2 131 448 553
138 1198 1690 1911
326 994 1213 1902
207 951 1491 1710
288 676 952 1561
310 579 792 1064
75 150 277 1104
280 971 1515 2015
1714 1876 2107 2126
198 394 551 2145
51 1145 1613 1766
793 1034 1082 1603
390 1423 1486 2010
676 850 1424 1676
706 767 888 1364
499 779 843 2108
317 1045 1497 1507
224 458 609 1933
219 400 689 1591
164 808 895 1902
629 1431 1552 1892
151 338 600 2097
189 1103 1392 1626
33 365 835 1215
573 1022 1576 1877
239 1169 1766 2061
607 846 990 2093
396 612 1427 1999
180 252 566 817
Consists of
The parity check matrix initial value table of an LDPC code having a coding rate of 7/12 is as follows:
182 275 329 391 518 548 588 595 669 672 787 820 967 1016 1023 1056 1088 1108 1170 1573 1639 1784
112 156 251 316 359 451 457 590 635 867 924 970 982 985 1028 1371 1439 1485 1571 1766 1784 1790
0 47 77 143 200 289 425 454 482 531 721 750 763 859 982 1037 1044 1068 1208 1517 1664 1772
28 116 127 142 184 255 279 395 413 453 570 629 676 717 750 842 1371 1599 1606 1653 1675 1764
81 129 142 267 285 471 498 632 680 893 945 994 1059 1105 1316 1326 1364 1616 1635 1715 1720 1747
25 53 69 263 520 553 556 573 920 976 1000 1043 1129 1141 1195 1319 1359 1391 1513 1680 1711 1736
1443 1572 1693 1754
82 470 732 738
1056 1079 1287 1656
85 798 951 1240
795 1208 1481 1703
638 660 935 1069
40 398 538 991
401 773 1187 1752
227 560 690 1741
378 675 881 1511
207 257 636 889
366 654 1041 1279
1079 1121 1434 1515
80 267 564 996
505 948 1271 1545
794 824 1226 1466
822 1021 1032 1474
304 771 1690 1740
69 932 974 1722
575 682 906 1377
418 1134 1633 1674
93 213 613 792
613 749 1264 1368
95 624 646 1107
1561 1592 1736 1774
322 603 1504 1683
52 478 497 1726
307 604 1202 1663
327 607 749 1456
107 510 1624 1708
381 1278 1330 1433
238 637 751 1315
698 1726 1742 1759
319 453 478 1537
642 815 1175 1558
722 939 974 1040
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 2/3 is:
66 80 110 250 268 296 342 502 564 631 845 934 998 1071 1090 1268 1282 1308 1428
3 23 44 212 368 616 681 778 800 844 856 889 949 967 1060 1292 1319 1398 1431
55 144 185 253 266 329 361 424 436 570 699 952 963 1012 1033 1254 1302 1304 1420
28 278 384 598 741 791 809 931 976 1084 1106 1183 1198 1212 1259 1263 1265 1337 1386
7 112 119 147 149 240 268 470 498 534 662 761 813 859 885 1097 1130 1226 1386
120 155 320 345 367 374 395 419 426 535 671 687 793 930 967 1035 1162 1300 1356
622 755 766 950
514 631 757 1073
489 541 614 691
660 786 1162 1216
219 447 635 787
29 572 578 758
170 634 1112 1291
608 892 1320 1345
444 693 1320 1358
358 448 842 1153
695 792 841 894
567 678 777 981
69 341 717 999
405 990 1171 1401
37 130 471 554
850 959 999 1208
464 624 970 1369
757 870 909 1072
45 168 1078 1203
592 735 1344 1401
32 215 445 915
120 1068 1350 1409
701 1062 1205 1319
103 793 1220 1303
579 651 738 757
444 1014 1251 1363
693 947 952 1176
278 499 1261 1325
49 485 1171 1233
238 559 650 947
865 980 1044 1401
50 83 310 500
186 644 1256 1387
340 434 869 1249
644 770 877 1076
299 315 849 1233
299 307 1085 1290
159 324 1091 1313
137 184 863 1404
398 431 478 1069
13 173 993 1133
129 329 730 1143
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 3/4 is:
27 103 130 135 146 249 432 446 501 618 706 795 843 988
80 295 372 403 585 642 719 740 805 904 908 958 999 1033
136 139 230 325 364 385 434 558 605 611 619 771 795 874
143 318 342 347 422 468 489 576 755 767 798 802 952 1014
35 40 187 241 310 458 590 687 698 719 739 765 786 1059
196 457 499 676 729 752 809 818 857 880 917 987 1050 1071
23 141 190 236 381 477 523 594 789 799 919 995 1012 1079
586 636 703 970
205 353 534 940
276 440 495 852
100 138 211 932
114 589 855 946
686 715 844 952
58 239 248 460
351 438 517 1049
245 467 847 867
54 629 698 743
79 490 628 714
138 586 778 861
42 410 485 921
61 882 884 1028
422 444 695 1032
333 385 506 698
83 137 397 534
37 387 489 1073
728 804 836 878
203 374 874 876
373 516 738 766
322 405 477 898
58 451 540 784
311 440 696 900
141 327 818 828
94 205 887 975
437 829 904 1066
3 152 712 889
452 504 689 975
450 651 808 820
425 681 721 845
77 319 330 901
553 769 865 870
168 825 831 938
43 183 771 782
41 325 491 1074
296 452 913 1075
416 728 964 1044
267 477 894 920
193 484 756 986
348 839 861 938
35 233 577 852
355 386 573 721
146 545 644 934
623 779 803 898
560 590 803 1073
219 428 713 1060
A data processing device. LDPC (Low Density Parity Check) code bits are written in the column direction of the storage means for storing in the row direction and the column direction, and the code bits of the LDPC code read in the row direction are used as symbols,
When m bit code bits of 2 bits or more of the LDPC code are transmitted as one symbol,
Column twist interleaving for changing the write start position when the code bits of the LDPC code are written in the column direction of the storage means for each column of the storage means, and rearranging the code bits of the LDPC code It is provided with sorting means to perform as a replacement process,
When the code length of the LDPC code is represented by N bits and the predetermined positive integer is represented by b,
The storage means stores mb bits in the row direction and stores N / (mb) bits in the column direction;
When the sign bit of the mb bits read in the row direction of the storage means is b symbols,
The LDPC code has an encoding rate of 1/4, 1/3, 5/12, 1/2, 7/12, 2/3, or 3/4, and a code length N of 4320 bits. And
The m bits are 2 bits, and the integer b is 2.
The sign bit of the 2 bits of the LDPC code are mapped to one of 2 ² signal points prescribed in a predetermined modulation scheme,
The storage means has four columns for storing 2 × 2 bits in the row direction,
The sorting means is
When the address of the head position in the column direction of the storage means is 0, and the address of each position in the column direction of the storage means is represented by an integer in ascending order,
The write start position of the first column of the four columns of the storage means is the position where the address is 0,
The write start position of the second column of the four columns of the storage means is the position where the address is 62,
The write start position of the third column of the four columns of the storage means is the position where the address is 36,
The write start position of the fourth column of the four columns of the storage means is the position where the address is 3,
The parity check matrix of the LDPC code is based on the parity check matrix initial value table that represents the position of one element of the information matrix corresponding to the information length corresponding to the code length and the coding rate of the parity check matrix every 60 columns. 1 element of the information matrix to be determined is arranged in a column direction with a period of every 60 columns,
The parity check matrix initial value table of an LDPC code with a coding rate of 1/4 is
111 115 245 809 815 864 1015 1050 2008 2077 2090 2277 2357 2382 2413 2455 2546 2598 2608 2664 2805 2981 3089
35 180 216 251 257 266 297 427 571 596 963 1252 1449 1588 1938 2069 2202 2404 2587 2652 2787 2855 3109
36 74 98 169 177 223 381 677 684 748 874 1308 1349 1436 1480 1786 2077 2551 2620 2905 3058 3194 3226
52 361 441 459 672 779 916 942 1189 1335 1725 1829 1932 1957 2055 2111 2378 2451 2572 2800 2847 2894 2934
146 344 392 427 639 853 1022 1070 1466 1488 1511 1564 1632 1730 1754 1921 1963 2122 2442 2634 2955 3092 3162
135 886 2142 2647
719 868 1316 1600
1067 1606 2385 2823
287 911 1506 2242
337 1192 2075 2268
163 1778 2314 2738
192 1401 1589 2046
648 1664 3039 3169
173 1160 1894 2000
73 770 1420 2687
1271 1706 2325 2917
73 1869 2883 3137
249 1012 1160 2721
Consists of
The parity check matrix initial value table of an LDPC code having a coding rate of 1/3 is:
91 115 152 392 509 892 985 1337 1542 1672 1820 2158 2330 2432 2660 2667 2831
364 524 557 1022 1201 1252 1300 1311 1357 1959 2114 2122 2130 2198 2311 2427 2539
245 458 664 869 1063 1164 1236 1398 1497 1669 1874 1955 1981 1989 2125 2349 2874
134 210 315 798 833 1232 1491 1841 1877 1957 1980 2057 2140 2275 2335 2436 2563
66 223 826 1044 1137 1253 1290 1570 1827 1847 1983 2429 2449 2455 2463 2722 2753
159 379 635 744 882 912 934 1086 1174 1545 1585 2225 2356 2747 2765 2807 2848
412 646 1187 2606
361 2212 2349 2505
1317 1442 2076 2611
1312 1940 2211 2295
1200 1581 2063 2410
8 951 1094 2384
102 362 802 2110
175 493 1344 2588
549 1113 1582 2311
1038 1830 2018 2507
880 1177 2078 2241
116 1174 2197 2282
152 1210 1464 2784
936 1185 1740 2087
590 1139 2280 2372
431 839 2281 2363
99 905 1633 2512
213 1050 1288 1707
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 5/12 is:
168 346 446 527 585 747 1129 1159 1276 1283 1361 1512 1527 1532 1537 1782 1794 1956 2133 2369
111 196 301 319 342 354 475 507 712 1026 1444 1454 1459 1553 1813 2024 2053 2162 2245 2479
69 286 372 399 741 759 1224 1515 1682 1685 1781 1843 1870 1984 2015 2045 2232 2236 2285 2411
92 518 550 565 631 643 825 834 987 1072 1108 1136 1227 1255 1341 1418 1430 1836 1880 2020
28 102 149 160 219 287 313 666 671 928 952 1438 1510 2055 2081 2119 2296 2342 2358 2445
147 194 351 460 509 641 748 755 970 1160 1337 1360 1410 1559 1650 1924 2072 2177 2266 2468
47 292 375 1912
957 1430 1717 2072
458 1607 1761 2489
290 805 1122 1189
324 1122 1293 2447
668 1317 2018 2437
507 803 819 1362
471 1952 2027 2359
88 1233 1543 1650
146 314 890 2419
410 1207 1638 2376
80 1302 1442 2166
1064 1263 1531 1696
180 535 1979 2017
910 924 1373 1693
91 1293 1647 1816
1121 1146 1264 2070
321 885 1630 1926
703 821 1155 1163
715 1198 1436 1576
393 758 950 2377
1337 1639 1674 2024
714 1088 1525 1547
1056 1410 1667 1973
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 1/2 is
135 300 342 383 482 543 641 662 798 1058 1125 1187 1398 1472 1582 1651 1716 1796 1799 1836
48 191 227 264 571 613 623 661 664 748 827 1052 1270 1366 1376 1494 1698 1718 1781 1886
75 233 317 382 605 623 656 768 846 1090 1161 1189 1245 1275 1347 1446 1616 1701 1735 1838
236 325 530 552 589 620 637 658 793 800 807 960 1049 1481 1554 1740 1841 1989 1991 2156
79 88 268 541 645 691 773 932 1077 1162 1516 1522 1540 1741 1781 1834 1862 1977 2020 2032
135 235 379 683 724 841 871 963 1014 1020 1241 1353 1533 1624 1643 1700 1957 2073 2107 2113
106 1706 2037 2074
2 131 448 553
138 1198 1690 1911
326 994 1213 1902
207 951 1491 1710
288 676 952 1561
310 579 792 1064
75 150 277 1104
280 971 1515 2015
1714 1876 2107 2126
198 394 551 2145
51 1145 1613 1766
793 1034 1082 1603
390 1423 1486 2010
676 850 1424 1676
706 767 888 1364
499 779 843 2108
317 1045 1497 1507
224 458 609 1933
219 400 689 1591
164 808 895 1902
629 1431 1552 1892
151 338 600 2097
189 1103 1392 1626
33 365 835 1215
573 1022 1576 1877
239 1169 1766 2061
607 846 990 2093
396 612 1427 1999
180 252 566 817
Consists of
The parity check matrix initial value table of an LDPC code having a coding rate of 7/12 is as follows:
182 275 329 391 518 548 588 595 669 672 787 820 967 1016 1023 1056 1088 1108 1170 1573 1639 1784
112 156 251 316 359 451 457 590 635 867 924 970 982 985 1028 1371 1439 1485 1571 1766 1784 1790
0 47 77 143 200 289 425 454 482 531 721 750 763 859 982 1037 1044 1068 1208 1517 1664 1772
28 116 127 142 184 255 279 395 413 453 570 629 676 717 750 842 1371 1599 1606 1653 1675 1764
81 129 142 267 285 471 498 632 680 893 945 994 1059 1105 1316 1326 1364 1616 1635 1715 1720 1747
25 53 69 263 520 553 556 573 920 976 1000 1043 1129 1141 1195 1319 1359 1391 1513 1680 1711 1736
1443 1572 1693 1754
82 470 732 738
1056 1079 1287 1656
85 798 951 1240
795 1208 1481 1703
638 660 935 1069
40 398 538 991
401 773 1187 1752
227 560 690 1741
378 675 881 1511
207 257 636 889
366 654 1041 1279
1079 1121 1434 1515
80 267 564 996
505 948 1271 1545
794 824 1226 1466
822 1021 1032 1474
304 771 1690 1740
69 932 974 1722
575 682 906 1377
418 1134 1633 1674
93 213 613 792
613 749 1264 1368
95 624 646 1107
1561 1592 1736 1774
322 603 1504 1683
52 478 497 1726
307 604 1202 1663
327 607 749 1456
107 510 1624 1708
381 1278 1330 1433
238 637 751 1315
698 1726 1742 1759
319 453 478 1537
642 815 1175 1558
722 939 974 1040
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 2/3 is:
66 80 110 250 268 296 342 502 564 631 845 934 998 1071 1090 1268 1282 1308 1428
3 23 44 212 368 616 681 778 800 844 856 889 949 967 1060 1292 1319 1398 1431
55 144 185 253 266 329 361 424 436 570 699 952 963 1012 1033 1254 1302 1304 1420
28 278 384 598 741 791 809 931 976 1084 1106 1183 1198 1212 1259 1263 1265 1337 1386
7 112 119 147 149 240 268 470 498 534 662 761 813 859 885 1097 1130 1226 1386
120 155 320 345 367 374 395 419 426 535 671 687 793 930 967 1035 1162 1300 1356
622 755 766 950
514 631 757 1073
489 541 614 691
660 786 1162 1216
219 447 635 787
29 572 578 758
170 634 1112 1291
608 892 1320 1345
444 693 1320 1358
358 448 842 1153
695 792 841 894
567 678 777 981
69 341 717 999
405 990 1171 1401
37 130 471 554
850 959 999 1208
464 624 970 1369
757 870 909 1072
45 168 1078 1203
592 735 1344 1401
32 215 445 915
120 1068 1350 1409
701 1062 1205 1319
103 793 1220 1303
579 651 738 757
444 1014 1251 1363
693 947 952 1176
278 499 1261 1325
49 485 1171 1233
238 559 650 947
865 980 1044 1401
50 83 310 500
186 644 1256 1387
340 434 869 1249
644 770 877 1076
299 315 849 1233
299 307 1085 1290
159 324 1091 1313
137 184 863 1404
398 431 478 1069
13 173 993 1133
129 329 730 1143
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 3/4 is:
27 103 130 135 146 249 432 446 501 618 706 795 843 988
80 295 372 403 585 642 719 740 805 904 908 958 999 1033
136 139 230 325 364 385 434 558 605 611 619 771 795 874
143 318 342 347 422 468 489 576 755 767 798 802 952 1014
35 40 187 241 310 458 590 687 698 719 739 765 786 1059
196 457 499 676 729 752 809 818 857 880 917 987 1050 1071
23 141 190 236 381 477 523 594 789 799 919 995 1012 1079
586 636 703 970
205 353 534 940
276 440 495 852
100 138 211 932
114 589 855 946
686 715 844 952
58 239 248 460
351 438 517 1049
245 467 847 867
54 629 698 743
79 490 628 714
138 586 778 861
42 410 485 921
61 882 884 1028
422 444 695 1032
333 385 506 698
83 137 397 534
37 387 489 1073
728 804 836 878
203 374 874 876
373 516 738 766
322 405 477 898
58 451 540 784
311 440 696 900
141 327 818 828
94 205 887 975
437 829 904 1066
3 152 712 889
452 504 689 975
450 651 808 820
425 681 721 845
77 319 330 901
553 769 865 870
168 825 831 938
43 183 771 782
41 325 491 1074
296 452 913 1075
416 728 964 1044
267 477 894 920
193 484 756 986
348 839 861 938
35 233 577 852
355 386 573 721
146 545 644 934
623 779 803 898
560 590 803 1073
219 428 713 1060
A data processing device. LDPC (Low Density Parity Check) code bits are written in the column direction of the storage means for storing in the row direction and the column direction, and the code bits of the LDPC code read in the row direction are used as symbols,
When m bit code bits of 2 bits or more of the LDPC code are transmitted as one symbol,
Column twist interleaving for changing the write start position when the code bits of the LDPC code are written in the column direction of the storage means for each column of the storage means, and rearranging the code bits of the LDPC code It is provided with sorting means to perform as a replacement process,
When the code length of the LDPC code is represented by N bits and the predetermined positive integer is represented by b,
The storage means stores mb bits in the row direction and stores N / (mb) bits in the column direction;
When the sign bit of the mb bits read in the row direction of the storage means is b symbols,
The LDPC code has an encoding rate of 1/4, 1/3, 5/12, 1/2, 7/12, 2/3, or 3/4, and a code length N of 4320 bits. And
The m bits are 4 bits, and the integer b is 1.
The sign bit of the 4 bits of the LDPC code are mapped to one of 2 ⁴ signal points prescribed in a predetermined modulation scheme,
The storage means has four columns for storing 4 × 1 bits in the row direction,
The sorting means is
When the address of the head position in the column direction of the storage means is 0, and the address of each position in the column direction of the storage means is represented by an integer in ascending order,
The write start position of the first column of the four columns of the storage means is the position where the address is 0,
The write start position of the second column of the four columns of the storage means is the position where the address is 62,
The write start position of the third column of the four columns of the storage means is the position where the address is 36,
The write start position of the fourth column of the four columns of the storage means is the position where the address is 3,
The parity check matrix of the LDPC code is based on the parity check matrix initial value table that represents the position of one element of the information matrix corresponding to the information length corresponding to the code length and the coding rate of the parity check matrix every 60 columns. 1 element of the information matrix to be determined is arranged in a column direction with a period of every 60 columns,
The parity check matrix initial value table of an LDPC code with a coding rate of 1/4 is
111 115 245 809 815 864 1015 1050 2008 2077 2090 2277 2357 2382 2413 2455 2546 2598 2608 2664 2805 2981 3089
35 180 216 251 257 266 297 427 571 596 963 1252 1449 1588 1938 2069 2202 2404 2587 2652 2787 2855 3109
36 74 98 169 177 223 381 677 684 748 874 1308 1349 1436 1480 1786 2077 2551 2620 2905 3058 3194 3226
52 361 441 459 672 779 916 942 1189 1335 1725 1829 1932 1957 2055 2111 2378 2451 2572 2800 2847 2894 2934
146 344 392 427 639 853 1022 1070 1466 1488 1511 1564 1632 1730 1754 1921 1963 2122 2442 2634 2955 3092 3162
135 886 2142 2647
719 868 1316 1600
1067 1606 2385 2823
287 911 1506 2242
337 1192 2075 2268
163 1778 2314 2738
192 1401 1589 2046
648 1664 3039 3169
173 1160 1894 2000
73 770 1420 2687
1271 1706 2325 2917
73 1869 2883 3137
249 1012 1160 2721
Consists of
The parity check matrix initial value table of an LDPC code having a coding rate of 1/3 is:
91 115 152 392 509 892 985 1337 1542 1672 1820 2158 2330 2432 2660 2667 2831
364 524 557 1022 1201 1252 1300 1311 1357 1959 2114 2122 2130 2198 2311 2427 2539
245 458 664 869 1063 1164 1236 1398 1497 1669 1874 1955 1981 1989 2125 2349 2874
134 210 315 798 833 1232 1491 1841 1877 1957 1980 2057 2140 2275 2335 2436 2563
66 223 826 1044 1137 1253 1290 1570 1827 1847 1983 2429 2449 2455 2463 2722 2753
159 379 635 744 882 912 934 1086 1174 1545 1585 2225 2356 2747 2765 2807 2848
412 646 1187 2606
361 2212 2349 2505
1317 1442 2076 2611
1312 1940 2211 2295
1200 1581 2063 2410
8 951 1094 2384
102 362 802 2110
175 493 1344 2588
549 1113 1582 2311
1038 1830 2018 2507
880 1177 2078 2241
116 1174 2197 2282
152 1210 1464 2784
936 1185 1740 2087
590 1139 2280 2372
431 839 2281 2363
99 905 1633 2512
213 1050 1288 1707
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 5/12 is:
168 346 446 527 585 747 1129 1159 1276 1283 1361 1512 1527 1532 1537 1782 1794 1956 2133 2369
111 196 301 319 342 354 475 507 712 1026 1444 1454 1459 1553 1813 2024 2053 2162 2245 2479
69 286 372 399 741 759 1224 1515 1682 1685 1781 1843 1870 1984 2015 2045 2232 2236 2285 2411
92 518 550 565 631 643 825 834 987 1072 1108 1136 1227 1255 1341 1418 1430 1836 1880 2020
28 102 149 160 219 287 313 666 671 928 952 1438 1510 2055 2081 2119 2296 2342 2358 2445
147 194 351 460 509 641 748 755 970 1160 1337 1360 1410 1559 1650 1924 2072 2177 2266 2468
47 292 375 1912
957 1430 1717 2072
458 1607 1761 2489
290 805 1122 1189
324 1122 1293 2447
668 1317 2018 2437
507 803 819 1362
471 1952 2027 2359
88 1233 1543 1650
146 314 890 2419
410 1207 1638 2376
80 1302 1442 2166
1064 1263 1531 1696
180 535 1979 2017
910 924 1373 1693
91 1293 1647 1816
1121 1146 1264 2070
321 885 1630 1926
703 821 1155 1163
715 1198 1436 1576
393 758 950 2377
1337 1639 1674 2024
714 1088 1525 1547
1056 1410 1667 1973
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 1/2 is
135 300 342 383 482 543 641 662 798 1058 1125 1187 1398 1472 1582 1651 1716 1796 1799 1836
48 191 227 264 571 613 623 661 664 748 827 1052 1270 1366 1376 1494 1698 1718 1781 1886
75 233 317 382 605 623 656 768 846 1090 1161 1189 1245 1275 1347 1446 1616 1701 1735 1838
236 325 530 552 589 620 637 658 793 800 807 960 1049 1481 1554 1740 1841 1989 1991 2156
79 88 268 541 645 691 773 932 1077 1162 1516 1522 1540 1741 1781 1834 1862 1977 2020 2032
135 235 379 683 724 841 871 963 1014 1020 1241 1353 1533 1624 1643 1700 1957 2073 2107 2113
106 1706 2037 2074
2 131 448 553
138 1198 1690 1911
326 994 1213 1902
207 951 1491 1710
288 676 952 1561
310 579 792 1064
75 150 277 1104
280 971 1515 2015
1714 1876 2107 2126
198 394 551 2145
51 1145 1613 1766
793 1034 1082 1603
390 1423 1486 2010
676 850 1424 1676
706 767 888 1364
499 779 843 2108
317 1045 1497 1507
224 458 609 1933
219 400 689 1591
164 808 895 1902
629 1431 1552 1892
151 338 600 2097
189 1103 1392 1626
33 365 835 1215
573 1022 1576 1877
239 1169 1766 2061
607 846 990 2093
396 612 1427 1999
180 252 566 817
Consists of
The parity check matrix initial value table of an LDPC code having a coding rate of 7/12 is as follows:
182 275 329 391 518 548 588 595 669 672 787 820 967 1016 1023 1056 1088 1108 1170 1573 1639 1784
112 156 251 316 359 451 457 590 635 867 924 970 982 985 1028 1371 1439 1485 1571 1766 1784 1790
0 47 77 143 200 289 425 454 482 531 721 750 763 859 982 1037 1044 1068 1208 1517 1664 1772
28 116 127 142 184 255 279 395 413 453 570 629 676 717 750 842 1371 1599 1606 1653 1675 1764
81 129 142 267 285 471 498 632 680 893 945 994 1059 1105 1316 1326 1364 1616 1635 1715 1720 1747
25 53 69 263 520 553 556 573 920 976 1000 1043 1129 1141 1195 1319 1359 1391 1513 1680 1711 1736
1443 1572 1693 1754
82 470 732 738
1056 1079 1287 1656
85 798 951 1240
795 1208 1481 1703
638 660 935 1069
40 398 538 991
401 773 1187 1752
227 560 690 1741
378 675 881 1511
207 257 636 889
366 654 1041 1279
1079 1121 1434 1515
80 267 564 996
505 948 1271 1545
794 824 1226 1466
822 1021 1032 1474
304 771 1690 1740
69 932 974 1722
575 682 906 1377
418 1134 1633 1674
93 213 613 792
613 749 1264 1368
95 624 646 1107
1561 1592 1736 1774
322 603 1504 1683
52 478 497 1726
307 604 1202 1663
327 607 749 1456
107 510 1624 1708
381 1278 1330 1433
238 637 751 1315
698 1726 1742 1759
319 453 478 1537
642 815 1175 1558
722 939 974 1040
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 2/3 is:
66 80 110 250 268 296 342 502 564 631 845 934 998 1071 1090 1268 1282 1308 1428
3 23 44 212 368 616 681 778 800 844 856 889 949 967 1060 1292 1319 1398 1431
55 144 185 253 266 329 361 424 436 570 699 952 963 1012 1033 1254 1302 1304 1420
28 278 384 598 741 791 809 931 976 1084 1106 1183 1198 1212 1259 1263 1265 1337 1386
7 112 119 147 149 240 268 470 498 534 662 761 813 859 885 1097 1130 1226 1386
120 155 320 345 367 374 395 419 426 535 671 687 793 930 967 1035 1162 1300 1356
622 755 766 950
514 631 757 1073
489 541 614 691
660 786 1162 1216
219 447 635 787
29 572 578 758
170 634 1112 1291
608 892 1320 1345
444 693 1320 1358
358 448 842 1153
695 792 841 894
567 678 777 981
69 341 717 999
405 990 1171 1401
37 130 471 554
850 959 999 1208
464 624 970 1369
757 870 909 1072
45 168 1078 1203
592 735 1344 1401
32 215 445 915
120 1068 1350 1409
701 1062 1205 1319
103 793 1220 1303
579 651 738 757
444 1014 1251 1363
693 947 952 1176
278 499 1261 1325
49 485 1171 1233
238 559 650 947
865 980 1044 1401
50 83 310 500
186 644 1256 1387
340 434 869 1249
644 770 877 1076
299 315 849 1233
299 307 1085 1290
159 324 1091 1313
137 184 863 1404
398 431 478 1069
13 173 993 1133
129 329 730 1143
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 3/4 is:
27 103 130 135 146 249 432 446 501 618 706 795 843 988
80 295 372 403 585 642 719 740 805 904 908 958 999 1033
136 139 230 325 364 385 434 558 605 611 619 771 795 874
143 318 342 347 422 468 489 576 755 767 798 802 952 1014
35 40 187 241 310 458 590 687 698 719 739 765 786 1059
196 457 499 676 729 752 809 818 857 880 917 987 1050 1071
23 141 190 236 381 477 523 594 789 799 919 995 1012 1079
586 636 703 970
205 353 534 940
276 440 495 852
100 138 211 932
114 589 855 946
686 715 844 952
58 239 248 460
351 438 517 1049
245 467 847 867
54 629 698 743
79 490 628 714
138 586 778 861
42 410 485 921
61 882 884 1028
422 444 695 1032
333 385 506 698
83 137 397 534
37 387 489 1073
728 804 836 878
203 374 874 876
373 516 738 766
322 405 477 898
58 451 540 784
311 440 696 900
141 327 818 828
94 205 887 975
437 829 904 1066
3 152 712 889
452 504 689 975
450 651 808 820
425 681 721 845
77 319 330 901
553 769 865 870
168 825 831 938
43 183 771 782
41 325 491 1074
296 452 913 1075
416 728 964 1044
267 477 894 920
193 484 756 986
348 839 861 938
35 233 577 852
355 386 573 721
146 545 644 934
623 779 803 898
560 590 803 1073
219 428 713 1060
A data processing device. LDPC (Low Density Parity Check) code bits are written in the column direction of the storage means for storing in the row direction and the column direction, and the code bits of the LDPC code read in the row direction are used as symbols,
When m bit code bits of 2 bits or more of the LDPC code are transmitted as one symbol,
Column twist interleaving for changing the write start position when the code bits of the LDPC code are written in the column direction of the storage means for each column of the storage means, and rearranging the code bits of the LDPC code It is provided with sorting means to perform as a replacement process,
When the code length of the LDPC code is represented by N bits and the predetermined positive integer is represented by b,
The storage means stores mb bits in the row direction and stores N / (mb) bits in the column direction;
When the sign bit of the mb bits read in the row direction of the storage means is b symbols,
The LDPC code has an encoding rate of 1/4, 1/3, 5/12, 1/2, 7/12, 2/3, or 3/4, and a code length N of 4320 bits. And
The m bits are 6 bits, and the integer b is 1.
The 6-bit code bit of the LDPC code is mapped to any one of ²⁶ signal points determined by a predetermined modulation method,
The storage means has six columns for storing 6 × 1 bits in the row direction,
The sorting means is
When the address of the head position in the column direction of the storage means is 0, and the address of each position in the column direction of the storage means is represented by an integer in ascending order,
Of the six columns of the storage means, the first column writing start position is the position where the address is 0,
Of the six columns of the storage means, the writing start position of the second column is the position where the address is 3,
The write start position of the third column of the six columns of the storage means is the position where the address is 68,
The write start position of the fourth column of the six columns of the storage means is the position where the address is 24,
The write start position of the fifth column of the six columns of the storage means is the position where the address is 47,
Of the six columns of the storage means, the writing start position of the sixth column is the position where the address is 4,
The parity check matrix of the LDPC code is based on the parity check matrix initial value table that represents the position of one element of the information matrix corresponding to the information length corresponding to the code length and the coding rate of the parity check matrix every 60 columns. 1 element of the information matrix to be determined is arranged in a column direction with a period of every 60 columns,
The parity check matrix initial value table of an LDPC code with a coding rate of 1/4 is
111 115 245 809 815 864 1015 1050 2008 2077 2090 2277 2357 2382 2413 2455 2546 2598 2608 2664 2805 2981 3089
35 180 216 251 257 266 297 427 571 596 963 1252 1449 1588 1938 2069 2202 2404 2587 2652 2787 2855 3109
36 74 98 169 177 223 381 677 684 748 874 1308 1349 1436 1480 1786 2077 2551 2620 2905 3058 3194 3226
52 361 441 459 672 779 916 942 1189 1335 1725 1829 1932 1957 2055 2111 2378 2451 2572 2800 2847 2894 2934
146 344 392 427 639 853 1022 1070 1466 1488 1511 1564 1632 1730 1754 1921 1963 2122 2442 2634 2955 3092 3162
135 886 2142 2647
719 868 1316 1600
1067 1606 2385 2823
287 911 1506 2242
337 1192 2075 2268
163 1778 2314 2738
192 1401 1589 2046
648 1664 3039 3169
173 1160 1894 2000
73 770 1420 2687
1271 1706 2325 2917
73 1869 2883 3137
249 1012 1160 2721
Consists of
The parity check matrix initial value table of an LDPC code having a coding rate of 1/3 is:
91 115 152 392 509 892 985 1337 1542 1672 1820 2158 2330 2432 2660 2667 2831
364 524 557 1022 1201 1252 1300 1311 1357 1959 2114 2122 2130 2198 2311 2427 2539
245 458 664 869 1063 1164 1236 1398 1497 1669 1874 1955 1981 1989 2125 2349 2874
134 210 315 798 833 1232 1491 1841 1877 1957 1980 2057 2140 2275 2335 2436 2563
66 223 826 1044 1137 1253 1290 1570 1827 1847 1983 2429 2449 2455 2463 2722 2753
159 379 635 744 882 912 934 1086 1174 1545 1585 2225 2356 2747 2765 2807 2848
412 646 1187 2606
361 2212 2349 2505
1317 1442 2076 2611
1312 1940 2211 2295
1200 1581 2063 2410
8 951 1094 2384
102 362 802 2110
175 493 1344 2588
549 1113 1582 2311
1038 1830 2018 2507
880 1177 2078 2241
116 1174 2197 2282
152 1210 1464 2784
936 1185 1740 2087
590 1139 2280 2372
431 839 2281 2363
99 905 1633 2512
213 1050 1288 1707
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 5/12 is:
168 346 446 527 585 747 1129 1159 1276 1283 1361 1512 1527 1532 1537 1782 1794 1956 2133 2369
111 196 301 319 342 354 475 507 712 1026 1444 1454 1459 1553 1813 2024 2053 2162 2245 2479
69 286 372 399 741 759 1224 1515 1682 1685 1781 1843 1870 1984 2015 2045 2232 2236 2285 2411
92 518 550 565 631 643 825 834 987 1072 1108 1136 1227 1255 1341 1418 1430 1836 1880 2020
28 102 149 160 219 287 313 666 671 928 952 1438 1510 2055 2081 2119 2296 2342 2358 2445
147 194 351 460 509 641 748 755 970 1160 1337 1360 1410 1559 1650 1924 2072 2177 2266 2468
47 292 375 1912
957 1430 1717 2072
458 1607 1761 2489
290 805 1122 1189
324 1122 1293 2447
668 1317 2018 2437
507 803 819 1362
471 1952 2027 2359
88 1233 1543 1650
146 314 890 2419
410 1207 1638 2376
80 1302 1442 2166
1064 1263 1531 1696
180 535 1979 2017
910 924 1373 1693
91 1293 1647 1816
1121 1146 1264 2070
321 885 1630 1926
703 821 1155 1163
715 1198 1436 1576
393 758 950 2377
1337 1639 1674 2024
714 1088 1525 1547
1056 1410 1667 1973
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 1/2 is
135 300 342 383 482 543 641 662 798 1058 1125 1187 1398 1472 1582 1651 1716 1796 1799 1836
48 191 227 264 571 613 623 661 664 748 827 1052 1270 1366 1376 1494 1698 1718 1781 1886
75 233 317 382 605 623 656 768 846 1090 1161 1189 1245 1275 1347 1446 1616 1701 1735 1838
236 325 530 552 589 620 637 658 793 800 807 960 1049 1481 1554 1740 1841 1989 1991 2156
79 88 268 541 645 691 773 932 1077 1162 1516 1522 1540 1741 1781 1834 1862 1977 2020 2032
135 235 379 683 724 841 871 963 1014 1020 1241 1353 1533 1624 1643 1700 1957 2073 2107 2113
106 1706 2037 2074
2 131 448 553
138 1198 1690 1911
326 994 1213 1902
207 951 1491 1710
288 676 952 1561
310 579 792 1064
75 150 277 1104
280 971 1515 2015
1714 1876 2107 2126
198 394 551 2145
51 1145 1613 1766
793 1034 1082 1603
390 1423 1486 2010
676 850 1424 1676
706 767 888 1364
499 779 843 2108
317 1045 1497 1507
224 458 609 1933
219 400 689 1591
164 808 895 1902
629 1431 1552 1892
151 338 600 2097
189 1103 1392 1626
33 365 835 1215
573 1022 1576 1877
239 1169 1766 2061
607 846 990 2093
396 612 1427 1999
180 252 566 817
Consists of
The parity check matrix initial value table of an LDPC code having a coding rate of 7/12 is as follows:
182 275 329 391 518 548 588 595 669 672 787 820 967 1016 1023 1056 1088 1108 1170 1573 1639 1784
112 156 251 316 359 451 457 590 635 867 924 970 982 985 1028 1371 1439 1485 1571 1766 1784 1790
0 47 77 143 200 289 425 454 482 531 721 750 763 859 982 1037 1044 1068 1208 1517 1664 1772
28 116 127 142 184 255 279 395 413 453 570 629 676 717 750 842 1371 1599 1606 1653 1675 1764
81 129 142 267 285 471 498 632 680 893 945 994 1059 1105 1316 1326 1364 1616 1635 1715 1720 1747
25 53 69 263 520 553 556 573 920 976 1000 1043 1129 1141 1195 1319 1359 1391 1513 1680 1711 1736
1443 1572 1693 1754
82 470 732 738
1056 1079 1287 1656
85 798 951 1240
795 1208 1481 1703
638 660 935 1069
40 398 538 991
401 773 1187 1752
227 560 690 1741
378 675 881 1511
207 257 636 889
366 654 1041 1279
1079 1121 1434 1515
80 267 564 996
505 948 1271 1545
794 824 1226 1466
822 1021 1032 1474
304 771 1690 1740
69 932 974 1722
575 682 906 1377
418 1134 1633 1674
93 213 613 792
613 749 1264 1368
95 624 646 1107
1561 1592 1736 1774
322 603 1504 1683
52 478 497 1726
307 604 1202 1663
327 607 749 1456
107 510 1624 1708
381 1278 1330 1433
238 637 751 1315
698 1726 1742 1759
319 453 478 1537
642 815 1175 1558
722 939 974 1040
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 2/3 is:
66 80 110 250 268 296 342 502 564 631 845 934 998 1071 1090 1268 1282 1308 1428
3 23 44 212 368 616 681 778 800 844 856 889 949 967 1060 1292 1319 1398 1431
55 144 185 253 266 329 361 424 436 570 699 952 963 1012 1033 1254 1302 1304 1420
28 278 384 598 741 791 809 931 976 1084 1106 1183 1198 1212 1259 1263 1265 1337 1386
7 112 119 147 149 240 268 470 498 534 662 761 813 859 885 1097 1130 1226 1386
120 155 320 345 367 374 395 419 426 535 671 687 793 930 967 1035 1162 1300 1356
622 755 766 950
514 631 757 1073
489 541 614 691
660 786 1162 1216
219 447 635 787
29 572 578 758
170 634 1112 1291
608 892 1320 1345
444 693 1320 1358
358 448 842 1153
695 792 841 894
567 678 777 981
69 341 717 999
405 990 1171 1401
37 130 471 554
850 959 999 1208
464 624 970 1369
757 870 909 1072
45 168 1078 1203
592 735 1344 1401
32 215 445 915
120 1068 1350 1409
701 1062 1205 1319
103 793 1220 1303
579 651 738 757
444 1014 1251 1363
693 947 952 1176
278 499 1261 1325
49 485 1171 1233
238 559 650 947
865 980 1044 1401
50 83 310 500
186 644 1256 1387
340 434 869 1249
644 770 877 1076
299 315 849 1233
299 307 1085 1290
159 324 1091 1313
137 184 863 1404
398 431 478 1069
13 173 993 1133
129 329 730 1143
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 3/4 is:
27 103 130 135 146 249 432 446 501 618 706 795 843 988
80 295 372 403 585 642 719 740 805 904 908 958 999 1033
136 139 230 325 364 385 434 558 605 611 619 771 795 874
143 318 342 347 422 468 489 576 755 767 798 802 952 1014
35 40 187 241 310 458 590 687 698 719 739 765 786 1059
196 457 499 676 729 752 809 818 857 880 917 987 1050 1071
23 141 190 236 381 477 523 594 789 799 919 995 1012 1079
586 636 703 970
205 353 534 940
276 440 495 852
100 138 211 932
114 589 855 946
686 715 844 952
58 239 248 460
351 438 517 1049
245 467 847 867
54 629 698 743
79 490 628 714
138 586 778 861
42 410 485 921
61 882 884 1028
422 444 695 1032
333 385 506 698
83 137 397 534
37 387 489 1073
728 804 836 878
203 374 874 876
373 516 738 766
322 405 477 898
58 451 540 784
311 440 696 900
141 327 818 828
94 205 887 975
437 829 904 1066
3 152 712 889
452 504 689 975
450 651 808 820
425 681 721 845
77 319 330 901
553 769 865 870
168 825 831 938
43 183 771 782
41 325 491 1074
296 452 913 1075
416 728 964 1044
267 477 894 920
193 484 756 986
348 839 861 938
35 233 577 852
355 386 573 721
146 545 644 934
623 779 803 898
560 590 803 1073
219 428 713 1060
A data processing device. LDPC (Low Density Parity Check) code bits are written in the column direction of the storage means for storing in the row direction and the column direction, and the code bits of the LDPC code read in the row direction are used as symbols,
When m bit code bits of 2 bits or more of the LDPC code are transmitted as one symbol,
Column twist interleaving for changing the write start position when the code bits of the LDPC code are written in the column direction of the storage means for each column of the storage means, and rearranging the code bits of the LDPC code It is provided with sorting means to perform as a replacement process,
When the code length of the LDPC code is represented by N bits and the predetermined positive integer is represented by b,
The storage means stores mb bits in the row direction and stores N / (mb) bits in the column direction;
When the sign bit of the mb bits read in the row direction of the storage means is b symbols,
The LDPC code has an encoding rate of 1/4, 1/3, 5/12, 1/2, 7/12, 2/3, or 3/4, and a code length N of 4320 bits. And
The m bits are 4 bits, and the integer b is 2.
The sign bit of the 4 bits of the LDPC code are mapped to one of 2 ⁴ signal points prescribed in a predetermined modulation scheme,
The storage means has 8 columns for storing 4 × 2 bits in the row direction,
The sorting means is
When the address of the head position in the column direction of the storage means is 0, and the address of each position in the column direction of the storage means is represented by an integer in ascending order,
The write start position of the first column of the eight columns of the storage means is the position where the address is 0,
The write start position of the second column of the eight columns of the storage means is the position where the address is 2,
The write start position of the third column of the eight columns of the storage means is the position where the address is 46,
The write start position of the fourth column of the eight columns of the storage means is the position where the address is 79,
The write start position of the fifth column of the eight columns of the storage means is the position where the address is 291;
The writing start position of the sixth column of the eight columns of the storage means is the position where the address is 146,
The write start position of the seventh column of the eight columns of the storage means is the position where the address is 3,
The write start position of the eighth column of the eight columns of the storage means is the position where the address is 13,
The parity check matrix of the LDPC code is based on the parity check matrix initial value table that represents the position of one element of the information matrix corresponding to the information length corresponding to the code length and the coding rate of the parity check matrix every 60 columns. 1 element of the information matrix to be determined is arranged in a column direction with a period of every 60 columns,
The parity check matrix initial value table of an LDPC code with a coding rate of 1/4 is
111 115 245 809 815 864 1015 1050 2008 2077 2090 2277 2357 2382 2413 2455 2546 2598 2608 2664 2805 2981 3089
35 180 216 251 257 266 297 427 571 596 963 1252 1449 1588 1938 2069 2202 2404 2587 2652 2787 2855 3109
36 74 98 169 177 223 381 677 684 748 874 1308 1349 1436 1480 1786 2077 2551 2620 2905 3058 3194 3226
52 361 441 459 672 779 916 942 1189 1335 1725 1829 1932 1957 2055 2111 2378 2451 2572 2800 2847 2894 2934
146 344 392 427 639 853 1022 1070 1466 1488 1511 1564 1632 1730 1754 1921 1963 2122 2442 2634 2955 3092 3162
135 886 2142 2647
719 868 1316 1600
1067 1606 2385 2823
287 911 1506 2242
337 1192 2075 2268
163 1778 2314 2738
192 1401 1589 2046
648 1664 3039 3169
173 1160 1894 2000
73 770 1420 2687
1271 1706 2325 2917
73 1869 2883 3137
249 1012 1160 2721
Consists of
The parity check matrix initial value table of an LDPC code having a coding rate of 1/3 is:
91 115 152 392 509 892 985 1337 1542 1672 1820 2158 2330 2432 2660 2667 2831
364 524 557 1022 1201 1252 1300 1311 1357 1959 2114 2122 2130 2198 2311 2427 2539
245 458 664 869 1063 1164 1236 1398 1497 1669 1874 1955 1981 1989 2125 2349 2874
134 210 315 798 833 1232 1491 1841 1877 1957 1980 2057 2140 2275 2335 2436 2563
66 223 826 1044 1137 1253 1290 1570 1827 1847 1983 2429 2449 2455 2463 2722 2753
159 379 635 744 882 912 934 1086 1174 1545 1585 2225 2356 2747 2765 2807 2848
412 646 1187 2606
361 2212 2349 2505
1317 1442 2076 2611
1312 1940 2211 2295
1200 1581 2063 2410
8 951 1094 2384
102 362 802 2110
175 493 1344 2588
549 1113 1582 2311
1038 1830 2018 2507
880 1177 2078 2241
116 1174 2197 2282
152 1210 1464 2784
936 1185 1740 2087
590 1139 2280 2372
431 839 2281 2363
99 905 1633 2512
213 1050 1288 1707
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 5/12 is:
168 346 446 527 585 747 1129 1159 1276 1283 1361 1512 1527 1532 1537 1782 1794 1956 2133 2369
111 196 301 319 342 354 475 507 712 1026 1444 1454 1459 1553 1813 2024 2053 2162 2245 2479
69 286 372 399 741 759 1224 1515 1682 1685 1781 1843 1870 1984 2015 2045 2232 2236 2285 2411
92 518 550 565 631 643 825 834 987 1072 1108 1136 1227 1255 1341 1418 1430 1836 1880 2020
28 102 149 160 219 287 313 666 671 928 952 1438 1510 2055 2081 2119 2296 2342 2358 2445
147 194 351 460 509 641 748 755 970 1160 1337 1360 1410 1559 1650 1924 2072 2177 2266 2468
47 292 375 1912
957 1430 1717 2072
458 1607 1761 2489
290 805 1122 1189
324 1122 1293 2447
668 1317 2018 2437
507 803 819 1362
471 1952 2027 2359
88 1233 1543 1650
146 314 890 2419
410 1207 1638 2376
80 1302 1442 2166
1064 1263 1531 1696
180 535 1979 2017
910 924 1373 1693
91 1293 1647 1816
1121 1146 1264 2070
321 885 1630 1926
703 821 1155 1163
715 1198 1436 1576
393 758 950 2377
1337 1639 1674 2024
714 1088 1525 1547
1056 1410 1667 1973
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 1/2 is
135 300 342 383 482 543 641 662 798 1058 1125 1187 1398 1472 1582 1651 1716 1796 1799 1836
48 191 227 264 571 613 623 661 664 748 827 1052 1270 1366 1376 1494 1698 1718 1781 1886
75 233 317 382 605 623 656 768 846 1090 1161 1189 1245 1275 1347 1446 1616 1701 1735 1838
236 325 530 552 589 620 637 658 793 800 807 960 1049 1481 1554 1740 1841 1989 1991 2156
79 88 268 541 645 691 773 932 1077 1162 1516 1522 1540 1741 1781 1834 1862 1977 2020 2032
135 235 379 683 724 841 871 963 1014 1020 1241 1353 1533 1624 1643 1700 1957 2073 2107 2113
106 1706 2037 2074
2 131 448 553
138 1198 1690 1911
326 994 1213 1902
207 951 1491 1710
288 676 952 1561
310 579 792 1064
75 150 277 1104
280 971 1515 2015
1714 1876 2107 2126
198 394 551 2145
51 1145 1613 1766
793 1034 1082 1603
390 1423 1486 2010
676 850 1424 1676
706 767 888 1364
499 779 843 2108
317 1045 1497 1507
224 458 609 1933
219 400 689 1591
164 808 895 1902
629 1431 1552 1892
151 338 600 2097
189 1103 1392 1626
33 365 835 1215
573 1022 1576 1877
239 1169 1766 2061
607 846 990 2093
396 612 1427 1999
180 252 566 817
Consists of
The parity check matrix initial value table of an LDPC code having a coding rate of 7/12 is as follows:
182 275 329 391 518 548 588 595 669 672 787 820 967 1016 1023 1056 1088 1108 1170 1573 1639 1784
112 156 251 316 359 451 457 590 635 867 924 970 982 985 1028 1371 1439 1485 1571 1766 1784 1790
0 47 77 143 200 289 425 454 482 531 721 750 763 859 982 1037 1044 1068 1208 1517 1664 1772
28 116 127 142 184 255 279 395 413 453 570 629 676 717 750 842 1371 1599 1606 1653 1675 1764
81 129 142 267 285 471 498 632 680 893 945 994 1059 1105 1316 1326 1364 1616 1635 1715 1720 1747
25 53 69 263 520 553 556 573 920 976 1000 1043 1129 1141 1195 1319 1359 1391 1513 1680 1711 1736
1443 1572 1693 1754
82 470 732 738
1056 1079 1287 1656
85 798 951 1240
795 1208 1481 1703
638 660 935 1069
40 398 538 991
401 773 1187 1752
227 560 690 1741
378 675 881 1511
207 257 636 889
366 654 1041 1279
1079 1121 1434 1515
80 267 564 996
505 948 1271 1545
794 824 1226 1466
822 1021 1032 1474
304 771 1690 1740
69 932 974 1722
575 682 906 1377
418 1134 1633 1674
93 213 613 792
613 749 1264 1368
95 624 646 1107
1561 1592 1736 1774
322 603 1504 1683
52 478 497 1726
307 604 1202 1663
327 607 749 1456
107 510 1624 1708
381 1278 1330 1433
238 637 751 1315
698 1726 1742 1759
319 453 478 1537
642 815 1175 1558
722 939 974 1040
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 2/3 is:
66 80 110 250 268 296 342 502 564 631 845 934 998 1071 1090 1268 1282 1308 1428
3 23 44 212 368 616 681 778 800 844 856 889 949 967 1060 1292 1319 1398 1431
55 144 185 253 266 329 361 424 436 570 699 952 963 1012 1033 1254 1302 1304 1420
28 278 384 598 741 791 809 931 976 1084 1106 1183 1198 1212 1259 1263 1265 1337 1386
7 112 119 147 149 240 268 470 498 534 662 761 813 859 885 1097 1130 1226 1386
120 155 320 345 367 374 395 419 426 535 671 687 793 930 967 1035 1162 1300 1356
622 755 766 950
514 631 757 1073
489 541 614 691
660 786 1162 1216
219 447 635 787
29 572 578 758
170 634 1112 1291
608 892 1320 1345
444 693 1320 1358
358 448 842 1153
695 792 841 894
567 678 777 981
69 341 717 999
405 990 1171 1401
37 130 471 554
850 959 999 1208
464 624 970 1369
757 870 909 1072
45 168 1078 1203
592 735 1344 1401
32 215 445 915
120 1068 1350 1409
701 1062 1205 1319
103 793 1220 1303
579 651 738 757
444 1014 1251 1363
693 947 952 1176
278 499 1261 1325
49 485 1171 1233
238 559 650 947
865 980 1044 1401
50 83 310 500
186 644 1256 1387
340 434 869 1249
644 770 877 1076
299 315 849 1233
299 307 1085 1290
159 324 1091 1313
137 184 863 1404
398 431 478 1069
13 173 993 1133
129 329 730 1143
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 3/4 is:
27 103 130 135 146 249 432 446 501 618 706 795 843 988
80 295 372 403 585 642 719 740 805 904 908 958 999 1033
136 139 230 325 364 385 434 558 605 611 619 771 795 874
143 318 342 347 422 468 489 576 755 767 798 802 952 1014
35 40 187 241 310 458 590 687 698 719 739 765 786 1059
196 457 499 676 729 752 809 818 857 880 917 987 1050 1071
23 141 190 236 381 477 523 594 789 799 919 995 1012 1079
586 636 703 970
205 353 534 940
276 440 495 852
100 138 211 932
114 589 855 946
686 715 844 952
58 239 248 460
351 438 517 1049
245 467 847 867
54 629 698 743
79 490 628 714
138 586 778 861
42 410 485 921
61 882 884 1028
422 444 695 1032
333 385 506 698
83 137 397 534
37 387 489 1073
728 804 836 878
203 374 874 876
373 516 738 766
322 405 477 898
58 451 540 784
311 440 696 900
141 327 818 828
94 205 887 975
437 829 904 1066
3 152 712 889
452 504 689 975
450 651 808 820
425 681 721 845
77 319 330 901
553 769 865 870
168 825 831 938
43 183 771 782
41 325 491 1074
296 452 913 1075
416 728 964 1044
267 477 894 920
193 484 756 986
348 839 861 938
35 233 577 852
355 386 573 721
146 545 644 934
623 779 803 898
560 590 803 1073
219 428 713 1060
A data processing device. LDPC (Low Density Parity Check) code bits are written in the column direction of the storage means for storing in the row direction and the column direction, and the code bits of the LDPC code read in the row direction are used as symbols,
When m bit code bits of 2 bits or more of the LDPC code are transmitted as one symbol,
Column twist interleaving for changing the write start position when the code bits of the LDPC code are written in the column direction of the storage means for each column of the storage means, and rearranging the code bits of the LDPC code It is provided with sorting means to perform as a replacement process,
When the code length of the LDPC code is represented by N bits and the predetermined positive integer is represented by b,
The storage means stores mb bits in the row direction and stores N / (mb) bits in the column direction;
When the sign bit of the mb bits read in the row direction of the storage means is b symbols,
The LDPC code has an encoding rate of 1/4, 1/3, 5/12, 1/2, 7/12, 2/3, or 3/4, and a code length N of 4320 bits. And
The m bits are 6 bits, and the integer b is 2.
The 6-bit code bit of the LDPC code is mapped to any one of ²⁶ signal points determined by a predetermined modulation method,
The storage means has 12 columns storing 6 × 2 bits in the row direction,
The sorting means is
When the address of the head position in the column direction of the storage means is 0, and the address of each position in the column direction of the storage means is represented by an integer in ascending order,
The write start position of the first column of the 12 columns of the storage means is the position where the address is 0,
Of the 12 columns of the storage means, the writing start position of the second column is the position where the address is 0,
Of the 12 columns of the storage means, the write start position of the third column is the position where the address is 3,
Of the 12 columns of the storage means, the write start position of the fourth column is the position where the address is 15,
The write start position of the fifth column of the 12 columns of the storage means is the position where the address is 119,
Of the 12 columns of the storage means, the writing start position of the sixth column is the position where the address is 32,
The write start position of the seventh column of the 12 columns of the storage means is the position where the address is 24,
The write start position of the eighth column of the 12 columns of the storage means, the address is the position of 169,
Of the 12 columns of the storage means, the write start position of the ninth column is the position where the address is 84,
Of the 12 columns of the storage means, the write start position of the 10th column is the position where the address is 3,
Of the 12 columns of the storage means, the write start position of the 11th column is the position where the address is 12,
Of the 12 columns of the storage means, the writing start position of the twelfth column is the position where the address is 3,
The parity check matrix of the LDPC code is based on the parity check matrix initial value table that represents the position of one element of the information matrix corresponding to the information length corresponding to the code length and the coding rate of the parity check matrix every 60 columns. 1 element of the information matrix to be determined is arranged in a column direction with a period of every 60 columns,
The parity check matrix initial value table of an LDPC code with a coding rate of 1/4 is
111 115 245 809 815 864 1015 1050 2008 2077 2090 2277 2357 2382 2413 2455 2546 2598 2608 2664 2805 2981 3089
35 180 216 251 257 266 297 427 571 596 963 1252 1449 1588 1938 2069 2202 2404 2587 2652 2787 2855 3109
36 74 98 169 177 223 381 677 684 748 874 1308 1349 1436 1480 1786 2077 2551 2620 2905 3058 3194 3226
52 361 441 459 672 779 916 942 1189 1335 1725 1829 1932 1957 2055 2111 2378 2451 2572 2800 2847 2894 2934
146 344 392 427 639 853 1022 1070 1466 1488 1511 1564 1632 1730 1754 1921 1963 2122 2442 2634 2955 3092 3162
135 886 2142 2647
719 868 1316 1600
1067 1606 2385 2823
287 911 1506 2242
337 1192 2075 2268
163 1778 2314 2738
192 1401 1589 2046
648 1664 3039 3169
173 1160 1894 2000
73 770 1420 2687
1271 1706 2325 2917
73 1869 2883 3137
249 1012 1160 2721
Consists of
The parity check matrix initial value table of an LDPC code having a coding rate of 1/3 is:
91 115 152 392 509 892 985 1337 1542 1672 1820 2158 2330 2432 2660 2667 2831
364 524 557 1022 1201 1252 1300 1311 1357 1959 2114 2122 2130 2198 2311 2427 2539
245 458 664 869 1063 1164 1236 1398 1497 1669 1874 1955 1981 1989 2125 2349 2874
134 210 315 798 833 1232 1491 1841 1877 1957 1980 2057 2140 2275 2335 2436 2563
66 223 826 1044 1137 1253 1290 1570 1827 1847 1983 2429 2449 2455 2463 2722 2753
159 379 635 744 882 912 934 1086 1174 1545 1585 2225 2356 2747 2765 2807 2848
412 646 1187 2606
361 2212 2349 2505
1317 1442 2076 2611
1312 1940 2211 2295
1200 1581 2063 2410
8 951 1094 2384
102 362 802 2110
175 493 1344 2588
549 1113 1582 2311
1038 1830 2018 2507
880 1177 2078 2241
116 1174 2197 2282
152 1210 1464 2784
936 1185 1740 2087
590 1139 2280 2372
431 839 2281 2363
99 905 1633 2512
213 1050 1288 1707
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 5/12 is:
168 346 446 527 585 747 1129 1159 1276 1283 1361 1512 1527 1532 1537 1782 1794 1956 2133 2369
111 196 301 319 342 354 475 507 712 1026 1444 1454 1459 1553 1813 2024 2053 2162 2245 2479
69 286 372 399 741 759 1224 1515 1682 1685 1781 1843 1870 1984 2015 2045 2232 2236 2285 2411
92 518 550 565 631 643 825 834 987 1072 1108 1136 1227 1255 1341 1418 1430 1836 1880 2020
28 102 149 160 219 287 313 666 671 928 952 1438 1510 2055 2081 2119 2296 2342 2358 2445
147 194 351 460 509 641 748 755 970 1160 1337 1360 1410 1559 1650 1924 2072 2177 2266 2468
47 292 375 1912
957 1430 1717 2072
458 1607 1761 2489
290 805 1122 1189
324 1122 1293 2447
668 1317 2018 2437
507 803 819 1362
471 1952 2027 2359
88 1233 1543 1650
146 314 890 2419
410 1207 1638 2376
80 1302 1442 2166
1064 1263 1531 1696
180 535 1979 2017
910 924 1373 1693
91 1293 1647 1816
1121 1146 1264 2070
321 885 1630 1926
703 821 1155 1163
715 1198 1436 1576
393 758 950 2377
1337 1639 1674 2024
714 1088 1525 1547
1056 1410 1667 1973
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 1/2 is
135 300 342 383 482 543 641 662 798 1058 1125 1187 1398 1472 1582 1651 1716 1796 1799 1836
48 191 227 264 571 613 623 661 664 748 827 1052 1270 1366 1376 1494 1698 1718 1781 1886
75 233 317 382 605 623 656 768 846 1090 1161 1189 1245 1275 1347 1446 1616 1701 1735 1838
236 325 530 552 589 620 637 658 793 800 807 960 1049 1481 1554 1740 1841 1989 1991 2156
79 88 268 541 645 691 773 932 1077 1162 1516 1522 1540 1741 1781 1834 1862 1977 2020 2032
135 235 379 683 724 841 871 963 1014 1020 1241 1353 1533 1624 1643 1700 1957 2073 2107 2113
106 1706 2037 2074
2 131 448 553
138 1198 1690 1911
326 994 1213 1902
207 951 1491 1710
288 676 952 1561
310 579 792 1064
75 150 277 1104
280 971 1515 2015
1714 1876 2107 2126
198 394 551 2145
51 1145 1613 1766
793 1034 1082 1603
390 1423 1486 2010
676 850 1424 1676
706 767 888 1364
499 779 843 2108
317 1045 1497 1507
224 458 609 1933
219 400 689 1591
164 808 895 1902
629 1431 1552 1892
151 338 600 2097
189 1103 1392 1626
33 365 835 1215
573 1022 1576 1877
239 1169 1766 2061
607 846 990 2093
396 612 1427 1999
180 252 566 817
Consists of
The parity check matrix initial value table of an LDPC code having a coding rate of 7/12 is as follows:
182 275 329 391 518 548 588 595 669 672 787 820 967 1016 1023 1056 1088 1108 1170 1573 1639 1784
112 156 251 316 359 451 457 590 635 867 924 970 982 985 1028 1371 1439 1485 1571 1766 1784 1790
0 47 77 143 200 289 425 454 482 531 721 750 763 859 982 1037 1044 1068 1208 1517 1664 1772
28 116 127 142 184 255 279 395 413 453 570 629 676 717 750 842 1371 1599 1606 1653 1675 1764
81 129 142 267 285 471 498 632 680 893 945 994 1059 1105 1316 1326 1364 1616 1635 1715 1720 1747
25 53 69 263 520 553 556 573 920 976 1000 1043 1129 1141 1195 1319 1359 1391 1513 1680 1711 1736
1443 1572 1693 1754
82 470 732 738
1056 1079 1287 1656
85 798 951 1240
795 1208 1481 1703
638 660 935 1069
40 398 538 991
401 773 1187 1752
227 560 690 1741
378 675 881 1511
207 257 636 889
366 654 1041 1279
1079 1121 1434 1515
80 267 564 996
505 948 1271 1545
794 824 1226 1466
822 1021 1032 1474
304 771 1690 1740
69 932 974 1722
575 682 906 1377
418 1134 1633 1674
93 213 613 792
613 749 1264 1368
95 624 646 1107
1561 1592 1736 1774
322 603 1504 1683
52 478 497 1726
307 604 1202 1663
327 607 749 1456
107 510 1624 1708
381 1278 1330 1433
238 637 751 1315
698 1726 1742 1759
319 453 478 1537
642 815 1175 1558
722 939 974 1040
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 2/3 is:
66 80 110 250 268 296 342 502 564 631 845 934 998 1071 1090 1268 1282 1308 1428
3 23 44 212 368 616 681 778 800 844 856 889 949 967 1060 1292 1319 1398 1431
55 144 185 253 266 329 361 424 436 570 699 952 963 1012 1033 1254 1302 1304 1420
28 278 384 598 741 791 809 931 976 1084 1106 1183 1198 1212 1259 1263 1265 1337 1386
7 112 119 147 149 240 268 470 498 534 662 761 813 859 885 1097 1130 1226 1386
120 155 320 345 367 374 395 419 426 535 671 687 793 930 967 1035 1162 1300 1356
622 755 766 950
514 631 757 1073
489 541 614 691
660 786 1162 1216
219 447 635 787
29 572 578 758
170 634 1112 1291
608 892 1320 1345
444 693 1320 1358
358 448 842 1153
695 792 841 894
567 678 777 981
69 341 717 999
405 990 1171 1401
37 130 471 554
850 959 999 1208
464 624 970 1369
757 870 909 1072
45 168 1078 1203
592 735 1344 1401
32 215 445 915
120 1068 1350 1409
701 1062 1205 1319
103 793 1220 1303
579 651 738 757
444 1014 1251 1363
693 947 952 1176
278 499 1261 1325
49 485 1171 1233
238 559 650 947
865 980 1044 1401
50 83 310 500
186 644 1256 1387
340 434 869 1249
644 770 877 1076
299 315 849 1233
299 307 1085 1290
159 324 1091 1313
137 184 863 1404
398 431 478 1069
13 173 993 1133
129 329 730 1143
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 3/4 is:
27 103 130 135 146 249 432 446 501 618 706 795 843 988
80 295 372 403 585 642 719 740 805 904 908 958 999 1033
136 139 230 325 364 385 434 558 605 611 619 771 795 874
143 318 342 347 422 468 489 576 755 767 798 802 952 1014
35 40 187 241 310 458 590 687 698 719 739 765 786 1059
196 457 499 676 729 752 809 818 857 880 917 987 1050 1071
23 141 190 236 381 477 523 594 789 799 919 995 1012 1079
586 636 703 970
205 353 534 940
276 440 495 852
100 138 211 932
114 589 855 946
686 715 844 952
58 239 248 460
351 438 517 1049
245 467 847 867
54 629 698 743
79 490 628 714
138 586 778 861
42 410 485 921
61 882 884 1028
422 444 695 1032
333 385 506 698
83 137 397 534
37 387 489 1073
728 804 836 878
203 374 874 876
373 516 738 766
322 405 477 898
58 451 540 784
311 440 696 900
141 327 818 828
94 205 887 975
437 829 904 1066
3 152 712 889
452 504 689 975
450 651 808 820
425 681 721 845
77 319 330 901
553 769 865 870
168 825 831 938
43 183 771 782
41 325 491 1074
296 452 913 1075
416 728 964 1044
267 477 894 920
193 484 756 986
348 839 861 938
35 233 577 852
355 386 573 721
146 545 644 934
623 779 803 898
560 590 803 1073
219 428 713 1060
A data processing device. LDPC (Low Density Parity Check) code bits are written in the column direction of the storage means for storing in the row direction and the column direction, and the code bits of the LDPC code read in the row direction are used as symbols,
When m bit code bits of 2 bits or more of the LDPC code are transmitted as one symbol,
Column twist interleaving for changing the write start position when the code bits of the LDPC code are written in the column direction of the storage means for each column of the storage means, and rearranging the code bits of the LDPC code A rearrangement step is performed as a replacement process.
When the code length of the LDPC code is represented by N bits and the predetermined positive integer is represented by b,
The storage means stores mb bits in the row direction and stores N / (mb) bits in the column direction;
When the sign bit of the mb bits read in the row direction of the storage means is b symbols,
The LDPC code has an encoding rate of 1/4, 1/3, 5/12, 1/2, 7/12, 2/3, or 3/4, and a code length N of 4320 bits. And
The m bits is 2 bits, and the integer b is 1.
The sign bit of the 2 bits of the LDPC code are mapped to one of 2 ² signal points prescribed in a predetermined modulation scheme,
The storage means has two columns for storing 2 × 1 bits in the row direction,
In the sorting step,
When the address of the head position in the column direction of the storage means is 0, and the address of each position in the column direction of the storage means is represented by an integer in ascending order,
The write start position of the first column of the two columns of the storage means is the position where the address is 0,
The write start position of the second column of the two columns of the storage means is the position where the address is 60,
The parity check matrix of the LDPC code is based on the parity check matrix initial value table that represents the position of one element of the information matrix corresponding to the information length corresponding to the code length and the coding rate of the parity check matrix every 60 columns. 1 element of the information matrix to be determined is arranged in a column direction with a period of every 60 columns,
The parity check matrix initial value table of an LDPC code with a coding rate of 1/4 is
111 115 245 809 815 864 1015 1050 2008 2077 2090 2277 2357 2382 2413 2455 2546 2598 2608 2664 2805 2981 3089
35 180 216 251 257 266 297 427 571 596 963 1252 1449 1588 1938 2069 2202 2404 2587 2652 2787 2855 3109
36 74 98 169 177 223 381 677 684 748 874 1308 1349 1436 1480 1786 2077 2551 2620 2905 3058 3194 3226
52 361 441 459 672 779 916 942 1189 1335 1725 1829 1932 1957 2055 2111 2378 2451 2572 2800 2847 2894 2934
146 344 392 427 639 853 1022 1070 1466 1488 1511 1564 1632 1730 1754 1921 1963 2122 2442 2634 2955 3092 3162
135 886 2142 2647
719 868 1316 1600
1067 1606 2385 2823
287 911 1506 2242
337 1192 2075 2268
163 1778 2314 2738
192 1401 1589 2046
648 1664 3039 3169
173 1160 1894 2000
73 770 1420 2687
1271 1706 2325 2917
73 1869 2883 3137
249 1012 1160 2721
Consists of
The parity check matrix initial value table of an LDPC code having a coding rate of 1/3 is:
91 115 152 392 509 892 985 1337 1542 1672 1820 2158 2330 2432 2660 2667 2831
364 524 557 1022 1201 1252 1300 1311 1357 1959 2114 2122 2130 2198 2311 2427 2539
245 458 664 869 1063 1164 1236 1398 1497 1669 1874 1955 1981 1989 2125 2349 2874
134 210 315 798 833 1232 1491 1841 1877 1957 1980 2057 2140 2275 2335 2436 2563
66 223 826 1044 1137 1253 1290 1570 1827 1847 1983 2429 2449 2455 2463 2722 2753
159 379 635 744 882 912 934 1086 1174 1545 1585 2225 2356 2747 2765 2807 2848
412 646 1187 2606
361 2212 2349 2505
1317 1442 2076 2611
1312 1940 2211 2295
1200 1581 2063 2410
8 951 1094 2384
102 362 802 2110
175 493 1344 2588
549 1113 1582 2311
1038 1830 2018 2507
880 1177 2078 2241
116 1174 2197 2282
152 1210 1464 2784
936 1185 1740 2087
590 1139 2280 2372
431 839 2281 2363
99 905 1633 2512
213 1050 1288 1707
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 5/12 is:
168 346 446 527 585 747 1129 1159 1276 1283 1361 1512 1527 1532 1537 1782 1794 1956 2133 2369
111 196 301 319 342 354 475 507 712 1026 1444 1454 1459 1553 1813 2024 2053 2162 2245 2479
69 286 372 399 741 759 1224 1515 1682 1685 1781 1843 1870 1984 2015 2045 2232 2236 2285 2411
92 518 550 565 631 643 825 834 987 1072 1108 1136 1227 1255 1341 1418 1430 1836 1880 2020
28 102 149 160 219 287 313 666 671 928 952 1438 1510 2055 2081 2119 2296 2342 2358 2445
147 194 351 460 509 641 748 755 970 1160 1337 1360 1410 1559 1650 1924 2072 2177 2266 2468
47 292 375 1912
957 1430 1717 2072
458 1607 1761 2489
290 805 1122 1189
324 1122 1293 2447
668 1317 2018 2437
507 803 819 1362
471 1952 2027 2359
88 1233 1543 1650
146 314 890 2419
410 1207 1638 2376
80 1302 1442 2166
1064 1263 1531 1696
180 535 1979 2017
910 924 1373 1693
91 1293 1647 1816
1121 1146 1264 2070
321 885 1630 1926
703 821 1155 1163
715 1198 1436 1576
393 758 950 2377
1337 1639 1674 2024
714 1088 1525 1547
1056 1410 1667 1973
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 1/2 is
135 300 342 383 482 543 641 662 798 1058 1125 1187 1398 1472 1582 1651 1716 1796 1799 1836
48 191 227 264 571 613 623 661 664 748 827 1052 1270 1366 1376 1494 1698 1718 1781 1886
75 233 317 382 605 623 656 768 846 1090 1161 1189 1245 1275 1347 1446 1616 1701 1735 1838
236 325 530 552 589 620 637 658 793 800 807 960 1049 1481 1554 1740 1841 1989 1991 2156
79 88 268 541 645 691 773 932 1077 1162 1516 1522 1540 1741 1781 1834 1862 1977 2020 2032
135 235 379 683 724 841 871 963 1014 1020 1241 1353 1533 1624 1643 1700 1957 2073 2107 2113
106 1706 2037 2074
2 131 448 553
138 1198 1690 1911
326 994 1213 1902
207 951 1491 1710
288 676 952 1561
310 579 792 1064
75 150 277 1104
280 971 1515 2015
1714 1876 2107 2126
198 394 551 2145
51 1145 1613 1766
793 1034 1082 1603
390 1423 1486 2010
676 850 1424 1676
706 767 888 1364
499 779 843 2108
317 1045 1497 1507
224 458 609 1933
219 400 689 1591
164 808 895 1902
629 1431 1552 1892
151 338 600 2097
189 1103 1392 1626
33 365 835 1215
573 1022 1576 1877
239 1169 1766 2061
607 846 990 2093
396 612 1427 1999
180 252 566 817
Consists of
The parity check matrix initial value table of an LDPC code having a coding rate of 7/12 is as follows:
182 275 329 391 518 548 588 595 669 672 787 820 967 1016 1023 1056 1088 1108 1170 1573 1639 1784
112 156 251 316 359 451 457 590 635 867 924 970 982 985 1028 1371 1439 1485 1571 1766 1784 1790
0 47 77 143 200 289 425 454 482 531 721 750 763 859 982 1037 1044 1068 1208 1517 1664 1772
28 116 127 142 184 255 279 395 413 453 570 629 676 717 750 842 1371 1599 1606 1653 1675 1764
81 129 142 267 285 471 498 632 680 893 945 994 1059 1105 1316 1326 1364 1616 1635 1715 1720 1747
25 53 69 263 520 553 556 573 920 976 1000 1043 1129 1141 1195 1319 1359 1391 1513 1680 1711 1736
1443 1572 1693 1754
82 470 732 738
1056 1079 1287 1656
85 798 951 1240
795 1208 1481 1703
638 660 935 1069
40 398 538 991
401 773 1187 1752
227 560 690 1741
378 675 881 1511
207 257 636 889
366 654 1041 1279
1079 1121 1434 1515
80 267 564 996
505 948 1271 1545
794 824 1226 1466
822 1021 1032 1474
304 771 1690 1740
69 932 974 1722
575 682 906 1377
418 1134 1633 1674
93 213 613 792
613 749 1264 1368
95 624 646 1107
1561 1592 1736 1774
322 603 1504 1683
52 478 497 1726
307 604 1202 1663
327 607 749 1456
107 510 1624 1708
381 1278 1330 1433
238 637 751 1315
698 1726 1742 1759
319 453 478 1537
642 815 1175 1558
722 939 974 1040
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 2/3 is:
66 80 110 250 268 296 342 502 564 631 845 934 998 1071 1090 1268 1282 1308 1428
3 23 44 212 368 616 681 778 800 844 856 889 949 967 1060 1292 1319 1398 1431
55 144 185 253 266 329 361 424 436 570 699 952 963 1012 1033 1254 1302 1304 1420
28 278 384 598 741 791 809 931 976 1084 1106 1183 1198 1212 1259 1263 1265 1337 1386
7 112 119 147 149 240 268 470 498 534 662 761 813 859 885 1097 1130 1226 1386
120 155 320 345 367 374 395 419 426 535 671 687 793 930 967 1035 1162 1300 1356
622 755 766 950
514 631 757 1073
489 541 614 691
660 786 1162 1216
219 447 635 787
29 572 578 758
170 634 1112 1291
608 892 1320 1345
444 693 1320 1358
358 448 842 1153
695 792 841 894
567 678 777 981
69 341 717 999
405 990 1171 1401
37 130 471 554
850 959 999 1208
464 624 970 1369
757 870 909 1072
45 168 1078 1203
592 735 1344 1401
32 215 445 915
120 1068 1350 1409
701 1062 1205 1319
103 793 1220 1303
579 651 738 757
444 1014 1251 1363
693 947 952 1176
278 499 1261 1325
49 485 1171 1233
238 559 650 947
865 980 1044 1401
50 83 310 500
186 644 1256 1387
340 434 869 1249
644 770 877 1076
299 315 849 1233
299 307 1085 1290
159 324 1091 1313
137 184 863 1404
398 431 478 1069
13 173 993 1133
129 329 730 1143
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 3/4 is:
27 103 130 135 146 249 432 446 501 618 706 795 843 988
80 295 372 403 585 642 719 740 805 904 908 958 999 1033
136 139 230 325 364 385 434 558 605 611 619 771 795 874
143 318 342 347 422 468 489 576 755 767 798 802 952 1014
35 40 187 241 310 458 590 687 698 719 739 765 786 1059
196 457 499 676 729 752 809 818 857 880 917 987 1050 1071
23 141 190 236 381 477 523 594 789 799 919 995 1012 1079
586 636 703 970
205 353 534 940
276 440 495 852
100 138 211 932
114 589 855 946
686 715 844 952
58 239 248 460
351 438 517 1049
245 467 847 867
54 629 698 743
79 490 628 714
138 586 778 861
42 410 485 921
61 882 884 1028
422 444 695 1032
333 385 506 698
83 137 397 534
37 387 489 1073
728 804 836 878
203 374 874 876
373 516 738 766
322 405 477 898
58 451 540 784
311 440 696 900
141 327 818 828
94 205 887 975
437 829 904 1066
3 152 712 889
452 504 689 975
450 651 808 820
425 681 721 845
77 319 330 901
553 769 865 870
168 825 831 938
43 183 771 782
41 325 491 1074
296 452 913 1075
416 728 964 1044
267 477 894 920
193 484 756 986
348 839 861 938
35 233 577 852
355 386 573 721
146 545 644 934
623 779 803 898
560 590 803 1073
219 428 713 1060
A data processing method. LDPC (Low Density Parity Check) code bits are written in the column direction of the storage means for storing in the row direction and the column direction, and the code bits of the LDPC code read in the row direction are used as symbols,
When m bit code bits of 2 bits or more of the LDPC code are transmitted as one symbol,
Column twist interleaving for changing the write start position when the code bits of the LDPC code are written in the column direction of the storage means for each column of the storage means, and rearranging the code bits of the LDPC code A rearrangement step is performed as a replacement process.
When the code length of the LDPC code is represented by N bits and the predetermined positive integer is represented by b,
The storage means stores mb bits in the row direction and stores N / (mb) bits in the column direction;
When the sign bit of the mb bits read in the row direction of the storage means is b symbols,
The LDPC code has an encoding rate of 1/4, 1/3, 5/12, 1/2, 7/12, 2/3, or 3/4, and a code length N of 4320 bits. And
The m bits are 2 bits, and the integer b is 2.
The sign bit of the 2 bits of the LDPC code are mapped to one of 2 ² signal points prescribed in a predetermined modulation scheme,
The storage means has four columns for storing 2 × 2 bits in the row direction,
In the sorting step,
When the address of the head position in the column direction of the storage means is 0, and the address of each position in the column direction of the storage means is represented by an integer in ascending order,
The write start position of the first column of the four columns of the storage means is the position where the address is 0,
The write start position of the second column of the four columns of the storage means is the position where the address is 62,
The write start position of the third column of the four columns of the storage means is the position where the address is 36,
The write start position of the fourth column of the four columns of the storage means is the position where the address is 3,
The parity check matrix of the LDPC code is based on the parity check matrix initial value table that represents the position of one element of the information matrix corresponding to the information length corresponding to the code length and the coding rate of the parity check matrix every 60 columns. 1 element of the information matrix to be determined is arranged in a column direction with a period of every 60 columns,
The parity check matrix initial value table of an LDPC code with a coding rate of 1/4 is
111 115 245 809 815 864 1015 1050 2008 2077 2090 2277 2357 2382 2413 2455 2546 2598 2608 2664 2805 2981 3089
35 180 216 251 257 266 297 427 571 596 963 1252 1449 1588 1938 2069 2202 2404 2587 2652 2787 2855 3109
36 74 98 169 177 223 381 677 684 748 874 1308 1349 1436 1480 1786 2077 2551 2620 2905 3058 3194 3226
52 361 441 459 672 779 916 942 1189 1335 1725 1829 1932 1957 2055 2111 2378 2451 2572 2800 2847 2894 2934
146 344 392 427 639 853 1022 1070 1466 1488 1511 1564 1632 1730 1754 1921 1963 2122 2442 2634 2955 3092 3162
135 886 2142 2647
719 868 1316 1600
1067 1606 2385 2823
287 911 1506 2242
337 1192 2075 2268
163 1778 2314 2738
192 1401 1589 2046
648 1664 3039 3169
173 1160 1894 2000
73 770 1420 2687
1271 1706 2325 2917
73 1869 2883 3137
249 1012 1160 2721
Consists of
The parity check matrix initial value table of an LDPC code having a coding rate of 1/3 is:
91 115 152 392 509 892 985 1337 1542 1672 1820 2158 2330 2432 2660 2667 2831
364 524 557 1022 1201 1252 1300 1311 1357 1959 2114 2122 2130 2198 2311 2427 2539
245 458 664 869 1063 1164 1236 1398 1497 1669 1874 1955 1981 1989 2125 2349 2874
134 210 315 798 833 1232 1491 1841 1877 1957 1980 2057 2140 2275 2335 2436 2563
66 223 826 1044 1137 1253 1290 1570 1827 1847 1983 2429 2449 2455 2463 2722 2753
159 379 635 744 882 912 934 1086 1174 1545 1585 2225 2356 2747 2765 2807 2848
412 646 1187 2606
361 2212 2349 2505
1317 1442 2076 2611
1312 1940 2211 2295
1200 1581 2063 2410
8 951 1094 2384
102 362 802 2110
175 493 1344 2588
549 1113 1582 2311
1038 1830 2018 2507
880 1177 2078 2241
116 1174 2197 2282
152 1210 1464 2784
936 1185 1740 2087
590 1139 2280 2372
431 839 2281 2363
99 905 1633 2512
213 1050 1288 1707
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 5/12 is:
168 346 446 527 585 747 1129 1159 1276 1283 1361 1512 1527 1532 1537 1782 1794 1956 2133 2369
111 196 301 319 342 354 475 507 712 1026 1444 1454 1459 1553 1813 2024 2053 2162 2245 2479
69 286 372 399 741 759 1224 1515 1682 1685 1781 1843 1870 1984 2015 2045 2232 2236 2285 2411
92 518 550 565 631 643 825 834 987 1072 1108 1136 1227 1255 1341 1418 1430 1836 1880 2020
28 102 149 160 219 287 313 666 671 928 952 1438 1510 2055 2081 2119 2296 2342 2358 2445
147 194 351 460 509 641 748 755 970 1160 1337 1360 1410 1559 1650 1924 2072 2177 2266 2468
47 292 375 1912
957 1430 1717 2072
458 1607 1761 2489
290 805 1122 1189
324 1122 1293 2447
668 1317 2018 2437
507 803 819 1362
471 1952 2027 2359
88 1233 1543 1650
146 314 890 2419
410 1207 1638 2376
80 1302 1442 2166
1064 1263 1531 1696
180 535 1979 2017
910 924 1373 1693
91 1293 1647 1816
1121 1146 1264 2070
321 885 1630 1926
703 821 1155 1163
715 1198 1436 1576
393 758 950 2377
1337 1639 1674 2024
714 1088 1525 1547
1056 1410 1667 1973
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 1/2 is
135 300 342 383 482 543 641 662 798 1058 1125 1187 1398 1472 1582 1651 1716 1796 1799 1836
48 191 227 264 571 613 623 661 664 748 827 1052 1270 1366 1376 1494 1698 1718 1781 1886
75 233 317 382 605 623 656 768 846 1090 1161 1189 1245 1275 1347 1446 1616 1701 1735 1838
236 325 530 552 589 620 637 658 793 800 807 960 1049 1481 1554 1740 1841 1989 1991 2156
79 88 268 541 645 691 773 932 1077 1162 1516 1522 1540 1741 1781 1834 1862 1977 2020 2032
135 235 379 683 724 841 871 963 1014 1020 1241 1353 1533 1624 1643 1700 1957 2073 2107 2113
106 1706 2037 2074
2 131 448 553
138 1198 1690 1911
326 994 1213 1902
207 951 1491 1710
288 676 952 1561
310 579 792 1064
75 150 277 1104
280 971 1515 2015
1714 1876 2107 2126
198 394 551 2145
51 1145 1613 1766
793 1034 1082 1603
390 1423 1486 2010
676 850 1424 1676
706 767 888 1364
499 779 843 2108
317 1045 1497 1507
224 458 609 1933
219 400 689 1591
164 808 895 1902
629 1431 1552 1892
151 338 600 2097
189 1103 1392 1626
33 365 835 1215
573 1022 1576 1877
239 1169 1766 2061
607 846 990 2093
396 612 1427 1999
180 252 566 817
Consists of
The parity check matrix initial value table of an LDPC code having a coding rate of 7/12 is as follows:
182 275 329 391 518 548 588 595 669 672 787 820 967 1016 1023 1056 1088 1108 1170 1573 1639 1784
112 156 251 316 359 451 457 590 635 867 924 970 982 985 1028 1371 1439 1485 1571 1766 1784 1790
0 47 77 143 200 289 425 454 482 531 721 750 763 859 982 1037 1044 1068 1208 1517 1664 1772
28 116 127 142 184 255 279 395 413 453 570 629 676 717 750 842 1371 1599 1606 1653 1675 1764
81 129 142 267 285 471 498 632 680 893 945 994 1059 1105 1316 1326 1364 1616 1635 1715 1720 1747
25 53 69 263 520 553 556 573 920 976 1000 1043 1129 1141 1195 1319 1359 1391 1513 1680 1711 1736
1443 1572 1693 1754
82 470 732 738
1056 1079 1287 1656
85 798 951 1240
795 1208 1481 1703
638 660 935 1069
40 398 538 991
401 773 1187 1752
227 560 690 1741
378 675 881 1511
207 257 636 889
366 654 1041 1279
1079 1121 1434 1515
80 267 564 996
505 948 1271 1545
794 824 1226 1466
822 1021 1032 1474
304 771 1690 1740
69 932 974 1722
575 682 906 1377
418 1134 1633 1674
93 213 613 792
613 749 1264 1368
95 624 646 1107
1561 1592 1736 1774
322 603 1504 1683
52 478 497 1726
307 604 1202 1663
327 607 749 1456
107 510 1624 1708
381 1278 1330 1433
238 637 751 1315
698 1726 1742 1759
319 453 478 1537
642 815 1175 1558
722 939 974 1040
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 2/3 is:
66 80 110 250 268 296 342 502 564 631 845 934 998 1071 1090 1268 1282 1308 1428
3 23 44 212 368 616 681 778 800 844 856 889 949 967 1060 1292 1319 1398 1431
55 144 185 253 266 329 361 424 436 570 699 952 963 1012 1033 1254 1302 1304 1420
28 278 384 598 741 791 809 931 976 1084 1106 1183 1198 1212 1259 1263 1265 1337 1386
7 112 119 147 149 240 268 470 498 534 662 761 813 859 885 1097 1130 1226 1386
120 155 320 345 367 374 395 419 426 535 671 687 793 930 967 1035 1162 1300 1356
622 755 766 950
514 631 757 1073
489 541 614 691
660 786 1162 1216
219 447 635 787
29 572 578 758
170 634 1112 1291
608 892 1320 1345
444 693 1320 1358
358 448 842 1153
695 792 841 894
567 678 777 981
69 341 717 999
405 990 1171 1401
37 130 471 554
850 959 999 1208
464 624 970 1369
757 870 909 1072
45 168 1078 1203
592 735 1344 1401
32 215 445 915
120 1068 1350 1409
701 1062 1205 1319
103 793 1220 1303
579 651 738 757
444 1014 1251 1363
693 947 952 1176
278 499 1261 1325
49 485 1171 1233
238 559 650 947
865 980 1044 1401
50 83 310 500
186 644 1256 1387
340 434 869 1249
644 770 877 1076
299 315 849 1233
299 307 1085 1290
159 324 1091 1313
137 184 863 1404
398 431 478 1069
13 173 993 1133
129 329 730 1143
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 3/4 is:
27 103 130 135 146 249 432 446 501 618 706 795 843 988
80 295 372 403 585 642 719 740 805 904 908 958 999 1033
136 139 230 325 364 385 434 558 605 611 619 771 795 874
143 318 342 347 422 468 489 576 755 767 798 802 952 1014
35 40 187 241 310 458 590 687 698 719 739 765 786 1059
196 457 499 676 729 752 809 818 857 880 917 987 1050 1071
23 141 190 236 381 477 523 594 789 799 919 995 1012 1079
586 636 703 970
205 353 534 940
276 440 495 852
100 138 211 932
114 589 855 946
686 715 844 952
58 239 248 460
351 438 517 1049
245 467 847 867
54 629 698 743
79 490 628 714
138 586 778 861
42 410 485 921
61 882 884 1028
422 444 695 1032
333 385 506 698
83 137 397 534
37 387 489 1073
728 804 836 878
203 374 874 876
373 516 738 766
322 405 477 898
58 451 540 784
311 440 696 900
141 327 818 828
94 205 887 975
437 829 904 1066
3 152 712 889
452 504 689 975
450 651 808 820
425 681 721 845
77 319 330 901
553 769 865 870
168 825 831 938
43 183 771 782
41 325 491 1074
296 452 913 1075
416 728 964 1044
267 477 894 920
193 484 756 986
348 839 861 938
35 233 577 852
355 386 573 721
146 545 644 934
623 779 803 898
560 590 803 1073
219 428 713 1060
A data processing method. LDPC (Low Density Parity Check) code bits are written in the column direction of the storage means for storing in the row direction and the column direction, and the code bits of the LDPC code read in the row direction are used as symbols,
When m bit code bits of 2 bits or more of the LDPC code are transmitted as one symbol,
Column twist interleaving for changing the write start position when the code bits of the LDPC code are written in the column direction of the storage means for each column of the storage means, and rearranging the code bits of the LDPC code A rearrangement step is performed as a replacement process.
When the code length of the LDPC code is represented by N bits and the predetermined positive integer is represented by b,
The storage means stores mb bits in the row direction and stores N / (mb) bits in the column direction;
When the sign bit of the mb bits read in the row direction of the storage means is b symbols,
The LDPC code has an encoding rate of 1/4, 1/3, 5/12, 1/2, 7/12, 2/3, or 3/4, and a code length N of 4320 bits. And
The m bits are 4 bits, and the integer b is 1.
The sign bit of the 4 bits of the LDPC code are mapped to one of 2 ⁴ signal points prescribed in a predetermined modulation scheme,
The storage means has four columns for storing 4 × 1 bits in the row direction,
In the sorting step,
When the address of the head position in the column direction of the storage means is 0, and the address of each position in the column direction of the storage means is represented by an integer in ascending order,
The write start position of the first column of the four columns of the storage means is the position where the address is 0,
The write start position of the second column of the four columns of the storage means is the position where the address is 62,
The write start position of the third column of the four columns of the storage means is the position where the address is 36,
The write start position of the fourth column of the four columns of the storage means is the position where the address is 3,
The parity check matrix of the LDPC code is based on the parity check matrix initial value table that represents the position of one element of the information matrix corresponding to the information length corresponding to the code length and the coding rate of the parity check matrix every 60 columns. 1 element of the information matrix to be determined is arranged in a column direction with a period of every 60 columns,
The parity check matrix initial value table of an LDPC code with a coding rate of 1/4 is
111 115 245 809 815 864 1015 1050 2008 2077 2090 2277 2357 2382 2413 2455 2546 2598 2608 2664 2805 2981 3089
35 180 216 251 257 266 297 427 571 596 963 1252 1449 1588 1938 2069 2202 2404 2587 2652 2787 2855 3109
36 74 98 169 177 223 381 677 684 748 874 1308 1349 1436 1480 1786 2077 2551 2620 2905 3058 3194 3226
52 361 441 459 672 779 916 942 1189 1335 1725 1829 1932 1957 2055 2111 2378 2451 2572 2800 2847 2894 2934
146 344 392 427 639 853 1022 1070 1466 1488 1511 1564 1632 1730 1754 1921 1963 2122 2442 2634 2955 3092 3162
135 886 2142 2647
719 868 1316 1600
1067 1606 2385 2823
287 911 1506 2242
337 1192 2075 2268
163 1778 2314 2738
192 1401 1589 2046
648 1664 3039 3169
173 1160 1894 2000
73 770 1420 2687
1271 1706 2325 2917
73 1869 2883 3137
249 1012 1160 2721
Consists of
The parity check matrix initial value table of an LDPC code having a coding rate of 1/3 is:
91 115 152 392 509 892 985 1337 1542 1672 1820 2158 2330 2432 2660 2667 2831
364 524 557 1022 1201 1252 1300 1311 1357 1959 2114 2122 2130 2198 2311 2427 2539
245 458 664 869 1063 1164 1236 1398 1497 1669 1874 1955 1981 1989 2125 2349 2874
134 210 315 798 833 1232 1491 1841 1877 1957 1980 2057 2140 2275 2335 2436 2563
66 223 826 1044 1137 1253 1290 1570 1827 1847 1983 2429 2449 2455 2463 2722 2753
159 379 635 744 882 912 934 1086 1174 1545 1585 2225 2356 2747 2765 2807 2848
412 646 1187 2606
361 2212 2349 2505
1317 1442 2076 2611
1312 1940 2211 2295
1200 1581 2063 2410
8 951 1094 2384
102 362 802 2110
175 493 1344 2588
549 1113 1582 2311
1038 1830 2018 2507
880 1177 2078 2241
116 1174 2197 2282
152 1210 1464 2784
936 1185 1740 2087
590 1139 2280 2372
431 839 2281 2363
99 905 1633 2512
213 1050 1288 1707
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 5/12 is:
168 346 446 527 585 747 1129 1159 1276 1283 1361 1512 1527 1532 1537 1782 1794 1956 2133 2369
111 196 301 319 342 354 475 507 712 1026 1444 1454 1459 1553 1813 2024 2053 2162 2245 2479
69 286 372 399 741 759 1224 1515 1682 1685 1781 1843 1870 1984 2015 2045 2232 2236 2285 2411
92 518 550 565 631 643 825 834 987 1072 1108 1136 1227 1255 1341 1418 1430 1836 1880 2020
28 102 149 160 219 287 313 666 671 928 952 1438 1510 2055 2081 2119 2296 2342 2358 2445
147 194 351 460 509 641 748 755 970 1160 1337 1360 1410 1559 1650 1924 2072 2177 2266 2468
47 292 375 1912
957 1430 1717 2072
458 1607 1761 2489
290 805 1122 1189
324 1122 1293 2447
668 1317 2018 2437
507 803 819 1362
471 1952 2027 2359
88 1233 1543 1650
146 314 890 2419
410 1207 1638 2376
80 1302 1442 2166
1064 1263 1531 1696
180 535 1979 2017
910 924 1373 1693
91 1293 1647 1816
1121 1146 1264 2070
321 885 1630 1926
703 821 1155 1163
715 1198 1436 1576
393 758 950 2377
1337 1639 1674 2024
714 1088 1525 1547
1056 1410 1667 1973
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 1/2 is
135 300 342 383 482 543 641 662 798 1058 1125 1187 1398 1472 1582 1651 1716 1796 1799 1836
48 191 227 264 571 613 623 661 664 748 827 1052 1270 1366 1376 1494 1698 1718 1781 1886
75 233 317 382 605 623 656 768 846 1090 1161 1189 1245 1275 1347 1446 1616 1701 1735 1838
236 325 530 552 589 620 637 658 793 800 807 960 1049 1481 1554 1740 1841 1989 1991 2156
79 88 268 541 645 691 773 932 1077 1162 1516 1522 1540 1741 1781 1834 1862 1977 2020 2032
135 235 379 683 724 841 871 963 1014 1020 1241 1353 1533 1624 1643 1700 1957 2073 2107 2113
106 1706 2037 2074
2 131 448 553
138 1198 1690 1911
326 994 1213 1902
207 951 1491 1710
288 676 952 1561
310 579 792 1064
75 150 277 1104
280 971 1515 2015
1714 1876 2107 2126
198 394 551 2145
51 1145 1613 1766
793 1034 1082 1603
390 1423 1486 2010
676 850 1424 1676
706 767 888 1364
499 779 843 2108
317 1045 1497 1507
224 458 609 1933
219 400 689 1591
164 808 895 1902
629 1431 1552 1892
151 338 600 2097
189 1103 1392 1626
33 365 835 1215
573 1022 1576 1877
239 1169 1766 2061
607 846 990 2093
396 612 1427 1999
180 252 566 817
Consists of
The parity check matrix initial value table of an LDPC code having a coding rate of 7/12 is as follows:
182 275 329 391 518 548 588 595 669 672 787 820 967 1016 1023 1056 1088 1108 1170 1573 1639 1784
112 156 251 316 359 451 457 590 635 867 924 970 982 985 1028 1371 1439 1485 1571 1766 1784 1790
0 47 77 143 200 289 425 454 482 531 721 750 763 859 982 1037 1044 1068 1208 1517 1664 1772
28 116 127 142 184 255 279 395 413 453 570 629 676 717 750 842 1371 1599 1606 1653 1675 1764
81 129 142 267 285 471 498 632 680 893 945 994 1059 1105 1316 1326 1364 1616 1635 1715 1720 1747
25 53 69 263 520 553 556 573 920 976 1000 1043 1129 1141 1195 1319 1359 1391 1513 1680 1711 1736
1443 1572 1693 1754
82 470 732 738
1056 1079 1287 1656
85 798 951 1240
795 1208 1481 1703
638 660 935 1069
40 398 538 991
401 773 1187 1752
227 560 690 1741
378 675 881 1511
207 257 636 889
366 654 1041 1279
1079 1121 1434 1515
80 267 564 996
505 948 1271 1545
794 824 1226 1466
822 1021 1032 1474
304 771 1690 1740
69 932 974 1722
575 682 906 1377
418 1134 1633 1674
93 213 613 792
613 749 1264 1368
95 624 646 1107
1561 1592 1736 1774
322 603 1504 1683
52 478 497 1726
307 604 1202 1663
327 607 749 1456
107 510 1624 1708
381 1278 1330 1433
238 637 751 1315
698 1726 1742 1759
319 453 478 1537
642 815 1175 1558
722 939 974 1040
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 2/3 is:
66 80 110 250 268 296 342 502 564 631 845 934 998 1071 1090 1268 1282 1308 1428
3 23 44 212 368 616 681 778 800 844 856 889 949 967 1060 1292 1319 1398 1431
55 144 185 253 266 329 361 424 436 570 699 952 963 1012 1033 1254 1302 1304 1420
28 278 384 598 741 791 809 931 976 1084 1106 1183 1198 1212 1259 1263 1265 1337 1386
7 112 119 147 149 240 268 470 498 534 662 761 813 859 885 1097 1130 1226 1386
120 155 320 345 367 374 395 419 426 535 671 687 793 930 967 1035 1162 1300 1356
622 755 766 950
514 631 757 1073
489 541 614 691
660 786 1162 1216
219 447 635 787
29 572 578 758
170 634 1112 1291
608 892 1320 1345
444 693 1320 1358
358 448 842 1153
695 792 841 894
567 678 777 981
69 341 717 999
405 990 1171 1401
37 130 471 554
850 959 999 1208
464 624 970 1369
757 870 909 1072
45 168 1078 1203
592 735 1344 1401
32 215 445 915
120 1068 1350 1409
701 1062 1205 1319
103 793 1220 1303
579 651 738 757
444 1014 1251 1363
693 947 952 1176
278 499 1261 1325
49 485 1171 1233
238 559 650 947
865 980 1044 1401
50 83 310 500
186 644 1256 1387
340 434 869 1249
644 770 877 1076
299 315 849 1233
299 307 1085 1290
159 324 1091 1313
137 184 863 1404
398 431 478 1069
13 173 993 1133
129 329 730 1143
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 3/4 is:
27 103 130 135 146 249 432 446 501 618 706 795 843 988
80 295 372 403 585 642 719 740 805 904 908 958 999 1033
136 139 230 325 364 385 434 558 605 611 619 771 795 874
143 318 342 347 422 468 489 576 755 767 798 802 952 1014
35 40 187 241 310 458 590 687 698 719 739 765 786 1059
196 457 499 676 729 752 809 818 857 880 917 987 1050 1071
23 141 190 236 381 477 523 594 789 799 919 995 1012 1079
586 636 703 970
205 353 534 940
276 440 495 852
100 138 211 932
114 589 855 946
686 715 844 952
58 239 248 460
351 438 517 1049
245 467 847 867
54 629 698 743
79 490 628 714
138 586 778 861
42 410 485 921
61 882 884 1028
422 444 695 1032
333 385 506 698
83 137 397 534
37 387 489 1073
728 804 836 878
203 374 874 876
373 516 738 766
322 405 477 898
58 451 540 784
311 440 696 900
141 327 818 828
94 205 887 975
437 829 904 1066
3 152 712 889
452 504 689 975
450 651 808 820
425 681 721 845
77 319 330 901
553 769 865 870
168 825 831 938
43 183 771 782
41 325 491 1074
296 452 913 1075
416 728 964 1044
267 477 894 920
193 484 756 986
348 839 861 938
35 233 577 852
355 386 573 721
146 545 644 934
623 779 803 898
560 590 803 1073
219 428 713 1060
A data processing method. LDPC (Low Density Parity Check) code bits are written in the column direction of the storage means for storing in the row direction and the column direction, and the code bits of the LDPC code read in the row direction are used as symbols,
When m bit code bits of 2 bits or more of the LDPC code are transmitted as one symbol,
Column twist interleaving for changing the write start position when the code bits of the LDPC code are written in the column direction of the storage means for each column of the storage means, and rearranging the code bits of the LDPC code A rearrangement step is performed as a replacement process.
When the code length of the LDPC code is represented by N bits and the predetermined positive integer is represented by b,
The storage means stores mb bits in the row direction and stores N / (mb) bits in the column direction;
When the sign bit of the mb bits read in the row direction of the storage means is b symbols,
The LDPC code has an encoding rate of 1/4, 1/3, 5/12, 1/2, 7/12, 2/3, or 3/4, and a code length N of 4320 bits. And
The m bits are 6 bits, and the integer b is 1.
The 6-bit code bit of the LDPC code is mapped to any one of ²⁶ signal points determined by a predetermined modulation method,
The storage means has six columns for storing 6 × 1 bits in the row direction,
In the sorting step,
When the address of the head position in the column direction of the storage means is 0, and the address of each position in the column direction of the storage means is represented by an integer in ascending order,
Of the six columns of the storage means, the first column writing start position is the position where the address is 0,
Of the six columns of the storage means, the writing start position of the second column is the position where the address is 3,
The write start position of the third column of the six columns of the storage means is the position where the address is 68,
The write start position of the fourth column of the six columns of the storage means is the position where the address is 24,
The write start position of the fifth column of the six columns of the storage means is the position where the address is 47,
Of the six columns of the storage means, the writing start position of the sixth column is the position where the address is 4,
The parity check matrix of the LDPC code is based on the parity check matrix initial value table that represents the position of one element of the information matrix corresponding to the information length corresponding to the code length and the coding rate of the parity check matrix every 60 columns. 1 element of the information matrix to be determined is arranged in a column direction with a period of every 60 columns,
The parity check matrix initial value table of an LDPC code with a coding rate of 1/4 is
111 115 245 809 815 864 1015 1050 2008 2077 2090 2277 2357 2382 2413 2455 2546 2598 2608 2664 2805 2981 3089
35 180 216 251 257 266 297 427 571 596 963 1252 1449 1588 1938 2069 2202 2404 2587 2652 2787 2855 3109
36 74 98 169 177 223 381 677 684 748 874 1308 1349 1436 1480 1786 2077 2551 2620 2905 3058 3194 3226
52 361 441 459 672 779 916 942 1189 1335 1725 1829 1932 1957 2055 2111 2378 2451 2572 2800 2847 2894 2934
146 344 392 427 639 853 1022 1070 1466 1488 1511 1564 1632 1730 1754 1921 1963 2122 2442 2634 2955 3092 3162
135 886 2142 2647
719 868 1316 1600
1067 1606 2385 2823
287 911 1506 2242
337 1192 2075 2268
163 1778 2314 2738
192 1401 1589 2046
648 1664 3039 3169
173 1160 1894 2000
73 770 1420 2687
1271 1706 2325 2917
73 1869 2883 3137
249 1012 1160 2721
Consists of
The parity check matrix initial value table of an LDPC code having a coding rate of 1/3 is:
91 115 152 392 509 892 985 1337 1542 1672 1820 2158 2330 2432 2660 2667 2831
364 524 557 1022 1201 1252 1300 1311 1357 1959 2114 2122 2130 2198 2311 2427 2539
245 458 664 869 1063 1164 1236 1398 1497 1669 1874 1955 1981 1989 2125 2349 2874
134 210 315 798 833 1232 1491 1841 1877 1957 1980 2057 2140 2275 2335 2436 2563
66 223 826 1044 1137 1253 1290 1570 1827 1847 1983 2429 2449 2455 2463 2722 2753
159 379 635 744 882 912 934 1086 1174 1545 1585 2225 2356 2747 2765 2807 2848
412 646 1187 2606
361 2212 2349 2505
1317 1442 2076 2611
1312 1940 2211 2295
1200 1581 2063 2410
8 951 1094 2384
102 362 802 2110
175 493 1344 2588
549 1113 1582 2311
1038 1830 2018 2507
880 1177 2078 2241
116 1174 2197 2282
152 1210 1464 2784
936 1185 1740 2087
590 1139 2280 2372
431 839 2281 2363
99 905 1633 2512
213 1050 1288 1707
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 5/12 is:
168 346 446 527 585 747 1129 1159 1276 1283 1361 1512 1527 1532 1537 1782 1794 1956 2133 2369
111 196 301 319 342 354 475 507 712 1026 1444 1454 1459 1553 1813 2024 2053 2162 2245 2479
69 286 372 399 741 759 1224 1515 1682 1685 1781 1843 1870 1984 2015 2045 2232 2236 2285 2411
92 518 550 565 631 643 825 834 987 1072 1108 1136 1227 1255 1341 1418 1430 1836 1880 2020
28 102 149 160 219 287 313 666 671 928 952 1438 1510 2055 2081 2119 2296 2342 2358 2445
147 194 351 460 509 641 748 755 970 1160 1337 1360 1410 1559 1650 1924 2072 2177 2266 2468
47 292 375 1912
957 1430 1717 2072
458 1607 1761 2489
290 805 1122 1189
324 1122 1293 2447
668 1317 2018 2437
507 803 819 1362
471 1952 2027 2359
88 1233 1543 1650
146 314 890 2419
410 1207 1638 2376
80 1302 1442 2166
1064 1263 1531 1696
180 535 1979 2017
910 924 1373 1693
91 1293 1647 1816
1121 1146 1264 2070
321 885 1630 1926
703 821 1155 1163
715 1198 1436 1576
393 758 950 2377
1337 1639 1674 2024
714 1088 1525 1547
1056 1410 1667 1973
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 1/2 is
135 300 342 383 482 543 641 662 798 1058 1125 1187 1398 1472 1582 1651 1716 1796 1799 1836
48 191 227 264 571 613 623 661 664 748 827 1052 1270 1366 1376 1494 1698 1718 1781 1886
75 233 317 382 605 623 656 768 846 1090 1161 1189 1245 1275 1347 1446 1616 1701 1735 1838
236 325 530 552 589 620 637 658 793 800 807 960 1049 1481 1554 1740 1841 1989 1991 2156
79 88 268 541 645 691 773 932 1077 1162 1516 1522 1540 1741 1781 1834 1862 1977 2020 2032
135 235 379 683 724 841 871 963 1014 1020 1241 1353 1533 1624 1643 1700 1957 2073 2107 2113
106 1706 2037 2074
2 131 448 553
138 1198 1690 1911
326 994 1213 1902
207 951 1491 1710
288 676 952 1561
310 579 792 1064
75 150 277 1104
280 971 1515 2015
1714 1876 2107 2126
198 394 551 2145
51 1145 1613 1766
793 1034 1082 1603
390 1423 1486 2010
676 850 1424 1676
706 767 888 1364
499 779 843 2108
317 1045 1497 1507
224 458 609 1933
219 400 689 1591
164 808 895 1902
629 1431 1552 1892
151 338 600 2097
189 1103 1392 1626
33 365 835 1215
573 1022 1576 1877
239 1169 1766 2061
607 846 990 2093
396 612 1427 1999
180 252 566 817
Consists of
The parity check matrix initial value table of an LDPC code having a coding rate of 7/12 is as follows:
182 275 329 391 518 548 588 595 669 672 787 820 967 1016 1023 1056 1088 1108 1170 1573 1639 1784
112 156 251 316 359 451 457 590 635 867 924 970 982 985 1028 1371 1439 1485 1571 1766 1784 1790
0 47 77 143 200 289 425 454 482 531 721 750 763 859 982 1037 1044 1068 1208 1517 1664 1772
28 116 127 142 184 255 279 395 413 453 570 629 676 717 750 842 1371 1599 1606 1653 1675 1764
81 129 142 267 285 471 498 632 680 893 945 994 1059 1105 1316 1326 1364 1616 1635 1715 1720 1747
25 53 69 263 520 553 556 573 920 976 1000 1043 1129 1141 1195 1319 1359 1391 1513 1680 1711 1736
1443 1572 1693 1754
82 470 732 738
1056 1079 1287 1656
85 798 951 1240
795 1208 1481 1703
638 660 935 1069
40 398 538 991
401 773 1187 1752
227 560 690 1741
378 675 881 1511
207 257 636 889
366 654 1041 1279
1079 1121 1434 1515
80 267 564 996
505 948 1271 1545
794 824 1226 1466
822 1021 1032 1474
304 771 1690 1740
69 932 974 1722
575 682 906 1377
418 1134 1633 1674
93 213 613 792
613 749 1264 1368
95 624 646 1107
1561 1592 1736 1774
322 603 1504 1683
52 478 497 1726
307 604 1202 1663
327 607 749 1456
107 510 1624 1708
381 1278 1330 1433
238 637 751 1315
698 1726 1742 1759
319 453 478 1537
642 815 1175 1558
722 939 974 1040
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 2/3 is:
66 80 110 250 268 296 342 502 564 631 845 934 998 1071 1090 1268 1282 1308 1428
3 23 44 212 368 616 681 778 800 844 856 889 949 967 1060 1292 1319 1398 1431
55 144 185 253 266 329 361 424 436 570 699 952 963 1012 1033 1254 1302 1304 1420
28 278 384 598 741 791 809 931 976 1084 1106 1183 1198 1212 1259 1263 1265 1337 1386
7 112 119 147 149 240 268 470 498 534 662 761 813 859 885 1097 1130 1226 1386
120 155 320 345 367 374 395 419 426 535 671 687 793 930 967 1035 1162 1300 1356
622 755 766 950
514 631 757 1073
489 541 614 691
660 786 1162 1216
219 447 635 787
29 572 578 758
170 634 1112 1291
608 892 1320 1345
444 693 1320 1358
358 448 842 1153
695 792 841 894
567 678 777 981
69 341 717 999
405 990 1171 1401
37 130 471 554
850 959 999 1208
464 624 970 1369
757 870 909 1072
45 168 1078 1203
592 735 1344 1401
32 215 445 915
120 1068 1350 1409
701 1062 1205 1319
103 793 1220 1303
579 651 738 757
444 1014 1251 1363
693 947 952 1176
278 499 1261 1325
49 485 1171 1233
238 559 650 947
865 980 1044 1401
50 83 310 500
186 644 1256 1387
340 434 869 1249
644 770 877 1076
299 315 849 1233
299 307 1085 1290
159 324 1091 1313
137 184 863 1404
398 431 478 1069
13 173 993 1133
129 329 730 1143
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 3/4 is:
27 103 130 135 146 249 432 446 501 618 706 795 843 988
80 295 372 403 585 642 719 740 805 904 908 958 999 1033
136 139 230 325 364 385 434 558 605 611 619 771 795 874
143 318 342 347 422 468 489 576 755 767 798 802 952 1014
35 40 187 241 310 458 590 687 698 719 739 765 786 1059
196 457 499 676 729 752 809 818 857 880 917 987 1050 1071
23 141 190 236 381 477 523 594 789 799 919 995 1012 1079
586 636 703 970
205 353 534 940
276 440 495 852
100 138 211 932
114 589 855 946
686 715 844 952
58 239 248 460
351 438 517 1049
245 467 847 867
54 629 698 743
79 490 628 714
138 586 778 861
42 410 485 921
61 882 884 1028
422 444 695 1032
333 385 506 698
83 137 397 534
37 387 489 1073
728 804 836 878
203 374 874 876
373 516 738 766
322 405 477 898
58 451 540 784
311 440 696 900
141 327 818 828
94 205 887 975
437 829 904 1066
3 152 712 889
452 504 689 975
450 651 808 820
425 681 721 845
77 319 330 901
553 769 865 870
168 825 831 938
43 183 771 782
41 325 491 1074
296 452 913 1075
416 728 964 1044
267 477 894 920
193 484 756 986
348 839 861 938
35 233 577 852
355 386 573 721
146 545 644 934
623 779 803 898
560 590 803 1073
219 428 713 1060
A data processing method. LDPC (Low Density Parity Check) code bits are written in the column direction of the storage means for storing in the row direction and the column direction, and the code bits of the LDPC code read in the row direction are used as symbols,
When m bit code bits of 2 bits or more of the LDPC code are transmitted as one symbol,
Column twist interleaving for changing the write start position when the code bits of the LDPC code are written in the column direction of the storage means for each column of the storage means, and rearranging the code bits of the LDPC code A rearrangement step is performed as a replacement process.
When the code length of the LDPC code is represented by N bits and the predetermined positive integer is represented by b,
The storage means stores mb bits in the row direction and stores N / (mb) bits in the column direction;
When the sign bit of the mb bits read in the row direction of the storage means is b symbols,
The LDPC code has an encoding rate of 1/4, 1/3, 5/12, 1/2, 7/12, 2/3, or 3/4, and a code length N of 4320 bits. And
The m bits are 4 bits, and the integer b is 2.
The sign bit of the 4 bits of the LDPC code are mapped to one of 2 ⁴ signal points prescribed in a predetermined modulation scheme,
The storage means has 8 columns for storing 4 × 2 bits in the row direction,
In the sorting step,
When the address of the head position in the column direction of the storage means is 0, and the address of each position in the column direction of the storage means is represented by an integer in ascending order,
The write start position of the first column of the eight columns of the storage means is the position where the address is 0,
The write start position of the second column of the eight columns of the storage means is the position where the address is 2,
The write start position of the third column of the eight columns of the storage means is the position where the address is 46,
The write start position of the fourth column of the eight columns of the storage means is the position where the address is 79,
The write start position of the fifth column of the eight columns of the storage means is the position where the address is 291;
The writing start position of the sixth column of the eight columns of the storage means is the position where the address is 146,
The write start position of the seventh column of the eight columns of the storage means is the position where the address is 3,
The write start position of the eighth column of the eight columns of the storage means is the position where the address is 13,
The parity check matrix of the LDPC code is based on the parity check matrix initial value table that represents the position of one element of the information matrix corresponding to the information length corresponding to the code length and the coding rate of the parity check matrix every 60 columns. 1 element of the information matrix to be determined is arranged in a column direction with a period of every 60 columns,
The parity check matrix initial value table of an LDPC code with a coding rate of 1/4 is
111 115 245 809 815 864 1015 1050 2008 2077 2090 2277 2357 2382 2413 2455 2546 2598 2608 2664 2805 2981 3089
35 180 216 251 257 266 297 427 571 596 963 1252 1449 1588 1938 2069 2202 2404 2587 2652 2787 2855 3109
36 74 98 169 177 223 381 677 684 748 874 1308 1349 1436 1480 1786 2077 2551 2620 2905 3058 3194 3226
52 361 441 459 672 779 916 942 1189 1335 1725 1829 1932 1957 2055 2111 2378 2451 2572 2800 2847 2894 2934
146 344 392 427 639 853 1022 1070 1466 1488 1511 1564 1632 1730 1754 1921 1963 2122 2442 2634 2955 3092 3162
135 886 2142 2647
719 868 1316 1600
1067 1606 2385 2823
287 911 1506 2242
337 1192 2075 2268
163 1778 2314 2738
192 1401 1589 2046
648 1664 3039 3169
173 1160 1894 2000
73 770 1420 2687
1271 1706 2325 2917
73 1869 2883 3137
249 1012 1160 2721
Consists of
The parity check matrix initial value table of an LDPC code having a coding rate of 1/3 is:
91 115 152 392 509 892 985 1337 1542 1672 1820 2158 2330 2432 2660 2667 2831
364 524 557 1022 1201 1252 1300 1311 1357 1959 2114 2122 2130 2198 2311 2427 2539
245 458 664 869 1063 1164 1236 1398 1497 1669 1874 1955 1981 1989 2125 2349 2874
134 210 315 798 833 1232 1491 1841 1877 1957 1980 2057 2140 2275 2335 2436 2563
66 223 826 1044 1137 1253 1290 1570 1827 1847 1983 2429 2449 2455 2463 2722 2753
159 379 635 744 882 912 934 1086 1174 1545 1585 2225 2356 2747 2765 2807 2848
412 646 1187 2606
361 2212 2349 2505
1317 1442 2076 2611
1312 1940 2211 2295
1200 1581 2063 2410
8 951 1094 2384
102 362 802 2110
175 493 1344 2588
549 1113 1582 2311
1038 1830 2018 2507
880 1177 2078 2241
116 1174 2197 2282
152 1210 1464 2784
936 1185 1740 2087
590 1139 2280 2372
431 839 2281 2363
99 905 1633 2512
213 1050 1288 1707
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 5/12 is:
168 346 446 527 585 747 1129 1159 1276 1283 1361 1512 1527 1532 1537 1782 1794 1956 2133 2369
111 196 301 319 342 354 475 507 712 1026 1444 1454 1459 1553 1813 2024 2053 2162 2245 2479
69 286 372 399 741 759 1224 1515 1682 1685 1781 1843 1870 1984 2015 2045 2232 2236 2285 2411
92 518 550 565 631 643 825 834 987 1072 1108 1136 1227 1255 1341 1418 1430 1836 1880 2020
28 102 149 160 219 287 313 666 671 928 952 1438 1510 2055 2081 2119 2296 2342 2358 2445
147 194 351 460 509 641 748 755 970 1160 1337 1360 1410 1559 1650 1924 2072 2177 2266 2468
47 292 375 1912
957 1430 1717 2072
458 1607 1761 2489
290 805 1122 1189
324 1122 1293 2447
668 1317 2018 2437
507 803 819 1362
471 1952 2027 2359
88 1233 1543 1650
146 314 890 2419
410 1207 1638 2376
80 1302 1442 2166
1064 1263 1531 1696
180 535 1979 2017
910 924 1373 1693
91 1293 1647 1816
1121 1146 1264 2070
321 885 1630 1926
703 821 1155 1163
715 1198 1436 1576
393 758 950 2377
1337 1639 1674 2024
714 1088 1525 1547
1056 1410 1667 1973
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 1/2 is
135 300 342 383 482 543 641 662 798 1058 1125 1187 1398 1472 1582 1651 1716 1796 1799 1836
48 191 227 264 571 613 623 661 664 748 827 1052 1270 1366 1376 1494 1698 1718 1781 1886
75 233 317 382 605 623 656 768 846 1090 1161 1189 1245 1275 1347 1446 1616 1701 1735 1838
236 325 530 552 589 620 637 658 793 800 807 960 1049 1481 1554 1740 1841 1989 1991 2156
79 88 268 541 645 691 773 932 1077 1162 1516 1522 1540 1741 1781 1834 1862 1977 2020 2032
135 235 379 683 724 841 871 963 1014 1020 1241 1353 1533 1624 1643 1700 1957 2073 2107 2113
106 1706 2037 2074
2 131 448 553
138 1198 1690 1911
326 994 1213 1902
207 951 1491 1710
288 676 952 1561
310 579 792 1064
75 150 277 1104
280 971 1515 2015
1714 1876 2107 2126
198 394 551 2145
51 1145 1613 1766
793 1034 1082 1603
390 1423 1486 2010
676 850 1424 1676
706 767 888 1364
499 779 843 2108
317 1045 1497 1507
224 458 609 1933
219 400 689 1591
164 808 895 1902
629 1431 1552 1892
151 338 600 2097
189 1103 1392 1626
33 365 835 1215
573 1022 1576 1877
239 1169 1766 2061
607 846 990 2093
396 612 1427 1999
180 252 566 817
Consists of
The parity check matrix initial value table of an LDPC code having a coding rate of 7/12 is as follows:
182 275 329 391 518 548 588 595 669 672 787 820 967 1016 1023 1056 1088 1108 1170 1573 1639 1784
112 156 251 316 359 451 457 590 635 867 924 970 982 985 1028 1371 1439 1485 1571 1766 1784 1790
0 47 77 143 200 289 425 454 482 531 721 750 763 859 982 1037 1044 1068 1208 1517 1664 1772
28 116 127 142 184 255 279 395 413 453 570 629 676 717 750 842 1371 1599 1606 1653 1675 1764
81 129 142 267 285 471 498 632 680 893 945 994 1059 1105 1316 1326 1364 1616 1635 1715 1720 1747
25 53 69 263 520 553 556 573 920 976 1000 1043 1129 1141 1195 1319 1359 1391 1513 1680 1711 1736
1443 1572 1693 1754
82 470 732 738
1056 1079 1287 1656
85 798 951 1240
795 1208 1481 1703
638 660 935 1069
40 398 538 991
401 773 1187 1752
227 560 690 1741
378 675 881 1511
207 257 636 889
366 654 1041 1279
1079 1121 1434 1515
80 267 564 996
505 948 1271 1545
794 824 1226 1466
822 1021 1032 1474
304 771 1690 1740
69 932 974 1722
575 682 906 1377
418 1134 1633 1674
93 213 613 792
613 749 1264 1368
95 624 646 1107
1561 1592 1736 1774
322 603 1504 1683
52 478 497 1726
307 604 1202 1663
327 607 749 1456
107 510 1624 1708
381 1278 1330 1433
238 637 751 1315
698 1726 1742 1759
319 453 478 1537
642 815 1175 1558
722 939 974 1040
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 2/3 is:
66 80 110 250 268 296 342 502 564 631 845 934 998 1071 1090 1268 1282 1308 1428
3 23 44 212 368 616 681 778 800 844 856 889 949 967 1060 1292 1319 1398 1431
55 144 185 253 266 329 361 424 436 570 699 952 963 1012 1033 1254 1302 1304 1420
28 278 384 598 741 791 809 931 976 1084 1106 1183 1198 1212 1259 1263 1265 1337 1386
7 112 119 147 149 240 268 470 498 534 662 761 813 859 885 1097 1130 1226 1386
120 155 320 345 367 374 395 419 426 535 671 687 793 930 967 1035 1162 1300 1356
622 755 766 950
514 631 757 1073
489 541 614 691
660 786 1162 1216
219 447 635 787
29 572 578 758
170 634 1112 1291
608 892 1320 1345
444 693 1320 1358
358 448 842 1153
695 792 841 894
567 678 777 981
69 341 717 999
405 990 1171 1401
37 130 471 554
850 959 999 1208
464 624 970 1369
757 870 909 1072
45 168 1078 1203
592 735 1344 1401
32 215 445 915
120 1068 1350 1409
701 1062 1205 1319
103 793 1220 1303
579 651 738 757
444 1014 1251 1363
693 947 952 1176
278 499 1261 1325
49 485 1171 1233
238 559 650 947
865 980 1044 1401
50 83 310 500
186 644 1256 1387
340 434 869 1249
644 770 877 1076
299 315 849 1233
299 307 1085 1290
159 324 1091 1313
137 184 863 1404
398 431 478 1069
13 173 993 1133
129 329 730 1143
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 3/4 is:
27 103 130 135 146 249 432 446 501 618 706 795 843 988
80 295 372 403 585 642 719 740 805 904 908 958 999 1033
136 139 230 325 364 385 434 558 605 611 619 771 795 874
143 318 342 347 422 468 489 576 755 767 798 802 952 1014
35 40 187 241 310 458 590 687 698 719 739 765 786 1059
196 457 499 676 729 752 809 818 857 880 917 987 1050 1071
23 141 190 236 381 477 523 594 789 799 919 995 1012 1079
586 636 703 970
205 353 534 940
276 440 495 852
100 138 211 932
114 589 855 946
686 715 844 952
58 239 248 460
351 438 517 1049
245 467 847 867
54 629 698 743
79 490 628 714
138 586 778 861
42 410 485 921
61 882 884 1028
422 444 695 1032
333 385 506 698
83 137 397 534
37 387 489 1073
728 804 836 878
203 374 874 876
373 516 738 766
322 405 477 898
58 451 540 784
311 440 696 900
141 327 818 828
94 205 887 975
437 829 904 1066
3 152 712 889
452 504 689 975
450 651 808 820
425 681 721 845
77 319 330 901
553 769 865 870
168 825 831 938
43 183 771 782
41 325 491 1074
296 452 913 1075
416 728 964 1044
267 477 894 920
193 484 756 986
348 839 861 938
35 233 577 852
355 386 573 721
146 545 644 934
623 779 803 898
560 590 803 1073
219 428 713 1060
A data processing method. LDPC (Low Density Parity Check) code bits are written in the column direction of the storage means for storing in the row direction and the column direction, and the code bits of the LDPC code read in the row direction are used as symbols,
When m bit code bits of 2 bits or more of the LDPC code are transmitted as one symbol,
Column twist interleaving for changing the write start position when the code bits of the LDPC code are written in the column direction of the storage means for each column of the storage means, and rearranging the code bits of the LDPC code A rearrangement step is performed as a replacement process.
When the code length of the LDPC code is represented by N bits and the predetermined positive integer is represented by b,
The storage means stores mb bits in the row direction and stores N / (mb) bits in the column direction;
When the sign bit of the mb bits read in the row direction of the storage means is b symbols,
The LDPC code has an encoding rate of 1/4, 1/3, 5/12, 1/2, 7/12, 2/3, or 3/4, and a code length N of 4320 bits. And
The m bits are 6 bits, and the integer b is 2.
The 6-bit code bit of the LDPC code is mapped to any one of ²⁶ signal points determined by a predetermined modulation method,
The storage means has 12 columns storing 6 × 2 bits in the row direction,
In the sorting step,
When the address of the head position in the column direction of the storage means is 0, and the address of each position in the column direction of the storage means is represented by an integer in ascending order,
The write start position of the first column of the 12 columns of the storage means is the position where the address is 0,
Of the 12 columns of the storage means, the writing start position of the second column is the position where the address is 0,
Of the 12 columns of the storage means, the write start position of the third column is the position where the address is 3,
Of the 12 columns of the storage means, the write start position of the fourth column is the position where the address is 15,
The write start position of the fifth column of the 12 columns of the storage means is the position where the address is 119,
Of the 12 columns of the storage means, the writing start position of the sixth column is the position where the address is 32,
The write start position of the seventh column of the 12 columns of the storage means is the position where the address is 24,
The write start position of the eighth column of the 12 columns of the storage means, the address is the position of 169,
Of the 12 columns of the storage means, the write start position of the ninth column is the position where the address is 84,
Of the 12 columns of the storage means, the write start position of the 10th column is the position where the address is 3,
Of the 12 columns of the storage means, the write start position of the 11th column is the position where the address is 12,
Of the 12 columns of the storage means, the writing start position of the twelfth column is the position where the address is 3,
The parity check matrix of the LDPC code is based on the parity check matrix initial value table that represents the position of one element of the information matrix corresponding to the information length corresponding to the code length and the coding rate of the parity check matrix every 60 columns. 1 element of the information matrix to be determined is arranged in a column direction with a period of every 60 columns,
The parity check matrix initial value table of an LDPC code with a coding rate of 1/4 is
111 115 245 809 815 864 1015 1050 2008 2077 2090 2277 2357 2382 2413 2455 2546 2598 2608 2664 2805 2981 3089
35 180 216 251 257 266 297 427 571 596 963 1252 1449 1588 1938 2069 2202 2404 2587 2652 2787 2855 3109
36 74 98 169 177 223 381 677 684 748 874 1308 1349 1436 1480 1786 2077 2551 2620 2905 3058 3194 3226
52 361 441 459 672 779 916 942 1189 1335 1725 1829 1932 1957 2055 2111 2378 2451 2572 2800 2847 2894 2934
146 344 392 427 639 853 1022 1070 1466 1488 1511 1564 1632 1730 1754 1921 1963 2122 2442 2634 2955 3092 3162
135 886 2142 2647
719 868 1316 1600
1067 1606 2385 2823
287 911 1506 2242
337 1192 2075 2268
163 1778 2314 2738
192 1401 1589 2046
648 1664 3039 3169
173 1160 1894 2000
73 770 1420 2687
1271 1706 2325 2917
73 1869 2883 3137
249 1012 1160 2721
Consists of
The parity check matrix initial value table of an LDPC code having a coding rate of 1/3 is:
91 115 152 392 509 892 985 1337 1542 1672 1820 2158 2330 2432 2660 2667 2831
364 524 557 1022 1201 1252 1300 1311 1357 1959 2114 2122 2130 2198 2311 2427 2539
245 458 664 869 1063 1164 1236 1398 1497 1669 1874 1955 1981 1989 2125 2349 2874
134 210 315 798 833 1232 1491 1841 1877 1957 1980 2057 2140 2275 2335 2436 2563
66 223 826 1044 1137 1253 1290 1570 1827 1847 1983 2429 2449 2455 2463 2722 2753
159 379 635 744 882 912 934 1086 1174 1545 1585 2225 2356 2747 2765 2807 2848
412 646 1187 2606
361 2212 2349 2505
1317 1442 2076 2611
1312 1940 2211 2295
1200 1581 2063 2410
8 951 1094 2384
102 362 802 2110
175 493 1344 2588
549 1113 1582 2311
1038 1830 2018 2507
880 1177 2078 2241
116 1174 2197 2282
152 1210 1464 2784
936 1185 1740 2087
590 1139 2280 2372
431 839 2281 2363
99 905 1633 2512
213 1050 1288 1707
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 5/12 is:
168 346 446 527 585 747 1129 1159 1276 1283 1361 1512 1527 1532 1537 1782 1794 1956 2133 2369
111 196 301 319 342 354 475 507 712 1026 1444 1454 1459 1553 1813 2024 2053 2162 2245 2479
69 286 372 399 741 759 1224 1515 1682 1685 1781 1843 1870 1984 2015 2045 2232 2236 2285 2411
92 518 550 565 631 643 825 834 987 1072 1108 1136 1227 1255 1341 1418 1430 1836 1880 2020
28 102 149 160 219 287 313 666 671 928 952 1438 1510 2055 2081 2119 2296 2342 2358 2445
147 194 351 460 509 641 748 755 970 1160 1337 1360 1410 1559 1650 1924 2072 2177 2266 2468
47 292 375 1912
957 1430 1717 2072
458 1607 1761 2489
290 805 1122 1189
324 1122 1293 2447
668 1317 2018 2437
507 803 819 1362
471 1952 2027 2359
88 1233 1543 1650
146 314 890 2419
410 1207 1638 2376
80 1302 1442 2166
1064 1263 1531 1696
180 535 1979 2017
910 924 1373 1693
91 1293 1647 1816
1121 1146 1264 2070
321 885 1630 1926
703 821 1155 1163
715 1198 1436 1576
393 758 950 2377
1337 1639 1674 2024
714 1088 1525 1547
1056 1410 1667 1973
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 1/2 is
135 300 342 383 482 543 641 662 798 1058 1125 1187 1398 1472 1582 1651 1716 1796 1799 1836
48 191 227 264 571 613 623 661 664 748 827 1052 1270 1366 1376 1494 1698 1718 1781 1886
75 233 317 382 605 623 656 768 846 1090 1161 1189 1245 1275 1347 1446 1616 1701 1735 1838
236 325 530 552 589 620 637 658 793 800 807 960 1049 1481 1554 1740 1841 1989 1991 2156
79 88 268 541 645 691 773 932 1077 1162 1516 1522 1540 1741 1781 1834 1862 1977 2020 2032
135 235 379 683 724 841 871 963 1014 1020 1241 1353 1533 1624 1643 1700 1957 2073 2107 2113
106 1706 2037 2074
2 131 448 553
138 1198 1690 1911
326 994 1213 1902
207 951 1491 1710
288 676 952 1561
310 579 792 1064
75 150 277 1104
280 971 1515 2015
1714 1876 2107 2126
198 394 551 2145
51 1145 1613 1766
793 1034 1082 1603
390 1423 1486 2010
676 850 1424 1676
706 767 888 1364
499 779 843 2108
317 1045 1497 1507
224 458 609 1933
219 400 689 1591
164 808 895 1902
629 1431 1552 1892
151 338 600 2097
189 1103 1392 1626
33 365 835 1215
573 1022 1576 1877
239 1169 1766 2061
607 846 990 2093
396 612 1427 1999
180 252 566 817
Consists of
The parity check matrix initial value table of an LDPC code having a coding rate of 7/12 is as follows:
182 275 329 391 518 548 588 595 669 672 787 820 967 1016 1023 1056 1088 1108 1170 1573 1639 1784
112 156 251 316 359 451 457 590 635 867 924 970 982 985 1028 1371 1439 1485 1571 1766 1784 1790
0 47 77 143 200 289 425 454 482 531 721 750 763 859 982 1037 1044 1068 1208 1517 1664 1772
28 116 127 142 184 255 279 395 413 453 570 629 676 717 750 842 1371 1599 1606 1653 1675 1764
81 129 142 267 285 471 498 632 680 893 945 994 1059 1105 1316 1326 1364 1616 1635 1715 1720 1747
25 53 69 263 520 553 556 573 920 976 1000 1043 1129 1141 1195 1319 1359 1391 1513 1680 1711 1736
1443 1572 1693 1754
82 470 732 738
1056 1079 1287 1656
85 798 951 1240
795 1208 1481 1703
638 660 935 1069
40 398 538 991
401 773 1187 1752
227 560 690 1741
378 675 881 1511
207 257 636 889
366 654 1041 1279
1079 1121 1434 1515
80 267 564 996
505 948 1271 1545
794 824 1226 1466
822 1021 1032 1474
304 771 1690 1740
69 932 974 1722
575 682 906 1377
418 1134 1633 1674
93 213 613 792
613 749 1264 1368
95 624 646 1107
1561 1592 1736 1774
322 603 1504 1683
52 478 497 1726
307 604 1202 1663
327 607 749 1456
107 510 1624 1708
381 1278 1330 1433
238 637 751 1315
698 1726 1742 1759
319 453 478 1537
642 815 1175 1558
722 939 974 1040
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 2/3 is:
66 80 110 250 268 296 342 502 564 631 845 934 998 1071 1090 1268 1282 1308 1428
3 23 44 212 368 616 681 778 800 844 856 889 949 967 1060 1292 1319 1398 1431
55 144 185 253 266 329 361 424 436 570 699 952 963 1012 1033 1254 1302 1304 1420
28 278 384 598 741 791 809 931 976 1084 1106 1183 1198 1212 1259 1263 1265 1337 1386
7 112 119 147 149 240 268 470 498 534 662 761 813 859 885 1097 1130 1226 1386
120 155 320 345 367 374 395 419 426 535 671 687 793 930 967 1035 1162 1300 1356
622 755 766 950
514 631 757 1073
489 541 614 691
660 786 1162 1216
219 447 635 787
29 572 578 758
170 634 1112 1291
608 892 1320 1345
444 693 1320 1358
358 448 842 1153
695 792 841 894
567 678 777 981
69 341 717 999
405 990 1171 1401
37 130 471 554
850 959 999 1208
464 624 970 1369
757 870 909 1072
45 168 1078 1203
592 735 1344 1401
32 215 445 915
120 1068 1350 1409
701 1062 1205 1319
103 793 1220 1303
579 651 738 757
444 1014 1251 1363
693 947 952 1176
278 499 1261 1325
49 485 1171 1233
238 559 650 947
865 980 1044 1401
50 83 310 500
186 644 1256 1387
340 434 869 1249
644 770 877 1076
299 315 849 1233
299 307 1085 1290
159 324 1091 1313
137 184 863 1404
398 431 478 1069
13 173 993 1133
129 329 730 1143
Consists of
The parity check matrix initial value table of an LDPC code with a coding rate of 3/4 is:
27 103 130 135 146 249 432 446 501 618 706 795 843 988
80 295 372 403 585 642 719 740 805 904 908 958 999 1033
136 139 230 325 364 385 434 558 605 611 619 771 795 874
143 318 342 347 422 468 489 576 755 767 798 802 952 1014
35 40 187 241 310 458 590 687 698 719 739 765 786 1059
196 457 499 676 729 752 809 818 857 880 917 987 1050 1071
23 141 190 236 381 477 523 594 789 799 919 995 1012 1079
586 636 703 970
205 353 534 940
276 440 495 852
100 138 211 932
114 589 855 946
686 715 844 952
58 239 248 460
351 438 517 1049
245 467 847 867
54 629 698 743
79 490 628 714
138 586 778 861
42 410 485 921
61 882 884 1028
422 444 695 1032
333 385 506 698
83 137 397 534
37 387 489 1073
728 804 836 878
203 374 874 876
373 516 738 766
322 405 477 898
58 451 540 784
311 440 696 900
141 327 818 828
94 205 887 975
437 829 904 1066
3 152 712 889
452 504 689 975
450 651 808 820
425 681 721 845
77 319 330 901
553 769 865 870
168 825 831 938
43 183 771 782
41 325 491 1074
296 452 913 1075
416 728 964 1044
267 477 894 920
193 484 756 986
348 839 861 938
35 233 577 852
355 386 573 721
146 545 644 934
623 779 803 898
560 590 803 1073
219 428 713 1060
A data processing method.

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