CA3040604C

CA3040604C - Receiving apparatus using low-density parity check code and bit deinterleaving and receiving method thereof

Info

Publication number: CA3040604C
Application number: CA3040604A
Authority: CA
Inventors: Se-Ho Myung; Hong-Sil Jeong; Kyung-Joong Kim
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2014-02-19
Filing date: 2015-02-23
Publication date: 2021-11-23
Anticipated expiration: 2035-02-23
Also published as: MX366541B; CA3040604A1; KR101800409B1; KR20170129668A; KR20190064556A; KR102245527B1; MX2019008372A; CA2940011A1; KR20150098226A; MX2016010774A; CA3133553A1; KR20190011795A; CN106471782B; KR101944526B1; CA2940011C; KR101986778B1; CN106471782A; CA3133553C

Abstract

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

Description

RECEIVING APPARATUS USING LOW-DENSITY PARITY CHECK CODE AND
BIT DEINTERLEAVING AND RECEIVING METHOD THEREOF
This application is a divisional of Canadian patent application No. 2940011 filed on February 23, 2015.
[Technical Field]
Apparatuses and methods consistent with exemplary embodiments relate to a transmitting apparatus and an interleaving method thereof, and more particularly, to a transmitting apparatus which processes and transmits data, and an interleaving method thereof.
[Background Art]
In the 21st century information-oriented society, broadcasting communication services are moving into the era of digitalization, multi-channel, wideband, and high quality. In particular, as high quality digital televisions, portable multimedia players and portable broadcasting equipment are increasingly used in recent years, there is an increasing demand for methods for supporting various receiving methods of digital broadcasting services.
In order to meet such demand, standard groups are establishing various standards and are providing a variety of services to satisfy users' needs. Therefore, there is a need for a method for providing improved services to users with high decoding and receiving performance.
[Disclosure]
[Technical Problem]
Exemplary embodiments of the inventive concept may overcome the above disadvantages and other disadvantages not described above. However, it is understood that the exemplary embodiment are not required to overcome the disadvantages described above, and may not overcome any of the problems described above.
The exemplary embodiments provide a transmitting apparatus which can map a bit included in a predetermined bit group from among a plurality of bit groups of a low density parity check (LDPC) codeword onto a predetermined bit of a modulation symbol, and transmit the bit, and an interleaving method thereof.
[Technical Solution]
According to an aspect of an exemplary embodiment, there is provided a transmitting apparatus including: an encoder configured to generate an LDPC codeword by LDPC encoding Date Recue/Date Received 2020-11-13

2 based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.
Each of the plurality of bit groups may be formed of M number of bits. M may be a common divisor of Nicipc and Kid and may be determined to satisfy Qtripc4Ntapc-Kkipc)/M. In this case, Qjdpc may be a cyclic shift parameter value regarding columns in a column group of an information word submatrix of the parity check matrix, Nidpc may be a length of the LDPC
codeword, and Kldpc may be a length of information word bits of the LDPC
codeword.
The interleaver may include: a parity interleaver configured to interleave parity bits of the LDPC codeword; a group interleaver configured to divide the parity-interleaved LDPC
codeword by the plurality of bit groups and rearrange an order of the plurality of bit groups in bit group wise; and a block interleaver configured to interleave the plurality of bit groups the order of which is rearranged.
The group interleaver may be configured to rearrange the order of the plurality of bit groups in bit group wise by using the following equation:
Yi = X,(i)(0 j where Xj is a jth bit group before the plurality of bit groups are interleaved, Yi is a j th bit group after the plurality of bit groups are interleaved, Ngroup _s i a total number of the plurality of bit groups, and 7t(j) is a parameter indicating an interleaving order.
Here, 7t(j) may be determined based on at least one of a length of the LDPC
codeword, a modulation method, and a code rate.
When the LDPC codeword has a length of 64800, the modulation method is 16-0AM, and the code rate is 6/15,71(j) may be defined as in table 11.
When the LDPC codeword has a length of 64800, the modulation method is 16-QAM, and the code rate is 10/15, 7t(j) may be defined as in table 14.
When the LDPC codeword has a length of 64800, the modulation method is 16-QAM, and the code rate is 12/15, 7t(j) may be defined as in table 15.
When the LDPC codeword has a length of 64800, the modulation method is 64-QAM, and the code rate is 6/15, 7r(j) may be defined as in table 17.

3 When the LDPC codeword has a length of 64800, the modulation method is 64-QAM, and the code rate is 8/15, n(j) may be defined as in table 18.
When the LDPC codeword has a length of 64800, the modulation method is 64-QAM, and the code rate is 12/15, 7r(j) may be defined as in table 21.
The block interleaver may be configured to interleave by writing the plurality of bit groups in each of a plurality of columns in bit group wise in a column direction, and reading each row of the plurality of columns in which the plurality of bit groups are written in bit group wise in a row direction.
The block interleaver may be configured to serially write, in the plurality of columns, at least some bit groups which are writable in the plurality of columns in bit group wise from among the plurality of bit groups, and then divide and write the other bit groups in an area which remains after the at least some bit groups are written in the plurality of columns in bit group wise.
According to an aspect of another exemplary embodiment, there is provided an interleaving method of a transmitting apparatus, including: generating an LDPC codeword by LDPC
encoding based on a parity check matrix; interleaving the LDPC codeword; and mapping the interleaved LDPC codeword onto a modulation symbol, wherein the mapping comprises mapping a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.
Each of the plurality of bit groups may be formed of M number of bits, and M
may be a common divisor of Niapc and Icipc and may be determined to satisfy Qidpc=(Nidpc-Kidpc)/M. In this case, Qtdpc may be a cyclic shift parameter value regarding columns in a column group of an information word submatrix of the parity check matrix, INTIdpc may be a length of the LDPC
codeword, and Kidp, may be a length of information word bits of the LDPC
codeword.
The interleaving may include: interleaving parity bits of the LDPC codeword;
dividing the parity-interleaved LDPC codeword by the plurality of bit groups and rearranging an order of the plurality of bit groups in bit group wise; and interleaving the plurality of bit groups the order of which is rearranged.
The rearranging in bit group wise may include rearranging the order of the plurality of bit groups in bit group wise by using the following equation:
Yi =XJ)(0 <N80) where N is a jth bit group before the plurality of bit groups are interleaved, Yj is a jth bit group

4 after the plurality of bit groups are interleaved, N gro up isa total number of the plurality of bit groups, and it(j) is a parameter indicating an interleaving order.
Here, 7r(j) may be determined based on at least one of a length of the LDPC
codeword, a modulation method, and a code rate.
When the LDPC codeword has a length of 64800, the modulation method is 16-QAM, and the code rate is 6/15, it(j) may be defined as in table 11.
When the LDPC codeword has a length o164800, the modulation method is 16-QAM, and the code rate is 10/15, it(j) may be defined as in table 14.
When the LDPC codeword has a length of 64800, the modulation method is 16-QAM, and the code rate is 12/15, ir(j) may be defined as in table 15.
When the LDPC codeword has a length of 64800, the modulation method is 64-QAM, and the code rate is 6/15, n(j) may be defined as in table 17.
When the LDPC codeword has a length of 64800, the modulation method is 64-QAM, and the code rate is 8/15, it(j) may be defined as in table 18.
When the LDPC codeword has a length of 64800, the modulation method is 64-QAM, and the code rate is 12/15, 7r(j) may be defined as in table 21.
The interleaving the plurality of bit groups may include interleaving by writing the plurality of bit groups in each of a plurality of columns in bit group wise in a column direction, and reading each row of the plurality of columns in which the plurality of bit groups are written in bit group wise in a row direction.
The interleaving the plurality of bit groups may include serially writing, in the plurality of columns, at least some bit groups which are writable in the plurality of columns in bit group wise from among the plurality of bit groups, and then dividing and writing the other bit groups in an area which remains after the at least some bit groups are written in the plurality of columns in bit group wise.
According to an embodiment, there is provided a transmitting apparatus comprising: an encoder configured to encode input bits to generate parity bits based on a low density parity check (LDPC) code according to a code rate of 6/15 and a code length of 64800;
an interleaver configured to interleave the parity bits, split a codeword into a plurality of bit groups, and interleave the plurality of bit groups to provide an interleaved codeword, wherein the codeword comprising the input bits and the interleaved parity bits; and a mapper configured to map bits of the interleaved codeword onto constellation points for 16-quadrature amplitude 4a modulation(QAM), wherein the plurality of bit groups are interleaved based on a following equation: Y = X'r(j) for (0 < j < Ng""P) , where Xi is a jth bit group among the plurality of bit groups, Yi is a ith bit group among the interleaved plurality of bit groups, Ngroup is a total number of the plurality of bit groups, and 71(j) denotes a permutation order for the interleaving of the plurality of bit groups, and wherein the a(j) is defined as follows:
Order of interleaving it(j) (0 j < 180) ¨
(bdc 46 47 48 49 SO 51 52 53 54 55 56 57 liatc 104 10.5 106 107 108 109 110 111 112 113 114 6/15 it(j) In another embodiment there is a receiving apparatus comprising a receiver configured to receive a signal from a transmitting apparatus; a demodulator configured to demodulate the signal to generate values according to a 16-quadrature amplitude modulation(QAM); a deinterleaver configured to split the values into a plurality of groups, deinterleave the plurality of groups and deinterleave one or more values among the deinterleaved plurality of groups to provide deinterleaved values; and a decoder configured to decode the deinterleaved values based on a low density parity check (LDPC) code having a code rate being 6/15 and a code length being 64800 bits, wherein the plurality of groups are deinterleaved based on a following equation:

4b YE(j) = Xj for (0 < Ngroup) where X3 is a jth group among the plurality of groups, Y3 is a jth group among the deinterleaved plurality of groups, Nwoup is a total number of the plurality of groups, and 7r(j) denotes a deinterleaving order for the deinterleaving, and wherein the 7c(j) is represented as follows:
Order of deinterleaving z(j) (0 j < 180) Code Rate 104 105 106 107 108 109 110 111 112 Ili 114 6/15 7(j) In another embodiment there is a receiving method comprising receiving a signal from a transmitting apparatus; demodulating the signal to generate values according to a 16-quadrature amplitude modulation(QAM); splitting the values into a plurality of groups;
deinterleaving the plurality of groups; deinterleaving one or more values among the deinterleaved plurality of groups to provide deinterleaved values; and decoding the deinterleaved values based on a low density parity check (LDPC) code having a code rate being 6/15 and a code length being 64800 bits, wherein the plurality of groups are deinterleaved based on a following equation:
Y7c(j) = Xj for (0 < .Ngroup) 4c where N is a jth group among the plurality of groups, Yj is a ith group among the deinterleaved plurality of groups, Ngroup is a total number of the plurality of groups, and z(j) denotes a deinterleaving order for the deinterleaving, and wherein the z(j) is represented as follows:
Order of deinterleaving sr(j) (0 <j < 180) Code Rate 144 57 67 116 59 70 156 172 65 149 155 82 138 136 141 Ill 96 170 90 140 64 159 IS

6/15 Tr(j) [Advantageous Effects]
According to various exemplary embodiments, improved decoding and receiving performance can be provided.
[Description of Drawings]
The above and/or other aspects will be more apparent by describing in detail exemplary embodiments, with reference to the accompanying drawings, in which:

5 FIG. 1 is a block diagram to illustrate a configuration of a transmitting apparatus, according to an exemplary embodiment;
FIGs. 2 to 4 are views to illustrate a configuration of a parity check matrix, according to exemplary embodiments;
FIG. 5 is a block diagram to illustrate a configuration of an interleaver, according to an exemplary embodiment;
FIGs. 6 to 8 are views to illustrate an interleaving method, according to exemplary embodiments;
FIGs. 9 to 14 are views to illustrate an interleaving method of a block interleaver, according to exemplary embodiments;
FIG. 15 is a view to illustrate an operation of a demultiplexer, according to an exemplary embodiment;
FIGs. 16 and 17 are views to illustrate a method for designing an interleaving pattern, according to exemplary embodiments;
FIG. 18 is a block diagram to illustrate a configuration of a receiving apparatus according to an exemplary embodiment;
FIG. 19 is a block diagram to illustrate a configuration of a deinterleaver, according to an exemplary embodiment;
FIG. 20 is a view to illustrate a deinterleaving method of a block deinterleaver, according to an exemplary embodiment; and FIG. 21 is a flowchart to illustrate an interleaving method, according to an exemplary embodiment.
[Mode for Invention]
Hereinafter, various exemplary embodiments will be described in greater detail with reference to the accompanying drawings.
In the following description, same reference numerals are used for the same elements when they are depicted in different drawings. The matters defined in the description, such as detailed construction and elements, are provided to assist in a comprehensive understanding of the exemplary embodiments. Thus, it is apparent that the exemplary embodiments can be carried out without those specifically defined matters. Also, functions or elements known in the related art are not described in detail since they would obscure the exemplary embodiments with

6 unnecessary detail.
FIG. 1 is a block diagram to illustrate a configuration of a transmitting apparatus according to an exemplary embodiment. Referring to FIG. 1, the transmitting apparatus 100 includes an encoder 110, an interleaver 120, and a modulator 130 (or a constellation mapper).
The encoder 110 generates a low density parity check (LDPC) codeword by performing LDPC encoding based on a parity check matrix. To achieve this, the encoder 110 may include an LDPC encoder (not shown) to perform the LDPC encoding.
Specifically, the encoder 110 LDPC-encodes information word(or information) bits to generate the LDPC codeword which is formed of information word bits and parity bits (that is, LDPC parity bits). Here, bits input to the encoder 110 may be used as the information word bits.
Also, since an LDPC code is a systematic code, the information word bits may be included in the LDPC codeword as they are.
The LDPC codeword is formed of the information word bits and the parity bits.
For example, the LDPC codeword is formed of Nidpc number of bits, and includes Kid number of information word bits and Npanty=Nicipc-KkiN number of parity bits.
In this case, the encoder 110 may generate the LDPC codeword by performing the LDPC
encoding based on the parity check matrix. That is, since the LDPC encoding is a process for generating an LDPC codeword to satisfy HC T=0, the encoder 110 may use the parity check matrix when performing the LDPC encoding. Herein, H is a parity check matrix and C is an LDPC codeword.
For the LDPC encoding, the transmitting apparatus 100 may include a memory and may pre-store parity check matrices of various formats.
For example, the transmitting apparatus 100 may pre-store parity check matrices which are defined in Digital Video Broadcasting-Cable version 2 (DVB-C2), Digital Video Broadcasting-Satellite-Second Generation (DVB-S2), Digital Video Broadcasting-Second Generation Terrestrial (DVB-T2), etc., or may pre-store parity check matrices which are defined in the North America digital broadcasting standard system Advanced Television System Committee (ATSC) 3.0 standards, which are currently being established. However, this is merely an example and the transmitting apparatus 100 may pre-store parity check matrices of other formats in addition to these parity check matrices.
Hereinafter, a parity check matrix according to various exemplary embodiments will be

7 explained in detail with reference to the drawings. In the parity check matrix, elements other than elements having 1 have 0.
For example, the parity check matrix according to an exemplary embodiment may have a configuration of FIG. 2.
Referring to FIG. 2, a parity check matrix 200 is formed of an information word submatrix(or an information submatrix) 210 corresponding to information word bits, and a parity submatrix 220 corresponding to parity bits.
The information word submatrix 210 includes &ape number of columns and the parity submatrix 220 includes Nparity=Niapc-Kidpc number of columns. The number of rows of the parity check matrix 200 is identical to the number of columns of the parity submatrix 220, Npariti,---Nldpe-Kldpc=
In addition, in the parity check matrix 200, NI* is a length of an LDPC
codeword, Kidpc is a length of information word bits, and Nparity=1\lidpc-Kidpc is a length of parity bits. The length of the LDPC codeword, the information word bits, and the parity bits mean the number of bits included in each of the LDPC codeword, the information word bits, and the parity bits.
Hereinafter, the configuration of the information word submatrix 210 and the parity submatrix 220 will be explained in detail.
The information word submatrix 210 includes Kid number of columns (that is, Oth column to (Kidpe-1)th column), and follows the following rules:
First, M number of columns from among Kidp, number of columns of the information word submatrix 210 belong to the same group, and Kid number of columns is divided into Kiape/M
number of column groups. In each column group, a column is cyclic-shifted from an immediately previous column by Chip. That is, Qidp, may be a cyclic shift parameter value regarding columns in a column group of the information word submatrix 210 of the parity check matrix 200.
Herein, M is an interval at which a pattern of a column group, which includes a plurality of columns, is repeated in the information word submatrix 210 (e.g., M=360), and Qidpc is a size by which one column is cyclic-shifted from an immediately previous column in a same column group in the information word submatrix 210. Also, M is a common divisor of Nidpc and Kid and is determined to satisfy Chapc=(Niapc-Kwpc)/M. Here, M and Qmpc are integers and Kidpc/M is also an integer. M and ORIN may have various values according to a length of the LDPC codeword

8 and a code rate (CR)(or, coding rate).
For example, when M,--360 and the length of the LDPC codeword, NI*, is 64800, Qidpc may be defined as in table 1 presented below, and, when M=360 and the length Nidpc of the LDPC
codeword is 16200, Qidpe may be defined as in table 2 presented below.
[Table 1]
Code Rate Nidpc M Qidpc

9/15 64800 360 72

10/15 64800 360 60

11/15 64800 360 48

12/15 64800 360 36

13/15 64800 360 24 [Table 2]
Code Rate Nidpc M Qiepc Second, when the degree of the 0th column of the ith column group (i=0, 1, ..., Kid,./M-1) is Di (herein, the degree is the number of value 1 existing in each column and all columns belonging to the same column group have the same degree), and a position (or an index) of each row where 1 exists in the Oth column of the ith column group is AT = .,R11 , an index of a row where kth 1 is located in the ith column in the ith column group is determined by following Equation 1:
Rz(ki) =Ri(ti) +adix mod(N ) lalx Pc (1), where k=0, 1,2, ...D1-1; i---0, 1, ..., Kidpc/M-1; and j=1, 2, ..., M-1.
Equation 1 can be expressed as following Equation 2:

.Kcj) = --i(reo) + modM) x Qop, mod(N ¨ K,pc) ... (2), where k=0, 1,2, ...Di-1; i=0, 1, ..., &ape/M-1; and j=1, 2, ..., M-1. Since j=1, 2, = ==, M-1, 0 mod M) of Equation 2 may be regarded as j.
In the above equations, Ri(ki) is an index of a row where kth 1 is located in the jth column in the =th column group, Nidpc is a length of an LDPC codeword, &apt is a length of information word bits, Di is a degree of columns belonging to the ith column group, M is the number of columns belonging to a single column group, and ()Mix is a size by which each column in the column group is cyclic-shifted.
As a result, referring to these equations, when only Ri(ko) is known, the index Ri(kj) of the row where the kth 1 is located in the jth column in the ith column group can be known. Therefore, when the index value of the row where the kth 1 is located in the 0th column of each column group is stored, a position of column and row where 1 is located in the parity check matrix 200 having the configuration of FIG. 2 (that is, in the information word submatrix 210 of the parity check matrix 200) can be known.
According to the above-described rules, all of the columns belonging to the ith column group have the same degree Di. Accordingly, the LDPC codeword which stores information on the parity check matrix according to the above-described rules may be briefly expressed as follows.
For example, when Nape is 30, Kidpe is 15, and Qldpc is 3, position information of the row where 1 is located in the Oth column of the three column groups may be expressed by a sequence of Equations 3 and may be referred to as "weight-1 position sequence".
RJ 20) = 2, R,(30) = 8, k40) ¨10, RTo =0,1212r; = 9,C =13, Rt), = 0,R = . fd 14 = = = (3), where Rj) is an index of a row where V' 1 is located in the jth column in the th column group.
The weight-1 position sequence like Equation 3 which expresses an index of a row where 1 is located in the Oth column of each column group may be briefly expressed as in Table 3 presented below:
[Table 3]

014:
Table 3 shows positions of elements having value 1 in the parity check matrix, and the ith weight-1 position sequence is expressed by indexes of rows where 1 is located in the 0th column belonging to the ith column group.
The information word submatrix 210 of the parity check matrix according to an exemplary embodiment may be defined as in Tables 4 to 8 presented below, based on the above descriptions.
Specifically, Tables 4 to 8 show indexes of rows where 1 is located in the Oth column of the ith column group of the information word submatrix 210. That is, the information word submatrix 210 is formed of a plurality of column groups each including M number of columns, and positions of 1 in the 0th column of each of the plurality of column groups may be defined by Tables 4 to 8.
Herein, the indexes of the rows where 1 is located in the Oth column of the ith column group mean "addresses of parity bit accumulators". The "addresses of parity bit accumulators" have the same meaning as defined in the DVB-C2/S2/T2 standards or the ATSC 3.0 standards which are currently being established, and thus, a detailed explanation thereof is omitted.
For example, when the length Nidpc of the LDPC codeword is 64800, the code rate is 6/15, and M is 360, the indexes of the rows where 1 is located in the 0th column of the ith column group of the information word submatrix 210 are as shown in Table 4 presented below:
[Table 4]

[nth% of row where-1 h locatectite Oth column of the'kkcolumn group.
0 1606 3402 4961.6751 7132 11516 12300 12482 12592 13342 13764 14123 35442 36153 36740 37085 37152 ma 176S8 2 15 1094 2020 3080 4194 5098 5631 6677 7839 $237 9604 10067 11017 3 700 WI 1703 6017 6490 7372 7825 9546 1039816605,18561 13745 21625 4 159 1010 2.571 3617 4452 4950 5556 5832 648/ 8227 9924 10836 14954 7. 112 2307 1628 2041 7324 5358 7988 8191 10322 11905 12919 14127 15515 15711 17061, 19024 21195 22902 23727 24401 955 4123 .51.456885 8123 9730 11340 12216 19194 20313 23056 24248 24830 25268 3197332839 33025 33296 3571.0 3736637509 12 520 2562 2794 3528 3860 4402 5676 6953 8655901* 9783 11933 15336

14 1856 15100 1937821848 12 9638 9063 1254630120 =

CA 3 0 4 0 6 0 4 2 0 1 9 ¨0 4 ¨ 1 7 26 also 16477 27934 30021 39 4796 6238 25203 rasa t 15698 18209 30683 71 inn 26195 37653 In another example, when the length Isikipc of the LDPC codeword is 64800, the code rate is 8/15, and M is 360, the indexes of the rows where 1 is located in the Oth column of the ill column group of the information word submatrix 210 are as shown in Table 5 presented below:
[Table 5]

Index of row where 1 is located in the 0th column of the ith column group 4 869 24504386 $316 6160 7107 10362 11132 11271 13149 16397 16532 17113 509 4292 5831 8559 1004410412 11283 14310 15888 17243 1753$ 19903 20528 22090 6 3892248 5840 6043 7000 9054 1107$ 11760 12217 1256$ 13387 15403 19422 19$28 21493 25142 27777 28566 28702 *77022002* 24106 2630029332 30081 30196 _8 1490 3084 3467 4401 4798 fl 87 7851 11368 12323 14325 14546 16360 183912261423021 21763 2547826491 .2908329757 13 $91781 1900 3814 4121 804489069175 11156 14841 15789 16033 1675$ 17292 18550 19310 2250$ 29567 19850 2395 3070 3437 4764 4905 66709244 11345 13352 13573 1397$ 14600 15871 19 69720354887 5275 6909 9166 1180.5 15338 16381 18403 20425 20683 21547 22 2423281* 10296 12727 .38 24016 25880 26268 41 129 $396 15132 1132 1290 $7$6 52 2n9 18227 27458 =

69 4839 1346'7 27488 7$ 232 11296 29978 81 10866 1,3202 22517 82 11159 16111 21608 _ In another example, when the length N1 of of the LDPC codeword is 64800, the code rate is th 10/15, and M is 360, the indexes of rows where 1 exists in the Oth column of the -column group of the information word submatrix 210 are defined as shown in Table 6 below.
[Table 6]

15 . Index of row where 1 is located in the Oth column of the ith cohrmn group .

. I 2559 40258344553091679718 1133.2 1485517104 17721 18900 18791 3 32713574 6941 67229131 266311 7007 1790939-419 19445' = 4' 1534598 102011.0975 1104811298 1271315564,15978 18395 175421816419451 . 6 2408 2929 36904357 5852 73298536 869310603 31003 14304 14937 15767 a ia zan zon 2945 5537 6396 $7,977311 7166'13045 1911413576 24149 . 9 085 1591 3248 35479 370639476274 62747864 S0332351415475 26446 14334 973377440335825 61667219 7633 0657 10103 1905214240 17321, 18126 19244 20209 11 , 1793 2041 29449418 6148 9091 96613 971920876 101921131219171173281002.21459 12 167 925 2824 2325 264(1266650706597 701511109 9519 11508 1654217912 196.23.
_13 2/9318963039 4303 45908787 12241 3.3540 1447815492-10601 14 5883495 9045 96148131 84048990 90599248 115741433s 18,157 18941 n8188919672299 30215074 7044 7396766995941024440697 11691 1.7902 21410 ,t5 , 1390157917392194 3701 38655713 6877 7263 L217212143 1276517121 34 5932484 3071 321940544125 5553 59396928 7036 80541217316280 1794519302' 19 2321619 3040,4903 743481469127 8.25.3 1C14113321"17.347.17436.18193 '1954639929 21 .482 915 1548 1637 66879338 101931176811m 34524 3.4393 17335 18787 ' = 1291 150042.044512 3999 5194.2403413164 1328913971 1440914113 23 2191.4775744* 7740 8129034189919136 120710009 109791395917673 18194 1322 2348 29705692 6349.7577 3782 911e9267 9376'12049 12943 16660 1697021521 27 112335672 19550' 18 5975 11.533 19339, la = 27613594113102 'SI. 32301148914997 51 saps 33779 20674, 33 2220 1783918533' 34 1019 9342 9931.
'35, 3728.559712142' . 'is, 252066669164 , .

' 38 10361239316539' 39' 075 240712861 40 49225411 16205, , 41 49491564716838.

, 43 - 429 1042117248 , 44 .4340 1043,1 12208:

= 46 ' 7156 18562 19772 =
= '47 = '4941 79091.4994 49 4539863248871' =
:19711719048_20246*_, _ _

16 52 ; 15592956 15113-1 56 ; 78191101817503 58 i 582$129211315 ; 5661265 17411 _ 13 ' 60511421011S11 64 , 152912955 15902 66 ' 678412092 1642/

71 ' 15517 1134111115 73 3416693112073 _ 75 ' 7051762614981 =77 I 420 459715617 79 3$39754I5575 SO 1 465812615 ism/

la .135-3=512-312-13 I, 22804754 7311 r3755-10811 19314 "
.86 ; 1.1955 1131819541 it7 17/65057 21566 69 ' 4/12 502 8 9300 ='111 141587,790218118 92 6436917.119 11441 .93 , 4162907616530 14 ' 85581711Si 11100 65 177651.9795 20116 '57 664014421 15175 top 5948 5146 12001 10-1,--171-25-95912445-102 17707946 52,44, 103,_ 7384 /211914919

17 lot JAM USW 211959 3.05 794,3 104301531137 iSs 50051153. iCt03.5 107 =triso is Eirs itst3 10g, 44251041401n 36,3716264511376 110 1444037$51 12634s1/.4724 25,221081345157 fl.3575314B43=13954 71)43251.3753:
/15. SieSti31155e4 116 1,601304$11623 117 Dint 167211187SG
ti-. 421 NO 18171 us* 59431917S 20721 In another example, when the length Nidpc of the LDPC codeword is 64800, the code rate is 10/15, and M is 360, the indexes of rows where 1 exists in the 0th column of the ith column group of the information word submatrix 210 are defined as shown in Table 7 below.
[Table 7]

18 i Index of row where 1 is located in the 0th column of the ith column group 11 3020 3857 5275 5786 6319 8608 11943 14062 17.144 17752 18001 18453 19311

19 1042 1832 2545 2719 2947 3672 3700 6249 6398 6833 11114 14283 17694 21 854 1294 2436 2852 4903 6466 7761. 9072 9564 10321 13638 15658 16946 1254 8163 887691S7 12141 14587 16545 1,7175.18191 11707 14014 21.531 74 t 2711 7970 18317

20 In another example, when the length Nmpc of the LDPC codeword is 64800, the code rate is 12/15, and M is 360, the indexes of rows where 1 exists in the Oth column of the lth column group of the information word submatrix 210 are defined as shown in Table 8 below.
[Table 8]

21 I Index of row where 1 k located in the 0th column of the ith column Toup . _ 0 584 1472.1671.1867.3338 3568 2723 41.855126 5889 7737 8032 8940 9725.
1 221:445 590 37791835 6929 7743 8280 8442 8491 8967 10042 1124212917 2 46624837 49005029 5449 5637 6751 8584 9936 11681 11811 11885 1208912909' 2 24183013 3647 4210 4473 7447.7502 9490 10067 11092 11139 11256 12201 4 2591 2947 33492406.44174519 51766672.8491 8863 9201 11294 1137q 12104 2.7101197 290 871:1727 3911 5411 '6676 8.701. 935010316.1079812439 6 1755 1897 2923-3584 3901 4043 5963 70547132 9165 10284.10824 11278 12069 7 2183 3740 4803 52175860.63756787 8219 8466 9039 10353 10583 11118 12782.
8 731594. 2146 27153501 3572 3639 3725 6959.7187 810610120.10507 10691.
9 240 732 1215.23.832788 2830 3499 38814187 4991.6425 7061 9756 10491 . 10 131 1568,1821:3424 1319 4515 4539 9012 9702 102103 1041711240 11518 12458;
51 2024 2970 3048 3538 36734151 52:845779 5926.9423 9945 10873 1178711837 12 10491218 1651 2328 3493 4353 5750,0483 7013 8752 9738 9503 11744 '11937 13 1193.2060 2289 2964 3473 4392 4753 6709 7162.8231 8326 11140 1190812243 =
24 9762120 2439'3338 3850 4559 5557.8745.9056 970910161 10542 10711 12039 2.4032996 311.7.3247 3712 3399 5844 5932. 7811 10152 10228 11498 1216212941 26. 1781 2229753533 nu 3951 5379 5774 7930 9824 10920 11035 17340 12449 17 229 3841589 2230;3464 3391.5958 26562942 9006 10175 11415.11745 12530 13 155 354 1090 13362002.2236.3559 3705 4922 5950'6576 3504 997212764) 19 303 876 2059 2142 5244 5330 6644 7576 8614 9598 /0410 10713.11033.12957 --3449 3617 4405 4602 4727-0182 8835:9928 9372 9044 10i37 16747 11655 12745 21 81.1 2565 28202677 8974 963211069.'12548 11839 12107 12411.12695. 12812 12. 9724123,1943 6385 6149 7339 7477 8379 9177 9359 10074 11709 '12552 12831 29 842.9731541 22622905 5276 07537099 7894 8128 8325 8663 337510090' . 24 -.474791 968 3902 4924.4955 5085 5908 5109' 5329 7931 9138 9401 10568 26 1334.7371 12801 .
27 11931447 7972:
28 635 125710597' 29 4843.5102.11056 3294,8013 10513 31 11118 10374 lams.
31 5353 7224 10112,-33 3398:7674 8569 ' 34 79/99475 10603 . 35 29979418.9581.
36 57'77'65291122r . . . . .
38. 940E41'5927 -483 7229 7548, .
,41. 7865 8239 9804 42 1915 itosp 11900 43 5180 7096 9481'

22 44 '1431.5786 8924 48 1915'2303 4006 50. '2594 9993 22742 51 1592602 '12079 53 õ. 5261 5798 8413 54 = 3882 6052 12047 55 , 4133 6775 9657 55' = 22L687411183 60 '3909 7103 12804 62. 585-4-5856 7581 - - =

54 2545 2h57 4451 66 244 1855 4891.

63 391 161.710325 OW '250.925910603 71 1742 13045 9529"
=
72 76678875,11451 73 4023 5108.6911 74,.; 8521 10184 11650 75 '57261086112348 76 3272.6101 7368 77 =1 1137 5358 , 7 78 .381.2424 8537=

30 1980 2219 4569 =
81 = 2463 5669 20329 82 '2803331412808 33 35781642.11533 ps 619 4585 7923- = "
85, 59379. 5575 87 Y11754744.1719 _ 38 .1092518 6755 ¨
89 '2105 16626 ii153 91 .5260 7641 6233 92 2998 3094 11214 =
=

23 93 ' 3398 6466 11494 96 1028 795t 10825 9i 392 3308 11417 99 ' 5639 9291 12571 _1G1H 1064 2848 22753 111 10641 133.93 12157 126 2070 7271' 8,553 134 516 -7779" 10940 133 7870831.7 19322 135 r6855 7638 12909 141 am 9035 12555 1421_39035485999,2 In the above-described examples, the length of the LDPC codeword is 64800 and the code rate is 6/15, 8/15, 10/15, and 12/15. However, this is merely an example and the position of 1 in

24 the information word submatrix 210 may be defined variously when the length of the LDPC
codeword is 16200 or the code rate has different values.
According to an exemplary embodiment, even when the order of numbers in a sequence corresponding to the ith column group of the parity check matrix 200 as shown in the above-described Tables 4 to 8 is changed, the changed parity check matrix is a parity check matrix used for the same code. Therefore, a case in which the order of numbers in the sequence corresponding to the ith column group in Tables 4 to 8 is changed is covered by the inventive concept.
= According to an exemplary embodiment, even when the arrangement order of sequences corresponding to each column group is changed in Tables 4 to 8, cycle characteristics on a graph of a code and algebraic characteristics such as degree distribution are not changed. Therefore, a case in which the arrangement order of the sequences shown in Tables 4 to 8 is changed is also covered by the inventive concept.
In addition, even when a multiple of Qicipc is equally added to all sequences corresponding to a certain column group in Tables 4 to 8, the cycle characteristics on the graph of the code or the algebraic characteristics such as degree distribution are not changed.
Therefore, a result of equally adding a multiple of Okipc to the sequences shown in Tables 4 to 8 is also covered by the inventive concept. However, it should be noted that, when the resulting value obtained by adding the multiple of Q1dpc to a given sequence is greater than or equal to (Nidpc.-Kidp,), a value obtained by applying a modulo operation for (N1dpe-Ktdpe) to the resulting value should be applied instead.
Once positions of the rows where 1 exists in the Oth column of the ith column group of the information word submatrix 210 are defined as shown in Tables 4 to 8, positions of rows where 1 exists in another column of each column group may be defined since the positions of the rows where 1 exists in the Oth column are cyclic-shifted by Qidpc in the next column.
For example, in the case of Table 4, in the 0th column of the 0th column group of the information word submatrix 210, 1 exists in the 1606th row, 3402nd row, 4961st row.....
In this case, since Qidpc.,--(Nidpc-Kidr.c)/M464800-25920)/360=108, the indexes of the rows where 1 is located in the 1st column of the Oth column group may be 1714(=1606+108), 3510(=3402+108), 5069(.4961+108),..., and the indexes of the rows where 1 is located in the 2hd column of the Oth column group may be 1822(=1714+108), 3618(.3510+108), 5177(=5069+108),....

25 In the above-described method, the indexes of the rows where 1 is located in all rows of each column group may be defined.
The parity submatrix 220 of the parity check matrix 200 shown in FIG. 2 may be defined as follows:
The parity submatrix 220 includes N1-K1 number number of columns (that is, Kapcth column to (Nipdc-1)th column), and has a dual diagonal or staircase configuration.
Accordingly, the degree of columns except the last column (that is, (Nidpc-1)th column) from among the columns included in the parity submatrix 220 is 2, and the degree of the last column is 1.
As a result, the information word submatrix 210 of the parity check matrix 200 may be defined by Tables 4 to 8, and the parity submatrix 220 of the parity check matrix 200 may have a dual diagonal configuration.
When the columns and rows of the parity check matrix 200 shown in FIG. 2 are permutated based on Equation 4 and Equation 5, the parity check matrix shown in FIG. 2 may be changed to a parity check matrix 300 shown in FIG. 3.
(0 i < M,0 j < Qwpc) (4) K ldpc Qldpc k +1 Kzdpc + M = 1+ k (0 < M ,0 1 < Qupc) (5) The method for permutating based on Equation 4 and Equation 5 will be explained below.
Since row permutation and column permutation apply the same principle, the row permutation will be explained by the way of an example.
In the case of the row permutation, regarding the Xth row, i and j satisfying X = Q toe X i + j are calculated and the Xth row is permutated by assigning the calculated i and j to Mx j+i. For example, regarding the 7th row, i and j satisfying 7 = 2 x i + j are 3 and 1, respectively. Therefore, the 7th row is permutated to the 13th row (10 x1+ 3 =13).
When the row permutation and the column permutation are performed in the above-described method, the parity check matrix of FIG. 2 may be converted into the parity check matrix of FIG.
3.
Referring to FIG. 3, the parity check matrix 300 is divided into a plurality of partial blocks, and a quasi-cyclic matrix of M xM corresponds to each partial block.
Accordingly, the parity check matrix 300 having the configuration of FIG. 3 is formed of matrix units of M x M. That is, the submatrices of M x M are arranged in the plurality of partial

26 blocks, constituting the parity check matrix 300.
Since the parity check matrix 300 is formed of the quasi-cyclic matrices of MxM, M
number of columns may be referred to as a column block and M number of rows may be referred to as a row block. Accordingly, the parity check matrix 300 having the configuration of FIG. 3 is formed of Nqc column=Nidpc/M number of column blocks and Nqc row=Nparity/M
number of row blocks.
Hereinafter, the submatrix of M xM will be explained.
First, the (Nqc_columel) th column block of the Oth row block has a form shown in Equation 6 presented below:
0 0 ... 0 0 10.,.00 A = 0 1 ... 00 0 0 ... 1 0 As described above, A 330 is an M xM matrix, values of the 0th row and the (M-1)th column are all "0", and, regarding 0< i<(M-2), the (i+1)th row of the lth column is "1" and the other values are "0".
Second, regarding 0<i<(NIdpc-Kidp,)/M-1 in the parity submatrix 320, the ith row block of the (Kidpc/M+i)th column block is configured by a unit matrix MM 340. In addition, regarding 0<i<(Nkipc-Kidp,)/M-2, the (i+1)th row block of the (Kmpc/M+i)th column block is configured by a unit matrix /,õ, 340.
Third, a block 350 constituting the information word submatrix 310 may have a cyclic-shifted format of a cyclic matrix P, P 41 , or an added format of the cyclic-shifted matrix P of the cyclic matrix P (or an overlapping format).
For example, a format in which the cyclic matrix P is cyclic-shifted to the right by 1 may be expressed by Equation 7 presented below:

001...0 P=
000...1 - = = = (7)

27 The cyclic matrix P is a square matrix having an M xM size and is a matrix in which a weight of each of M number of rows is 1 and a weight of each of M number of columns is 1.
When aki is 0, the cyclic matrix P, that is, P indicates a unit matrix I õõõm , and when aki is co, 13 is a zero matrix.
A submatrix existing where the ith row block and the jth column block intersect in the parity check matrix 300 of FIG. 3 may be Pa" . Accordingly, i and j indicate the number of row blocks and the number of column blocks in the partial blocks corresponding to the information word.
Accordingly, in the parity check matrix 300, the total number of columns is INlidpc=Mx Nqc_coltunc, and the total number of rows is Npanty=M x Nqc_row. That is, the parity check matrix 300 is formed of Nqc_coiumn number of "column blocks" and Nqc_row number of "row blocks".
Hereinafter, a method for performing LDPC encoding based on the parity check matrix 200 as shown in FIG. 2 will be explained. An LDPC encoding process when the parity check matrix 200 is defined as shown in Table 4 by way of an example will be explained for the convenience of explanation.
First, when information word bits having a length of Kid are [io, It, = .., ], and parity bits having a length of Niapc-Kidpc are [Po, Pi, 132)... the LDPC
encoding is performed by the following process.
Step 1) Parity bits are initialized as '0'. That is, po= pi= p2=...= Pkix-Kko,..1 =0.
Step 2) The 0th information word bit io is accumulated in a parity bit having the address of the parity bit defined in the first row (that is, the row of i=0) of table 4 as the index of the parity bit.
This may be expressed by Equation 8 presented below:

28 P1606= P1606 0 P24533= P 24533 0 i 0 P3402= P3402010 P25376= P 25376 0 i 0 P4961= P4961 Oi 0 P25667 = P25667010 P6751 = P6751010 P26836= P26836 0 i P7132= P71320 i 0 P31799= P31799 i 0 P11516 = P11516 OiD P34173.= P34173 0 i P12300= P12300 P35462=' P 35462 0 i 0 P12482= P12482 Oi 0 P36153= P36153 i 0 P12592= P12592 0 i 0 P36740= P 36740 0 i 0 l3342= P13342 Oi 0 P37085= P37085 0 i o P13764= P13764 810 P37152= P3715201 0 P14123= P14123 Oi 0 P37468= P 37468 01 0 P21576= P21576 010 P37658= P 37658 i 0 P23946= P23946 0 i 0 =
= = .(8) Herein, io is a Oth information word bit, pi is an ith parity bit, and e is a binary operation.
According to the binary operation, le 1 equals 0, 1 ED 0 equals 1, 0 e 1 equals 1, 0021 0 equals 0.
Step 3) The other 359 information word bits in, (m=1, 2, ..., 359) are accumulated in the parity bit. The other information word bits may belong to the same column group as that of io. In this case, the address of the parity bit may be determined based on Equation 9 presented below:
(x + (m mod 360) x adr)mod(N1ap, ¨ Icipc ) (9) Herein, x is an address of a parity bit accumulator corresponding to the information word bit je, and Qmpc is a size by which each column is cyclic-shifted in the information word submatrix, and may be 108 in the case of table 4. In addition, since m=1, 2, ..., 359, (m mod 360) in Equation 9 may be regarded as m.
As a result, information word bits in, (m=1,2,..., 359) are accumulated in the parity bits having the address of the parity bit calculated based on Equation 9 as the index. For example, an operation as shown in Equation 10 presented below may be performed for the information word bit

29 P1714 = P1714 1 P24641= P24641 e1 P3510 = P35100I1 P25484= P25484 011 P5059 = P50690 i 1 P25775= P25775 ell P6859 = P68590 i 1 P26944= P26944 1 P7240 = P72400 i 1 P31907= P31907 011 P11624= P11624 0 i 1 P34281= P34281 0 i 1 P12408= P12408 0 i 1 P35570= P35570 011 P12590= P12590 0 I 1 P36261= P36261 011 P12700= P12700 0 i 1 P36848= P36848 e1 P13450= P13450 0 i 1 P37193= P37193 0 ii P13872= P13872 0 i 1 P37260= P37260 0 i 1 P14231 = P14231 011 P37576= P37576 Ii P21684= P21684 (Di 1 P37766= P37766 0i 1 P24054= P24054 e1 ...(10) Herein, i is a 1st information word bit, pi is an ith parity bit, and is a binary operation.
According to the binary operation, 19 1 equals 0, 1 8 0 equals 1, 0 8 1 equals 1, oe 0 equals 0.
Step 4) The 360th information word bits 1360 is accumulated in a parity bit having the address of the parity bit defined in the 2nd row (that is, the row of i=1) of table 4 as the index of the parity bit.
Step 5) The other 359 information word bits belonging to the same group as that of the information word bit i360 are accumulated in the parity bit. In this case, the address of the parity bit may be determined based on Equation 9. However, in this case, x is the address of the parity bit accumulator corresponding to the information word bit 1360.
Step 6) Steps 4 and 5 described above are repeated for all of the column groups of table 4.
Step 7) As a result, a parity bit pi is calculated based on Equation 11 presented below. In this case, i is initialized as 1.
pi= pi ED = 1,2,...,N,, ¨ K tdp, ¨1... (11) In Equation 11, pi is an ith parity bit, NI* is a length of an LDPC codeword, Kid is a length of an information word of the LDPC codeword, and ED is a binary operation.
As a result, the encoder 110 may calculate the parity bits according to the above-described

30 method.
In another example, a parity check matrix according to an exemplary embodiment may have a configuration as shown in FIG. 4.
Referring to FIG. 4, the parity check matrix 400 may be formed of 5 matrices A, B, C, Z, and D. Hereinafter, the configuration of each matrix will be explained to explain the configuration of the parity check matrix 400.
First, M1, M2, Qt, and Q2, which are parameter values related to the parity check matrix 400 as shown in FIG. 4, may be defined as shown in table 9 presented below according to the length and the code rate of the LDPC codeword.
[Table 9]
Rate. Length sizes Af 180. 5040 5 139 16200, 720 10080. 2 28 = 16200 1080 8640 3 24 6/15 64800 1080 . 37800 3 105 The matrix A is formed of K number of columns and g number of rows, and the matrix C is formed of K+g number of columns and N-K-g number of rows. Herein, K is a length of information word bits, and N is a length of the LDPC codeword.
Indexes of rows where 1 is located in the 0th column of the ith column group in the matrix A
and the matrix C may be defined based on table 10 according to the length and the code rate of the LDPC codeword. In this case, an interval at which a pattern of a column is repeated in each of the matrix A and the matrix C, that is, the number of columns belonging to the same group, may be 360.
For example, when the length N of the LDPC codeword is 64800 and the code rate is 6/15, the indexes of rows where 1 is located in the 0th column of the ith column group in the matrix A
and the matrix C are defined as shown in table 10 presented below:
[Table 10]

31 . Index of row where us located in the 0th column of the ith column group :0 71275856%67.11964 17373 11159 26426 2846928477 1 257312 672 2533 5316 65789037 10Z3.115845 36497 '2 233765 904 1366 3875 1314515405 18620 2191010825-.4 23496.891 2512 12589 14074 1939/20339.2765828614:
. 5 47371215912884374 98911125511381424242 32728 -3: = 5.15,t7 113 11823 17106.17900 19138 22315 24395 26448 7 45733 816 1923 3727174%2.5746 3380615995 36657 : 8 17487 6752670'3912 5145'1%09 239913107836624 - 9 72751773 193,71731428512 30665.30034 31015 31549 10' 257345.594'14041 1914124914. 26164 28809 3295534753 ii . 59 241 491 26509670 17433 1773518988-22235 30742.
= 12.. 1913299 655 6757830410917 16092.19387 2075537690' 13 351 916 926 18151 2170823216.30321 33578 3405137949 14 54332 3782010 3332 562316301 34337.36451 37851 15 139257106811090'20189 29694:29732.3264035133 36494' - 17- = 137571)5195006 6099797914429 15659 25443 32789 r 18 46282 28716258;18383,20258 27186 2749428429 38266 19 445466'1058 2868997611294 20364 23695 3662535330 20 .154900 93r 12518 14644'17715.19523 21111 33868 34570 -21 6266 5861020-2017023131 31041 31965-32224 35.189 = 23 332 675 1033 18n11004 15439 20765 31721 342251134363 = .24 527558332 3867 5318 831710833 18466 1842725377 26I = 339 536 1035, 57256916 1014614487 21156 28123 32614 ; . 27 455830 10787511 1139112362 1.2705.1740128857 34032.
= /3 /22531 9855593902283011409323445 25127 29011.
19 . 37 39378510257768 11157 22276 127612823130394 = _30 .234 257 1045 1307 29013 6337.26530 28142 3412915997:
.31 3546 978 9912-997812567 17843 24194 34187 35206

-32. 39959967 502710847 1465718859 28075 28214-36325:
53. 275477823 11178180712899710521 31661 31941-.32116 34 185351) 966-11733 12013'12760 13351 19372-32634 35504 ^ 35 7-60891.104611150 10151 21631.29930 3101433050.34840 36; = 360319 10575316 5938 14186 164043244534021 35722 t 37 306344 670.52246674 10105 13751 255833958835943'5 .30 813332 894 3%5 142751.4497 22505 2112828719 312.46--40 .2.1541L7605886 25612 13556 3221312194 35991 36130 . 41 2254691057-23838587 20555 2343128102-30147 12859, 42 288664 980 81.18 8531 2167823787 26708 28798-34490' 43 -89352847 6656-9189 21549252251:708031238 35823 -44 '6642443 359;36139773 14944-1546419185 25913 45 505875 931.16612 17669251017 18129334313573837381 ' 46 346 423 806 56697668 8789, 9928 19724 24039 27193 ; 47 .41450 105515117389 754920215 221p18221 35437 43 18163882415754508 :13588.19683 21750.30311 33430 '49* 25758 935 2855 81.87. S05121859 299413321714293 50 34962471'62698699S 64358974106491593217378 51 3364117871 3581 9830 108851383/ 16027-11203 35655, 52 15.849 1078 17301931921964 28164.28720 32557 35495 55.. 23449prlps 9431.9605-9700 0113 11332 12679 24255 54 . 516 638,733' 8651 19871' 22740 2579130152 3265935568' 55 ,253 sp.879 2066 15685 22952 237652538134556 37293 56' ,94 954.998'20033369 6870 732119856.31373 341188 57: :79 350933 4853 5252.11932.12058 21631 24552 24876 58 :245-547 7784035 10391.10656 13194325:32350.3417 591 '149 33 9436 69718356871511577, /2376 256134 31249 = =
= E0. '36149 220 6936 18408 19192 19288 23063,28411 35312' 61:, 273 641042 5327.10011 18041 21794 29097 397901425 51' 45 138 7212701 10154. 13002:13930 26625.28458= 28965';
63: . 121009 1040 1990 2930 51021215:226251301119286 64. 125 241'811.2245 3199 8415-21.133,26766 272263883g 65' 45476 1075-739615141 20414 31244 33336 35004 38391 66' 432578657:1343 10465 11.314 11507233142772034465, 67. .248.291555.1971.3989 891218000 19998 2393234652 68- :68 694 837 224574727137111075 12868 2093735591 = 272924 9441930 4350:62039737,19705 19023E09 21314979 231116324109. 19527 2192031413:34177 71 197 2531041249, 43$ 10021,14358 29551179943057_5;
72 = . 9802 16164 17499 12378 2240322704 26742 25908.
73: . 9064 19194 12305 14957;16155.2600 3.2613.34536 74- 5178 631910239.19343'25628 30577 31110:32291 In the above-described example, the length of the LDPC codeword is 64800 and the code rate 6/15. However, this is merely an example and the indexes of rows where 1 is located in the Oth column of the ith column group in the matrix A and the matrix C may be defined variously when the length of the LDPC codeword is 16200 or the code rate has different values.
Hereinafter, positions of rows where 1 exists in the matrix A and the matrix C
will be explained with reference to table 10 by way of an example.
Since the length N of the LDPC codeword is 64800 and the code rate is 6/15 in table 10, M1=1080, M2=37800, Qi=3, and 02=105 in the parity check matrix 400 defined by table 10 with reference to table 9.
Herein, Oi is a size by which columns of the same column group are cyclic-shifted in the matrix A, and 02 is a size by which columns of the same column group are cyclic-shifted in the matrix C.
In addition, QI=Mail-, 02=M2/1-, Mi=g, and M2=N-K-g, and L is an interval at which a pattern of a column is repeated in the matrix A and the matrix C, and for example, may be 360.
The index of the row where 1 is located in the matrix A and the matrix C may be determined based on the Mi value.
For example, since M1=1080 in the case of table 10, the positions of the rows where 1 exists

33 in the Oth column of the ith column group in the matrix A may be determined based on values smaller than 1080 from among the index values of table 10, and the positions of the rows where 1 exists in the Oth column of the ith column group in the matrix C may be determined based on values greater than or equal to 1080 from among the index values of table 10.
Specifically, in table 10, the sequence corresponding to the Oth column group is "71, 276, 856, 6867, 12964, 17373, 18159, 26420, 28460, 28477". Accordingly, in the case of the Oth column of the 0th column group of the matrix A, 1 may be located in the 71st row, 276th row, and 856th row, and, in the case of the Oth column of the 0th column group of the matrix C, 1 may be located in the 6867th row, 12964th row, 17373'd row, 18159th row, 26420th row, 28460' row, and 28477th row.
Once positions of 1 in the 0th column of each column group of the matrix A are defined, positions of rows where 1 exists in another column of each column group may be defined by cyclic-shifting from the previous column by Q1. Once positions of 1 in the Oth column of each column group of the matrix C are defined, position of rows where 1 exists in another column of each column group may be defined by cyclic-shifting from the previous column by Q2.
In the above-described example, in the case of the 0th column of the 0th column group of the matrix A, 1 exists in the 71st row, 276th row, and 856th row. In this case, since Q1=3, the indexes of rows where 1 exists in the lst column of the 0th column group are 74(=71+3), 279(.276+3), and 859(=856+3), and the index of rows where 1 exists in the 2'd column of the 0th column group are 77(=74+3), 282 (=279+3), and 862(=859+3).
In the case of the Oth column of the Oth column group of the matrix C, 1 exists in the 6867th row, 12964th row, 17373'd row, 18159th row, 26420th row, 28460th row, and 28477th row. In this case, since 02=105, the index of rows where 1 exists in the lst column of the 0th column group are 6972(=6867+105), 13069(.12964+105), 17478(=17373+105), 18264(=18159+105), 26525(=26420+105), 28565(=28460+105), 28582(=28477+105), and the indexes of rows where 1 exists in the 2nd column of the 0th column group are 7077(.6972+105), 13174(.13069+105), 17583(.17478+105), 18369(=18264+105), 26630(=26525+105), 28670(=28565+105), 28687(=28582+105).
In this method, the positions of rows where 1 exists in all column groups of the matrix A and the matrix C are defined.
The matrix B may have a dual diagonal configuration, the matrix D may have a diagonal

34 configuration (that is, the matrix D is an identity matrix), and the matrix Z
may be a zero matrix.
As a result, the parity check matrix 400 shown in FIG. 4 may be defined by the matrices A, B, C, D, and Z having the above-described configurations.
Hereinafter, a method for performing LDPC encoding based on the parity check matrix 400 shown in FIG. 4 will be explained. An LDPC encoding process when the parity check matrix 400 is defined as shown in Table 10 by way of an example will be explained for the convenience of explanation.
For example, when an information word block S=(so, Sici) is LDPC-encoded, an LDPC codeword A = , including a parity bit P=(1)43,P1,¨,Pmi+m2-,) may be generated.
M1 and M2 indicate the size of the matrix B having the dual diagonal configuration and the size of the matrix C having the diagonal configuration, respectively, and Mi=g, M2=N-K-g.
A process of calculating a parity bit is as follows. In the following explanation, the parity check matrix 400 is defined as shown in table 10 by way of an example, for the convenience of explanation.
Step 1) X and p are initialized as ?1=s1 (i=0,1,..., K-1), pi=0 M1+M2-1).
Step 2) The 0th information word bit X43 is accumulated in the address of the parity bit defined in the first row (that is, the row of i=0) of table 10. This may be expressed by Equation 12 presented below:
P71= P710 k 0 P17373= P17373 X 0 P276= P276 0 P18159= Pms C) X O
P866= P856 0 132642o = P26420 0 0 p6867= p6807 0 28460rP 28460ÃOP
P12964= PI29&4O P28477 = P28477 0 0 ...(12) Step 3) Regarding the next L-1 number of information word bits X,õ, (m=1, 2, ..., L-1), X,õ is accumulated in the parity bit address calculated based on Equation 13 presented below:
(x + Q,)modMi (if x < ) M1 +{(x¨M1+mxQ2)modM2} (if Mi )...(13) Herein, x is an address of a parity bit accumulator corresponding to the 0th information word bit 4.

35 In addition, 01=M1/L and Q2=M2/L. In addition, since the length N of the LDPC
codeword is 64800 and the code rate is 6/15 in table 10, M1=1080, M2=37800, Qi=3, Q2=105, and L=360 with reference to table 9.
Accordingly, an operation as shown in Equation 14 presented below may be performed for the 1st information word bit P74= P740 A, 1 P17478= P17478 A- 1 P2791.7* P279 A- 1 P18264= P182640Xl P859= P859 A-1 P26525= P26525 A- 1 P6972 = P69720 k 1 P28565= P28565 OA- 1 P13069 P13069 0 A- 1 P28582=
Step 4) Since the same address of the parity bit as in the second row (that is the row of i=1) of table 10 is given to the Lth information word bit AL, in a similar method to the above-described method, the address of the parity bit regarding the next L-1 number of information word bits (m=L+1, L+2, 2L4) is calculated based on Equation 13. In this case, x is the address of the parity bit accumulator corresponding to the information word bit AL, and may be obtained based on the second row of table 10.
Step 5) The above-described processes are repeated for L number of new information word bits of each group by considering new rows of table 10 as the address of the parity bit accumulator.
Step 6) After the above-described processes are repeated for the codeword bits AID to 4-1, values regarding Equation 15 presented below are calculated in sequence from i=1:
P, = P, ED P,i(i = 1,2,...,M, ¨1) ...(15) Step 7) Parity bits AK to ./1õ.,õ1_1 corresponding to the matrix B having the dual diagonal configuration are calculated based on Equation 16 presented below:
+Lxt+s = PQ,xS+t (0 s < L ,0 t <Q1) ...(16) Step 8) The address of the parity bit accumulator regarding L number of new codeword bits AK to 2K,mi_1 of each group is calculated based on table 10 and Equation 13.
Step 9) After the codeword bits AK to it are calculated, parity bits A.K.m, to .11e+m1+m24 corresponding to the matrix C having the diagonal configuration are calculated based on

36 Equation 17 presented below:
il'IC+Mi+Lxt+s = P (0 5_ s <L,0 5_ t <Q2) ...(17) As a result, the parity bits may be calculated in the above-described method.
Referring back to FIG. 1, the encoder 110 may perform the LDPC encoding by using various code rates such as 3/15, 4/15, 5/15, 6/15, 7/15, 8/15, 9/15, 10/15, 11/15, 12/15, 13/15, etc. In addition, the encoder 110 may generate an LDPC codeword having various lengths such as 16200, 64800, etc., based on the length of the information word bits and the code rate.
In this case, the encoder 110 may perform the LDPC encoding by using the parity check matrix, and the parity check matrix is configured as shown in FIGS. 2 to 4.
In addition, the encoder 110 may perform Bose, Chaudhuri, Hocquenghem (BCH) encoding as well as LDPC encoding. To achieve this, the encoder 110 may further include a BCH encoder (not shown) to perform BCH encoding.
In this case, the encoder 110 may perform encoding in an order of BCH encoding and LDPC
encoding. Specifically, the encoder 110 may add BCH parity bits to input bits by performing BCH encoding and LDPC-encodes the information word bits including the input bits and the BCH parity bits, thereby generating the LDPC codeword.
The interleaver 120 interleaves the LDPC codeword. That is, the interleaver 120 receives the LDPC codeword from the encoder 110, and interleaves the LDPC codeword based on various interleaving rules.
In particular, the interleaver 120 may interleave the LDPC codeword such that a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC
codeword (that is, a plurality of groups or a plurality of blocks) is mapped onto a predetermined bit of a modulation symbol. Accordingly, the modulator 130 may map a bit included in a predetermined group from among the plurality of groups of the LDPC codeword onto a predetermined bit of the modulation symbol.
To achieve this, as shown in FIG. 5, the interleaver 120 may include a parity interleaver 121, a group interleaver (or a group-wise interleaver 122), a group twist interleaver 123 and a block interleaver 124.
The parity interleaver 121 interleaves the parity bits constituting the LDPC
codeword.
Specifically, when the LDPC codeword is generated based on the parity check matrix 200 = having the configuration of FIG. 2, the parity interleaver 121 may interleave only the parity bits

37 of the LDPC codeword by using Equations 18 presented below:
ci for 0<i<ICIdpc, and c,c4.,+Q.,., for 05_s<M, 05_t<Q1dp, ... (18), where M is an interval at which a pattern of a column group is repeated in the information word submatrix 210, that is, the number of columns included in a column group (for example, M=360), and Oidp. is a size by which each column is cyclic-shifted in the information word submatrix 210. That is, the parity interleaver 121 performs parity interleaving with respect to the LDPC codeword c=(co, ci, and outputs Uquo, UN4).
The LDPC codeword parity-interleaved in the above-described method may be configured such that a predetermined number of continuous bits of the LDPC codeword have similar decoding characteristics (cycle distribution, a degree of a column, etc.).
For example, the LDPC codeword may have the same characteristics on the basis of M
number of continuous bits. Herein, M is an interval at which a pattern of a column group is repeated in the information word submatrix 210 and, for example, may be 360.
Specifically, a product of the LDPC codeword bits and the parity check matrix should be "0".
This means that a sum of products of the ith LDPC codeword bit, c,;(i=0, 1, ..., N1dpc-1) and the ith column of the parity check matrix should be a "0" vector. Accordingly, the ith LDPC codeword bit may be regarded as corresponding to the ith column of the parity check matrix.
In the case of the parity check matrix 200 of FIG. 2, M number of columns in the information word submatrix 210 belong to the same group and the information word submatrix 210 has the same characteristics on the basis of a column group (for example, the columns belonging to the same column group have the same degree distribution and the same cycle characteristic).
In this case, since M number of continuous bits in the information word bits correspond to the same column group of the information word submatrix 210, the information word bits may be formed of M number of continuous bits having the same codeword characteristics. When the parity bits of the LDPC codeword are interleaved by the parity interleaver 121, the parity bits of the LDPC codeword may be formed of M number of continuous bits having the same codeword characteristics.
However, regarding the LDPC codeword encoded based on the parity check matrix 300 of FIG. 3 and the parity check matrix 400 of FIG. 4, parity interleaving may not be performed. In this case, the parity interleaver 121 may be omitted.
The group interleaver 122 may divide the parity-interleaved LDPC codeword into a plurality

38 of bit groups and rearrange the order of the plurality of bit groups in bit group wise (or bit group unit). That is, the group interleaver 122 may interleave the plurality of bit groups in bit group wise.
To achieve this, the group interleaver 122 divides the parity-interleaved LDPC
codeword into a plurality of bit groups by using Equation 19 or Equation 20 presented below.
1 Y =={Ukii i i-k 360 ,(:11c<N,õpc}for05 j<N
group ... (19) Xj = tuk 1360 x j k < 360 x (j +1),0 k < .1s1h,pcIfor0 5. j <Ng,õõp... (20) where Ngroup _ is the total number of bit groups, X, is the jth bit group, and uk is the le LDPC codeword bit input to the group interleaver 122.1n addition, ¨k is the largest integer below k/360.
i Since 360 in these equations indicates an example of the interval M at which the pattern of a column group is repeated in the information word submatrix, 360 in these equations can be changed to M.
The LDPC codeword which is divided into the plurality of bit groups may be as shown in FIG.
6.
Referring to FIG. 6, the LDPC codeword is divided into the plurality of bit groups and each bit group is formed of M number of continuous bits. When M is 360, each of the plurality of bit groups may be formed of 360 bits. Accordingly, the bit groups may be formed of bits corresponding to the column groups of the parity check matrix.
Specifically, since the LDPC codeword is divided by M number of continuous bits, Kldpc number of information word bits are divided into (Kiope/M) number of bit groups and Mope-Knipe number of parity bits are divided into (Nicipc-Kkipc)/M number of bit groups.
Accordingly, the LDPC codeword may be divided into (Mopc/M) number of bit groups in total.
For example, when M=360 and the length Mope of the LDPC codeword is 16200, the number of groups Ngroups constituting the LDPC codeword is 45(.16200/360), and, when M=360 and the length Nidpc of the LDPC codeword is 64800, the number of bit groups Ngroup constituting the LDPC codeword is 180(=64800/360).
As described above, the group interleaver 122 divides the LDPC codeword such that M
number of continuous bits are included in a same group since the LDPC codeword has the same codeword characteristics on the basis of M number of continuous bits.
Accordingly, when the

39 LDPC codeword is grouped by M number of continuous bits, the bits having the same codeword characteristics belong to the same group.
In the above-described example, the number of bits constituting each bit group is M. However, this is merely an example and the number of bits constituting each bit group is variable.
For example, the number of bits constituting each bit group may be an aliquot part of M. That is, the number of bits constituting each bit group may be an aliquot part of the number of columns constituting a column group of the information word submatrix of the parity check matrix. In this case, each bit group may be formed of aliquot part of M number of bits. For example, when the number of columns constituting a column group of the information word submatrix is 360, that is, M=360, the group interleaver 122 may divide the LDPC codeword into a plurality of bit groups such that the number of bits constituting each bit group is one of the aliquot parts of 360.
In the following explanation, the number of bits constituting a bit group is M
by way of an example, for the convenience of explanation.
Thereafter, the group interleaver 122 interleaves the LDPC codeword in bit group wise.
Specifically, the group interleaver 122 may group the LDPC codeword into the plurality of bit groups and rearrange the plurality of bit groups in bit group wise. That is, the group interleaver 122 changes positions of the plurality of bit groups constituting the LDPC
codeword and rearranges the order of the plurality of bit groups constituting the LDPC
codeword in bit group wise.
Herein, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise such that bit groups including bits mapped onto the same modulation symbol from among the plurality of bit groups are spaced apart from one another at predetermined intervals.
In this case, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by considering at least one of the number of rows and columns of the block interleaver 124, the number of bit groups of the LDPC codeword, and the number of bits included in each bit group, such that bit groups including bits mapped onto the same modulation symbol are spaced apart from one another at predetermined intervals.
To achieve this, the group interleaver 122 may rearrange the order of the plurality of groups in bit group wise by using Equation 21 presented below:
Yi = X,,(1)(0. j < N ) gr "P . . . (21),

40 where Xi is the jth bit group before group interleaving, and Yi is the jth bit group after group interleaving. In addition, 7c(j) is a parameter indicating an interleaving order and is determined by at least one of a length of an LDPC codeword, a modulation method, and a code rate. That is, 7c(j) denotes a permutation order for group wise interleaving.
Accordingly, X,0 is a 7z(j)th bit group before group interleaving, and Equation 21 means that the pre-interleaving 7c(j)th bit group is interleaved into the jth bit group.
According to an exemplary embodiment, an example of 7c(j) may be defined as in Tables 11 to 22 presented below.
In this case, 7c(j) is defined according to a length of an LPDC codeword and a code rate, and a parity check matrix is also defined according to a length of an LDPC codeword and a code rate.
Accordingly, when LDPC encoding is performed based on a specific parity check matrix according to a length of an LDPC codeword and a code rate, the LDPC codeword may be interleaved in bit group wise based on 7c(j) satisfying the corresponding length of the LDPC
codeword and code rate.
For example, when the encoder 110 performs LDPC encoding at a code rate of 6/15 to generate an LDPC codeword of a length of 64800, the group interleaver 122 may perform interleaving by using 7c(j) which is defined according to the length of the LDPC codeword of 16200 and the code rate of 6/15 in tables 11 to 22 presented below.
For example, when the length of the LDPC codeword is 64800, the code rate is 6/15, and the modulation method(or modulation format) is 16-Quadrature Amplitude Modulation (QAM), 7c(j) may be defined as in table 11 presented below. In particular, table 11 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 4.
[Table 11]
Order of bit groups to be block interleaved n(j) (05. j <180) j-th block of 0 1 2 3 4 5 6 7 8 9 group- 23 2 2 2 2 2 2 3 3 3 3 3 3 3 wise interleaver 7 8 9 0 1 2 3 4 5 6 7 8 9 output 69

41 716)-th 3 14 5 4 6 4 1 4 2 3 2 3 2 3 block of 4 3 group- 8 8 3 2 9 1 0 6 1 0 3 0 5 4 wise 12 1 9 1 1 3 1 1 7 1 1 1 1 1 7 01 4 15 05 1 9 77 4 0 45 62 02 2.0 26 5 3 52 29 74 25 2 28 interleaver 1 1 1 1 8 1 7 1 1 7 1 1 8 input 71 42 78 54 5 07 5 2 51 7 17 09 0 06 34 8 22 32 35 , In the case of Table 11, Equation 21 may be expressed as Y0=X,0)=X55, Y1=-X710)=X146, Y2=X11(2)=X83, ===, Y178=Xx(178)=X132, and Y179=Xit(t79)=X1,35. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 55th bit group to the 0th bit group, the 146th bit group to the 151 bit group, the 83`d bit group to the 21 bit group, ..., the 132hd bit group to the 178th bit group, and the 135th bit group to the 179th bit group.
In another example, when the length of the LDPC codeword is 64800, the code rate is 8/15, and the modulation method is 16-QAM, n(j) may be defined as in table 12 presented below. In particular, table 12 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 5.
[Table 12]
j-th Order of bit groups to be block interleaved block of 71(j) (0 Sj < 180) group- 1 2 3 4 5 6 7 8 9 1 1 1 1 1 wise interleaver 4 5 6 7 8 9 0 1 2 3 4 5 6 output 4 4 5 5 5 5 5 5 5 5 5 5 6

42 1' 1 1 1 1 1 1 1 1 16 1 1 1 t 1 1 1 1 1 1 1 1 1 rt(j)-th 92 1 6 6 2 2 2 2 6 5 7 5 4 block of group- 4 1 7 0 2 0 0 1 8 9 7 4 5 2 wise 1 1 3 1 1 1 1 1 1 1 1 1 interleaver _______________________________________________________________ input o 42 6 4 61 70 34 56 2 54 74 45 46 4 24 6 02 33 76 32 35 11 1 1 1 1 1 I 1 9 1 1' 1 1 1 In the case of Table 12, Equation 21 may be expressed as Y0=X.(0)=X58, Yi=X41)=X55, Y2=X*2)=Xiii, =-=, Yi78=X/07a)=X171, and Yi79=X707(1)=X155. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 58th bit group to the 0th bit group, the 55th bit group to the 1st bit group, the 1111h bit group to the 2nd bit group, ..., the 171st bit group to the 178111 bit group, and the 155th bit group to the 179th bit group.
In another example, when the length of the LDPC codeword is 64800, the code rate is 10/15, and the modulation method is 16-QAM, n(j) may be defined as in table 13 presented below. In particular, table 13 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 6.
[Table 13]
j-th Order of bit groups to be block interleaved block of n(j) (0 j < 180) i 1 1 1 1 1 1 1 1 1 1 2' 2` 2 group- 1 2 3 4 5 6 7 8 9

43 wise 2 2 2 2 2 2 3 3 3 3 3 3 3 interleaver output 7 8 9 0 1 2 3 4 5 6 7 8 9 0 _ .

13 I 1 r 1 1 1 1 1 1 1 1 1 1 f 8 5 1 4 4 4 3 4- 9 1 9 - 8 1 4 9 n(j)-th 10 8 3 7 3 8 7 6 5 7 1 4 1 -block of group- 05 19 9 2 0 01 14 2 7 5 17 3 5 7 6 8 12 8 06 wise 16 7 1 5 2 6 1 7 1 6 2 2 1 0 8 8 9 3 4 9 9 34 3 4 (1 56 0 0 5 1 8 6 28 interleaver input 7 1 61 62 23 38 73 77 00 2 7 37 32 69 58 3 1 In the case of Table 13, Equation 21 may be expressed as Y0=Xn(0)=X74, Y1=Nto)=X53, Y2=X(2)=X84, = = 5 Y178=XX(178)=X159) and Yi79--.X,(l79)=X163. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 74th bit group to the 0th bit group, the 53'd bit group to the 1St bit group, the 84th bit group to the 2nd bit = =
group, ..., the 159th bit group to the 178th bit group, and the 163rd bit group to the 1791h pit group.
In another example, when the length of the LDPC codeword is 64800, the code rate is 10/15, and the modulation method is 16-QAM, rt(j) may be defined as in table 14 presented below. In particular, table 14 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 7.
[Table 14]
j-th Order of bit groups to be block .. interleaved block of n(j) (0 j <180)

44 group- 0 1 2 3 4 5 6 7 8 9 1 1 1 1 wise interleaver 4 5 6 7 8 9 0 1 2 3 4 5 6 4 4 4 output 46 5 5 5 5 5 5 5 5 5 2- 7 3 2 9 6 1 1 1 .. 1 8 4 1 9 7 4 8 1 6 4 6 _ 7CW-lh 38 7 1 5 8 1 1 7 7 6 4 9 3 9 block of group- 4 4 4 11 5 0 4 5 0 0 7 01 9 3 wise 3 1 5 1 1 1 8 1 1 1 1 1 1 interleaver input 58 20 2 ¨

In the case of Table 14, Equation 21 may be expressed as Yo:---X70)=X6s, Yi=X,E0)=X7i, Y2=X*2)=X54, = = = , Y178=Xn078)=X135, and Yi79=X7079)=X24. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 68th bit group to the Oth bit group, the 71st bit group to the 1st bit group, the 54th bit group to the 2nd bit group,..., the 1351h bit group to the 178th bit group, and the 24th bit group to the 179th bit group.
In another example, when the length of the LDPC codeword is 64800, the code rate is 12/15, and the modulation method is 16-QAM, 7r(j) may be defined as in table 15 presented below. In particular, table 15 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 8.
[Table 15]

45 Order of bit groups to be block interleaved It(j) (0 j < 180) j-th block of 46 4 4 4 5 5 5 5 5 5 5 5 5 group- 8 9 0 1 2 3 4 5 6 7 8 9 0 wise 69 interleaver 9 9 9 9 9 9 9 1 1 1 1 1 1 output 3 4 block of group- 04 24 2 0 18 4 4 1 wise 17 1 1 1 1 1 1 1 1 1 1 1 1 1 interleaver input 3 52 46 77 03 60 47 6 72 44 50 32 76 68 67 62 70 38 51 61 0 6 30 In the case of Table 15, Equation 21 may be expressed as Yo=-----xxorXt2o, Yi=Xxo)=X32, Y2=Xx(2)=X38, = = =, Y178=Xic(178)=Xtot, and Yi79=XIT,u79)=X39. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 120th bit group to the Oth bit group, the 32'd bit group to the bit group, the 38th bit group to the 2"
bit group, ..., the 101st bit group to the 1781h bit group, and the 39t bit group to the 179th bit group.
In another example, when the length of the LDPC codeword is 64800, the code rate is 6/15, and the modulation method is 16-QAIVI, n(j) may be defined as in table 16 presented below. In particular, table 16 may be applied when LDPC encoding is performed based on the parity check

46 matrix defined by table 10.
[Table 16]
Order of bit groups to be block interleaved n(j) (0 j <180) j-th 23 block of 4 4 4 46 5 5 5 5 5 5 5 5 5 5 group- 7 8 9 0 1 2 3 4 5 6 7 8 9 0 wise 69 interleaver " 9 9 9 9 9 9 9 1 1 1 1 1 1 output 3 4 11 I 1 1 1 I I 1 1 1 1 1 1 1 1 .. 1 .. 1 .. 1 .. 1 , .. 1 .. 1 .. 1 .. 1 13 1 1 1 1 - I 1 1 1 1 1 1 1 1 .. 1 ..
1 .. 1 .. 1 .. 1 .. 1 .. 1 .. 1 .. 1 68 57 67 0 03 0 50 25 05 29 ' 46 41 52 64 7t6)-th 6 1 1 4 1 1 6 6 8 3 1 6 8 block of group- 7 9 6 8 55 1 6 6 9 8 2 54 3 1 wise 14 3 2 2 1 3 6 1 1 3 5 9 1 1 interleaver input 66 7 61 74 9 3 t 1 9 In the case of Table 16, Equation 21 may be expressed as Y0=X0)=X163, Yi=Xx0)=Xi6o, Y2=Xx(2)=X138, Y178=X7,(178)=X148, and Yr79=X70.79)=X98. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 163rd bit group to the 0th bit group, the 160th bit group to the 1st bit group, the 138th bit group to the 2nd bit group, ..., the 148th bit group to the 178th bit group, and the 981h bit group to the 179th bit group.
In another example, when the length of the LDPC codeword is 64800, the code rate is 6/15,

47 and the modulation method is 64-QAM, n(j) may be defined as in table 17 presented below. In particular, table 17 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 4.
[Table 17]
Order of bit groups to be block interleaved n(j) (0 j <180) tit. 1 1 1 2 -j-th 23 block of - 4 4 4 5 5 5 5 5 5 5 5 5 5 group- 7 8 9 0 1 2 3 4 5 6 7 8 9 0 wise 69 _ interleaver 9 9 9 9 9 9 9 1 1 1 1 1 1 3 output 4 5 _11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 a 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 , - _ 710)-1h 16 1 5 6 5 6 5 I 7 5 1 6 3 2 block of 11 4 8 1 1 2 7 1 7 7 1 1 1 1 .2-group- 3 8 8 229 37 0 3 66 5 7 42 74 5 49 8 45 2 69 0 33 63 19 wise 82 0 1 1 1 1 1 9 1 1 8 1 1 1 interleaver-it 1 8 7 1 1 1 9 1 9 1 1 1 1 1 1 input o 18 27 4 9 08 26 31 3 11 1 25 62 57 58 09 40 23 54 50 0 1 3 30 24 75 20 0 02 0 14 59 6 77 78 21 68 5 17 55 =
In the case of Table 17, Equation 21 May be expressed as Yo.X7c0FX29, Y1=X*1)=X17, Y2-An(2)=X38, = = =) Y178=X,1078)=X117, and Yi79=-X71079)=X155. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 291h bit group to the Oth bit group, the 17th bit group to the 1st bit group, the 38th bit group to the 2nd bit group, ..., the 117th bit group to the 178th bit group, and the 155th bit group to the 179th bit group.

48 In another example, when the length of the LDPC codeword is 64800, the code rate is 8/15, and the modulation method is 64-QAM, 7t(j) may be defined as in table 18 presented below. In particular, table 18 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 5.
[Table 18]
Order of bit groups to be block interleaved n(j) (0 j <180) 2 2 2 2 2 - 2 3 3 3 3 3 3' 3 3-block of group- 7 8 9 0 1 2 3 4 5 6 7 8 9 0 8 8 8 8 8 8 9 9¨

wise 69 interleaver 9 9 9 9 9 9 9 1 1 1 1 1 1 output 3 4 5 6 7 8 9 OD 01 02 03 04 05 06 07 08 09 10 11 12 13 14 n(j)-th 9 6 5 8 7 1 8 7 6 8 7 1 1 1 block of 1 1 1' 1 2 3 2 1 1 1 1 2 1 1 1 1 1' 3 1 3 1 2 I

group- 21 08 39 42 4 4 0 57 59 38 43 9 40 63 50 75 14 1 2 5 45 8 wise 2 27 1 9 1 1 1 1 2 2 1 1 4 1 interleaver _________________________________________________________ input 34 1 4 79 29 69 01 9 09 27 68 76 1 In the case of Table 18, Equation 21 may be expressed as Y0=X70)=X86, Yi=Xx(1)=X71, Y2=X(2)=X5i, ===9 Yi78=Xx(178)=X174, and Yi79=X2:039)=-X12.8. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 861 bit group to the 0th bit group, the 711' bit group to the 11' bit group, the 5111 bit group to the 2nd bit

49 group, ..., the 174th bit group to the 1781h bit group, and the 1281h bit group to the 1791h bit group.
In another example, when the length of the LDPC codeword is 64800, the code rate is 10/15, and the modulation method is 64-QAM, n(j) may be defined as in table 19 presented below. In particular, table 19 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 6.
[Table 19]
Order of bit groups to be block interleaved 7r(j) (0 j <180) j-th 23 block of 4 4 4 5 5 5 5 5 5- 5 5 5 5 group- 7 8 9 0 1 2 3 4 5 6 7 8 9 0 _ wise 69 (1 1 2 3 4 5 6 7 8 9 0 1 2 3 interleaver 9 9 9 9 9 9 9 1 1 1 1 1 1 output =11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 13 1 1 1 1 1 1 1 1 1 1 1 1 1 1 __ 1 __ 1 __ 1 __ 1 __ 1 __ 1 __ 1 __ 1 6 .. 5 .. 5 .. 9 .. 1 .. 5 .. 5 .. 8 n(j)-th 8 5 6 7 1 8 1 6- 1 1 6 4 - 1 8 block of -4 .. 6 .. 7 .. 6 .. 9 .. 6 .. 1 .. 1 group- 7 8 wise 15 2 1 4 5 1 1 I 3 1 2 1 2 I

36 58 34 3 8 41 60 $
interleaver -= 0 9 input 54 1 69 1 71 62 39 75 29 5 67 31 In the case of Table 19, Equation 21 may be expressed as Yo=X70)=X73, Yi.--Xx0)=X36, Y2=Xit2)=X21, = ==9 Y178=Xx(178):-'--X149, and Yr79=X7079)=X135. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 73rd

50 bit group to the Oth bit group, the 36th bit group to the 1st bit group, the 21st bit group to the 2nd bit group, ..., the 1491h bit group to the 178th bit group, and the 135th bit group to the 179th bit group.
In another example, when the length of the LDPC codeword is 64800, the code rate is 10/15, and the modulation method is 64-QAM, n(j) may be defined as in table 20 presented below. In particular, table 20 may be applied when LDPC encoding is performed 'based on the parity check matrix defined by table 7.
[Table 20]
Order of bit groups to be block interleaved rt(j) (0 5_ j <180) j-th 23 block of 4 4 4 5 5 5 5 5 5 5 5 5 5 6 group-wise 69 interleaver 9 9 9 9 9 9 9 1 I 1 1 I I

output 3 4 7t(j)-th 1 6 1 1 3 1 5 1 3 9 7 9 1 8 block of as group- 29 Win 19 0 8 5 interleaver input 6 5 1 0 1 68 21 53 40 52 35 74 1 1 I 1 1 1 1 1 1 1 t 1 1 I 1 I

: = ' In the case of Table 20, Equation 21 may be expressed as Yo=XE(0)=X113, YI=Xx(1)=Xtis, Y2=Xn(2)=X47, == Yr73=X7078)=Xi3o, and Yr9=X7079)=X176. Accordingly, the group interleaver

51 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 113th bit group to the Oth bit group, the 115th bit group to the 11' bit group, the 47th bit group to the 2nd bit group, ..., the 130th bit group to the 178th bit group, and the 1761h bit group to the 179th bit group.
In another example, when the length of the LDPC codeword is 64800, the code rate is 12/15, and the modulation method is 64-QAM, n(j) may be defined as in table 21 presented below. In particular, table 21 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 8.
[Table 21]
Order of bit groups to be block interleaved n(j) (0 j <180) j-th 23 block of 4 4 4 46 5 5 5 5 5 5 5 5 5 5 group- 7 8 9 0 1 2 3 4 5 6 7 8 9 0 wise 69 interleaver 9 9 9 9 9 9 9 1 1 1 1 1 1 output 6 7 13 f 1 1 1 1 - 1 1 1 1 f 1 1 I

37 ii 9 116)-th 10 7 2 6 7 2 1 8 9 1 1 1 2 4 block of group- 8213 34 2 05 8 7 35 6 6 40 4 6 9 4 20 08 3 5 9 21 8 9 wise 29 interleaver it 1 1 7 1 1 1 1 3 1 1 1 1 1 1 input 6 23 14 0 07 78 45 73 6 44 30 76 71 75 25 9 62 59 0 64 15 69 72 5 61 51 19 22 52 57 37 =48 53 70 54 66 3 50 6 67 74 63 9

52 In the case of Table 21, Equation 21 may be expressed as Y0=X7,0)=X83, Yi=X7,0)=X93, Y2=Xx(2)=X94, = = Y178=Xz(178)=X2, and Yr9=Xõ079)=X14. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 83'd bit group to the 0th bit group, the 93rd bit group to the 1' bit group, the 94th bit group to the 2nd bit group, ..., the 2nd bit group to the 17816 bit group, and the 1416 bit group to the 179th bit group.
In another example, when the length of the LDPC codeword is 64800, the code rate is 6/15, and the modulation method is 64-QAM, it(j) may be defined as in table 22 presented below. In particular, table 22 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 10.
[Table 22]
Order of bit groups to be block interleaved 7r(j) (0 j <180) j-th - 23 block of 4 4 4 5 5 5 5 5 5 5 5 5 5 6 group- 7 8 9 0 1 2 3 4 5 6 7 8 9 0 -wise 69 interleaver 9 9 9 9 9 9 9 1 1 1 1 1 1 output 6 7 - 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1' 1 1- 1 I 1 ir(j)-th block of 64 55 1 02 3 1 1 7 1 26 7 6 group- 8 5 3 wise 7 1 7 1 4 3 3 2 1 4 6 4 1 3 interleaver 1 07 7 11 2 5 8 3 00 5 9 0 29 3 63 9 12 45 4 05 17 input 8 _

53 1 2 1 60 1 35 1 32 1 34 4 1 46 1 4 1 2 " 1 " 1 " 1 69 I
In the case of Table 22, Equation 21 may be expressed as Y0=X*0)=X175, Y1=X710)=X177, Yz=Xx(2)=X173, = = Yi78=Xxo.78)=X3i, and Yi-T9=X7(l79)=X72. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 175th bit group to the Oth bit group, the 177th bit group to the 1St bit group, the 173rd bit group to the 2nd bit group, ..., the 31st bit group to the 178th bit group, and the 72" bit group to the 179th bit group.
In the above-described examples, the length of the LDPC codeword is 64800 and the code rate is 6/15, 8/15, 10/15, and 12/15. However, this is merely an example and the interleaving pattern may be defined variously when the length of the LDPC codeword is 16200 or the code rate has different values.
As described above, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by using Equation 21 and Tables 11 to 22.
"j-th block of Group-wise Interleaver output" in tables 11 to 22 indicates the j-th bit group output from the group interleaver 122 after interleaving, and "a(j)-th block of Group-wise Interleaver input" indicates the rc(j)-th bit group input to the group interleaver 122.
In addition, since the order of the bit groups constituting the LDPC codeword is rearranged by the group interleaver 122 in bit group wise, and then the bit groups are block-interleaved by the block interleaver 124, which will be described below, "Order of bit groups to be block interleaved" is set forth in Tables 11 to 22 in relation to it(j).
The LDPC codeword which is group-interleaved in the above-described method is illustrated in FIG. 7. Comparing the LDPC codeword of FIG. 7 and the LDPC codeword of FIG.
6 before group interleaving, it can be seen that the order of the plurality of bit groups constituting the LDPC codeword is rearranged.
That is, as shown in FIGs. 6 and 7, the groups of the LDPC codeword are arranged in order of bit group X0, bit group X1, ..., bit group XNgroup-i before being group-interleaved, and are arranged in an order of bit group Yo, bit group Yi, ..., bit group Y
- Ngroup.1 after being group-interleaved. In this case, the order of arranging the bit groups by the group interleaving may be determined based on Tables 11 to 22.
The group twist interleaver 123 interleaves bits in a same group. That is, the group twist interleaver 123 may rearrange the order of the bits in the same bit group by changing the order of

54 the bits in the same bit group.
In this case, the group twist interleaver 123 may rearrange the order of the bits in the same bit group by cyclic-shifting a predetermined number of bits from among the bits in the same bit group.
For example, as shown in FIG. 8, the group twist interleaver 123 may cyclic-shift bits included in the bit group Y1 to the right by 1 bit. In this case, the bits located in the 0th position, the 1st position, the Vid position, ..., the 3586 position, and the 359th position in the bit group Yi as shown in FIG. 8 are cyclic-shifted to the right by 1 bit. As a result, the bit located in the 359th position before being cyclic-shifted is located in the front of the bit group Y1 and the bits located in the 0th position, the 15t position, the 2nd position, ..., the 358th position before being cyclic-shifted are shifted to the right serially by 1 bit and located.
In addition, the group twist interleaver 123 may rearrange the order of bits in each bit group by cyclic-shifting a different number of bits in each bit group.
For example, the group twist interleaver 123 may cyclic-shift the bits included in the bit group Y1 to the right by 1 bit, and may cyclic-shift the bits included in the bit group Y2 to the right by 3 bits.
However, the above-described group twist interleaver 123 may be omitted according to circumstances.
In addition, the group twist interleaver 123 is placed after the group interleaver 122 in the above-described example. However, this is merely an example. That is, the group twist interleaver 123 changes only the order of bits in a certain bit group and does not change the order of the bit groups. Therefore, the group twist interleaver 123 may be placed before the group interleaver 122.
The block interleaver 124 interleaves the plurality of bit groups the order of which has been rearranged. Specifically, the block interleaver 124 may interleave the plurality of bit groups the order of which has been rearranged by the group interleaver 122 in bit group wise (or bits group unit). The block interleaver 124 is formed of a plurality of columns each including a plurality of rows and may interleave by dividing the plurality of rearranged bit groups based on a modulation order determined according to a modulation method.
In this case, the block interleaver 124 may interleave the plurality of bit groups the order of which has been rearranged by the group interleaver 122 in bit group wise.
Specifically, the block

55 interleaver 124 may interleave by dividing the plurality of rearranged bit groups according to a modulation order by using a first part and a second part.
Specifically, the block interleaver 124 interleaves by dividing each of the plurality of columns into a first part and a second part, writing the plurality of bit groups in the plurality of columns of the first part serially in bit group wise, dividing the bits of the other bit groups into groups (or sub bit groups) each including a predetermined number of bits based on the number of columns, and writing the sub bit groups in the plurality of columns of the second part serially.
Herein, the number of bit groups which are interleaved in bit group wise may be determined by at least one of the number of rows and columns constituting the block interleaver 124, the number of bit groups and the number of bits included in each bit group. In other words, the block interleaver 124 may determine the bit groups which are to be interleaved in bit group wise considering at least one of the number of rows and columns constituting the block interleaver 124, the number of bit groups and the number of bits included in each bit group, interleave the corresponding bit groups in bit group wise, and divide bits of the other bit groups into sub bit groups and interleave the sub bit groups. For example, the block interleaver 124 may interleave at least part of the plurality of bit groups in bit group wise using the first part, and divide bits of the other bit groups into sub bit groups and interleave the sub bit groups using the second part.
Meanwhile, interleaving bit groups in bit group wise means that the bits included in the same bit group are written in the same column. In other words, the block interleaver 124, in case of bit groups which are interleaved in bit group wise, may not divide the bits included in the same bit groups and write the bits in the same column, and in case of bit groups which are not interleaved in bit group wise, may divide the bits in the bit groups and write the bits in different columns.
Accordingly, the number of rows constituting the first part is a multiple of the number of bits included in one bit group (for example, 360), and the number of rows constituting the second part may be less than the number of bits included in one bit group.
In addition, in all bit groups interleaved by the first part, the bits included in the same bit group are written and interleaved in the same column of the first part, and in at least one group interleaved by the second part, the bits are divided and written in at least two columns of the second part.
The specific interleaving method will be described later.
Meanwhile, the group twist interleaver 123 changes only the order of bits in the bit group and

56 does not change the order of bit groups by interleaving. Accordingly, the order of the bit groups to be block-interleaved by the block interleaver 124, that is, the order of the bit groups to be input to the block interleaver 124, may be determined by the group interleaver 122. Specifically, the order of the bit groups to be block-interleaved by the block interleaver 124 may be determined by z(j) defined in Tables 11 to 22.
As described above, the block interleaver 124 may interleave the plurality of bit groups the order of which has been rearranged in bit group wise by using the plurality of columns each including the plurality of rows.
In this case, the block interleaver 124 may interleave the LDPC codeword by dividing the plurality of columns into at least two parts. For example, the block interleaver 124 may divide each of the plurality of columns into the first part and the second part and interleave the plurality of bit groups constituting the LDPC codeword.
In this case, the block interleaver 124 may divide each of the plurality of columns into N
number of parts (N is an integer greater than or equal to 2) according to whether the number of bit groups constituting the LDPC codeword is an integer multiple of the number of columns constituting the block interleaver 124, and may perform interleaving.
When the number of bit groups constituting the LDPC codeword is an integer multiple of the number of columns constituting the block interleaver 124, the block interleaver 124 may interleave the plurality of bit groups constituting the LDPC codeword in bit group wise without dividing each of the plurality of columns into parts.
Specifically, the block interleaver 124 may interleave by writing the plurality of bit groups of the LDPC codeword on each of the columns in bit group wise in a column direction, and reading each row of the plurality of columns in which the plurality of bit groups are written in bit group Wise in a row direction.
In this case, the block interleaver 124 may interleave by writing bits included in a predetermined number of bit groups, which corresponds to a quotient obtained by dividing the number of bit groups of the LDPC codeword by the number of columns of the block interleaver 124, on each of the plurality of columns serially in a column direction, and reading each row of the plurality of columns in which the bits are written in a row direction.
Hereinafter, the group located in the th position after being interleaved by the group interleaver 122 will be referred to as group Y.

57 For example, it is assumed that the block interleaver 124 is formed of C
number of columns each including RI number of rows. In addition, it is assumed that the LDPC
codeword is formed of Ngroup number of bit groups and the number of bit groups Ngroup is a multiple of C.
In this case, when the quotient obtained by dividing Ngroup number of bit groups constituting the LDPC codeword by C number of columns constituting the block interleaver 124 is A
(=Ngroup/C) (A is an integer greater than 0), the block interleaver 124 may interleave by writing A
(=Ngroup/C) number of bit groups on each column serially in a column direction and reading bits written on each column in a row direction.
For example, as shown in FIG. 9, the block interleaver 124 writes bits included in bit group Yo, bit group Y1,..., bit group YA-1 in the lst column from the lst row to the Rill' row, writes bits included in bit group YA, bit group YA+15 = = bit group Y2A-1 in the 2nd column from the 1st row to the Rith row, ..., and writes bits included in bit group YcA-A, bit group YCA-A+1, bit group YCA...1 in the column C from the 1s1 row to the Rid' row. The block interleaver 124 may read the bits written in each row of the plurality of columns in a row direction.
Accordingly, the block interleaver 124 interleaves all bit groups constituting the LDPC
codeword in bit group wise.
However, when the number of bit groups of the LDPC codeword is not an integer multiple of the number of columns of the block interleaver 124, the block interleaver 124 may divide each column into 2 parts and interleave a part of the plurality of bit groups of the LDPC codeword in bit group wise, and divide bits of the other bit groups into sub bit groups and interleave the sub bit groups. In this case, the bits included in the other bit groups, that is, the bits included in the number of groups which correspond to the remainder when the number of bit groups constituting the LDPC codeword is divided by the number of columns are not interleaved in bit group wise, but interleaved by being divided according to the number of columns.
Specifically, the block interleaver 124 may interleave the LDPC codeword by dividing each of the plurality of columns into two parts.
In this case, the block interleaver 124 may divide the plurality of columns into the first part and the second part based on at least one of the number of columns of the block interleaver 124, the number of bit groups of the LDPC codeword, and the number of bits of bit groups.
Here, each of the plurality of bit groups may be formed of 360 bits. In addition, the number of bit groups of the LDPC codeword is determined based on the length of the LDPC
codeword and

58 the number of bits included in the bit group. For example, when an LDPC
codeword in the length of 16200 is divided such that each bit group has 360 bits, the LDPC
codeword is divided into 45 bit groups. Alternatively, when an LDPC codeword in the length of 64800 is divided such that each bit group has 360 bits, the LDPC codeword may be divided into 180 bit groups.
Further, the number of columns constituting the block interleaver 124 may be determined according to a modulation method. This will be explained in detail below.
Accordingly, the number of rows constituting each of the first part and the second part may be determined based on the number of columns constituting the block interleaver 124, the number of bit groups constituting the LDPC codeword, and the number of bits constituting each of the plurality of bit groups.
Specifically, in each of the plurality of columns, the first part may be formed of as many rows as the number of bits included in at least one bit group which can be written in each column in bit group wise from among the plurality of bit groups of the LDPC codeword, according to the number of columns constituting the block interleaver 124, the number of bit groups constituting the LDPC codeword, and the number of bits constituting each bit group.
In each of the plurality of columns, the second part may be formed of rows excluding as many rows as the number of bits included in at least some bit groups which can be written in each of the plurality of columns in bit group wise. Specifically, the number rows of the second part may be the same value as a quotient when the number of bits included in all bit groups excluding bit groups corresponding to the first part is divided by the number of columns constituting the block interleaver 124. In other words, the number of rows of the second part may be the same value as a quotient when the number of bits included in the remaining bit groups which are not written in the first part from among bit groups constituting the LDPC codeword is divided by the number of columns.
That is, the block interleaver 124 may divide each of the plurality of columns into the first part including as many rows as the number of bits included in bit groups which can be written in each column in bit group wise, and the second part including the other rows.
Accordingly, the first part may be formed of as many rows as the number of bits included in bit groups, that is, as many rows as an integer multiple of M. However, since the number of codeword bits constituting each bit group may be an aliquot part of M as described above, the first part may be formed of as many rows as an integer multiple of the number of bits

59 constituting each bit group.
In this case, the block interleaver 124 may interleave by writing and reading the LDPC
codeword in the first part and the second part in the same method.
Specifically, the block interleaver 124 may interleave by writing the LDPC
codeword in the plurality of columns constituting each of the first part and the second part in a column direction, and reading the plurality of columns constituting the first part and the second part in which the LDPC codeword is written in a row direction.
That is, the block interleaver 124 may interleave by writing the bits included in at least some bit groups which can be written in each of the plurality of columns in bit group wise in each of the plurality of columns of the first part serially, dividing the bits included in the other bit groups except the at least some bit groups and writing in each of the plurality of columns of the second part in a column direction, and reading the bits written in each of the plurality of columns constituting each of the first part and the second part in a row direction.
In this case, the block interleaver 124 may interleave by dividing the other bit groups except the at least some bit groups from among the plurality of bit groups based on the number of columns constituting the block interleaver 124.
Specifically, the block interleaver 124 may interleave by dividing the bits included in the other bit groups by the number of a plurality of columns, writing each of the divided bits in each of a plurality of columns constituting the second part in a column direction, and reading the plurality of columns constituting the second part, where the divided bits are written, in a row direction.
That is, the block interleaver 124 may divide the bits included in the other bit groups except the bit groups written in the first part from among the plurality of bit groups of the LDPC
codeword, that is, the bits in the number of bit groups which correspond to the remainder when the number of bit groups constituting the LDPC codeword is divided by the number of columns, by the number of columns, and may write the divided bits in each column of the second part serially in a column direction.
For example, it is assumed that the block interleaver 124 is formed of C
number of columns each including R1 number of rows. In addition, it is assumed that the LDPC
codeword is formed of Ngroup number of bit groups, the number of bit groups Ngroup is not a multiple of C, and AxC +1= N smip (A is an integer greater than 0). In other words, it is assumed that when the

60 number of bit groups constituting the LDPC codeword is divided by the number of columns, the quotient is A and the remainder is 1.
In this case, as shown in FIGs 10 and 11, the block interleaver 124 may divide each column into a first part including R1 number of rows and a second part including R2 number of rows. In this case, R1 may correspond to the number of bits included in bit groups which can be written in each column in bit group wise, and R2 may be R1 subtracted from the number of rows of each column.
That is, in the above-described example, the number of bit groups which can be written in each column in bit group wise is A, and the first part of each column may be formed of as many rows as the number of bits included in A number of bit groups, that is, may be formed of as many rows as Ax M number.
In this case, the block interleaver 124 writes the bits included in the bit groups which can be written in each column in bit group wise, that is, A number of bit groups, in the first part of each column in the column direction.
That is, as shown in FIGs. 10 and 11, the block interleaver 124 writes the bits included in each of bit group YO, bit group Yi, = = =, group YA.1 in the 1g to Rid' rows of the first part of the 1g column, writes bits included in each of bit group 'IA, bit group YA+1, =.., bit group Y2A.1 in the 15`
to Rid' rows of the first part of the 2n1 column, ..., writes bits included in each of bit group Y
- CA-A, bit group YCA-Ai.i, ..., bit group Yci in the 15t to Rith rows of the first part of the column C.
As described above, the block interleaver 124 writes the bits included in the bit groups which can be written in each column in bit group wise in the first part of each column.
In other words, in the above exemplary embodiment, the bits included in each of bit group (Y0), bit group bit group (YA.1) may not be divided and all of the bits may be written in the first column, the bits included in each of bit group (YA), bit group (YA+1),--, bit group (Y2A-1) may not be divided and all of the bits may be written in the second column,õ, and the bits included in each of bit group (YcA.A), bit group (YcA.A+1),... , group (YcA.1) may not be divided and all of the bits may be written in the C column. As such, all bit groups interleaved by the first part are written in the same column of the first part.
Thereafter, the block interleaver 124 divides bits included in the other bit groups except the bit groups written in the first part of each column from among the plurality of bit groups, and writes the bits in the second part of each column in the column direction. In this case, the block

61 interleaver 124 divides the bits included in the other bit groups except the bit groups written in the first part of each column by the number of columns, so that the same number of bits are written in the second part of each column, and writes the divided bits in the second part of each column in the column direction.
In the above-described example, since A xC +1=N group when the bit groups constituting the LDPC codeword are written in the first part serially, the last bit group YNg,õp_i of the LDPC
codeword is not written in the first part and remains. Accordingly, the block interleaver 124 divides the bits included in the bit group YNgroup-i into C number of sub bit groups as shown in FIG. 10, and writes the divided bits (that is, the bits corresponding to the quotient when the bits included in the last group (YNgr0up-1) are divided by C) in the second part of each column serially.
The bits divided based on the number of columns may be referred to as sub bit groups. In this case, each of the sub bit groups may be written in each column of the second part. That is, the bits included in the bit groups may be divided and may form the sub bit groups.
That is, the block interleaver 124 writes the bits in the 1st to R2th rows of the second part of the 1sE column, writes the bits in the 1st to R2th rows of the second part of the 2nd column, ..., and writes the bits in the 1st to RP rows of the second part of the column C. In this case, the block interleaver 124 may write the bits in the second part of each column in the column direction as shown in FIG. 10.
That is, in the second part, the bits constituting the bit group may not be written in the same column and may be written in the plurality of columns. In other words, in the above example, the last bit group (YNgr0up-1) is formed of M number of bits and thus, the bits included in the last bit group (YNgroup-i) may be divided by M/C and written in each column. That is, the bits included in the last bit group (YNgroup4) are divided by M/C, forming M/C number of sub bit groups, and each of the sub bit groups may be written in each column of the second part.
Accordingly, in at least one bit group which is interleaved by the second part, the bits included in the at least one bit group are divided and written in at least two columns constituting the second part.
In the above-described example, the block interleaver 124 writes the bits in the second part in the column direction. However, this is merely an example. That is, the block interleaver 124 may write the bits in the plurality of columns of the second part in the row direction. In this ease, the block interleaver 124 may write the bits in the first part in the same method as described above.

62 Specifically, referring to FIG. 11, the block interleaver 124 writes the bits from the 1st row of the second part in the 1st column to the 1st row of the second part in the column C, writes the bits from the 2" row of the second part in the 1st column to the 2nd row of the second part in the column C, etc., and writes the bits from the R2th row of the second part in the 1st column to the R2th row of the second part in the column C.
On the other hand, the block interleaver 124 reads the bits written in each row of each part serially in the row direction. That is, as shown in FIGs. 10 and 11, the block interleaver 124 reads the bits written in each row of the first part of the plurality of columns serially in the row direction, and reads the bits written in each row of the second part of the plurality of columns serially in the row direction.
Accordingly, the block interleaver 124 may interleave a part of the plurality of bit groups constituting the LDPC codeword in bit group wise, and divide and interleave some of the remaining bit groups. That is, the block interleaver 124 may interleave by writing the LDPC
codeword constituting a predetermined number of bit groups from among the plurality of bit groups in the plurality of columns of the first part in bit group wise, dividing the bits of the other bit groups and writing the bits in each of the columns of the second part, and reading the plurality of columns of the first and second parts in the row direction.
As described above, the block interleaver 124 may interleave the plurality of bit groups in the methods described above with reference to FIGs. 9 to 11.
In particular, in the case of FIG. 10, the bits included in the bit group which does not belong to the first part are written in the second part in the column direction and read in the row direction. In view of this, the order of the bits included in the bit group which does not belong to the first part is rearranged. Since the bits included in the bit group which does not belong to the first part are interleaved as described above, bit rrror rate (BER)/frame error rate (FER) performance can be improved in comparison with a case in which such bits are not interleaved.
However, the bit group which does not belong to the first part may not be interleaved as shown in FIG. 11. That is, since the block interleaver 124 writes and reads the bits included in the group which does not belong to the first part in and from the second part in the row direction, the order of the bits included in the group which does not belong to the first part is not changed and the bits are output to the modulator 130 serially. In this case, the bits included in the group which does not belong to the first part may be output serially and mapped onto a modulation

63 symbol.
In FIGs. 10 and 11, the last single bit group of the plurality of bit groups is written in the second part. However, this is merely an example. The number of bit groups written in the second part may vary according to the total number of bit groups of the LDPC
codeword, the number of columns and rows, the number of transmission antennas, etc.
The block interleaver 124 may have a configuration as shown in tables 23 and 24 presented below:
[Table 23]
Nicbc--- 64800 QPSK; 16 QAM 64QAM ;250'c*M
1024 pANI 4096i G 2 4 = ip 8' 10 12 Rt 32400 16200 10800 7920 6480 5400 R2 .0 0 0 180 0 0, _ .
[Table 24]
, .
= tikapetr. 16200 OPSK 16 QAM = ; 64 QAM 256 QAM .1024 QAM 4096 QAM
C 2: . 4 i 6 8 4 .10. 12 R1 7920 3960 ; 2520 '1800 1.440 1080 R2 180. 90 180 225 180 r 270 Herein, C (or Nc) is the number of columns of the block interleaver 124, R1 is the number of rows constituting the first part in each column, and R2 is the number of rows constituting the second part in each column.
Referring to Tables 23 and 24, the number of columns has the same value as a modulation order according to a modulation method, and each of a plurality of columns is formed of rows corresponding to the number of bits constituting the LDPC codeword divided by the number of a plurality of columns.
For example, when the length Nidpc of the LDPC codeword is 64800 and the modulation method is 16-QAM, the block interleaver 124 is formed of 4 columns as the modulation order is 4 in the case of 16-QAM, and each column is formed of rows as many as R1+R2=16200(=64800/4). In another example, when the length Nkip, of the LDPC
codeword is 64800 and the modulation method is 64-QAM, the block interleaver 124 is formed of 6 columns as the modulation order is 6 in the case of 64-QAM, and each column is formed of rows as many as R1+R2=10800(=64800/6).

64 Meanwhile, referring to Tables 23 and 24, when the number of bit groups constituting an LDPC codeword is an integer multiple of the number of columns, the block interleaver 124 interleaves without dividing each column. Therefore, R1 corresponds to the number of rows constituting each column, and R2 is 0. In addition, when the number of bit groups constituting an LDPC codeword is not an integer multiple of the number of columns, the block interleaver 124 interleaves the groups by dividing each column into the first part formed of R1 number of rows, and the second part formed of R2 number of rows.
When the number of columns of the block interleaver 124 is equal to the number of bits constituting a modulation symbol, bits included in a same bit group are mapped onto a single bit of each modulation symbol as shown in Tables 23 and 24.
For example, when N1apc=64800 and the modulation method is 16-QAM, the block interleaver 124 may be formed of four (4) columns each including 16200 rows. In this case, the bits included in each of the plurality of bit groups are written in the four (4) columns and the bits written in the same row in each column are output serially. In this case, since four (4) bits constitute a single modulation symbol in the modulation method of 16-QAM, bits included in the same bit group, that is, bits output from a single column, may be mapped onto a single bit of each modulation symbol. For example, bits included in a bit group written in the 1st column may be mapped onto the first bit of each modulation symbol.
In another example, when Nidpc=64800 and the modulation method is 64-QAM, the block interleaver 124 may be formed of six (6) columns each including 10800 rows. In this case, the bits included in each of the plurality of bit groups are written in the six (6) columns and the bits written in the same row in each column are output serially. In this case, since six (6) bits constitute a single modulation symbol in the modulation method of 64-QAM, bits included in the same bit group, that is, bits output from a single column, may be mapped onto a single bit of each modulation symbol. For example, bits included in a bit group written in the lst column may be mapped onto the first bit of each modulation symbol.
Referring to Tables 23 and 24, the total number of rows of the block interleaver 124, that is, R1-FR2, is Nkipc/C.
In addition, the number of rows of the first part, R1, is an integer multiple of the number of bits included in each group, M (e.g., M=360), and maybe expressed as Ngroup /
C iX M and the number of rows of the second part, R2, may be Islidpc/C-Ri. Herein, LN p C is the largest

65 integer below IsIg.p/C. Since R1 is an integer multiple of the number of bits included in each group, M, bits may be written in R1 in bit groups wise.
In addition, when the number of bit groups of the LDPC codeword is not a multiple of the number of columns, it can be seen from Tables 23 and 24 that the block interleaver 124 interleaves by dividing each column into two parts.
Specifically, the length of the LDPC codeword divided by the number of columns is the total number of rows included in the each column. In this case, when the number of bit groups of the LDPC codeword is a multiple of the number of columns, each column is not divided into two parts. However, when the number of bit groups of the LDPC codeword is not a multiple of the number of columns, each column is divided into two parts.
For example, it is assumed that the number of columns of the block interleaver 124 is identical to the number of bits constituting a modulation symbol, and an LDPC
codeword is formed of 64800 bits as shown in Table 28. In this case, each bit group of the LDPC codeword is formed of 360 bits, and the LDPC codeword is formed of 64800/360(.180) bit groups.
When the modulation method is 16-QAM, the block interleaver 124 may be formed of four (4) columns and each column may have 6480014(=16200) rows.
In this case, since the number of bit groups of the LDPC codeword divided by the number of columns is 180/4(=45), bits can be written in each column in bit group wise without dividing each column into two parts. That is, bits included in 45 bit groups which is the quotient when the number of bit groups constituting the LDPC codeword is divided by the number of columns, that is, 45x360(=16200) bits can be written in each column.
However, when the modulation method is 256-QAM, the block interleaver 124 may be formed of eight (8) columns and each column may have 64800/8(.8100) rows.
In this ease, since the number of bit groups of the LDPC codeword divided by the number of columns is 180/8=22.5, the number of bit groups constituting the LDPC codeword is not an integer multiple of the number of columns. Accordingly, the block interleaver 124 divides each of the eight (8) columns into two parts to perform interleaving in bit group wise.
In this case, since the bits should be written in the first part of each column in bit group wise, the number of bit groups which can be written in the first part of each column in bit group wise is 22, which is the quotient when the number of bit groups constituting the LDPC
codeword is divided by the number of columns, and accordingly, the first part of each column has

66 22x360(=7920) rows. Accordingly, 7920 bits included in 22 bit groups may be written in the first part of each column.
The second part of each column has rows which are the rows of the first part subtracted from the total rows of each column. Accordingly, the second part of each column includes 8100-7920(=180) rows.
In this case, the bits included in the other bit groups which have not been written in the first part are divided and written in the second part of each column.
Specifically, since 22x8(=176) bit groups are written in the first part, the number of bit groups to be written in the second part is 180-176 (=4) (for example, bit group Y176, bit group Y177, bit group Y178, and bit group Y179 from among bit group Yo, bit group Y1, bit group Y2, = =
bit group Y178, and bit group Y179 constituting the LDPC codeword).
Accordingly, the block interleaver 124 may write the four (4) bit groups which have not been written in the first part and remains from among the groups constituting the LDPC codeword in the second part of each column serially.
That is, the block interleaver 124 may write 180 bits of the 360 bits included in the bit group Y176 in the l row to the 180th row of the second part of the 1st column in the column direction, and may write the other 180 bits in the 1" row to the 180th row of the second part of the 2nd column in the column direction. In addition, the block interleaver 124 may write 180 bits of the 360 bits included in the bit group Yin in the 1st row to the 180th row of the second part of the 3' column in the column direction, and may write the other 180 bits in the 1" row to the 180th row of the second part of the 4th column in the column direction. In addition, the block interleaver 124 may write 180 bits of the 360 bits included in the bit group Y178 in the 1st row to the 180th row of the second part of the 5th column in the column direction, and may write the other 180 bits in the 1" row to the 180th row of the second part of the 6'h column in the column direction. In addition, the block interleaver 124 may write 180 bits of the 360 bits included in the bit group Y179 in the 1st row to the 180th row of the second part of the 7th column in the column direction, and may write the other 180 bits in the 1" row to the 180th row of the second part of the 8th column in the column direction.
Accordingly, the bits included in the bit group which has not been written in the first part and remains are not written in the same column in the second part and may be divided and written in the plurality of columns.

67 Hereinafter, the block interleaver 124 of FIG. 5 according to an exemplary embodiment will be explained in detail with reference to FIG. 12.
In a group-interleaved LDPC codeword (vo, v1, ..., ), Yi is continuously arranged like V={Yo, YI, = = = YN -11 -The LDPC codeword after group interleaving may be interleaved by the block interleaver 124 as shown in FIG. 12. In this case, the block interleaver 124 divide a plurality of columns into the first part(Part 1) and the second part(Part 2) based on the number of columns of the block interleaver 124 and the number of bits of bit groups. In this case, in the first part, the bits constituting the bit groups may be written in the same column, and in the second part, the bits constituting the bit groups may be written in a plurality of columns(i.e. the bits constituting the bit groups may be written in at least two columns).
Specifically, input bits vi are written serially from the first part to the second part column wise, and then read out serially from the first part to the second part row wise. That is, the data bits vi are written serially into the block interleaver column-wise starting in the first aprt and continuing column-wise finishing in the second part, and then read out serially row-wise from the first part and then row-wise from the second part. Accordingly, the bit included in the same bit group in the first part may be mapped onto a single bit of each modulation symbol.
In this case, the number of columns and the number of rows of the first part and the second part of the block interleaver 124 vary according to a modulation format and a length of the LDPC codeword as in Table 25 presented below. That is, the first part and the second part block interleaving configurations for each modulation format and code length are specified in Table 25 presented below. Herein, the number of columns of the block interleaver 124 may be equal to the number of bits constituting a modulation symbol. In addition, a sum of the number of rows of the first part, Nri and the number of rows of the second part, 1\1,2, is equal to Nidp,JNc (herein, Nc is LNgrcup /Nd X 360 the number of columns). In addition, since N11(= )is a multiple of 360, a multiple of bit groups may be written in the first part.
[Table 25]

68 Rows in Part 1 No Rows in Part 2 N r2 Modulation Columns Ne NI* =64800 Nidpc =16200 Nidpe =64800 Nidpc =16200 256-QAM 7920 1800 180 225 8 , Hereinafter, an operation of the block interleaver 124 will be explained in detail.
Specifically, as shown in FIG. 12, the input bit v, (0 i <Nc xN,) is written in r, row of ci z column of the first part of the block interleaver 124. Herein, c, and r, are ci = ---' and r,=(i [
Arri mod Nil), respectively.
In addition, the input bit vi (N õxNõ i<N,õpc) is written in ri row of ci, column of the second part of the block interleaver 124. Herein, c, and r, satisfy ci =C><
Nri )] and Nõ
r,=Nõ+{(i-Nc x No) mod Nr2} , respectively.
An output bit q;(0j<N1cipc) is read from cj column of ri row. Herein, rj and cj satisfy r.= -.L. and ci.(j mod Nc), respectively.
[
For example, when the length Map, of an LDPC codeword is 64800 and the modulation method is 256-QAM, the order of bits output from the block interleaver 124 may be (qchqi,q2,=== 0:163357,C163358,(163359,(163360,C163361, = = = ,C164799)=
070,V7920,V15840,...,V47519,V55439)V63359,V63360,V63540)-3V64799). Herein, the indexes of the right side of the foregoing equation may be specifically expressed for the eight (8) columns as 0, 7920, 15840, 23760, 31680, 39600, 47520, 55440, 1, 7921, 15841, 23761, 31681, 39601, 47521, 55441, ... , 7919, 15839, 23759, 31679, 39599, 47519, 55439, 63359, 63360, 63540, 63720, 63900, 64080, 64260, 64440, 64620, ... , 63539, 63719, 63899, 64079, 64259, 64439, 64619, 64799.
Hereinafter, the interleaving operation of the block interleaver 124 will be explained in detail.
The block interleaver 124 may interleave by writing a plurality of bit groups in each column in bit group wise in a column direction, and reading each row of the plurality of columns in

69 which the plurality of bit groups are written in bit group wise in a row direction.
In this case, the number of columns constituting the block interleaver 124 may vary according to a modulation method, and the number of rows may be the length of the LDPC
codeword/the number of columns.
For example, when the modulation method is 16-QAM, the block interleaver 124 may be formed of 4 columns. In this case, when the length Nidp, of the LDPC codeword is 16200, the number of rows is 16200 (=64800/4). In another example, when the modulation method is 64-QAM, the block interleaver 124 may be formed of 6 columns. In this case, when the length IsTidpc of the LDPC codeword is 64800, the number of rows is 10800 (-64800/6).
Hereinafter, the method for interleaving the plurality of bit groups in bit group wise by the block interleaver 124 will be explained in detail.
When the number of bit groups constituting the LDPC codeword is an integer multiple of the number of columns, the block interleaver 124 may interleave by writing the bit groups as many as the number of bit groups divided by the number of columns in each column serially in bit group wise.
For example, when the modulation method is 16-QAM and the length Mdi. of the LDPC
codeword is 64800, the block interleaver 124 may be formed of four (4) columns each including 16200 rows. In this case, since the LDPC codeword is divided into (64800/360=180) number of bit groups when the length Nidp, of the LDPC codeword is 64800, the number of bit groups (.180) of the LDPC codeword may be an integer multiple of the number of columns (=4) when the modulation method is 16-QAM. That is, no remainder is generated when the number of bit groups of the LDPC codeword is divided by the number of columns.
In this case, as shown in FIG. 13, the block interleaver 124 writes the bits included in each of the bit group Yo, bit group Y1....., bit group Y44 in the 1st row to 16200th row of the first column, writes the bits included in each of the bit group Y45, the bit group the bit group Y89 in the 1st row to 16200th row of the second column, writes the bits included in each of the bit group Y90, the bit group Y91,..., the bit group Yi34 in the 1st row to 162001h row of the third column, and writes the bits included in each of the bit group Y135, the bit group Y136,..., the bit group Y179 in the 1st row to 16200th row of the fourth column. In addition, the block interleaver 124 may read the bits written in each row of the two columns serially in the row direction.
In another, when the modulation method is 64-QAM and the length N1 of of the LDPC

70 codeword is 64800, the block interleaver 124 may be formed of six (6) columns each including 10800 rows. In this case, since the LDPC codeword is divided into (64800/360=180) number of bit groups when the length I=lidpc of the LDPC codeword is 64800, the number of bit groups (=180) of the LDPC codeword may be an integer multiple of the number of columns (.4) when the modulation method is 64-QAM. That is, no remainder is generated when the number of bit groups of the LDPC codeword is divided by the number of columns.
In this case, as shown in FIG. 14, the block interleaver 124 writes the bits included in each of the bit group Yo, bit group Y1....., bit group Y29 in the r row to 10800th row of the first column, writes the bits included in each of the bit group Y30, the bit group Y31,..., the bit group Y59 in the 1st row to 108001h row of the second column, writes the bits included in each of the bit group Y60, the bit group the bit group Y89 in the 1st row to 10800th row of the third column, writes the bits included in each of the bit group Y90, the bit group Y91,..., the bit group Y119 in the 15' row to 10800th row of the fourth column, writes the bits included in each of the bit group Y120, the bit group Y121,-=., the bit group Y149 in the 1.m row to 10800th row of the fifth column, and writes the bits included in each of the bit group Y150, the bit group Y151,..., the bit group Y179 in the lst row to 10800th row of the sixth column.. In addition, the block interleaver 124 may read the bits written in each row of the two columns serially in the row direction.
As described above, when the number of bit groups constituting the LDPC
codeword is an integer multiple of the number of columns of the block interleaver 124, the block interleaver 124 may interleave the plurality of bit groups in bit group wise, and accordingly, the bits belonging to the same bit group may be written in the same column.
As described above, the block interleaver 124 may interleave the plurality of bit groups of the LDPC codeword in the method described above with reference to FIGs. 13 and 14.
The modulator 130 maps the interleaved LDPC codeword onto a modulation symbol.

Specifically, the modulator 130 may demultiplex the interleaved LDPC codeword, modulate the demultiplexed LDPC codeword, and map the LDPC codeword onto a constellation.
In this case, the modulator 130 may generate a modulation symbol using the bits included in each of a plurality of bit groups.
In other words, as described above, the bits included in different bit groups are written in each column of the block interleaver 124, and the block interleaver 124 reads the bits written in each column in the row direction. In this case, the modulator 130 generates a modulation symbol by

71 mapping the bits read in each column onto each bit of the modulation symbol.
Accordingly, each bit of the modulation symbol belongs to a different bit group.
For example, it is assumed that the modulation symbol consists of C number of bits. In this case, the bits which are read from each row of C number of columns of the block interleaver 124 may be mapped onto each bit of the modulation symbol and thus, each bit of the modulation symbol consisting of C number of bits belong to C number of different bit groups.
Hereinbelow, the above feature will be described in greater detail.
First, the modulator 130 demultiplexes the interleaved LDPC codeword. To achieve this, the modulator 130 may include a demultiplexer (not shown) to demultiplex the interleaved LDPC
codeword.
The demultiplexer (not shown) demultiplexes the interleaved LDPC codeword.
Specifically, the demultiplexer (not shown) performs serial-to-parallel conversion with respect to the interleaved LDPC codeword, and demultiplexes the interleaved LDPC codeword into a cell having a predetermined number of bits (or a data cell).
For example, as shown in FIG. 15, the demultiplexer (not shown) receives the LDPC
codeword Q.(q0, qi, q2, ...) output from the interleaver 120, outputs the received LDPC
codeword bits to a plurality of substreams serially, converts the input LDPC
codeword bits into cells, and outputs the cells.
In this case, the bits having the same index in each of the plurality of substreams may constitute the same cell. Accordingly, the cells may be configured like (yo,o, Yi,o, = ", n1moD-1,0)=(go, qi, ChMOD-1), (y0,1, Yi,i, = = =, YliMOD-1,0( q1Mon, qnMOD+1, = = =
, Cl2x9MOD-1), = = = ==
Herein, the number of substreams, Nsubsteams, may be equal to the number of bits constituting a modulation symbol, Timm Accordingly, the number of bits constituting each cell may be equal to the number of bits constituting a modulation symbol (that is, a modulationorder).
For example, when the modulation method is 16-QAM, the number of bits constituting the modulation symbol, Timm, is 4 and thus the number of substreams, Nsubstreams, is 4, and the cells may be configured like (yo,o, Y1,0) Y2,0) Y3,0)=(:10) qi, (12, q3), Y2,1, y33).--(q4,445, q6,q7), (Y02, Y1,2, Y2,2) Y3,2)4(18, C1914410, C111)) = = = =
In another example, when the modulation method is 64-QAM, the number of bits constituting the modulation symbol, 1lmoD, is 6 and thus the number of substreams, Nsubstreains, is 6, and the cells may be configured like (yo,o, yi,o, yzo, Y3,o, Y4,o, Y5,o)=(Qo, Ql, (12, (13, (14) C15), (370,1, yi,i, y2,1, Y3,1,

72 Y4,1, Y5,1)4q6,c17, (18,c19, (310,2, Y1,2, y2,2, Y3,2, Y4,2, Y5,2)=(C112, (113)(114, q15, (116/ CI17), '= = =
The modulator 130 may map the demultiplexed LDPC codeword onto modulation symbols.
Specifically, the modulator 130 may modulate bits (that is, cells) output from the demultiplexer (not shown) in various modulation methods such as Quadrature Phase Shift Keying (QPSK), 16-QAM, 64-QAM, 256-QAM, 1024-QAM, 4096-QAM, etc. For example, when the modulation method is QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and QAM, the number of bits constituting the modulation symbol, Timm (that is, the modulation order), may be 2, 4, 6, 8, 10 and 12, respectively.
In this case, since each cell output from the demultiplexer (not shown) is formed of as many bits as the number of bits constituting the modulation symbol, the modulator 130 may generate the modulation symbol by mapping each cell output from the demultiplexer (not shown) onto a constellation point serially. Herein, the modulation symbol corresponds to a constellation point on the constellation.
However, the above-described demultiplexer (not shown) may be omitted according to circumstances. In this case, the modulator 130 may generate modulation symbols by grouping a predetermined number of bits from interleaved bits serially and mapping the predetermined number of bits onto constellation points. In this case, the modulator 130 may generate the modulation symbols by mapping rimoD number of bits onto the constellation points serially according to a modulation method.
The modulator 130 may modulate by mapping cells output from the demultiplexer (not shown) onto constellation points in a non-uniform constellation (NUC) method.
In the non-uniform constellation method, once a constellation point of the first quadrant is defined, constellation points in the other three quadrants may be determined as follows. For example, when a set of constellation points defined for the first quadrant is X, the set becomes ¨
conj(X) in the case of the second quadrant, becomes conj(X) in the case of the third quadrant, and becomes ¨(X) in the case of the fourth quadrant.
That is, once the first quadrant is defined, the other quadrants may be expressed as follows:
1 Quarter (first quadrant)=X
2 Quarter (second quadrant)=-conj(X) =
3 Quarter (third quadrant)=conj(X) 4 Quarter (fourth quadrant)=-X
Specifically, when the non-uniform M-QAM is used, M number of constellation points may

73 be defined as z={zo, z1, zm_i}. In this case, when the constellation points existing in the first quadrant are defined as {xo, xi, x2, ..., xm/4.1}, z may be defined as follows:
from zo to zw44=from Xo to Xm/4 from zfris to z22m/4.4.-conj(from x0 to xm/4) from Z2xmi4 to z3.14/4-1=conj(from x0 to xmf4) from Z3,,m/4 to Z4õw4_1=-(fr0111 5E0 to xmg) Accordingly, the modulator 130 may map the bits [yo, ym_i] output from the demultiplexer (not shown) onto constellation points in the non-uniform constellation method by mapping the output bits onto zt, having an index of L = E (y x 2m1). An example of the constellation i.0 defined according to the non-uniform constellation method may be expressed as in tables 26 to 30 presented below when the code rate is 5/15, 7/15, 9/15, 11/15, 13/15:
[Table 26]
Input data cell y Constellation point z.
(00) (1+10/.K
(01) (1-11)/K
(10) (-1+11)/K
(11) [Table 27]
, t= tist4., Oa: ,OAS nsflitofts- 14*S R1fiS myis =
085304020131, L211100.50261 =84055Øb751 08909.1.20071 0217540.415191 0.951140.45471. 11259440,21541 0.4517+055111 *I =
.8.1662+Cul5101 0.501401.21011= 0E2515+0411S 1,100740.49011 0.08,78Ø1sni.
9.184740.211041 0.154540.29441 -0.951444130611, .2 5.2002.00,5115i.., 08684+6.26,24i= 1.10.8.0815111 11.2476441_41811, .11.412641.54451 lis2t4p.sttat 0.294841.55401 0.50674Ø45241 05115.1.401150.28241Ø66171 4184514L211611 Ai.66.14i24711 1,20811+088521 1290040.7921 imiUthica54o1 A53951.0,34671 [Table 28]
= Shape ROMA, ,11611J913 , _1111141_11/15 RIRLIAS
RS1_20,115 R(14_11115 R04,17,13' ,J154._13/13 _ to 0.43104.163231, 43132+0,611181; '1002411.232.0i. 033117411.111491r, 10130000.267111" .1,1331741:61/01 1;0164+03,39-41- 4.41115411.74734.
210.0A3871,. 0:79774111.65241 1:3561+Ã1.04111 _0.1511411.85421., 12191+0J1113.
a.isseklisu .0:701+4416.231 :0.1.34,.0:53054 .2- . 4.1050.1.80.11. 0.14114.90201=
'1.021140,23.140. 41.156146.21.11.= 5.1.0048.2210.= . 059294084121,.
,1.0474441.1695t, 81125441.0246.
00' = totaviOnlr =
4310041h3o331- v.:FM.1E21o2a 413300.2750e , .ostiar4e245r.' '0,15LS03.1.172.1,.. 072434015944.= '0.1230.1.10051 0.8 474140.1182451'. = 0.1420.1802,71 0,6175.082101.
0.2100+1.40561 -8,5012=041441 1,00134084001 '041215=0.40171.
6.2119Ø731111 )0.0172,420141, 0.0410.1.23611. 0.728240.17561E-0.021,201.12710 ;.!:6118Ø243511. =11.709146.107W Ø586848.15610 =
= ke asaroo,s=po toszt=oarno =
tnimo.,saii) cose40.1.7961. :82009+1.0819P 0339740.3401r -14261.40.25461.' 0.619740.11,015.
8262040.7540 0542040,19,1dt= ,03102.40,001st. 441025.40.12361-485.2"044.081210- 0,3060Ø880.5 11,0164nant :0-.1694Ø3.30 - 0c7111.114.201.91 0.3211.11,1192,71 õAL3M/HAM1ê , 8.5609404B641 A11s4e_un4 .080044405020.,. 0.1002+41:41781 0.726140 MOM
0,9131+0.4021: 0.25524282941 0.9.21+0,1114.1.
0.118041.02774: 11.3925111.1511111. 11.113111.22531 124319:40.42031 :L11.5+ 0.54153 00, ' 0.7540.4.26531 03130n.2601 . *011711 .0-11199i1 253 31 03441+4085591, '0.1544408714r.; 85.407.40.133M
easar.41.27330.
ulli = 04145048.12404: 0.2922+280945 0.0125+035631 Ø101845.461.11., .850584049105' '0.51129.1-3051.. 11.416540.11001._ 0.5507.1.1701f 0.261540a4701.. 4.0905+051199. :144754030456 01650.0,61311 0,1116441167er.
0.01.190450751 8.15110+0-70579 ,052115+081400-wW _ .030114442675r.. ,1019740,21511:. .0,169140.20201 2418241221011 0,1512Ø33/55=" = L784.040.511264 .0107140M951 H1.21814014361.. 0,1356,49.74001, 5.22194082601. .0101241.01101 =
'0.9916Ø1710i ms. ,a,vemeuster ...1.8/01.340.7.9221= .8.016140,01164 -5.466140.20115 catrpastoor L301.441.io3av o.2207#1:39241. . 1.341240.14448 [Table 29]

74 wshape wuc_sa fl3 ix gs 10&84_11/13 MIXJ4 sAs 202_68_11125 MC 14 UAS NUC 64-131 0.438746022 033424160281 . 1.4827+0.24201 03547+031481 1.4.24441.28710 03317+0.6970 1.02540153941 418224 137/51 11 16(123+0.41871 4120774.65811 1.2563.4114111 0.15814,681111 12150421331 0139603.88241 AnSswIssai 1.1184 4. 0.84621 =
118751+108811 91711430281 2.021140.21741 0.15674027491 1.03864022191 0.1323444371 104744026951 03113.1.38431 43 ^ = 111511140.87531 0255643039 0.8792+057021 0.1336427001, 0.8494461451 020/5413721 0,724340.19341 03635 + 0.77071 44 002+03219 0.60024.33451 02920+148271 0.617740.40301 _02931+1.46561 0.562240.4500 1069340.94411 1.113640.3661i 4 0.201410.78181 , 0.6577420841 , 0.8410425631 0326240.17581 03230+1.2279 0.67394.14351 0.703240.80.731 1.0095 0.48823 4 . 0.10494 8441 03021417111 0.71744192111 035684.17561, 0.206941.06491 0.3597+0.14011 1.426140.22164 0.2101 40.24921 17 0.213341.75401 _0302.100_15561 '0.52312.43.87934 0377140.11161 036774029711 036604.11044 0.61064.17831 03482 0.4477i =
0.78184020191 03556=039221- 030404024751 0.563940.88643 0.411940.11771 0.6004402923 0139240.4078/ 0.15244439431 4 032120022011 0352431901 0.10264035911 0.1980+1.02771 0.39984.25161 0.212043252 042624042051 0.1482 0.68771 40 _0.754426553 a8450.1.26191 0.689540.18711 0.11199.113153 0.7442.44991 0.9594+1.07241 014074011361 04692 4. 1.09931 41 03454430491 412922.132943,0862640.35131 0.28544.46911 .03954+043281.
0.58294139951 0.42040.13881 0.4492Ø73531 42 0.23754.24791 02939455491 01475403314 13.14544605111 0116640.16781 0.243944151781 0.1.38340.73571 0.1519+0.13191 L.413 0247940.26751 1.019740.23591 0.1691430221 1.0311240.21411 0.1582+031231 03780Ø19591 0.4197472061 0.146840.40251 NIA 026931027011 1-2626484571 0187140.62551 . 1.236240.114161 0.1355474024 1.22394.67601 016824103161 04763 034071 KIS 0.27014.2841 3.48944029221 0359540.61261 1486300.29731 0.3227+0.62001 1.365344123231 µ_ 0.2287+1.39141 0.4411 + 0.426T1 [Table 30]
=

75 /Shape ++6/15 47/15 113115 89/15 1110/15 011/15 412/15 80 0.68004.69261 1.2905+1.30991 1.01044.37881 1.323141.15061 1.60974.15481 0.310540.33121 1.101441.16701 0.355640.31971 ' 81 0.3911+1.36451 105044.95771 104/0447.98621 0.91514113111 1.55496146051 0.434.1.413601 0.165741.24211 0.367940.4601 .2 0.21914.7529 1.53214019351 1.640440.74281 1.143940.89741 1.32264.12901 0.314940.49291 1.29574.80391 0.50494035711 .3 0.217441.42081 , /157740.11161 1324540.94141 0.334340.92711 1.27724.38291 0.440040.48071 1.0881+0.89561 0.505640.50631 0.1165841.24871 1.788140.25091 0.719841.24271 1.53984.79611 1.2753+1.02421 0181140.33751 0.5795+1.2110 0.21134034971 0.7275+116671 1,42754.14001 2.81066.00401 630914.55991 1.44344.75401 0.063340.34041_ 0.663741.42151 0.211640.49001 0.87474104701 1.478440.52011 01595+1.03171 1.212140.65741 1.049140.84761 0.18184.48511 0.693041.00811 0.07136114191 87 0.793011.04061 1.34084.4340 0.61184067211 . 0.95796263731 1.1361+0.62531 0.063140.48151 0,811494.96471 0.049040.49601 99 0.209610.97681 0.70374.58871 1676240.20011 0.774641.58671 0.932640.09701 0308440.19711 1.10634.51151 0.35276220861 89 0.2241+1.04541 0.925040.64551 06997411441 0.187641.24291 0.89124.28041 0.435640.19931 1.0E0594.49521 0.34971007131 810 0.185840.96781 0.825640.56011 1.42/210.47691 0.59924.91091 1.1044411021 0.309140.06761 1.41714.59011 0.4997421131 all 0.1901410659 0.177140.61101 1.147940.63121 0.67994.97431 1.064863.32671 0.434140.06911 1.046040.6939 0.497440 06921 212 055474093121 1.008040.18431 040794.65661 0.5836438791 0.732540.60711 0.17756119851 0.663940.62161 0.20864010791 013 0.64794016511 1.075940.17211 0.7284+0.69571 0.69154.57661 0.126040.45591 006404019781 0.13534.58511 0.20944001901 814 0.60734091821 1.009 6Ø27311 0.57244.70311 0.5251.4.705/1 0.874440.7131 0.177540.04761 0.687967.80221 0.067640.20791 *15 0.59554094201 1.066240.29641 0.630263.12591 0.686840.67931 0.9882413001 0.064740.06691 0.163440.78221 0.0698/0.06831 .16 1.40704017914 0.2334+1.55541 0.1457+1.40101 1.61164.14971 0.18464.54071 0.7455Ø34111 0.121341.43661 0.358640.79591 .17 1.72274029001 0.816541.10921 0.1886+113461 0.951140.11401 0.4867+157431 0.581140.33961 0.1077+120981 0.3571+0.63921 .1.8 1.32464025621 0.60914.27291 0.117441.10351 1.2970412341 0.136341.35791 0.755640.46691 0.065140.98011 0.50344010711 1+19 1.36364036541 0.672841.14561 0.1095+1.01321 1.02664011911 0.4023+1.30761 0.51626147561 0.100941.01151 010634.66001 a20 1.37064121341 0.306141.74691 0.4197+1.36361 1.58914.44961 1054241.25841 0.95564.32301 0.3764+1.42641 0.2141418611 811 1.61014.14031 0.132741.40561 0.585341.68201 0.932/14.15861 0.7875+144301 /.176740.30911 0.3237+1.2130 0.210940.63401 42 1.16144.79091 0.35224.34141 0.3439+1.06891 1.279640.31941 0.168741.04071 0.937340.47201 0.520540.98141 0.071340.80931 41 1.224140.73671 0.2273+1.30811 0.323440.99621 1.01814.34471 0.65024.11511 1.205140.51351 0.3615+1.01631 0.069640.64671 a24 0.976940.18631 0.50974.80981 0.109210.61741 0.594140.10591 0.0932+697451 0.736740.20151 0.071540.65961 01719+1.08621 125 0.9451+0.20571 0.552840.83471 0.107440.63071 0.71154.11001 0.284240.93441 0.5811410151 0.21164.65571 0190641/7551 .26 1.010040.11821 0.48434..14861 0.110940.69961 0.58634.1139 011424114481 0.73164.06691 0.07294.81311 0.43214019041 517 0.97954014171 0.53044.87591 0.10764.73451 0.690940.1/661 0.3385+1.09731 0578240.06691 0.21584.82461 0.4551+1.18121 a21 0.1241404159 0.17154.91471 0.329140.62641 0.5843+0.36041 0.6062+0.74651 0.906240.19711 0.50364.64671 0.230940.94141 .29 0123240.4136 0.15404.95101 0.312640.63731 0.89704.35921 17.460740.115381 1.282940.11851 0.3576417.65721 0.107741.31911 130 057994033911 0.19644.94381 03392/0.69991 0.580810.31501 0.72634.17641 0.9156+0.07351 0.51156180861 007714018521 031 017964033561 0.178840.98321 0320210.72621 166764.32941 0145041.170671 1.101140.07351 0.35934,82451 0.090241.17531 432 0,13764033431 0.375240.16671 0.965140.10661 0.140641.61821 0265540.07461 0.324440.10441 1.254540.10101 0.81014031271 .33 0138340.31921 0.37344.16671 0.907540.16611 0.117241.29341 0.26644.07591 0.4389412181 1.067640.09561 012564032561 .34 0.13634.3322/ 0.3758416611 0.972440.11711 0.22114.96411 0.45724).a3521 0.3207464151 1.471240.1167/ 0.659340.39681 835 0.137040.32731 0374640.16491 0.918640.17911 0.1220+1.03931 0.451640.10611 0.450940.63711 0.899110.08821 0.662340.51821 .36 0.165500.32651 0.40134.12301 0134210.13721 0.112440.61011 0.255940.17901 0.192040.11961 0.551840.0690 1.018640.36451 837 0.1656432271 0.400140.11301 0.655040.14951 0.1177460411 0.258640.17721 0.063340.81671 0.690340.05521 1.00014.52421 238 0.1634/0.31461 0.4037+0.12301 0.629040.13931 1113640.74551 03592428111 019114.63711 0.57424.19971 1.19670.27251 .39 4 0.163640.12081 0.40194.12161 0.649440.15041 0.1115+0.71601 0.31211426541 0.064010.64151 0.73744.15641 1.392840.34081 .40 0.177940.63411 0.602540.39141 1.312740.12401 0.432441.56791 0.770640.09221 0.3331+1.06691 1.2378Ø30491 0.801140.22271 x41. 0.182840.68451 0.59464.392131 0957240.43441 0.3984+1.28151 0.740740.22601 0.465541.00871 1.051160.30321 0.798140.07351 942 0.174540.1129 0.61164.38791 1.24030.26311 0.376440.95341 0.61801009171 0.3433+1.215651 1.45844035111 0.645940.21981 843 0.179340.68291 0.60194.38371 1.025440.41301 0.36684.03011 0.60194.16581 0.500441.60621 0.91074.24031 0 643540.07131 x44 0.354740.60091 0.737767.16181 0.609640.42141 0.36674.59951 0600740 49101 01971+1.00511 0.632/40.47291 094610.13051 145 0.359340.60111 0.729840.151121 0.677340.41841 0.3312401960 0.667340.39281 0.073541.02911 0.71104.43921 0.961540.07351 046 0.35764069901 0.72744.17321 0399540.41021 0.36874.71941 0.47864039351 0.1498+1.50181 0.6045+0.32741 1332740.10391 *07 0.362440.59941 0.71654.17461 0053110.41011 0.337340.69641 0317640.33911 0.046541.25531 0.7629019651 1.135910.08091 .411 026974.14431 0.15094.24251 0.125042.11531 0.106500.11461 0.07574.10031 03011400801 0.059600.07391 0.63020017091 849 0.270440.14331 0.1503424001 0.125340.11531 0.114540.1109 0.07534.10041 0.61674.91531 017674.07311 0114540.69341 250 0.384440.14421 0.1515+0.24371 0.124540.11521 0.105344112741 0.077740.47681 0.76364.62551 0.0612+0.21981 0.66434064841 x51 0.265040.14321 0.150310.24251 0.124740.11561 0.113440.1138 0.086740.47541 060004.63271 13.111154.21921 066004.67361 652 0.276340.163/2 0.121540.23881 0376640.11441 0.11114.38211 01013422431 0.98984.76801 04218+0.07151 1./61240.69421 x53 0276840.16261 0.127940.24191 0.370740.12371 0.11164.38671 0.101040.22421 1.585540.14951 0197640.07251 0.97054.69421 .54 0.271500.16301 0.127900.24311 0.377900.12601 0.10804.34311 019504039191 0.947667.41751 0433740.21151 1169840.62591 x55 0.271940.16111 0.12796124061 0.371740.12521 0.1177+0.3459 0.18814019691 1.46264.40151 0.305740.21671 1.2183+0.42411 456 0.648840.16961 0.33944037641 0.116140.36931 0,36444.1030 0.093010.81221 0.827641.02251 0.066710.51241 0.7989+1.04981 657 0.6462017061 0.33644.57221 0.115740.36451 0.326200.1104 022154.71401 0.631341.03641 0.200840.50951 0.43954142031 x58 0.64544017451 033284.57511 0./17640.34631 0.363140.11731 0.09371065141 0.281541.28651 0.06254036581 0.61114.02461 859 0.643140.17531 0.33034036981 0.117140.14241 032194.11961 0.15404.61661 0.634241.2709 0.1999+0.36421 0.630241.2411.1 x60 0385440.31261 0.149140.63161 0353040.38991 0.366540.37511 0.4810463061 1.042240.95931 0.4816+0.49461 1.055040.89241 .61 061624.31671 0.14614.62801 034224018061 0.331040.37951 0.385640.70371 117494.85391 0,33E6060501 0.36126.28001 002 0586400.31751 0.15094.62801 036146137551 5.367240.33531 0.35274.52301 1.1551+1.18471 0,457110.34991 1.269640.89691 .113 0.59734032541 0.147340.61151 0.35094016561 0.33364.34011 0.3103455591 1.477/10.67121 0.331640.35091 1.0342+1.11811 Table 26 indicates non-uniform QPSK, table 27 indicates non-uniform 16-QAM, Tables 28

76 and 29 indicate non-uniform 64-QAM, and table 30 indicates non-uniform 256-QAM.
Referring to these tables, the constellation point of the first quadrant may be defined with reference to tables 26 to 30, and the constellation points in the other three quadrants may be defined in the above-described method.
However, this is merely an example and the modulator 130 may map the output bits outputted from the demultiplexer (not shown) onto the constellation points in various methods.
The interleaving is performed in the above-described method for the following reasons.
Specifically, when the LDPC codeword bits are mapped onto the modulation symbol, the bits may have different reliability (that is, receiving performance or receiving probability) according to where the bits are mapped onto in the modulation symbol. The LDPC codeword bits may have different codeword characteristics according to the configuration of a parity check matrix. That is, the LDPC codeword bits may have different codeword characteristics according to the number of 1 existing in the column of the parity check matrix, that is, the column degree.
Accordingly, the interleaver 120 may interleave to map the LDPC codeword bits having a specific codeword characteristic onto specific bits in the modulation symbol by considering both the codeword characteristics of the LDPC codeword bits and the reliability of the bits constituting the modulation symbol.
For example, when the LDPC codeword formed of bit groups Xe to X179 is group-interleaved based on Equation 21 and Table 11, the group interleaver 122 may output the bit groups in the order of X55, X146, X83, = = =, X132, X135.
In this case, when the modulation method is 16-QAM, the number of columns of the block interleaver 124 is four (4) and each column may be formed of 16200 rows.
Accordingly, from among the 180 groups constituting the LDPC codeword, 45 bit groups (X55, X1.46, )C53, X52, X62, X176, X160, X68, X53, X56, X81, X97, X79, X113, X163, X61, X58, X69, X133, X108, X66, X71, X86, X144, X57, X67, X116; X59, X70, X156, X172/ X65, X149, X155, X82/ X138/ X136, X141/
X1, X9, X170, X90, X140/ X64, X159) may be inputted to the first column of the block interleaver 124, 45 bit groups (X1.5, X14, X37, X54/ X44, X63, X43, X18, X47, X7, X25, X34, X29, X30, X26, X39/
X16, X41, X45, X36, X0, X23, X32, X28, X27, X38, X48, X33, X22, X49, X51, X60, X46, X21, X4, X3, X20, X13, X50, X35, X24, X4(J, X17, X42, X6) may be inputted to the second column of the block interleaver 124, 45 bit groups (X112, _93X , X -127, X101, X94, X115/ X105, X31, X19/ X177/ X74, X10/ X145, X162, X102, X120, X12,6, X95, X73, X152, X129, X174, X125, X72, X128, X78, X171, X8, X142, X178, X154,

77 X85, X107, X75) X121 X9, X151/ X77, X117, X109, X80, X106, X134, X98, Xi) may be inputted to the third column of the block interleaver 124, and 45 bit groups (X122, X173, X161, X150, X110, X175, X166, X131, X119, X103, X139, X148, X157, X114, X147, X87, X158, X121, X164, X104, X89, X179, X123, X118, X99, X88, X11, X92, X165, X84, X168, X124, X169/ X2, X130, X167, X153, X137, X143, X91, X100, X5, X761 X132, X135) may be inputted to the fourth column of the block interleaver 124.
In addition, the block interleaver 124 may output the bits inputted to the 1st row to the last row of each column serially, and the bits outputted from the block interleaver 124 may be inputted to the modulator 130 serially. In this case, the demultiplexer (not shown) may be omitted or the bits may be outputted serially without changing the order of bits inputted to the demultiplexer (not shown). Accordingly, the bits included in each of the bit groups X55, X15, X112, and X1n may constitute the modulation symbol.
When the modulation method is 64-QAM, the number of columns of the block interleaver 124 is six (6) and each column may be formed of 10800 rows.
Accordingly, from among the 180 groups constituting the LDPC codeword, 30 bit groups (X55, X146, X83, X52, X62, X176, X160, X68, X53, X56, X81, X97, X79, X113, X163, X61, X58, X69, X133, X108, X66, X71, X86) X144) X571 X67) X116) X59, X70, X156) may be inputted to the first column of the block interleaver 124, 30 bit groups (X172, X65, X149, X155, X82, X138, X136, X141, X111, X96, X170, X90, X140, X64, X159, X15, X14, X37, X54, X44, )(63, X43, X18, X47, X7, X25, X34, X29, X30, X26) may be inputted to the second column of the block interleaver 124, 30 bit groups (X39, X16, X41, X45, X36, XO, X23; X32, X28, X27, X38, X48, X33, X22, X49, X51, X60, X46, X21, X4, X3, X20, X13, X50, X35, X24, X40, X17, X42, X6) may be inputted to the third column of the block interleaver 124, 30 bit groups (X112, X93, X127, X101, X94, X115, X105, X31, X19, X177, X74, X10, X145, X162, X102, X120, X126, X95, X73, X152, X129, X174; X125, X72, X128, X78, X171, X8, X142, X178) may be inputted to the fourth column of the block interleaver 124, 30 bit groups (X154, X85, X107, X75, X12, X9, X151, X77, X117, X109, )(80, X106, X134, X98, Xi, X122, X173, X161, X150, X110, X175, X166, X131, X119, X103, X139, X148, X157, X114, X147) may be inputted to the fifth column of the block interleaver 124, and 30 bit groups (X87, X158, X121, X164, X104, X89, X1795 X1235 X118, X99, X88, X11, X92, X165, X84, X168, X124, X169, X2, X130, X167, X153, X137, X143, X91, X100) X5, X76, X132, X135) may be inputted to the sixth column of the block interleaver 124.
In addition, the block interleaver 124 may output the bits inputted to the 1st row to the last row of each column serially, and the bits outputted from the block interleaver 124 may be

78 inputted to the modulator 130 serially. In this case, the demultiplexer (not shown) may be omitted or the bits may be outputted serially without changing the order of bits inputted to the demultiplexer (not shown). Accordingly, the bits included in each of the bit groups X55, X172, X39, X112, X154 ,and X87 may constitute the modulation symbol.
As described above, since a specific bit is mapped onto a specific bit in a modulation symbol through interleaving, a receiver side can achieve high receiving performance and high decoding performance.
That is, when LDPC codeword bits of high decoding performance are mapped onto high reliability bits from among bits of each modulation symbol, the receiver side may show high decoding performance, but there is a problem that the LDPC codeword bits of the high decoding performance may not be received. In addition, when the LDPC codeword bits of high decoding performance are mapped onto low reliability bits from among the bits of the modulation symbol, initial receiving performance is excellent, and thus, overall performance is also excellent.
However, when many bits showing poor decoding performance are received, error propagation may occur.
Accordingly, when LDPC codeword bits are mapped onto modulation symbols, an LDPC
codeword bit having a specific codeword characteristic is mapped onto a specific bit of a modulation symbol by considering both codeword characteristics of the LDPC
codeword bits and reliability of the bits of the modulation symbol, and is transmitted to the receiver side.
Accordingly, the receiver side can achieve high receiving performance and decoding performance.
Hereinafter, a method for determining n(j), which is a parameter used for group interleaving, according to various exemplary embodiments, will be explained.
According to an exemplary embodiment, when the length of the LDPC codeword is 64800, the size of the bit group is determined to be 360 and thus 180 bit groups exist. In addition, there may be 180! possible interleaving patterns (Herein, factorial means A!=Ax(A-1) x ...x2x1) regarding an integer A.
In this case, since a reliability level between the bits constituting a modulation symbol may be the same according to a modulationorder, many number of interleaving patterns may be regarded as the same interleaving operation when theoretical performance is considered.
For example, when an MSB bit of the X-axis (or rear part-axis) and an MSB bit the Y-axis(or imaginary part-

79 axis) of a certain modulation symbol have the same theoretical reliability, the same theoretical performance can be achieved regardless of the way how specific bits are interleaved to be mapped onto the two MSB bits.
However, such a theoretical prediction may become incorrect as a real channel environment is established. For example, in the case of the QPSK modulation method, two bits of a symbol in a part of a symmetric channel like an additive white Gaussian noise (AWGN) channel theoretically have the same reliability. Therefore, there should be no difference in the performance theoretically when any interleaving method is used. However, in a real channel environment, the performance may be different depending on the interleaving method. In the case of a well-known Rayleigh channel which is not a real channel, the performance of QPSK greatly depends on the interleaving method and thus the performance can be predicted somewhat only by the reliability between bits of a symbol according to a modulation method. However, there should be a limit to predicting the performance.
In addition, since code performance by interleaving may be greatly changed according to a channel which evaluates performance, channels should be always considered to drive an interleaving pattern. For example, a good interleaving pattern in the AWGN
channel may be not good in the Rayleigh channel. If a channel environment where a given system is used is closer to the Rayleigh channel, an interleaving pattern which is better in the Rayleigh channel than in the AWGN channel may be selected.
As such, not only a specific channel environment but also various channel environments considered in a system should be considered in order to derive a good interleaving pattern. In addition, since there is a limit to predicting real performance only by theoretical performance prediction, the performance should be evaluated by directly conducting computation experiments and then the interleaving pattern should be finally determined.
However, since there are so many number of possible interleaving patterns to be applied (for example, 180!), reducing the number of interleaving patterns used to predict and test performance is an important factor in designing a high performance interleaver.
Therefore, the interleaver is designed through the following steps according to an exemplary embodiment.
1) Channels C1, C2, Ck to be considered by a system are determined.
2) A certain interleaver pattern is generated.

80 3) A theoretical performance value is predicted by applying the interleaver generated in step 2) to each of the channels determined in step 1). There are various methods for predicting a theoretical performance value, but a well-known noise threshold determining method like density evolution analysis is used according to an exemplary embodiment. The noise threshold recited herein refers to a value that can be expressed by a minimum necessary signal-to-noise ratio (SNR) capable of error-free transmission on the assumption that a cycle-free characteristic is satisfied when the length of a code is infinite and the code is expressed by the Tanner graph. The density evolution analysis may be implemented in various ways, but is not the subject matter of the inventive concept and thus a detailed description thereof is omitted.
4) When noise thresholds for the channels are expressed as THIN, TH2[i], THk[i] for the i-th generated interleaver, a final determination threshold value may be defined as follows:
TH[i]=WixTHi [i]+W2xTH2N+ +WkxTHk[i], where W1+W2+ .. = +Wk=1,W1,W2, = = = 3 Wk> 0 Here, W1, W2, ..., Wk are adjusted according to importance of the channels.
That is, W1, W2, Wk are adjusted to a larger value in a more important channel and Wi, W2, Wk are adjusted to a smaller value in a less important channel (for example, if the weight values of AWGN and Rayleigh channels are W1 and W2, respectively, Wi may be set to 0.25 and W2 may be set to 0.75 when one of the channels is determined to be more important.).
5) B number of interleaver patterns are selected in an ascending order of TH[i] values from among the tested interleaver patterns and are directly tested by conducting performance computation experiments. An PER level for the test is determined as 10" ¨3 (for example, B=100).
6) D number of best interleaver patterns are selected from among the B number of interleaver patterns tested in step 5) (for example, D=5).
In general, an interleaver pattern which has a great SNR gain in the area of FER=10" ¨3 may be selected as a good performance interleaver in step of 5). However, according to an exemplary embodiment, as shown in FIG. 16, performance of FER required in the system based on the result of real computation experiments for the area of FER=10" ¨3 may be predicted through extrapolation, and then an interleaver pattern having good performance in comparison with the expected performance in the PER required in the system may be determined as a good interleaver pattern. According to an exemplary embodiment, the extrapolation based on a linear

81 function may be applied. However, various extrapolation methods may be applied. FIG. 16 illustrates an example of performance extrapolation predicted by the result of computation experiments.
7) The D number of interleaver patterns selected in step 6) are tested by conducting performance computation experiments in each channel. Herein, the PER level for testing is selected as PER required in the system (for example, FER=10^ ¨6 ) 8) When an error floor is not observed after the computation experiments, an interleaving pattern having the greatest SNR gain is determined as a final interleaving pattern.
FIG. 17 is a view schematically showing a process of determining B number of interleaver patterns in the steps 2), 3), 4), and 5) of the above-described method for determining the interleaving pattern in the case of AWGN and Rayleigh channels for example.
Referring to FIG. 17, necessary variables i, j, and etc. are initialized in operation S1701, and a noise threshold for the AWGN channel THIN and a noise threshold for the Rayleigh channel TH2[i] are calculated in operation S1702. Then, a final determination noise threshold TH[i]
defined in step 4) is calculated in operation S1703, and is compared with a previously calculated final determination noise threshold TH[i-1J in operation S1704. When the final determination noise threshold TH[i] is smaller than the previously calculated final determination noise threshold TH[i-1], TH_S[i] is replaced with the TH[i] and is sotred in operation S1706. Next, i, j values increase by 1 in operation S1707 and this process is repeated until the i value exceeds A
which is pre-defined in operation S1708. In this case, A is the total number of interleaver patterns to be tested in steps 2), 3), 4), and 5) and A is typically determined to be greater than or equal to 10000. When all operations described above are completed, interleaver patterns corresponding to TH_S[0], TH_S[1], TH_S[B-1]
which are stored in a descending order of final noise thresholds values in operation S1709.
The transmitting apparatus 100 may transmit the signal mapped onto the constellation to a receiving apparatus (for example, 1200 of FIG. 18). For example, the transmitting apparatus 100 may map the signal mapped onto the constellation onto an Orthogonal Frequency Division Multiplexing (OFDM) frame using OFDM, and may transmit the signal to the receiving apparatus 1200 through an allocated channel.
FIG. 18 is a block diagram to illustrate a configuration of a receiving apparatus according to an exemplary embodiment. Referring to FIG. 18, the receiving apparatus 1200 includes a

82 demodulator 1210, a multiplexer 1220, a deinterleaver 1230 and a decoder 1240.
The demodulator 1210 receives and demodulates a signal transmitted from the transmitting apparatus 100. Specifically, the demodulator 1210 generates a value corresponding to an LDPC
codeword by demodulating the received signal, and outputs the value to the multiplexer 1220. In this case, the demodulator 1210 may use a demodulation method corresponding to a modulation method used in the transmitting apparatus 100. To do so, the transmitting apparatus 100 may transmit information regarding the modulation method to the receiving apparatus 1200, or the transmitting apparatus 100 may perform modulation using a pre-defined modulation method between the transmitting apparatus 100 and the receiving apparatus 1200.
The value corresponding to the LDPC codeword may be expressed as a channel value for the received signal. There are various methods for determining the channel value, and for example, a method for determining a Log Likelihood Ratio (LLR) value may be the method for determining the channel value.
The LLR value is a log value for a ratio of the probability that a bit transmitted from the transmitting apparatus 100 is 0 and the probability that the bit is 1. In addition, the LLR value may be a bit value which is determined by a hard decision, or may be a representative value which is determined according to a section to which the probability that the bit transmitted from the transmitting apparatus 100 is 0 or 1 belongs.
The multiplexer 1220 multiplexes the output value of the demodulator 1210 and outputs the value to the deinterleaver 1230.
Specifically, the multiplexer 1220 is an element corresponding to a demultiplexer (not shown) provided in the transmitting apparatus 100, and performs an operation corresponding to the demultiplexer (not shown). That is, the multiplexer 1220 performs an inverse operation of the operation of the demultiplexer (not shown), and performs cell-to-bit conversion with respect to the output value of the demodulator 1210 and outputs the LLR value in the unit of bit. However, when the demultiplexer (not shown) is omitted from the transmitting apparatus 100, the multiplexer 1220 may be omitted from the receiving apparatus 1200.
The information regarding whether the demultiplexing operation is performed or not may be provided by the transmitting apparatus 100, or may be pre-defined between the transmitting apparatus 100 and the receiving apparatus 1200.
The deinterleaver 1230 deinterleaves the output value of the multiplexer 1220 and outputs the

83 values to the decoder 1240.
Specifically, the deinterleaver 1230 is an element corresponding to the interleaver 120 of the transmitting apparatus 100 and performs an operation corresponding to the interleaver 120. That is, the deinterleaver 1230 deinterleaves the LLR value by performing the interleaving operation of the interleaver 120 inversely.
To do so, the deinterleaver 1230 may include a block deinterleaver 1231, a group twist deinterleaver 1232, a group deinterleaver 1233, and a parity deinterleaver 1234 as shown in FIG.
18.
The block deinterleaver 1231 deinterleaves the output of the multiplexer 1220 and outputs the value to the group twist deinterleaver 1232.
Specifically, the block deinterleaver 1231 is an element corresponding to the block interleaver 124 provided in the transmitting apparatus 100 and performs the interleaving operation of the block interleaver 124 inversely.
That is, the block deinterleaver 1231 deinterleaves by writing the LLR value output from the multiplexer 1220 in each row in the row direction and reading each column of the plurality of rows in which the LLR value is written in the column direction by using at least one row formed of the plurality of columns.
In this case, when the block interleaver 124 interleaves by dividing the column into two parts, the block deinterleaver 1231 may deinterleave by dividing the row into two parts.
In addition, when the block interleaver 124 writes and reads in and from the bit group that does not belong to the first part in the row direction, the block deinterleaver 1231 may deinterleave by writing and reading values corresponding to the group that does not belong to the first part in the row direction.
Hereinafter, the block deinterleaver 1231 will be explained with reference to FIG. 20.
However, this is merely an example and the block deinterleaver 1231 may be implemented in other methods.
An input LLR NT; (0<i<N1dpc) is written in a ri row and a ci column of the block deinterleaver 1231. Herein, ci=0 mod NO and r = ¨ ,i [
On the other hand, an output LLR ci,(0i<Islex Mn) is read from a ci column and a ri row of the

84 i first part of the block deinterleaver 1231. Herein, cg = ¨ , ri.(i mod Nil).
[
Nrl In addition, an output LLR qi(Ncx Nrii<Nidpc) is read from a c, column and a ri row of the 0 ¨ NcxNri)]
second part. Herein, c . [; , ri=1=1,1+{(i-Nex Nri) mode Na}.
Nr2 The group twist deinterleaver 1232 deinterleaves the output value of the block deinterleaver 1231 and outputs the value to the group deinterleaver 1233.
Specifically, the group twist deinterleaver 1232 is an element corresponding to the group twist interleaver 123 provided in the transmitting apparatus 100, and may perform the interleaving operation of the group twist interleaver 123 inversely.
That is, the group twist deinterleaver 1232 may rearrange the LLR values of the same bit group by changing the order of the LLR values existing in the same bit group.
When the group twist operation is not performed in the transmitting apparatus 100, the group twist deinterleaver 1232 may be omitted.
The group deinterleaver 1233 (or the group-wise deinterleaver) deinterleaves the output value of the group twist deinterleaver 1232 and outputs the value to the parity deinterleaver 1234.
Specifically, the group deinterleaver 1233 is an element corresponding to the group interleaver 122 provided in the transmitting apparatus 100 and may perform the interleaving operation of the group interleaver 122 inversely.
That is, the group deinterleaver 1233 may rearrange the order of the plurality of bit groups in bit group wise. In this case, the group deinterleaver 1233 may rearrange the order of the plurality of bit groups in bit group wise by applying the interleaving method of Tables 11 to 22 inversely according to a length of the LDPC codeword, a modulation method and a code rate.
The parity deinterleaver 1234 performs parity deinterleaving with respect to the output value of the group deinterleaver 1233 and outputs the value to the decoder 1240.
Specifically, the parity deinterleaver 1234 is an element corresponding to the parity interleaver 121 provided in the transmitting apparatus 100 and may perform the interleaving operation of the parity interleaver 121 inversely. That is, the parity deinterleaver 1234 may deinterleave the LLR values corresponding to the parity bits from among the LLR values output from the group deinterleaver 1233. In this case, the parity deinterleaver 1234 may deinterleave the LLR value corresponding to the parity bits inversely to the parity interleaving method of

85 Equation 18.
However, the parity deinterleaver 1234 may be omitted depending on the decoding method and embodiment of the decoder 1240.
Although the deinterleaver 1230 of FIG. 18 includes three (3) or four (4) elements as shown in FIG. 19, operations of the elements may be performed by a single element.
For example, when bits each of which belongs to each of bit groups Xa, Xb, Xc, Xd constitute a single modulation symbol, the deinterleaver 1230 may deinterleave these bits to locations corresponding to their bit groups based on the received single modulation symbol.
For example, when the code rate is 6/15 and the modulation method is 16-QAM, the group deinterleaver 1233 may perform deinterleaving based on table 11.
In this case, bits each of which belongs to each of bit groups X55, X15, X112, X122 may constitute a single modulation symbol. Since one bit in each of the bit groups X55, X15, X112, X122 constitutes a single modulation symbol, the deinterleaver 1230 may map bits onto decoding initial values corresponding to the bit groups X55, X15, X112, X122 based on the received single modulation symbol.
The decoder 1240 may perform LDPC decoding by using the output value of the deinterleaver 1230. To achieve this, the decoder 1240 may include an LDPC
decoder (not shown) to perform the LDPC decoding.
Specifically, the decoder 1240 is an element corresponding to the encoder 110 of the transmitting apparatus 100 and may correct an error by performing the LDPC
decoding by using the LLR value output from the deinterleaver 1230.
For example, the decoder 1240 may perform the LDPC decoding in an iterative decoding method based on a sum-product algorithm. The sum-product algorithm is one example of a message passing algorithm, and the message passing algorithm refers to an algorithm which exchanges messages (e.g., LLR value) through an edge on= a bipartite graph, calculates an output message from messages input to variable nodes or check nodes, and updates.
The decoder 1240 may use a parity check matrix when performing the LDPC
decoding. In this case, the parity check matrix used in the decoding may have the same configuration as that of the parity check matrix used in the encoding of the encoder 110, and this has been described above with reference to FIGs. 2 to 4.
In addition, information on the parity check matrix and information on the code rate, etc.

86 which are used in the LDPC decoding may be pre-stored in the receiving apparatus 1200 or may be provided by the transmitting apparatus 100.
FIG. 21 is a flowchart to illustrate an interleaving method of a transmitting apparatus according to an exemplary embodiment.
First, an LDPC codeword is generated by LDPC encoding based on a parity check matrix (S1410), and the LDPC codeword is interleaved (S1420).
Then, the interleaved LDPC codeword is mapped onto a modulation symbol (S1430). In this case, a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword may be mapped onto a predetermined bit in the modulation symbol.
Each of the plurality of bit groups may be formed of M number of bits, and M
may be a common divisor of Nidpc and Kidp, and may be determined to satisfy Qtapc=-(Nidpc-Kidpc)/M.
Herein, ()mix is a cyclic shift parameter value regarding columns in a column group of an information word submatrix of the parity check matrix, Nicipc is a length of the LDPC codeword, and Kkipc is a length of information word bits of the LDPC codeword.
Operation S1420 may include interleaving parity bits of the LDPC codeword, dividing the parity-interleaved LDPC codeword by the plurality of bit groups and rearranging the order of the plurality of bit groups in bit group wise, and interleaving the plurality of bit groups the order of which is rearranged.
The order of the plurality of bit groups may be rearranged in bit group wise based on the above-described Equation 21 presented above.
As described above, 7r(j) in Equation 21 may be determined based on at least one of a length of the LDPC codeword, a modulation method, and a code rate.
For example, when the LDPC codeword has a length of 64800, the modulation method is 16-QAM, and the code rate is 6/15, Ir(j) may be defined as in table 11.
In addition, when the LDPC codeword has a length of 64800, the modulation method is 16-QAM, and the code rate is 10/15, n(j) may be defined as in table 14.
In addition, when the LDPC codeword has a length of 64800, the modulation method is 16-QAM, and the code rate is 12/15, n(j) may be defined as in table 15.
In addition, when the LDPC codeword has a length of 64800, the modulation method is 64-QAM, and the code rate is 6/15, it(j) may be defined as in table 17.

87 In addition, when the LDPC codeword has a length of 64800, the modulation method is 64-OAM, and the code rate is 8/15, 7c(j) may be defined as in table 18.
In addition, when the LDPC codeword has a length of 64800, the modulation method is 64-QAM, and the code rate is 12/15, n(j) may be defined as in table 21.
The interleaving the plurality of bit groups may include: writing the plurality of bit groups in each of a plurality of columns in bit group wise in a column direction, and reading each row of the plurality of columns in which the plurality of bit groups are written in bit group wise in a row direction.
In addition, the interleaving the plurality of bit groups may include:
serially write, in the plurality of columns, at least some bit group which is writable in the plurality of columns in bit group wise from among the plurality of bit groups, and then dividing and writing the other bit groups in an area which remains after the at least some bit group is written in the plurality of columns in bit group wise.
A non-transitory computer readable medium, which stores a program for performing the interleaving methods according to various exemplary embodiments in sequence, may be provided.
The non-transitory computer readable medium refers to a medium that stores data semi-permanently rather than storing data for a very short time, such as a register, a cache, and a memory, and is readable by an apparatus. Specifically, the above-described various applications or programs may be stored in a non-transitory computer readable medium such as a compact disc (CD), a digital versatile disk (DVD), a hard disk, a Blu-ray disk, a universal serial bus (USB), a memory card, and a read only memory (ROM), and may be provided.
At least one of the components, elements or units represented by a block as illustrated in FIGs. 1, 5, 15, 18 and 19 may be embodied as various numbers of hardware, software and/or firmware structures that execute respective functions described above, according to an exemplary embodiment. For example, at least one of these components, elements or units may use a direct circuit structure, such as a memory, processing, logic, a look-up table, etc.
that may execute the respective functions through controls of one or more microprocessors or other control apparatuses. Also, at least one of these components, elements or units may be specifically embodied by a module, a program, or a part of code, which contains one or more executable instructions for performing specified logic functions. Also, at least one of these components,

88 elements or units may further include a processor such as a central processing unit (CPU) that performs the respective functions, a microprocessor, or the like. Further, although a bus is not illustrated in the above block diagrams, communication between the components, elements or units may be performed through the bus. Functional aspects of the above exemplary embodiments may be implemented in algorithms that execute on one or more processors.
Furthermore, the components, elements or units represented by a block or processing steps may employ any number of related art techniques for electronics configuration, signal processing and/or control, data processing and the like.
The foregoing exemplary embodiments and advantages are merely exemplary and are not to be construed as limiting the present inventive concept. The exemplary embodiments can be readily applied to other types of apparatuses. Also, the description of the exemplary embodiments is intended to be illustrative, and not to limit the scope of the inventive concept, and many alternatives, modifications, and variations will be apparent to those skilled in the art.

Claims

CLAIMS:

1. A receiving apparatus comprising:
a receiver configured to receive a signal from a transmitting apparatus;
a demodulator configured to demodulate the signal to generate values based on a 16-quadrature amplitude modulation(QAM);
a deinterleaver configured to split the values into a plurality of groups, and deinterleave the plurality of groups; and a decoder configured to decode values of the deinterleaved plurality of groups based on a low density parity check (LDPC) code, a code rate of the LDPC code being 6/15 and a code length of the LDPC code being 64800 bits, wherein the plurality of groups are deinterleaved based on a following equation:
Y7,0, = X, for (0 j < N ) group where N is a jth group among the plurality of groups, Y, is a jth group among the deinterleaved plurality of groups, N group iS a number of the plurality of groups, and 7c(j) denotes an interleaving order for the deinterleaving, and wherein the n(j) is represented as follows:
Order of interleaving rt(j) (0 < j <180) CodeRle j 1((i 6ns Date Recue/Date Received 2021-09-30

2. The receiving apparatus of claim 1, wherein each of the plurality of groups comprises 360 values.

3. A receiving method comprising:
receiving a signal from a transmitting apparatus;
demodulating the signal to generate values based on a 16-quadrature amplitude modulation(QAM);
splitting the values into a plurality of groups;
deinterleaving the plurality of groups; and decoding values of the deinterleaved plurality of groups based on a low density parity check (LDPC) code, a code rate of the LDPC code being 6/15 and a code length of the LDPC code being 64800 bits, wherein the plurality of groups are deinterleaved based on a following equation:
Y,,o) = X, for (0 j < N ) group where x, is a jth group among the plurality of groups, Y, is a jth group among the deinterleaved plurality of groups, NT,roup -S i a number of the plurality of groups, and 7c(j) denotes an interleaving order for the deinterleaving, and wherein the 71(j) is represented as follows:
Order of interleaving rt(j) (0 < j <180) CodeRate 1(6 ) Date Recue/Date Received 2021-09-30

4. The receiving method of claim 3, wherein each of the plurality of groups comprises 360 values.

5. The receiving apparatus of claim 1, wherein the deinterleaver is configured to deinterleave one or more values among the value of the deinterleaved plurality of groups, and wherein the decoder is configured to decode value of the deinterleaved plurality of groups comprising the deinterleaved one or more values.

6. The receiving method of claim 3, further comprising:
deinterleaving one or more values among the value of the deinterleaved plurality of groups, wherein the decoding is performed by decoding value of the deinterleaved plurality of groups comprising the deinterleaved one or more values.
Date Recue/Date Received 2021-09-30