KR20150050488A - transmitting apparatus and signal processing method thereof - Google Patents

Abstract

A transmitting apparatus is disclosed. The transmitting apparatus comprises: an encoding part performing LPDC encoding and generating an LDPC signal language; an interleaver interleaving the LDPC signal language; and a modulation part modulating the LDPC signal language, and generating a modulation symbol, wherein the interleaver comprises a group interleaver grouping the LDPC signal into multiple bit groups, and realigns order of the multiple bit groups, and a block interleaver consisting of multiple columns including multiple rows respectively, and interleaving by distinguishing multiple bit groups realigned based on a modulation order determined upon a modulation method. The block interleaver distinguishes each of multiple columns into a first part and a second part, lights multiple bit groups to multiple columns composing the first part in order by a bit group unit, dividing bits composing remaining bit groups into a bit group consisting of preset bit number respectively based on the number of the multiple columns, lights the divided bit groups to the multiple columns composing the second part in order to perform interleaving.

Description

TECHNICAL FIELD [0001] The present invention relates to a transmission apparatus and a signal processing method thereof,

BACKGROUND OF THE INVENTION 1. Field of the Invention [0002] The present invention relates to a transmission apparatus and a signal processing method thereof, and more particularly, to a transmission apparatus that processes and transmits data and a signal processing method thereof.

In a communication / broadcasting system, the link performance can be significantly degraded by various noise, fading phenomena and inter-symbol interference (ISI) of the channel. Therefore, in order to realize high-speed digital communication / broadcasting systems requiring high data throughput and reliability, such as next generation mobile communication, digital broadcasting, and portable Internet, it is required to develop a technique for overcoming noise, fading and intersymbol interference . As a part of research for overcoming noise and the like, recently, error-correcting code has been actively studied as a method for improving the reliability of communication by efficiently restoring information distortion.

The Low Density Parity Check (LDPC) code, first introduced by Gallager in the 1960s, has long been forgotten due to the complexity of the technology at that time. However, since turbo codes proposed by Berrou, Glavieux, and Thitimajshima in 1993 show performance close to the channel capacity of Shannon, many interpretations on the performance and characteristics of turbo codes have been made, and it has been studied a lot about iterative decoding and graph based channel coding. As a result of this research, iterative decoding based on a sum-product algorithm is applied on a Tanner graph corresponding to an LDPC code and then decoded in the late 1990's. It has been found that it has performance close to the capacity of the talk channel.

When an LDPC code is transmitted using a higher order modulation scheme, performance may vary depending on the method of mapping codeword bits to higher order modulation bits. Therefore, there is a need for a method of mapping the LDPC codeword bits to a higher order modulation bit for an LDPC code having excellent performance.

It is an object of the present invention to provide a transmission apparatus capable of mapping a bit included in a predetermined group among a plurality of groups constituting an LDPC codeword to a predetermined bit in a modulation symbol and transmitting the bit, And a method for processing the same.

According to an aspect of the present invention, there is provided a transmission apparatus including an encoder for performing LDPC encoding to generate an LDPC codeword, an interleaver for interleaving the LDPC codeword, and an interleaved LDPC Wherein the interleaver comprises: a group interleaver for grouping the LDPC codewords into a plurality of bit groups and reordering the order of the plurality of bit groups in group units; And a block interleaver which is composed of a plurality of columns including a plurality of columns and which performs interleaving of the plurality of rearranged bit groups based on a modulation order determined according to the modulation scheme, A first part and a second part, and the plurality of bit groups constitute the first part Sequentially divides the bits constituting the rest of the bit groups into bit groups each having a predetermined number of bits based on the number of the plurality of columns and outputs the divided bit groups to the second part And sequentially performs interleaving by writing to the plurality of columns.

Here, the number of the plurality of columns has the same value as the modulation order according to the modulation scheme, and each of the plurality of columns is a row corresponding to a value obtained by dividing the number of bits constituting the LDPC codeword by the number of the plurality of columns Lt; / RTI >

The first part may include a plurality of bit groups of the plurality of bit groups constituting the LDPC codeword according to the number of the plurality of columns, the number of bit groups and the number of bits constituting each bit group in each of the plurality of columns. Wherein each of the plurality of columns is constituted by a number of bits corresponding to the number of bits included in at least a part of the bit groups writable in units of bit groups in each column of the plurality of columns, And a row excluding rows corresponding to the number of bits included in at least a part of bit groups writable in units of bit groups in each of the plurality of columns.

Here, the number of rows of the second part may have a value equal to a quotient of dividing the number of bits included in all bit groups except the bit group corresponding to the first part by the number of columns constituting the block interleaver have.

The block interleaver sequentially writes bits included in at least a part of bit groups writable in units of bit groups into each of a plurality of columns constituting the first part, The bits included in the remaining bit groups are divided based on the number of the plurality of columns and can be sequentially written to each of the plurality of columns constituting the second part.

Here, the block interleaver may divide the bits included in the remaining bit group into the number of the plurality of columns, write each of the divided bits in a column direction in each of a plurality of columns constituting the second part, The plurality of columns constituting the first part and the second part may be read in the row direction and interleaving may be performed.

The modulation order may be 2, 4, 6, 8, 10, or 12 when the modulation scheme is QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM or 4096-QAM.

Meanwhile, a signal processing method of a transmission apparatus according to an embodiment of the present invention includes generating an LDPC codeword by performing LDPC coding, interleaving the LDPC codeword, and interleaving the interleaved LDPC codeword according to a modulation scheme Modulating the LDPC codeword into a plurality of groups, rearranging the order of the plurality of groups in a group unit, and generating a modulation symbol by including a plurality of rows And dividing and rearranging the plurality of reordering groups based on a modulation order determined according to the modulation scheme using a plurality of columns, wherein the step of dividing and interleaving the plurality of reordering groups comprises: Each of the plurality of columns is divided into a first part and a second part, and the plurality of groups are divided into a plurality of And the bits constituting the remaining groups are divided into bit groups each of which is formed by a predetermined number of bits based on the number of the plurality of columns, and the divided bit groups are divided into a plurality of bits constituting the second part And performs interleaving.

Here, the number of the plurality of columns has the same value as the modulation order according to the modulation scheme, and each of the plurality of columns is constituted by a row of a value obtained by dividing the number of bits constituting the LDPC codeword by the number of the plurality of columns .

The first part may include a plurality of bit groups of the plurality of bit groups constituting the LDPC codeword according to the number of the plurality of columns, the number of bit groups and the number of bits constituting each bit group in each of the plurality of columns. Wherein each of the plurality of columns is constituted by a number of bits corresponding to the number of bits included in at least a part of the bit groups writable in units of bit groups in each column of the plurality of columns, And a row excluding rows corresponding to the number of bits included in at least a part of bit groups writable in units of bit groups in each of the plurality of columns.

Here, the number of rows of the second part may have a value equal to a quotient of dividing the number of bits included in all bit groups except the bit group corresponding to the first part by the number of the plurality of columns.

The interleaving may include writing bits included in at least a part of bit groups writable in units of bit groups sequentially to each of a plurality of columns constituting the first part, The bits included in the remaining bit groups except for the group may be divided based on the number of the plurality of columns and sequentially written into each of the plurality of columns constituting the second part.

Here, the interleaving may be performed by dividing the bits included in the remaining bit groups into the number of the plurality of columns, writing each of the divided bits in a column direction to each of the plurality of columns constituting the second part , A plurality of columns constituting the first part and the second part may be read in the row direction and interleaving may be performed.

The modulation order may be 2, 4, 6, 8, 10, or 12 when the modulation scheme is QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM or 4096-QAM.

According to various embodiments of the present invention, it is possible to provide better decoding and reception performance.

1 is a block diagram illustrating a configuration of a transmitting apparatus according to an embodiment of the present invention;
2 and 3 are views for explaining the structure of a parity check matrix according to an embodiment of the present invention,
4 is a block diagram illustrating a structure of an interleaver according to an embodiment of the present invention.
5 to 7 are diagrams illustrating a method of processing an LDPC codeword group by group according to an embodiment of the present invention,
8 to 11 are views for explaining the structure and interleaving method of a block interleaver according to an embodiment of the present invention,
12 and 13 are diagrams for explaining the operation of the demultiplexer according to an embodiment of the present invention,
FIG. 14 is a diagram for explaining an example of a uniform constellation modulation method according to an embodiment of the present invention;
FIGS. 15 to 19 are diagrams for explaining an example of a non-uniform constellation modulation method according to an embodiment of the present invention;
20 is a block diagram for explaining a structure of an interleaver according to another embodiment of the present invention;
FIGS. 21 and 23 are diagrams for explaining the structure and interleaving method of a block-row interleaver according to an embodiment of the present invention,
24 is a block diagram illustrating a configuration of a receiving apparatus according to an embodiment of the present invention;
25 and 27 are block diagrams illustrating a structure of a deinterleaver according to an embodiment of the present invention.
26 is a view for explaining a block deinterleaver according to an embodiment of the present invention;
28 is a flowchart for explaining a signal processing method according to an embodiment of the present invention.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

1 is a block diagram illustrating a configuration of a transmitting apparatus according to a first embodiment of the present invention. Referring to FIG. 1, a transmitting apparatus 100 includes an encoding unit 110, an interleaver 120, and a modulating unit 130 (or a constellation mapper).

The encoding unit 110 performs Low Density Parity Check (LDPC) encoding to generate an LDPC codeword. To this end, the encoding unit 110 may include an LDPC encoder (not shown) for performing LPDC encoding.

Specifically, the encoding unit 110 may perform LDPC encoding of input bits with information bits to generate an LDPC codeword composed of information bits and parity bits (i.e., LDPC parity bits) . In this case, since the LPDC code is a systematic code, information bits can be directly included in the LDPC codeword.

In this case, the LDPC codeword consists of information bits and parity bits. For example, it consists LDPC codeword is N _ldpc bits and may comprise K _ldpc of bits comprising information bits and _parity N = N -K _{ldpc ldpc} parity bits consisting of bits.

In this case, the encoding unit 110 may perform LDPC encoding based on a parity check matrix (PCM) to generate an LDPC codeword. That is, the process for performing LDPC encoding is in terms of generating a LDPC code words to satisfy the H and C ^T = 0, the encoding unit 110 may be used when LDPC encoding parity check matrix. Here, H denotes a parity check matrix, and C denotes an LDPC codeword.

To this end, the transmitting apparatus 100 may have a separate memory and store various types of parity check matrices.

For example, the transmitting apparatus 100 may be a DVB-C2 (Digital Video Broadcasting-Cable version 2), a DVB-S2 (Digital Video Broadcasting-Satellite-Second Generation) Or a parity check matrix defined in the ATSC (Advanced Television Systems Committee) 3.0 standard, which is currently being standardized, may be stored in the parity check matrix. However, this is only an example, and the transmitting apparatus 100 may store various types of parity check matrices in addition to the above.

Hereinafter, the structure of the parity check matrix will be described in detail with reference to FIG. 2 and FIG.

Referring to FIG. 2, the parity check matrix 200 includes an information word partial matrix 210, which is a partial matrix corresponding to information word bits, and a parity partial matrix 220, which is a partial matrix corresponding to parity bits. Elements of the parity check matrix 200 excluding 1 are 0.

The information word _sub- matrix 210 includes K _ldpc columns and the parity submatrix 220 includes N _parity = N _ldpc- K _ldpc columns. On the other hand, the number of rows of the parity check matrix 200 is equal to the number of columns N _parity = N _ldpc- K _ldpc of the parity partial matrix 220.

In the parity check matrix 200, N _ldpc denotes the length of the LDPC codeword, K _ldpc denotes the length of the information bits, and N _parity = N _ldpc -K _ldpc denotes the length of the parity bits. Here, the length of the LDPC codeword, information word bits, and parity bits means the number of bits included in each of the LDPC codeword, information word bits, and parity bits.

Hereinafter, the structure of the information word partial matrix 210 and the parity partial matrix 220 will be described.

The information word submatrix 210 is a matrix including K _ldpc columns (i.e., the 0th column to the K _ldpc -1 th column), and follows the following rules.

First, the K _ldpc columns constituting the information word submatrix 210 belong to the same M groups, and are divided into a total of K _ldpc / M column groups. The columns belonging to the same column group have cyclic shift by Q _ldpc .

Here, M is the interval at which the pattern of the column is repeated in the information word _sub- matrix 210 (for example, M = 360), and Q _ldpc is the size at which each column is _cyclically shifted in the information word _sub- M and Q _ldpc are integers and are determined such that Q _ldpc = (N _{ldpc -} K _ldpc ) / M holds. At this time, K _ldpc / M is also an integer. Meanwhile, M and Q _ldpc can have various values according to the length of the LDPC codeword and the code rate.

For example, M = 360, and if the case of the LDPC codeword length N _ldpc is 64800 Q _ldpc is defined as shown in Table 1 below, M = 360 and the LDPC codeword length N _ldpc is 16200 to the Q _ldpc As shown in Table 2 below.

이라 하면, i 번째 열 그룹 내의 j 번째 열에서 k 번째 무게-1(weight-1)이 위치한 행의 인덱스

(즉, i 번째 열 그룹 내의 j 번째 열에서 k 번째 1이 위치한 행의 인덱스)는 하기의 수학식 1과 같이 결정된다.Second, the degree of the 0th column of the i-th (i = 0,1, .., K _ldpc / M-1) column group (where the degree is the number of 1 values existing in the column, (Or the index of all the rows belonging to is the same) is _denoted by D _i , and the position (or index) of each row having 1 in the 0th column of the i-th column group is

, The index of the row where the kth weight -1 (weight-1) is located in the jth column in the i-th column group

(I. E., The index of the row in which the kth < th > 1 in the jth column in the ith column group is located) is determined as follows:

Here, k = 0,1,2, ..., D _i -1, i = 0,1, ..., K _ldpc / M-1, j = 1,2, ..., M-1.

Meanwhile, Equation 1 can be expressed equally as Equation 2 below

Here, k = 0,1,2, ..., D _i -1, i = 0,1, ..., K _ldpc / M-1, j = 1,2, ..., M-1.

는 i 번째 열 그룹 내의 j 번째 열에서 k 번째 무게-1이 위치한 행의 인덱스, N_ldpc는 LDPC 부호어의 길이, K_ldpc는 정보어 비트들의 길이, D_i는 i 번째 열 그룹에 속하는 열들의 차수, M은 하나의 열 그룹에 속하는 열의 개수, Q_ldpc는 각 열이 시클릭 쉬프트되는 크기를 의미한다.In these equations,

Of the i-th column belonging to the index of the row in the k-th weight-1 in the j-th column in the column group, N _ldpc length, K is the length _ldpc, D _i of information bits of the LDPC codeword is the i th column group, Order, M is the number of columns belonging to one column group, and Q _ldpc is the size by which each column is _cyclically shifted.

값만을 알면 i 번째 열 그룹 내의 j 번째 열에서 k 번째 무게-1이 있는 행의 인덱스

를 알 수 있게 된다. 그러므로, 각각의 열 그룹 내의 첫 번째 열에서 k 번째 무게-1이 있는 행의 인덱스 값을 저장하면, 도 2의 구조를 갖는 패리티 검사 행렬(200)(즉, 패리티 검사 행렬(200)의 정보어 부분 행렬(210))에서 무게-1이 있는 열과 행의 위치가 파악될 수 있다.As a result, referring to these equations

If the value is known only, the index of the row having the kth weight -1 in the jth column in the ith column group

. Therefore, if the index value of the row having the kth weight -1 in the first column in each column group is stored, the parity check matrix 200 having the structure of FIG. 2 (i.e., the information word of the parity check matrix 200) The partial matrix 210), the position of the row and column with weight -1 can be grasped.

According to the above rules, the orders of the columns belonging to the ith column group are all the same as D _i . Accordingly, an LDPC code storing information on a parity check matrix according to the above rules can be briefly expressed as follows.

For example, the N _ldoc 30, K _ldpc is 15, Q _ldpc the case of three, position information of the rows are in weight -1 in the 0th column of the three columns group to represented by a sequence such as the equation (3) , Which may be referred to as a " weight-1 position sequence ".

는 i번째 열 그룹 내의 j번째 열에서 k번째 무게-1이 있는 행의 인덱스를 의미한다.From here,

Denotes an index of a row having the kth weight -1 in the jth column in the ith column group.

The weight-1 position sequences such as Equation (3) representing the index of the row where 1 is located in the 0th column of each column group can be expressed more simply as shown in Table 3 below.

Table 3 shows the position of the weight-1, that is, the one having the value 1 in the parity check matrix. In the i-th weight-1 position sequence, Lt; / RTI >

The information word sub-matrix 210 of the parity check matrix according to an embodiment of the present invention may be defined by the following Tables 4 to 27 based on the above description.

Specifically, Tables 4 to 27 show indexes of a row in which 1 is located in the 0th column of the i-th column group of the information word submatrix 210. [ That is, the information word sub-matrix 210 is composed of a plurality of column groups each including M columns, and the position of 1 in the 0th column of each of the plurality of column groups can be defined by Tables 4 to 27 .

Here, the indexes of the row where 1 is located in the 0th column of the i-th column group means "addresses of parity bit accumulators". In the meantime, the "addresses of parity bit accumulators" have the same meanings as those defined in the DVB-C2 / S2 / T2 standard or the ATSC 3.0 standard currently being established.

For example, when the length N _ldpc of the LDPC codeword is 16200, the coding rate is 5/15, and M is 360, the indexes of the row where 1 is located in the 0th column of the i-th column group of the information word submatrix 210 As shown in Table 4 below.

As another example, when the length N _ldpc of the LDPC codeword is 16200, the coding rate is 6/15, and M is 360, the indexes of the row where 1 is located in the 0th column of the i-th column group of the information word submatrix 210 As shown in Table 5 below.

As another example, when the length N _ldpc of the LDPC codeword is 16200, the coding rate is 7/15, and M is 360, the index of the row where 1 is located in the 0th column of the i-th column group of the information word submatrix 210 Are shown in Table 6 below.

As another example, when the length N _ldpc of the LDPC codeword is 16200, the coding rate R is 8/15, and M is 360, the number of rows of the row where the 1 is located in the 0th column of the i-th column group 210 of the information word submatrix 210 The indices are the same as in Table 7, Table 8 or Table 9 below.

As another example, when the length N _ldpc of the LDPC codeword is 16200, the coding rate is 9/15, and M is 360, the index of the row where 1 is located in the 0th column of the i-th column group of the information word submatrix 210 Are shown in Table 10 below.

As another example, when the length N _ldpc of the LDPC codeword is 16200, the code rate is 10/15, and M is 360, the index of the row where 1 is located in the 0th column of the i-th column group of the information word submatrix 210 Are shown in Table 11, Table 12, or Table 13 below.

As another example, when the length N _ldpc of the LDPC codeword is 16200, the coding rate is 11/15, and M is 360, the index of the row where 1 is located in the 0th column of the i-th column group of the information word submatrix 210 Are shown in Table 14 below.

As another example, when the length N _ldpc of the LDPC codeword is 16200, the coding rate is 12/15, and M is 360, the index of the row where 1 is located in the 0th column of the i th column group of the information word submatrix 210 Are shown in Table 15 or Table 16 below.

As another example, when the length N _ldpc of the LDPC codeword is 16200, the coding rate is 13/15, and M is 360, the index of the row where 1 is located in the 0th column of the i-th column group of the information word submatrix 210 Are shown in Table 17 below.

As another example, when the length N _ldpc of the LDPC codeword is 64800, the coding rate is 5/15, and M is 360, the index of the row where 1 is located in the 0th column of the i-th column group of the information word submatrix 210 Are shown in Table 18 below.

As another example, when the length N _ldpc of the LDPC codeword is 64800, the coding rate is 6/15, and M is 360, the index of the row where 1 is located in the 0th column of the i-th column group of the information word submatrix 210 Are shown in Table 19 below.

As another example, when the length N _ldpc of the LDPC codeword is 64800, the coding rate is 7/15, and M is 360, the index of the row where 1 is located in the 0th column of the i-th column group of the information word submatrix 210 Are shown in Table 20 or Table 21 below.

As another example, when the length N _ldpc of the LDPC codeword is 64800, the coding rate is 8/15, and M is 360, the index of the row where 1 is located in the 0th column of the i-th column group of the information word submatrix 210 Are shown in Table 22 below.

As another example, when the length N _ldpc of the LDPC codeword is 64800, the coding rate is 9/15, and M is 360, the index of the row where 1 is located in the 0th column of the i-th column group of the information word submatrix 210 Are shown in Table 23 below.

As another example, when the length N _ldpc of the LDPC codeword is 64800, the coding rate is 10/15, and M is 360, the index of the row where 1 is located in the 0th column of the i-th column group of the information word submatrix 210 Are shown in Table 24 below.

As another example, when the length N _ldpc of the LDPC codeword is 64800, the coding rate is 11/15, and M is 360, the index of the row where 1 is located in the 0th column of the i-th column group of the information word submatrix 210 Are shown in Table 25 below.

As another example, when the length N _ldpc of the LDPC codeword is 64800, the coding rate is 12/15, and M is 360, the index of the row where 1 is located in the 0th column of the i-th column group of the information word submatrix 210 Are shown in Table 26 below.

As another example, when the length N _ldpc of the LDPC codeword is 64800, the code rate is 13/15, and M is 360, the index of the row where 1 is located in the 0th column of the i-th column group of the information word submatrix 210 Are shown in Table 27 below.

In Table 4 to Table 27, even though the order of the numbers in the sequence corresponding to each i-th column group is changed, the order of the sequence in the sequence corresponding to each i-th column group in Tables 4 to 27 May be an example of codes considered in the present invention.

In addition, even if the order of the sequences corresponding to the respective column groups is changed in Tables 4 to 27, the logarithmic characteristics such as the cycle characteristics and the order distributions on the graph of the sign do not change, An example of a change is an example.

In addition, since the algebraic properties such as the cycle characteristic and the order distribution on the graph of the sign do not change as a result of adding the multiple of Q _ldpc to all the sequences corresponding to arbitrary column groups in Tables 4 to 27, The results obtained by adding a multiple of Q _ldpc to all of the sequences shown in Table 27 may be one example. Note that if a value is greater than (N _ldpc -K _ldpc ) by a factor of Q _ldpc times the given sequence, then the modulo operation (N _ldpc -K _ldpc ) To the value applied.

On the other hand, if the position of the row in which the 1 exists in the 0th column of the i-th column group of the information word sub-matrix 210 is defined as shown in Tables 4 to 27, it is _cyclically shifted by Q _ldpc , The position of the row where a 1 exists in the column can be defined.

For example, in the case of Table 4, in the 0th column of the 0th column group of the information word partial matrix 210, the 245th row, the 449th row, the 491st row, 1 is present.

In this case, the index of the row where 1 is located in the first column of the 0th column group is 275 (= 245 + 30) because Q _ldpc = (N _ldpc -K _ldpc ) / M = (16200-5400) / 360 = , 479 (= 449 + 30), 521 (= 491 + 30), ... , And the index of the row in which the 1 is located in the second column of the 0th column group may be 305 (= 275 + 30), 509 (= 479 + 30), 551 (= 521 + 30),.

By such a method, an index of a row in which 1 is located in every row of each column group can be defined.

In the parity check matrix 200 shown in FIG. 2, the parity partial matrix 220 may be defined as follows.

The parity partial matrix 220 is a partial matrix including N _ldpc- K _ldpc columns (i.e., K _ldpc th column to N _ldpc -1 th column), and has a dual diagonal or staircase structure. Therefore, the order of the remaining columns excluding the last column (i.e., N _ldpc- 1) in the parity part matrix 220 is 2, and the order of the last column is 1. [

As a result, the information word partial matrix 210 in the parity check matrix 200 is defined by Tables 4 to 27, and the parity partial matrix 220 may have a double diagonal structure.

2 is permutated based on the following equations (4) and (5), the parity check matrix 200 shown in FIG. 2 corresponds to the parity check matrix shown in FIG. 3 May be expressed in the form of a parity check matrix 300 shown in FIG.

A method of performing permutation based on Equation (4) and Equation (5) is as follows. Here, the low permutation and the column permutation are applied to the same principle. Hereinafter, the low permutation will be described as an example.

In the case of the low permutation, i, j satisfying X = Q _ldpc x i + j for the X th row is calculated, and the calculated i, j is substituted into M x j + i, . For example, in the case of the seventh row, since i and j satisfying 7 = 2 x i + j are 3,1, respectively, the seventh row is permutated to 10 x 1 + 3 = thirteenth row.

When the low permutation and the column permutation are performed in this manner, the parity check matrix of FIG. 2 can be expressed as shown in FIG.

Referring to FIG. 3, the parity check matrix 300 includes a parity check matrix 300 divided into a plurality of partial blocks, and a quasi-cyclic (M × M) Matrix.

Accordingly, the parity check matrix 300 having the structure as shown in FIG. 3 is configured in matrix units of M × M size. That is, the parity check matrix 300 is constructed by arranging partial matrices having M × M sizes in a plurality of partial blocks.

As described above, since the parity check matrix 300 is composed of M × M sub-matrixes, it is possible to designate M columns as a column-block and M rows as a row-block have. Thus, parity check matrix 300 has a structure as shown in FIG. 3 used in the present invention is N _{qc _ column} = N _ldpc / M column blocks and N _{qc _ row} = N _parity / M of which consists of a block of lines .

Hereinafter, a partial matrix having an M × M size will be described.

First, the 0-th line block _{(qc _} N _column -1) th column block in the form of equation (6) below.

As described above, the A 330 is an M × M matrix, and the values of the 0th row and the (M-1) th column are both '0' 1) th row is '1' and all other values are '0'.

Second, in the parity part matrix _{(320) 0≤i≤ (N ldpc -K} ldpc) with respect to _{/ M-1 (K ldpc /} M + i) i -th row block of the first column block is a unit matrix I _{M × M} ( 340). Further, in _{0≤i≤ (N ldpc -K ldpc) /} M-2 with respect to the (K _ldpc / M + i) th column of the block (i + 1) th row block is an identity matrix I _{M × M} (340) .

또는, 순환 행렬 P가 시클릭 쉬프트된 행렬

이 합해진 형태(또는, 중첩된 형태)가 될 수 있다. Third, the block 350 composing the information word partial matrix 310 is a block in which the circulating matrix P is a cyclic shifted form

Alternatively, if the cyclic matrix P is a cyclic shifted matrix

(Or a superimposed form).

For example, the form in which the circulation matrix P is cyclically shifted by 1 in the right direction can be expressed by Equation (7).

The circulating matrix P is a square matrix having an M × M size, and the circulating matrix P represents a matrix in which the weight of each of the M rows is 1 and the weight of each of the M columns is also 1. When the superscript a _ij is 0, ie, P ⁰ represents the identity matrix I _{M × M} , and the superscript a _ij is ∞, ie, P ^∞ represents a zero matrix.

가 될 수 있다. 따라서, i와 j는 정보어 부분에 해당하는 부분 블록들의 행 블록과 열 블록의 개수를 나타낸다. 따라서, 패리티 검사 행렬(300)은 전체 열의 개수가 N_ldpc=M×N_{qc _ column}이고, 전체 행의 개수가 N_parity=M×N_{qc _ row}가 된다. 즉, 패리티 검사 행렬(300)은 N_{qc _ column} 개의 "열 블록"과 N_{qc _ row} 개의 "행 블록"으로 구성된다.3, a partial matrix existing at the intersection of the i-th row block and the j-th column block of the parity check matrix 300

. Thus, i and j represent the number of row blocks and column blocks of partial blocks corresponding to the information word portion. Thus, parity check matrix 300 is the total number of columns N _ldpc = M × N _{_ qc column,} the number of the entire line is the _parity N = M × N _{_ qc row.} That is, the parity check matrix 300 is composed of N _{_ qc column} of "column block" and N _{qc _ row} of "line block".

Returning to FIG. 1, the encoding unit 110 may encode various codes such as 5/15, 6/15, 7/15, 8/15, 9/15, 10/15, 11/15, 12/15, 13/15, Rate can be used to perform LDPC encoding. The encoding unit 110 may generate LDPC codewords having various lengths such as 16200 and 64800 based on the length of the information word bits and the code rate.

In this case, the encoding unit 110 can perform LDPC encoding using the parity check matrix, and the specific structure of the parity check matrix has been described above with reference to FIG. 2 and FIG.

In addition, the encoding unit 110 may perform BCH (Bose, Chaudhuri, Hocquenghem) encoding as well as LDPC encoding. For this, the encoding unit 110 may further include a BCH encoder (not shown) for performing BCH encoding.

In this case, the encoding unit 110 can perform encoding in the order of BCH encoding and LDPC encoding. Specifically, the encoding unit 110 performs BCH encoding on the input bits to add a BCH parity bit, performs LDPC encoding on the bits to which the BCH parity bit is added, as information bits, and generates an LDPC codeword You may.

The interleaver 120 interleaves the LDPC codeword. That is, the interleaver 120 receives the LDPC codeword from the encoding unit 110 and interleaves the LDPC codeword based on various interleaving rules.

In particular, the interleaver 120 is configured so that the bits included in the predetermined group among the plurality of groups (or the plurality of bit groups or the plurality of blocks) constituting the LDPC codeword are mapped to predetermined bits in the modulation symbol, Can be interleaved. Accordingly, the modulator 130 can map the bits included in the predetermined group among the plurality of groups constituting the LDPC codeword to predetermined bits in the modulation symbol.

Hereinafter, the interleaving rules used in the interleaver 120 will be described more specifically.

block Interleaver  When to use

According to an embodiment of the present invention, the interleaver 120 interleaves the LDPC codeword by the following method, and determines whether the bits included in the predetermined group among the plurality of groups constituting the interleaved LDPC codeword are within the modulation symbol To be mapped to a predetermined bit. Reference is made to Fig. 4 for a detailed description.

4 is a block diagram illustrating the structure of an interleaver according to an embodiment of the present invention. 4, the interleaver 120 includes a parity interleaver 121, a group interleaver (or a group-wise interleaver 122), a group twisted interleaver 123, and a block interleaver 124.

The parity interleaver 121 interleaves the parity bits constituting the LDPC codeword.

Specifically, when the LDPC codeword is generated based on the parity check matrix 200 having the structure as shown in FIG. 2, the parity interleaver 121 interleaves only the parity bits among the LDPC codewords using the following equation (8) .

)에 대해 패리티 인터리빙을 수행하여 U=(u₀,u₁,…,

)를 출력할 수 있다.Here, M is the interval at which the pattern of the column is repeated in the information word _sub- matrix 210, that is, the number of columns included in the column group (for example, M = 360), Q _ldpc is the The size of the column is the cyclic shift. That is, the parity interleaver 121 receives the LDPC codeword c = (c ₀ , c ₁ ,

) Are subjected to parity interleaving to obtain U = (u ₀ , u ₁ , ...,

Can be output.

When the LDPC codeword coded based on the parity check matrix 200 shown in FIG. 2 is parity interleaved based on Equation (8), the parity interleaved LDPC codeword is encoded by the parity check matrix 300 as shown in FIG. LDPC codeword. Therefore, when the LDPC codeword is generated based on the parity check matrix 300 shown in FIG. 3, the parity interleaver 121 can be omitted.

On the other hand, the parity-interleaved LDPC codeword after being encoded based on the parity check matrix 200 having the form of FIG. 2 and the LDPC codeword encoded based on the parity check matrix 300 having the form of FIG. The consecutive bits may be configured to have similar decoding characteristics (e.g., cycle distribution, order of columns, etc.).

For example, an LDPC codeword may have the same characteristics in consecutive M bits. Here, M may be 360, for example, at a repetition interval of the pattern of columns in the information word submatrix.

Specifically, LDPC codeword, and bits and the parity check matrix should be a product of '0', which i is from 0 to N-th i _ldpc -1 LDPC codeword bit _{c i (i = 0,1, ...} , N _ldpc -1) and the sum of the products of the columns of the i-th parity check matrix should be a '0' vector. Therefore, the i-th LDPC codeword bit can be regarded as corresponding to the i-th column of the parity check matrix.

In the case of the parity check matrix 200 as shown in FIG. 2, the information word submatrices 210 belong to the same group of M columns, and have the same characteristics in units of column groups (for example, The columns have the same degree distribution and the same cycle characteristics).

In this case, since the M consecutive bits in the information word bits correspond to the same column group of the information word sub-matrix 210, the information word bits can be composed of consecutive M bits having the same codeword characteristic . Meanwhile, if the parity bits of the LDPC codeword are interleaved by the parity interleaver 121, the parity bits of the LDPC codeword may be composed of consecutive M bits having the same codeword characteristic.

3, the information word partial matrix 310 and the parity partial matrix 320 of the parity check matrix 300 may include M columns by row and column permutation, The information bits and the parity bits of the LDPC codeword coded based on the parity check matrix 300 can be composed of consecutive M bits having the same codeword property .

Here, the low permutation has no influence on the algebraic properties of the LDPC code itself, such as cycle characteristics, order distribution, and minimum distance, in that the row permutation is merely to rearrange the order of the rows in the parity check matrix. The column permutation is performed for the parity partial matrix 320 so as to correspond to the parity interleaving performed in the parity interleaver 121. In the column permutation, the LDPC codes coded by the parity check matrix 300 shown in FIG. The parity bits of the codeword may be composed of consecutive M bits such as parity bits of the LDPC codeword coded by the parity check matrix 200 as shown in FIG.

As described above, the bits constituting the LDPC codeword can have the same characteristics in consecutive M bits.

The group interleaver 122 may divide the LDPC codeword into a plurality of groups and rearrange the order of the plurality of groups into group wise. Alternatively, the group interleaver 122 may classify the parity interleaved LDPC codewords into a plurality of groups, and rearrange the order of the plurality of groups into group wise.

That is, the group interleaver 122 can interleave the plurality of groups in units of groups.

For this, the group interleaver 122 divides the parity-interleaved LDPC codewords into a plurality of groups using Equation (9) or Equation (10) below.

는 k/360 이하의 가장 큰 정수를 나타낸다. In these equations, N _group represents the total number of groups, X _j represents the j-th group, and u _k represents the k-th LDPC codeword bit input to the group interleaver 122. And,

Represents the largest integer of k / 360 or less.

On the other hand, in these equations, 360 represents an example of M, which is an interval in which a column pattern is repeated in an information word partial matrix. In these equations, 360 can be changed to M.

On the other hand, LDPC codewords divided into a plurality of groups can be represented as shown in FIG.

Referring to FIG. 5, it can be seen that the LDPC codewords are divided into a plurality of groups, and each group consists of M consecutive bits. Here, when M is 360, each of the plurality of groups may be configured with 360 bits. Accordingly, each group may be composed of bits corresponding to each column group of the parity check matrix.

Specifically, since the LDPC codeword is divided into consecutive M bits, the K _ldpc information bits are divided into (K _ldpc / M) groups, and the N _ldpc -K _ldpc parity bits (N _ldpc -K _ldpc ) / M groups. Accordingly, the LDPC codeword can be divided into a total of (N _ldpc / M) groups. For example, if M = 360, the number of groups N _group is 180 when the length N _ldpc of the LDPC codeword is 64800, and the number N _group of _groups becomes 45 when the length _Nldpc of the LDPC codeword is 16200 .

The reason why the group interleaver 122 divides the LDPC codeword into the same group of consecutive M bits is that the LDPC coders have the same codeword characteristics in consecutive M bits as described above. Accordingly, when the LDPC codeword is divided into consecutive M bits, bits having the same codeword characteristics can be included in the same group.

In the example described above, the number of bits constituting each group is M, but this is merely an example, and the number of bits constituting each group can be variously changed.

For example, the number of bits constituting each group may be a divisor of M. That is, the number of bits constituting each group may be a divisor of the number of columns constituting the column group of the information word partial matrix of the parity check matrix. In this case, each group may be composed of a few bits of M. For example, when the number of columns constituting the column group of the information word partial matrix is 360, that is, M = 360, the group interleaver 122 determines whether the number of bits constituting each group is 360 The LDPC codeword can be divided into a plurality of groups.

However, for convenience of explanation, only the case where the number of bits constituting the group is M will be described below.

Then, the group interleaver 122 interleaves the LDPC codeword group by group. Specifically, the group interleaver 122 may group the LDPC codewords into a plurality of groups and rearrange the groups into a plurality of groups. That is, the group interleaver 122 can rearrange the order of a plurality of groups constituting the LDPC codeword group by changing positions of a plurality of groups constituting the LDPC codeword.

Here, the group interleaver 122 may rearrange the order of the plurality of groups so that groups including bits mapped to the same modulation symbol among the plurality of groups are spaced apart by a predetermined interval.

In this case, the group interleaver 122 determines the number of bits to be mapped to the same modulation symbol in consideration of the number of rows and columns constituting the block interleaver 124, the number of groups constituting the LDPC codeword, The order of the plurality of groups may be rearranged in groups so that the groups including the groups are spaced apart by a predetermined interval.

For this, the group interleaver 122 may rearrange the order of the plurality of groups into groups using the following Equation (11).

Here, X _j denotes the j-th group before the group interleaving, Y _j represents the j th group after group interleaving. Further,? (J) is a parameter indicating an interleaving sequence and may be determined by at least one of the length, the coding rate and the modulation method of the LDPC codeword.

Therefore, X _(j) represents the group of π (j) before group interleaving, and Equation (11) means that the group π (j) before interleaving is interleaved into the jth group after interleaving.

Meanwhile, a specific example of? (J) according to an embodiment of the present invention can be defined as shown in Tables 28 to 35 below.

In this case,? (J) is defined according to the length and coding rate of the LDPC codeword, and the parity check matrix is also defined according to the length and coding rate of the LDPC codeword. Therefore, when LDPC coding is performed based on a specific parity check matrix according to the length and the coding rate of the LDPC codeword, the LDPC codeword is divided into a group of the LDPC codewords based on? (J) satisfying the length and the coding rate of the LDPC codeword, Lt; / RTI >

For example, when the encoding unit 110 performs LDPC encoding with a coding rate of 10/15 to generate an LDPC codeword having a length of 16,200, the group interleaver 122 performs the LDPC encoding on the basis of Tables 28 to 35 The interleaving can be performed using? (J) defined by the length of the LDPC codeword of 16200 and the coding rate of 10/15.

For example, if the length of the LDPC codeword is 16200, the coding rate is 10/15, and the modulation scheme is 16-QAM (quadrature amplitude modulation), the group interleaver 122 sets π (j) defined as Table 28 So that interleaving can be performed.

On the other hand, a concrete example of? (J) is as follows.

For example, when the LDPC codeword length _Nldpc is 16200 and the coding rates are 10/15, 11/15, 12/15, and 13/15 and the modulation method is 16-QAM, π (j) Can be defined as follows.

For Table 28, Equation 11 _{Y 0 = X π (0)} = X 7, Y 1 = X π (1) = X 17, Y 2 = X π (2) = X 33, ..., Y _{43 = X π (43) =} X 13, can be expressed as _{Y 44 = X π (44)} = X 44. Accordingly, the group interleaver 122 sets the seventh group to 0, the 17 th group to the 1 st, the 33 th group to the 2 nd, the 13 th group to the 43 th, the 44 th group to 44 The order of a plurality of groups can be rearranged in a group unit by changing the order.

As another example, when the LDPC codeword length _Nldpc is 16200 and the coding rates are 6/15, 7/15, 8/15, 9/15 and the modulation scheme is 64-QAM, π (j) Can be defined as follows.

For Table 29, Equation 11 _{Y 0 = X π (0)} = X 32, Y 1 = X π (1) = X 4, Y 2 = X π (2) = X 23, ..., Y ₄₃ = X ₍₄₃₎ = X ₄₃ , Y ₄₄ = X ₍₄₄₎ = X ₄₄ . Accordingly, the group interleaver 122 sets the 32nd group to the 0th, the 4th group to the 1st, the 23rd group to the 2nd, the 43rd group to the 43rd, the 44th group to 44 The order of a plurality of groups can be rearranged in a group unit by changing the order.

As another example, when the LDPC codeword length _Nldpc is 16200 and the coding rates are 10/15, 11/15, 12/15, and 13/15 and the modulation scheme is 256-QAM, π (j) Can be defined as follows.

For Table 30, Equation 11 _{Y 0 = X π (0)} = X 28, Y 1 = X π (1) = X 6, Y 2 = X π (2) = X 15, ..., Y ₄₃ = X ₍₄₃₎ = X ₄₃ , Y ₄₄ = X ₍₄₄₎ = X ₄₄ . Accordingly, the group interleaver 122 sets the 28th group to the 0th, the 6th group to the 1st, the 15th group to the 2nd, the 43rd group to the 43rd, the 44th group to 44 The order of a plurality of groups can be rearranged in a group unit by changing the order.

As another example, when the LDPC codeword length _Nldpc is 16200 and the coding rates are 6/15, 7/15, 8/15, 9/15 and the modulation scheme is 1024-QAM, π (j) Can be defined as follows.

For Table 31, Equation 11 _{Y 0 = X π (0)} = X 16, Y 1 = X π (1) = X 13, Y 2 = X π (2) = X 1, ..., Y ₄₃ = X ₍₄₃₎ = X ₄₃ , Y ₄₄ = X ₍₄₄₎ = X ₄₄ . Accordingly, the group interleaver 122 sets the 16th group to the 0th, the 13th group to the 1st, the 1st group to the 2nd, the 43rd group to the 43rd, the 44th group to 44 The order of a plurality of groups can be rearranged in a group unit by changing the order.

As another example, when the LDPC codeword length _Nldpc is 64800 and the coding rates are 6/15, 7/15, 8/15, 9/15 and the modulation method is 256-QAM,? (J) Can be defined as follows.

For Table 32, Equation 11 _{Y 0 = X π (0)} = X 48, Y 1 = X π (1) = X 4, Y 2 = X π (2) = X 15, ..., Y ₁₇₈ = X ₍₁₇₈₎ = X ₁₇₈ , Y ₁₇₉ = X ₍₁₇₉₎ = X ₁₇₉ . Accordingly, the group interleaver 122 sets the 48th group to the 0th, the 4th group to the 1st, the 15th group to the 2nd, ..., the 178th group to 178th, the 179th group to 179 The order of a plurality of groups can be rearranged in a group unit by changing the order.

As another example, when the length Nldpc of the LDPC codeword is 64800 and the coding rates are 6/15, 7/15, 8/15, 9/15 and the modulation method is 16-QAM, π (j) Can be defined as follows.

For Table 33, Equation 11 _{Y 0 = X π (0)} = X 121, Y 1 = X π (1) = X 39, Y 2 = X π (2) = X 139, ..., Y ₁₇₈ = X ₍₁₇₈₎ = X ₂ , Y ₁₇₉ = X ₍₁₇₉₎ = X ₉₆ . Accordingly, the group interleaver 122 sets the 121nd group to 0, the 39th group to the 1st, the 139th group to the 2nd, ..., the 2nd group to the 178th, the 96th group to 179 The order of a plurality of groups can be rearranged in a group unit by changing the order.

As another example, when the LDPC codeword length N _ldpc is 64,800 and the coding rates are 10/15, 11/15, 12/15, 13/15 and the modulation scheme is 64-QAM, π (j) Can be defined as follows.

For Table 34, Equation 11 _{Y 0 = X π (0)} = X 49, Y 1 = X π (1) = X 105, Y 2 = X π (2) = X 104, ..., Y ₁₇₈ = X ₍₁₇₈₎ = X ₁₆₄ , Y ₁₇₉ = X ₍₁₇₉₎ = X ₁₇₆ . Accordingly, the group interleaver 122 sets the 49th group to the 0th, the 105th group to the 1st, the 104th group to the 2nd, ..., the 164th group to the 178th, the 176th group to 179 The order of a plurality of groups can be rearranged in a group unit by changing the order.

As another example, when the LDPC codeword length _Nldpc is 64,800 and the coding rates are 10/15, 11/15, 12/15, 13/15 and the modulation scheme is 1024-QAM, π (j) Can be defined as follows.

For Table 35, Equation 11 _{Y 0 = X π (0)} = X 45, Y 1 = X π (1) = X 37, Y 2 = X π (2) = X 31, ..., Y ₁₇₈ = X ₍₁₇₈₎ = X ₁₉ , Y ₁₇₉ = X ₍₁₇₉₎ = X ₁₆₅ . Accordingly, the group interleaver 122 sets the 45th group to the 0th, the 37th group to the 1st, the 31st to the 2nd, ..., the 19th group to 178th, the 165th group to 179 The order of a plurality of groups can be rearranged in a group unit by changing the order.

In this manner, the group interleaver 12 can rearrange the order of the plurality of groups into groups using Equation (11) and Table 28 to Table 35. [

On the other hand, the group interleaver 122 may rearrange the order of the plurality of groups into groups using the following equation (12).

Here, X _j denotes the j-th group before the group interleaving, Y _j represents the j th group after group interleaving. Further,? (J) is a parameter indicating an interleaving sequence and may be determined by at least one of the length, the coding rate and the modulation method of the LDPC codeword.

Therefore, Y _{? (J)} represents the group? (J) after group interleaving, and Equation (12) means that the jth group before interleaving is interleaved into? (J) group after interleaving.

Meanwhile, a specific example of? (J) according to an embodiment of the present invention can be defined as shown in Tables 36 to 43 below.

In this case,? (J) is defined according to the length and coding rate of the LDPC codeword, and the parity check matrix is also defined according to the length and coding rate of the LDPC codeword. Therefore, when LDPC coding is performed based on a specific parity check matrix according to the length and the coding rate of the LDPC codeword, the LDPC codeword is divided into a group of the LDPC codewords based on? (J) satisfying the length and the coding rate of the LDPC codeword, Lt; / RTI >

For example, when the encoding unit 110 performs LDPC encoding with a coding rate of 10/15 in order to generate an LDPC codeword having a length of 16,200, the group interleaver 122 performs the LDPC coding on the The interleaving can be performed using? (J) defined by the length of the LDPC codeword of 16200 and the coding rate of 10/15.

For example, when the length of the LDPC codeword is 16200 and the coding rate is 10/15 and the modulation scheme is 16-QAM, the group interleaver 122 performs interleaving using? (J) defined as Table 36 can do.

On the other hand, a concrete example of? (J) is as follows.

For example, when the LDPC codeword length _Nldpc is 16200 and the coding rates are 10/15, 11/15, 12/15, and 13/15 and the modulation method is 16-QAM,? (J) Can be defined as follows.

For Table 36, the expression (12) is _{X 0 = Y π (0)} = Y 35, X 1 = Y π (1) = Y 31, X 2 = Y π (2) = Y 39, ..., X ₄₃ = Y _{π (43)} = Y ₁₅ , X ₄₄ = Y _{π (44)} = Y ₄₄ . Accordingly, the group interleaver 122 sets the 0 th group to the 35 th, the 1 st group to 31 th, the 2 nd group to the 39 th, ..., the 43 th group to the 15 th, the 44 th group to 44 The order of a plurality of groups can be rearranged in a group unit by changing the order.

As another example, when the LDPC codeword length _Nldpc is 16200 and the coding rates are 6/15, 7/15, 8/15, 9/15 and the modulation scheme is 64-QAM, π (j) Can be defined as follows.

For Table 37, the expression (12) is _{X 0 = Y π (0)} = Y 18, X 1 = Y π (1) = Y 31, X 2 = Y π (2) = Y 41, ..., X ₄₃ = Y _{? 43} = Y ₄₃ , X ₄₄ = Y _{? 44} = Y ₄₄ . Accordingly, the group interleaver 122 sets the 0th group to 18 th, the 1 st group to 31st, the 2 nd group to 41st, ..., 43rd group to 43rd, 44th group to 44 The order of a plurality of groups can be rearranged in a group unit by changing the order.

As another example, when the LDPC codeword length _Nldpc is 16200 and the coding rates are 10/15, 11/15, 12/15, and 13/15 and the modulation scheme is 256-QAM,? (J) Can be defined as follows.

For Table 38, the expression (12) is _{X 0 = Y π (0)} = Y 4, X 1 = Y π (1) = Y 13, X 2 = Y π (2) = Y 31, ..., X ₄₃ = Y _{? 43} = Y ₄₃ , X ₄₄ = Y _{? 44} = Y ₄₄ . Accordingly, the group interleaver 122 sets the 0th group to the 4th, the 1st group to the 13th, the 2nd group to the 31st, ..., the 43rd group to the 43rd, the 44th group to 44 The order of a plurality of groups can be rearranged in a group unit by changing the order.

As another example, when the LDPC codeword length _Nldpc is 16200 and the coding rates are 6/15, 7/15, 8/15, 9/15 and the modulation scheme is 1024-QAM, π (j) Can be defined as follows.

For Table 39, the expression (12) is _{X 0 = Y π (0)} = Y 10, X 1 = Y π (1) = Y 2, X 2 = Y π (2) = Y 28, ..., X ₄₃ = Y _{? 43} = Y ₄₃ , X ₄₄ = Y _{? 44} = Y ₄₄ . Accordingly, the group interleaver 122 sets the 0th group to the 10th, the 1st group to the 2nd, the 2nd group to the 28th, ..., the 43rd group to the 43rd, the 44th group to 44 The order of a plurality of groups can be rearranged in a group unit by changing the order.

As another example, when the LDPC codeword length _Nldpc is 64,800 and the coding rates are 6/15, 7/15, 8/15, 9/15 and the modulation scheme is 256-QAM, π (j) Can be defined as follows.

For Table 40, Equation (12) is _{X 0 = Y π (0)} = Y 9, X 1 = Y π (1) = Y 6, X 2 = Y π (2) = Y 160, ..., X ₁₇₈ = Y _{17 (178)} = Y ₁₇₇ , X ₁₇₉ = Y _{17 (179)} = Y ₁₇₆ . Accordingly, the group interleaver 122 sets the 0th group to the 9th, the 1st group to the 6th, the 2nd group to the 160th, ..., the 178th group to 177th, the 179th group to 176 The order of a plurality of groups can be rearranged in a group unit by changing the order.

As another example, when the LDPC codeword length _Nldpc is 64,800 and the coding rates are 6/15, 7/15, 8/15, 9/15 and the modulation method is 16-QAM,? (J) Can be defined as follows.

For Table 41, the expression (12) is _{X 0 = Y π (0)} = Y 135, X 1 = Y π (1) = Y 56, X 2 = Y π (2) = Y 178, ..., X ₁₇₈ = Y ₍₁₇₈₎ = Y ₁₃₇ , X ₁₇₉ = Y ₍₁₇₉₎ = Y ₂₆ . Accordingly, the group interleaver 122 sets the 0th group to the 135th, the 1st group to the 56th, the 2nd group to the 178th, ..., the 178th group to 137th, the 179th group to 26 The order of a plurality of groups can be rearranged in a group unit by changing the order.

As another example, when the LDPC codeword length _Nldpc is 64,800 and the coding rates are 10/15, 11/15, 12/15, 13/15 and the modulation scheme is 64-QAM, π (j) Can be defined as follows.

For Table 42, the expression (12) is _{X 0 = Y π (0)} = Y 138, X 1 = Y π (1) = Y 176, X 2 = Y π (2) = Y 114, ..., X ₁₇₈ = Y ₍₁₇₈₎ = Y ₁₅₅ , X ₁₇₉ = Y ₍₁₇₉₎ = Y ₁₃₀ . Accordingly, the group interleaver 122 sets the 0th group to 138th, the 1st group to 176th, the 2nd group to 114th, ..., the 178th group to 155th, the 179th group to 130 The order of a plurality of groups can be rearranged in a group unit by changing the order.

As another example, when the LDPC codeword length _Nldpc is 64800 and the coding rates are 10/15, 11/15, 12/15, and 13/15 and the modulation scheme is 1024-QAM,? (J) Can be defined as follows.

For Table 43, the expression (12) is _{X 0 = Y π (0)} = Y 12, X 1 = Y π (1) = Y 32, X 2 = Y π (2) = Y 13, ..., X ₁₇₈ = Y ₍₁₇₈₎ = Y ₁₅₃ , X ₁₇₉ = Y ₍₁₇₉₎ = Y ₁₆₃ . Accordingly, the group interleaver 122 sets the 0th group to 12th, the 1th group to 32nd, the 2 nd group to 13th, ..., the 178th group to 153th, the 179th group to 163 The order of a plurality of groups can be rearranged in a group unit by changing the order.

In this way, the group interleaver 12 can rearrange the order of the plurality of groups into groups using Equation (12) and Table 36 to Table 43. [

On the other hand, the groups constituting the LDPC codeword are reordered in group units by the group interleaver 122 and then block interleaved by a block interleaver 124, which will be described later. In Table 28 to Table 43, ) With respect to " Order of bits group to be block interleaved ".

According to the above-described method, the group interleaved LDPC codeword is as shown in FIG. Comparing the LDPC codeword shown in FIG. 6 with the LDPC codeword before the group interleaving shown in FIG. 5, it can be seen that the order of a plurality of groups constituting the LDPC codeword is rearranged.

That is, as shown in FIGS. 5 and 6, the LDPC codeword is divided into groups X ₀ , X ₁ ,... , Group X _{Ngroup 1} , and group interleaved to group Y ₀ , group Y ₁ , ... , And group Y _{Ngroup- 1} . In this case, the order in which the groups are arranged by group interleaving can be determined based on Tables 28 to 43. [

The group twisted interleaver 123 interleaves the bits in the same group. That is, the group twist interleaver 123 may rearrange the order of the bits in the same group by changing the order of the bits existing in the same group.

In this case, the group twisted interleaver 123 may cyclically shift the bits in the same group by a predetermined number of bits to rearrange the order of the bits in the same group.

For example, as shown in FIG. 7, the group twist interleaver 123 may cyclically shift the bits included in the group Y ₁ by one bit in the right direction. In this case, as shown in FIG. 7, in the group Y ₁ , 0 th, 1 st, 2 nd, , 358 th, 359 positioned who bit in the second are 1 is clicking shift when the right by bit, cyclic shift of 359 th position 0 before the bit is a group Y ₁ is located at the front side is shifted cyclic in was prior to First, first, second, ... , And the bits located at the 358th position are sequentially shifted by one bit to the right.

In addition, the group twist interleaver 123 may rearrange the order of the bits in each group by cyclically shifting a different number of bits for each group.

For example, the group twist interleaver 123 may cyclically shift the bits included in the group Y ₁ by one bit in the right direction and cyclically shift the bits included in the group Y ₂ by three bits in the right direction .

However, the above-described group twist interleaver 123 may be omitted in some cases.

Further, in the above-described example, the group twist interleaver 123 is described as being disposed after the group interleaver 122, but this is also only an example. That is, the group twist interleaver 123 may be arranged before the group interleaver 122 in that it changes the order of the bits constituting the group in the group but does not change the order of the groups themselves.

The block interleaver 124 interleaves a plurality of ordered reordering groups. Specifically, the block interleaver 124 is composed of a plurality of columns each including a plurality of rows. The block interleaver 124 classifies a plurality of re-arranged groups based on the modulation order determined according to the modulation method, Can be performed.

In this case, the group interleaver 122 can interleave a plurality of groups in which the order of groups is rearranged in groups. Specifically, the block interleaver 124 interleaves the first part (part 1) and the second part 2) may be used to interleave a plurality of groups in accordance with the modulation order.

Specifically, the block interleaver 124 divides each of the plurality of columns into a first part and a second part, sequentially writes a plurality of groups into a plurality of columns constituting the first part in units of a group, (Or a sub-bit group) formed by a predetermined number of bits based on the number of the plurality of columns and dividing the divided groups into a plurality of columns constituting the second part in sequence And interleaving can be performed.

Here, the number of groups interleaved in a group unit may be determined according to at least one of the number of rows and columns constituting the block interleaver 124, the number of groups, and the number of bits included in each group. That is, the block interleaver 124 determines a group to be interleaved in a group of a plurality of groups in consideration of at least one of the number of rows and columns, the number of groups, and the number of bits included in each group constituting the block interleaver 124 Interleaves the group in units of groups, and interleaves the remaining groups. For example, the block interleaver 124 may interleave at least some of the plurality of groups in a group unit using the first part, and may interleave the remaining groups using the second part.

On the other hand, interleaving on a group basis means that bits included in the same group are written in the same column. That is, in the case of a group interleaved on a group basis, the block interleaver 124 writes the bits included in the same group into the same column without dividing the bits, and divides the bits included in the group into groups It is possible to perform interleaving by writing to another column.

Accordingly, the number of rows constituting the first part is a multiple of the number of bits (for example, 360) included in one group, and the number of rows constituting the second part may be smaller than the number of bits contained in one group have.

In addition, all the groups interleaved by the first part are interleaved with the bits included in the same group written in the same column of the first part, and at least one group interleaved by the second part is interleaved by at least two Lt; RTI ID = 0.0 > columns. ≪ / RTI >

Details of this interleaving method will be described later.

On the other hand, the interleaving performed in the group twisted interleaver 123 changes the order of the bits in the group, and the order of the group itself is not changed by interleaving. Therefore, the order of the groups to be block-interleaved in the block interleaver 124, that is, the order of the groups input to the block interleaver 124, can be determined by the group interleaver 122. [ For example, the order of groups to be block interleaved by the block interleaver 124 may be determined by? (J) defined in Tables 28 to 43.

As described above, the block interleaver 124 may be composed of a plurality of columns each including a plurality of rows, and the LDPC codeword may be interleaved by dividing the plurality of columns into at least two parts.

For example, the block interleaver 124 may interleave a plurality of groups constituting an LDPC codeword by dividing each of the plurality of columns into a first part and a second part.

In this case, the block interleaver 124 divides each of the plurality of columns into N (N is an integer of 2 or more) according to whether or not the number of groups constituting the LDPC codeword is an integral multiple of the number of columns constituting the block interleaver 124, And interleaving can be performed.

First, when the number of groups constituting the LDPC codeword is an integral multiple of the number of columns constituting the block interleaver 124, the block interleaver 124 constructs LDPC codewords without dividing each of the plurality of columns into parts A plurality of groups can be interleaved on a group basis.

Specifically, the block interleaver 124 writes a plurality of groups constituting an LDPC codeword in a column direction in each column in a group unit, and each row of a plurality of columns in which a plurality of groups are written in a group unit, so that interleaving can be performed.

In this case, the block interleaver 124 divides the bits included in the group corresponding to the quotient obtained by dividing the number of groups constituting the LDPC codeword by the number of columns constituting the block interleaver 124, , And interleaving can be performed by reading each row of the plurality of columns in which the bits are written, in the row direction.

Hereinafter, for convenience of explanation, the group located at the j-th position after being interleaved by the group interleaver 122 is referred to as a group Y _j .

For example, it is assumed that the block interleaver 124 is composed of C columns each including R ₁ rows. It is assumed that the LDPC codeword is composed of groups of Y _groups , and the number of _groups , Y _group, is a multiple of C.

In this case, the block interleaver 124 divides the number of groups Y groups constituting the LDPC codeword into Y _groups / C groups each of which is Y group / C divided by the number C of columns constituting the block interleaver 124. Therefore, It is possible to sequentially write in the column direction and read the bits written in each column in the row direction to perform interleaving.

For example, as shown in Figure 8, a block interleaver 124 1 from row R ₁ groups to the second row (Y _0), a group of the first column (Y _1), ..., a group (Y _{p -1} ) and light from the bits included in each of the first row of the second column in the first row R ₁ group (Y _p), the group (Y _{p +1),} ..., a group (Y _{q -1)} to each the light with the bit, and ..., from the first row of the first column C ₁ group, R (Y _z), the group (Y _{z +1)} th row, ..., the group (Y _{Ngroup -1),} respectively And read the bits written in each row of the plurality of columns in the row direction.

Accordingly, the block interleaver 124 interleaves all the groups constituting the LDPC codeword group by group.

However, if the number of groups constituting the LDPC codeword is not an integral multiple of the number of columns constituting the block interleaver 124, the block interleaver 124 divides each of the plurality of columns into two parts to obtain an LDPC codeword Interleaving a part of a plurality of constituent groups in units of a group, and interleaving the remaining groups. In this case, the bits included in the group of the remainder when the bits included in the remaining group, that is, the number of groups constituting the LDPC codeword, are divided by the number of columns, are not interleaved in units of groups, It can be divided and interleaved in each column according to the number.

Specifically, the block interleaver 124 may interleave the LDPC codeword by dividing each of the plurality of columns into two parts.

In this case, the block interleaver 124 multiplies a plurality of columns based on the number of columns constituting the block interleaver 124, the number of groups constituting the LDPC codeword and the number of bits constituting each of the plurality of groups, And the second part.

Here, each of the plurality of groups may be constituted by 360 bits. The number of groups constituting the LDPC codeword is determined according to the length of the LDPC codeword and the number of bits included in each group. For example, if an LDPC codeword having a length of 16,200 is divided into groups of 360 bits, the LDPC codeword is divided into 45 groups. An LDPC codeword having a length of 64,800 is divided into groups of 360 bits The DPC codeword can be divided into 180 groups. In addition, the number of columns constituting the block interleaver 124 can be determined according to a modulation method, and a specific example related thereto will be described later.

Accordingly, the number of rows constituting each of the first and second parts is determined based on the number of columns constituting the block interleaver 124, the number of groups constituting the LDPC codeword and the number of bits constituting each of the plurality of groups ≪ / RTI >

Specifically, the first part includes a plurality of LDPC codewords, each of which constitutes an LDPC codeword in accordance with the number of columns constituting the block interleaver 124, the number of groups constituting the LDPC codeword, May be composed of as many rows as the number of bits included in at least one group writable in each group in each of a plurality of columns among the groups of the groups.

The second part may be composed of a plurality of rows excluding rows corresponding to the number of bits contained in at least some groups writable in each of the plurality of columns in each of the plurality of columns in each of the plurality of columns have. Specifically, the number of rows of the second part may have the same value as the quotient of dividing the number of bits included in all bit groups except the group corresponding to the first part by the number of columns constituting the block interleaver 124 . That is, the number of rows of the second part may have the same value as the quotient of dividing the number of bits included in the remaining groups written in the first part of the groups constituting the LDPC codeword by the number of columns.

On the other hand, the block interleaver 124 divides each of the plurality of columns into a first part including a row corresponding to the number of bits included in a group writable in each column in each column and a second part including a remaining row, Each column can be distinguished.

Accordingly, the first part may be composed of a number of bits included in the group, that is, an integer multiple of M. However, as described above, since the number of codeword bits constituting each group can be a divisor of M, the first part may be constituted by a line of an integral multiple of the number of bits constituting each group have.

In this case, the block interleaver 124 can perform interleaving by writing and reading the LDPC codewords in the first part and the second part in the same manner.

Specifically, the block interleaver 124 writes an LDPC codeword in a column direction in a plurality of columns constituting each of the first and second parts, and generates a plurality of LDPC codewords It is possible to perform the interleaving by reading the row in the row direction.

That is, the block interleaver 124 sequentially writes the bits included in at least a part of the groups that can be written in each group in each of the plurality of columns into each of the plurality of columns constituting the first part, The bits included in the remaining groups except for the group are divided into the plurality of columns constituting the second part in the column direction and the bits written to each of the plurality of columns constituting each of the first and second parts are divided into rows Direction and perform interleaving.

In this case, the block interleaver 124 may perform interleaving by dividing the remaining groups except for at least some groups in the plurality of groups based on the number of columns constituting the block interleaver 124.

Specifically, the block interleaver 124 divides the bits included in the remaining group into a plurality of columns, writes each of the divided bits in a column direction to each of a plurality of columns constituting the second part, It is possible to read a plurality of rows constituting the second part written in the row direction and perform interleaving.

That is, the block interleaver 124 stores the number of groups that are written in the first part of the plurality of groups constituting the LDPC codeword, that is, the groups constituting the LDPC codeword, by the remainder The bits included in the group of bits can be divided into the number of columns, and the divided bits can be sequentially written in the columns in each column of the second part.

For example, it is assumed that the block interleaver 124 is composed of C columns each including R ₁ rows. Assume that the LDPC codeword is composed of groups of Y _groups , the group Y _group is not a multiple of C, and A × C + 1 = Y _group (A is an integer larger than 0). That is, when the number of groups constituting the LDPC codeword is divided by the number of columns, it is assumed that the quotient is A and the remainder is 1.

In this case, the block interleaver 124 can be divided into a first part including R ₁ rows and a second part including R ₂ rows, as shown in FIGS. 9 and 10. In this case, R ₁ may be as many as the number of bits included in a group writable in each column in each column, and R ₂ may be a value excluding R ₁ from the number of rows constituting each column.

That is, in the above-described example, the number of groups writable in each column in each column is A, and the first part of each column may be composed of the number of bits contained in A groups, that is, A × M rows.

In this case, the block interleaver 124 writes the bits included in the group that can be written in each group into each column, that is, A groups, into the first part of each column in the column direction.

That is, as shown in FIGS. 9 and 10, the block interleaver 124 divides the group (Y ₀ ), the group (Y ₁ ), ..., and the group (Y ₁ ) into rows from the first row to the R ₁ row constituting the first part of the first column, group (Y _{n -1)} and light the bits included in each of the first group from the row R ₁ row constituting a first part of the second column (Y _n), the group (Y _{n +1)} ,. ., a group (Y _{m -1)} and light the bits included in respective, ..., the first group from the row R ₁ row constituting a first part of the column C (Y _e), group ( Y _{e +1} ), ..., and a group (Y _{Ngroup- 2} ).

In this way, the block interleaver 124 writes the bits included in the group writable in each column in each column into the first part of each column in a group unit.

That is, in the above example, the bits included in each of the group (Y ₀ ), the group (Y ₁ ), ..., and the group (Y _{n -1} ) are all written in the first column without being divided, _n), the group (Y _{n +1),} ..., a group (Y _{m -1)} bits included in each of all are not divided and written into the second column, ..., the group (Y _e), group (Y _{e +1} ), ..., and the group (Y _{Ngroup- 2} ) may all be written to the C column without being divided. Thus, it can be seen that all the bits interleaved by the first part are written into the same column of the first part as the bits included in the same group.

Thereafter, the block interleaver 124 may divide the bits included in the remaining groups except for the group written in the first part of each column among the plurality of groups, and write the bits into the second part of each column in the column direction. At this time, the block interleaver 124 divides the bits included in the remaining groups except for the group written in the first part of each column into the number of columns so that the same number of bits are written in the second part of each column, Can be written in the column direction in each column of the second part.

Here, each divided bit based on the number of columns may be referred to as a sub bit group, in which case each of the sub bit groups may be written to each column of the second part.

(Y _Ngroup-1 ), which is the last group of the LDPC codeword, is written in the first part, when the groups constituting the LDPC codeword are sequentially written into the first part, since A × C + 1 = Y _group is satisfied in the above- 1 It is not written to the part. As a result, the block interleaver 124 is split open-circuit C, and the bits included in a group (Y _{Ngroup -1)} as shown in Figure 9 each of the divided bits (that is, the bits included in the last group (Y _{Ngroup -1)} The bits corresponding to the quotient divided by C) can be sequentially written to the second part of each column.

Here, each divided bit based on the number of columns may be referred to as a sub-bit group, in which case each of the sub-bit groups may be written to each column of the second part. That is, the bits included in the bit group can be divided to form a sub bit group.

That is, a block interleaver 124 from the first line to write a bit from the first line constituting the second part of the first column to the R _2-th row, and constituting a second part of the second column R ₂ row , And write the bits from the first row to the R ₂ -th row constituting the second part of the column C of the second column. At this time, the block interleaver 124 can write the bits in the column direction to the second part of each column as shown in FIG.

That is, in the second part, the bits constituting the bit group can be written in a plurality of columns without being written in the same column. That is, in the above example, since the last group (Y _{Ngroup- 1} ) is composed of M bits, the bits included in the last group (Y _{Ngroup- 1} ) can be divided into M / . That is, the bits included in the last group (Y _{Ngroup- 1} ) are divided into M / C groups, and the divided M / C groups are formed into sub-bit groups, and each sub-bit group can be written to each column of the second part .

Accordingly, it can be seen that at least one group interleaved by the second part is divided into at least two columns constituting the second part and the bits included in at least one group are written.

In the above example, the block interleaver 124 writes bits in the column direction in the second part, but this is merely an example. That is, the block interleaver 124 may write bits in a plurality of columns of the second part in the row direction. In this case, the block interleaver 124 can write the bits for the first part in the same manner as described above.

10, the block interleaver 124 writes bits in the first column from the first row to the first column constituting the second part in the first column to the first column constituting the second part in the first column, R 2 from the _second line constituting a second part in the second light, the bits from the second line to the second line constituting a second part in the C column, ..., and a first column constituting a part in the Bits from the C column to the R ₂ -th row constituting the second part.

On the other hand, the block interleaver 124 sequentially reads the bits written in each row of each part in the row direction. 9 and 10, the block interleaver 124 sequentially reads the bits written in the respective rows of the first part of the plurality of columns in the row direction and sequentially writes the bits written to each row of the second part of the plurality of columns Can be sequentially read out in the row direction.

Accordingly, the block interleaver 124 can interleave a part of a plurality of groups constituting the LDPC codeword group by group and perform interleaving by dividing the remaining part of the groups. That is, the block interleaver 124 writes an LDPC codeword constituting a predetermined number of groups among a plurality of groups into a plurality of columns constituting the first part, and writes the LDPC codeword constituting the remaining group to the second It is possible to divide and write each of the columns constituting the part, and to perform interleaving by reading a plurality of columns constituting the first and second parts in the row direction.

As described above, the block interleaver 124 can interleave a plurality of groups using the method described with reference to FIG. 8 to FIG.

In particular, in the case of FIG. 9, the bits included in the group not belonging to the first part are written in the column direction in the second part and read in the row direction, . In this manner, the bit error rate (FER) / frame error rate (FER) performance can be improved as compared with the case where interleaving is not performed because the bits included in the group not belonging to the first part are interleaved.

However, a group not belonging to the first part as shown in FIG. 10 may not be interleaved. In other words, as shown in FIG. 10, the block interleaver 124 writes and reads the bits included in the group not belonging to the first part in the row direction to the second part, so that the bits included in the group not belonging to the first part The order can be output to the modulation unit 130 sequentially without changing the order. In this case, the bits included in the group not belonging to the first part may be sequentially output and mapped to the modulation symbol.

9 and 10, the last one of the plurality of groups is written to the second part. However, this is only an example, and the number of groups written in the second part is the same as that of the group constituting the LDPC codeword The number of columns and rows, the number of transmission antennas, and the like.

On the other hand, the block interleaver 124 may have a different structure depending on whether the bits included in the same group are mapped to one bit in the modulation symbol or the bits included in the same group are mapped to two bits in the modulation symbol .

On the other hand, in the case of a transmission / reception system using a plurality of antennas, the number of columns constituting the block interleaver 124 may be determined by simultaneously considering the number of bits constituting the modulation symbol and the number of antennas to be used. For example, in the case of a system in which bits included in the same group are mapped to one bit in a modulation symbol and two antennas are used, the block interleaver 124 multiplies the number of columns by two times the number of bits constituting the modulation symbol You can decide.

First, when the bits included in the same group are mapped to one bit in the modulation symbol, the block interleaver 124 may have a structure as shown in Tables 44 and 45 below.

Here, C (or N _c ) is the number of columns constituting the block interleaver 124, R ₁ is the number of rows constituting the first part in each column, R ₂ is the number of rows constituting the second part in each column The number of rows to be processed.

Referring to Table 44 and Table 45, the number of the plurality of columns has the same value as the modulation order according to the modulation scheme, and each of the plurality of columns is divided into a number of rows by a value obtained by dividing the number of bits constituting the LDPC codeword by the number of the columns . ≪ / RTI >

For example, when the length of the LDPC codeword is Nldpc = 64800 and modulation is performed by the 16-QAM method, the modulation order of the 16-QAM is 4, so the block interleaver 124 is composed of four columns, R1 + R2 = 16200 (= 64800/4) rows.

On the other hand, with reference to Table 44 and Table 45, when the number of the group constituting the LDPC codeword times the integer number of columns, the block interleaver 124 is the R ₁ each, in that interleaving without separate each column The number of rows constituting the column becomes R ₂ = 0. When the number of groups constituting the LDPC codeword is not an integral multiple of the number of columns, the block interleaver 124 divides each column into a first part composed of R ₁ rows and a second part composed of R ₂ rows Interleaving is performed by dividing into parts.

On the other hand, when the number of columns of the block interleaver 124 is equal to the number of bits constituting the modulation symbol, as shown in Tables 44 and 45, the bits included in the same group can be mapped to one bit in the modulation symbol.

For example, when N _ldpc = 64800 and the modulation scheme is 16-QAM, the block interleaver 124 may be composed of four columns each including 16,200 rows. In this case, a plurality of groups are written into four columns in a group unit, and the bits written to the same row in each column are sequentially output. In this case, when the modulation scheme is 16-QAM, the bits included in the same group, that is, the bits output from one column, can be mapped to one bit in the modulation symbol in that 4 bits constitute one modulation symbol have. For example, the bits contained in the group written to the first column may be mapped to the first bit of each modulation symbol.

On the other hand, when the bits included in the same group are mapped to two bits in the modulation symbol, the block interleaver 124 may have a structure as shown in Tables 46 and 47 below.

Here, C (or N _c ) is the number of columns constituting the block interleaver 124, R ₁ is the number of rows constituting the first part in each column, R ₂ is the number of rows constituting the second part in each column The number of rows to be processed.

Table 46 and referring to Table 47, constituting the case where the number of groups constituting the LDPC codeword times the integer number of rows block interleaver 124 R ₁ in that it performs the interleaving does not separate each column, each column The number of rows to be processed is R ₂ = 0. When the number of groups constituting the LDPC codeword is not an integral multiple of the number of columns, the block interleaver 124 divides each column into a first part composed of R ₁ rows and a second part composed of R ₂ rows Interleaving is performed by dividing into parts.

When the number of columns of the block interleaver 124 is half of the number of bits constituting the modulation symbol, as shown in Table 46 and Table 47, the bits included in the same group can be mapped to two bits in the modulation symbol.

For example, when N _ldpc = 64800 and the modulation scheme is 16-QAM, the block interleaver 124 may be composed of two columns each including 32400 rows. In this case, a plurality of groups are written into two columns in a group unit, and the bits written to the same row in each column are sequentially output. On the other hand, in the case where the modulation scheme is 16-QAM, bits output from two rows constitute one modulation symbol because 4 bits constitute one modulation symbol. Therefore, the bits included in the same group, i.e., the bits output from one column, can be mapped to two bits in the modulation symbol. For example, the bits contained in the group written to the first column may be mapped to bits present in any two positions in the modulation symbol.

On the other hand, referring to Tables 44 to 47, it can be seen that the number of all the rows of the block interleaver 124, that is, R ₁ + R ₂ is N _ldpc / C.

이고, 제2 파트의 행의 개수인 R₂는 N_ldpc/C-R₁이 될 수 있다. 여기에서,

는 N_group/C 이하의 가장 큰 정수를 나타낸다. 이와 같이, R₁은 각 그룹에 포함된 비트의 개수인 M의 정수 배가 된다는 점에서 R₁에는 그룹 단위의 비트들이 라이트될 수 있다. R ₁ , the number of rows of the first part, is an integer multiple of M (for example, M = 360), which is the number of bits included in each group

And R ₂ , the number of rows of the second part, can be N _ldpc / CR ₁ . From here,

_Represents the largest integer equal to or smaller than N _group / C. In this way, since R ₁ is an integral multiple of M, which is the number of bits included in each group, the bits in group units can be written to R ₁ .

Referring to Tables 44 to 47, when the number of groups constituting the LDPC codeword is not a multiple of the number of columns, the block interleaver 124 divides each column into two parts and performs interleaving .

Specifically, the value obtained by dividing the length of the LDPC codeword by the number of columns is the total number of rows included in each column. At this time, when the number of groups constituting the LDPC codeword is a multiple of the number of columns, each column is not divided into two parts. However, if the number of groups constituting the LDPC codeword is not a multiple of the number of columns, each column can be divided into two parts.

For example, as shown in Table 44, it is assumed that the number of columns of the block interleaver 124 is equal to the number of bits constituting the modulation symbol, and the LDPC codeword is composed of 64,800 bits. At this time, each group constituting the LDPC codeword is composed of 360 bits, and the LDPC codeword is composed of 64 groups of 64800/360 = 180.

On the other hand, when the modulation scheme is 16-QAM, the block interleaver 124 is composed of four columns, and each column can be composed of 64800/4 = 16,200 rows.

At this time, the value obtained by dividing the number of groups constituting the LDPC codeword by the number of columns is 180/4 = 45, so that the bits can be written into each column in each column without dividing each column into two parts. That is, in each column, bits included in 45 groups, that is, 45 × 360 = 16200 bits, which is a quotient obtained by dividing the number of groups constituting the LDPC codeword by the number of columns, can be written.

However, when the modulation scheme is 256-QAM, the block interleaver 124 is composed of 8 columns, and each column can be composed of 64800/8 = 8100 rows.

At this time, since the value obtained by dividing the number of groups constituting the LDPC codeword by the number of columns is 180/8 = 22.5, the number of groups constituting the LDPC codeword is not an integral multiple of the number of columns. Accordingly, the block interleaver 124 divides each of the eight columns into two parts in order to perform interleaving on a group basis.

In this case, since the bits must be written in units of groups in the first part of each column, the number of groups that can be written in the first unit of each column is divided by the number of groups constituting the LDPC codeword by the number of columns The first part of each column can be composed of 22 x 360 = 7920 rows. Accordingly, 7920 bits included in 22 groups can be written in the first part of each column.

On the other hand, the second part of each column is composed of a row excluding all the rows constituting the first part in the entire row of each column. Thus, the second part of each column may consist of 8100-7920 = 180 rows.

At this time, the bits included in the remaining group that can not be written in the first part can be divided and written into the second part of each column.

Specifically, since 22 x 8 = 176 groups are written in the first part, the number of groups written in the second part is 180-176 = 4 (for example, the group (Y ₀ ) constituting the LDPC codeword, (Y _1), the group (Y _2), ..., a group (Y _178), the group (Y ₁₇₉₎ of the group (Y _176), the group (Y _177), the group (Y _178), the group (Y ₁₇₉₎ .

Accordingly, the block interleaver 124 can write the remaining four groups in the first part of the group constituting the LDPC codeword sequentially to the second part of each column.

That is, the block interleaver 124 writes 180 bits out of the 360 bits included in the group Y ₁₇₆ in the column direction from the first row to the 180th row of the second part of the first column, and outputs the remaining 180 bits It is possible to write in the column direction from the first row to the 180th row of the second part of the second column. The block interleaver 124 writes 180 bits out of the 360 bits included in the group Y ₁₇₇ in the column direction from the first row to the 180th row of the second part of the third column and outputs the remaining 180 bits It is possible to write in the column direction from the first row to the 180th row of the second part of the fourth column. The block interleaver 124 writes 180 bits out of the 360 bits included in the group Y ₁₇₈ in the column direction from the first row to the 180th row of the second part of the fifth column and outputs the remaining 180 bits It is possible to write in the column direction from the first row to the 180th row of the second part of the sixth column. The block interleaver 124 writes the 180 bits out of the 360 bits included in the group Y ₁₇₉ in the column direction from the first row to the 180th row of the second part of the seventh column and writes the remaining 180 bits It is possible to write in the column direction from the first row to the 180th row of the second part of the eighth column.

Accordingly, the bits included in the group written in the first part and written in the remaining part can be written into a plurality of columns without being written to the same column in the second part.

Hereinafter, a concrete example of the block interleaver of FIG. 4 will be described in more detail with reference to FIG.

)는 V={Y₀,Y₁,…,

}과 같이 Y_j가 연속적으로 배치될 수 있다. The group interleaved LDPC codeword (v ₀ , v ₁ , ...,

) Is expressed as V = {Y ₀ , Y ₁ , ... ,

Y _j} is such as may be placed consecutively.

After group interleaving, the LDPC codeword can be interleaved by the block interleaver 124 as shown in FIG. In this case, the block interleaver 124 may divide the plurality of columns into the first part and the second part based on the number of columns and the number of bits of the group constituting the block interleaver 124. In this case, the bits constituting the group are written to the same column in the first part, and the bits constituting the group are written to the plurality of columns in the second part.

Specifically, the input bits v _i are serially written in column wise starting from the first part to the second part, and are sequentially written in row wise from the first part to the second part Lead. Accordingly, the bits included in the same group in the first part can be mapped to one bit in each modulation symbol.

)은 360의 배수이므로, 복수의 비트 그룹이 제1 파트에 라이트될 수 있다. In this case, the number of columns and the number of rows of the first part and the second part of the block interleaver 124 according to the modulation scheme and the length (i.e., code length) of the LDPC codeword can be as shown in Table 48 below. Here, the number of columns of the block interleaver 124 may be equal to the number of bits constituting the modulation symbol. The sum of N _r1 , the number of rows of the first part, and N _r2 , the number of rows of the second part, is equal to N _ldpc / N _c , where N _c is the number of columns. Then, N _r1 (=

Is a multiple of 360, a plurality of bit groups can be written to the first part.

Hereinafter, the operation of the block interleaver 124 will be described in more detail.

, r_i=(i mod N_r1)와 같다.Specifically, as shown in FIG. 11, the input bit v _i (0? I <N _c × N _r1 ) is written to the r _i row of the c _i column of the first part of the block interleaver 124. Here, c _i and r _i are

, and r _i = (i mod N _r1 ).

, r_i=N_r1+{(i-N_c×N_r1) mod N_r2}와 같다.Then, the input bits, _{v i (N c × N r1} ≤i <N ldpc) are written into the second part of the column c _i r _i rows of the block interleaver (124). Here, c _i and r _i are

, r _i = N _r1 + {(iN _c × N _r1 ) mod N _r2 }.

, c_j=(j mod N_c)와 같다.On the other hand, the output bit q _j (0≤j <N _ldpc) are read out from the column c _j r _j of the line. Here, c _j and r _j are

, c _j = (j mod N _c ).

For example, when the length N _LDPC of the LDPC codeword is 64800 and the modulation scheme is 256-QAM, the order of bits output from the block interleaver 124 is (q ₀ , q ₁ , q ₂ , q ₆₃₃₅₇ , q ₆₃₃₅₈ , q ₆₃₃₅₉ , q ₆₃₃₆₀ , q ₆₃₃₆₁ , ..., q ₆₄₇₉₉ ) = (v ₀ , v ₇₉₂₀ , v ₁₅₈₄₀ , ..., v ₄₇₅₁₉ , v ₅₅₄₃₉ , v ₆₃₃₅₉ , v ₆₃₃₆₀ , v ₆₃₅₄₀ , ..., v ₆₄₇₉₉ ). Here, if the index in the right-hand term is described in more detail for all eight columns, 0, 7920, 15840, 23760, 31680, 39600, 47520, 55440, 1, 7921, 15841, 23761, 31681, 39601, 47521, 55441, ... , 7919, 15839, 23759, 31679, 39599, 47519, 55439, 63359, 63360, 63540, 63720, 63900, 64080, 64260, 64440, 64620, ... ... , 63539, 63719, 63899, 64079, 64259, 64439, 64619, 64799.

In the example described above, the number of columns constituting the block interleaver 124 has the same value as the modulation order or has the same value as half of the modulation order. However, this is merely an example, and the block interleaver 124 The number of columns constituting may be a multiple value of the modulation order. In this case, the number of rows constituting each column may be a value obtained by dividing the length of the LDPC codeword by the number of columns.

For example, when the modulation scheme is QPSK (that is, the modulation order is 2), the number of columns constituting the block interleaver 124 may be four instead of two. At this time, when the length Nldpc of the LDPC codeword is 16200, the number of rows constituting each column can be 4050 (= 16200/4).

On the other hand, the block interleaver 124 performs interleaving in the same manner as the case where the number of columns has the same value as the modulation order or the same value as half of the modulation order even when the number of columns has a multiple of the modulation order A detailed description thereof will be omitted.

In this case, the number of columns constituting the block interleaver 124 may have the same value as the modulation order or may be an integral multiple of the modulation order, so that the number of rows of the second part is the same as the number of rows excluding the group corresponding to the first part It may have the same value as a quotient obtained by dividing the number of bits included in all bit groups by a modulation order or a multiple of a modulation order.

Returning to FIG. 1, the modulator 130 modulates an interleaved LDPC codeword according to a modulation scheme to generate a modulation symbol. Specifically, the modulator 130 demultiplexes the interleaved LDPC codeword, modulates the demultiplexed LDPC codeword, and maps the constellation to generate a modulation symbol.

In this case, the modulator 130 may generate modulation symbols using the bits included in each of the plurality of groups.

That is, as described above, bits included in different groups are written into each column of the block interleaver 124, and the block interleaver 124 reads the bits written in each column in the row direction. In this case, the modulator 130 maps the bits read from each column of the block interleaver 124 to each bit of the modulation symbol to generate a modulation symbol. Accordingly, each bit of the modulation symbol may be a bit included in a different group.

For example, it is assumed that a modulation symbol is composed of C bits. In this case, in the event that the bits read in each row of the C columns of the block interleaver 124 can be mapped to each bit of the modulation symbol, each bit of the modulation symbol consisting of C bits is eventually divided into C different groups Can be included bits.

Hereinafter, this will be described in more detail.

First, the modulator 130 can demultiplex the interleaved LDPC codeword. For this, the modulator 130 may include a demultiplexer (not shown) for demultiplexing the interleaved LDPC codeword.

A demultiplexer (not shown) demultiplexes the interleaved LDPC codeword. Specifically, a demultiplexer (not shown) performs a serial-to-parallel conversion on an interleaved LDPC codeword to convert an interleaved LDPC codeword into a cell having a predetermined number of bits Or a data cell).

12, a demultiplexer (not shown) receives the LDPC codeword Q = (q ₀ , q ₁ , q ₂ , ...) output from the interleaver 120 and receives The LDPC codeword bits may be sequentially output to one of the plurality of sub-streams, and the input LDPC codeword bits may be converted into cells and output.

Here, the number of _substreams N _substreams is equal to the number of bits η _MOD constituting the modulation symbol, and the number of bits constituting the cell may be equal to N _ldpc / η _MOD . Meanwhile, the number of cells generated according to the length of the η _MOD and the length of the LDPC codeword N _ldpc according to the modulation scheme may be as shown in Table 49 below.

On the other hand, bits having the same index in each of a plurality of sub-streams can constitute the same cell. That is, in each cell 12 _{(y 0, 0, y 1} , 0, ..., y η MOD -1,0), (y 0,1, y 1,1, ..., y η MOD _-1 , 1, ..., and so on.

Meanwhile, a method of demultiplexing the LDPC codeword bits input to the demultiplexer (not shown) may be various. That is, the demultiplexer (not shown) may change the order of the LDPC codeword bits and output the LDPC codeword bits to each of the plurality of sub-streams, or sequentially output the LDPC codeword bits to the plurality of streams without changing the order of the LDPC codeword bits. This operation can be determined according to the number of columns used for interleaving in the block interleaver 124. [

Specifically, when the block interleaver 124 includes a column of half the number of bits constituting the modulation symbol, the demultiplexer (not shown) changes the order of the input LDPC codeword bits so that the sub- And an example of how to change the order is shown in Table 50 below.

For example, in the case of 16-QAM in the modulation scheme shown in Table 50, the number of bits constituting the modulation symbol is four and the number of sub-streams is four in the case of 16-QAM. In this case, a demultiplexer (not shown) outputs bits sequentially satisfying i mod 4 = 0 to the 0th sub-stream among the sequentially input bits, and outputs bits satisfying i mod 4 = 1 The bits satisfying i mod 4 = 2 are outputted as the first sub stream, and the bits satisfying the index i i mod 4 = 3 are output as the third sub stream. have.

Accordingly, the LDPC codeword bits q ₀ , q ₁ , q ₂ , ... input to the demultiplexer (not shown) are (y _{0 , 0} , y _{1 , 0} , y _{2 , 0} , y _{3 , 0) = (q 0, q} 2, q 1, q 3), (y 0,1, y 1,1, y 2,1, y 3,1) = (q 4, q 6, q 5, q ₇ ), ... &lt; / RTI &gt;

If the block interleaver 124 includes the same number of bits as the number of bits constituting the modulation symbol, the demultiplexer (not shown) may sequentially change the order of the input LDPC codeword bits . That is, as illustrated in Figure 13, and sequentially output to a demultiplexer (not shown) is input LDPC codeword bits (q _0, q _1, q _2, ...), each sub-stream, and thus, each cell _{(y 0,0, y 1,0, ...} , y η MOD -1,0) = (q 0, q 1, ..., q η MOD -1), (y 0, 1, y 1, ₁ , ..., y _{η MOD -1,1} ) = (q _{η MOD} , q _{η MOD +1} , ..., q _{2 × ηMOD-1} ) _,.

In the above example, the demultiplexer (not shown) sequentially outputs the LDPC codeword bits to the plurality of streams without changing the order of the input LDPC codeword bits, but this is merely an example. That is, according to an embodiment of the present invention, when the block interleaver 124 includes the same number of columns as the number of bits constituting the modulation symbol, the demultiplexer (not shown) may be omitted.

Meanwhile, the modulator 130 may map the demultiplexed LDPC codeword to the modulation symbol. However, if the demultiplexer (not shown) is omitted as described above, the modulator 130 may map the LDPC codeword bits output from the interleaver 120, i.e., the block interleaved LDPC codeword bits to the modulation symbol have.

Specifically, the modulator 130 modulates bits (i.e., cells) output from the demultiplexer (not shown) into various modulations such as QPSK, 16-QAM, 64-QAM, 256-QAM, 1024- Modulation scheme can be used. Here, when the modulation method is QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM and 4096-QAM, the number of bits η _MOD (ie, modulation order) , 4, 6, 8, 10, and 12, respectively.

In this case, since each cell output from the demultiplexer (not shown) is composed of as many bits as the number of bits constituting the modulation symbol, the modulator 130 sequentially outputs each cell output from the demultiplexer (not shown) To generate a modulation symbol. Here, the modulation symbol corresponds to a constellation point in the constellation.

However, if the demultiplexer (not shown) is omitted, the modulator 130 may sequentially generate a modulation symbol by dividing the interleaved bits by a predetermined number of bits and mapping the interleaved bits to the property points. In this case, the modulator 130 can generate modulation symbols by sequentially using the bits of eta _MOD in accordance with the modulation scheme.

Meanwhile, the modulator 130 may perform modulation by mapping the cells output from the demultiplexer (not shown) to sexual points using a uniform constellation (UC) scheme.

Here, the uniform constellation scheme refers to a scheme of mapping a modulation symbol to a store point so that the real component Re (z _q ) and imaginary component Im (z _q ) of the store point are symmetrical and the modulation symbol is formed at equal intervals. Accordingly, at least two of the modulation symbols mapped to the constellation in the uniform constellation scheme can have the same demodulation performance.

Meanwhile, an example of a method of generating a modulation symbol in a uniform constellation scheme according to an embodiment of the present invention can be shown in the following Tables 51 to 58, and an example of a case of a uniform constellation 64-QAM is shown in FIG. 14 Respectively.

Here, Tables 51 and 52 are used for determining the real component Re (z _q ) and the imaginary component Im (z _q ) in the case of performing modulation in the QPSK scheme, and Tables 53 and 54 are respectively used for determining 16- (Z _q ) and Im (z _q ) in the case of performing modulation in the QAM scheme, and Table 55 and Table 56 are used to determine the real component ( _Req ) in the case of performing modulation in the 64- Re (z _q) and an imaginary component Im (z _q) to be used to determine, Table 57 and Table 58, and the real component Re (z _q) in the case of performing the modulation with 256-QAM scheme imaginary component Im (z _q ).

Referring to Tables 51 to 58, performance (e.g., reliability) varies depending on whether a plurality of bits constituting a modulation symbol correspond to a most significant byte (MSB) and a least significant bit (LSB) Able to know.

For example, in the case of 16-QAM, the first bit and the second bit of the four bits constituting the modulation symbol are the real number component Re (z _q ) and the imaginary number Im (z _q ) are the bits for determining each symbol, and the third and fourth bits are the bits for determining the size of the constellation point to which the modulation symbol is mapped.

In this case, it can be seen that the reliability is higher than the third bit, which is the bits for determining the sign, and the fourth bit, which determine the size, among the four bits constituting the modulation symbol.

As another example, in the case of 64-QAM, the first bit and the second bit of the six bits constituting the modulation symbol are the real number component Re (zq) and imaginary number component Im (zq) of the property point to which the modulation symbol is mapped, respectively Lt; / RTI &gt; The third to sixth bits are bits for determining the size of a property to which a modulation symbol is mapped. Of these, the third bit and the fourth bit determine a relatively large size, and the fifth bit and the sixth bit (E.g., -7, -5) or (-3, -1) to which the modulation symbol is mapped by the third bit is determined, If the third bit determines (-7, -5), the fourth bit determines whether -7 or -5.

In this case, among the six bits constituting the modulation symbol, the first bit, which is a code determining bit, and the third bit and the fourth bit, which are the second most reliable bits and determine a relatively large size, are relatively It can be seen that the reliability is higher than the fifth bit and the sixth bit, which determine the small size.

As described above, in the case of the uniform constellation scheme, the bits constituting the modulation symbol may have different reliability depending on the position mapped in the modulation symbol.

Meanwhile, the modulator 130 may perform modulation by mapping the cells output from the demultiplexer (not shown) to sex points using a non-uniform constellation (NUC) scheme.

Specifically, the modulator 130 demultiplexes the bits output from the demultiplexer (not shown) into non-uniform 16-QAM, non-uniform 64-QAM, non-uniform 256-QAM, non-uniform 1024- 4096-QAM, and the like.

Hereinafter, a method of generating a modulation symbol using a non-uniform constellation scheme according to an embodiment of the present invention will be described.

First, the characteristics of the non-uniform constellation method will be described as follows.

Unlike the uniform constellation scheme, in the non-uniform constellation scheme, the stores may not be regularly arranged. Accordingly, when the non-uniform constellation scheme is used, the SNR of a specific value or less can be improved and a high SNR gain can be obtained as compared with the uniform constellation scheme.

On the other hand, the constellation can be determined by one or more parameters such as the spacing between storages, and the like. In the uniform constellation method, the number of parameters required to specify uniform constellation method can be 1, in that the distribution points are regularly distributed. On the other hand, in the case of the nonuniform constellation method, the number of parameters required to specify the nonuniform constellation method And the number of parameters can be increased as the constellation (for example, the number of stores) increases.

On the other hand, in the case of non-uniform constellation, the x-axis and the y-axis can be designed symmetrically or non-symmetrically. Designing without symmetric can provide better performance, but may increase decoding complexity.

Hereinafter, an example of the case where the design is not simulated is suggested. In this case, if only the sex shop in the first quadrant is defined, the location of the sex shop in the other three quadrants can be determined by the following method. For example, if the set of stores defined for the first quadrant is X, then -conj (X) for the second quadrant, conj (X) for the third quadrant, and - (X) for the fourth quadrant .

In other words, if you define the first quadrant, the other quadrants can be expressed as:

1 Quarter (= 1 quadrant) = X

2 Quarter = -conj (X)

3 Quarter = conj (X)

4 Quarter = -X

Specifically, when non-uniform M-QAM is used, _{M storages} can be defined as z = {z ₀ , z ₁ , ..., z _{M -1} }. In this case, the sex shop in the first quadrant is {x ₀ , x ₁ , x ₂ , ... , x _{M / 4-1} }, z can be defined as follows.

z ₀ to z _{M / 4-1} = x ₀ to x _{M / 4}

z _{M / 4} to z _{2 x M / 4-1} = -conj (x ₀ to x _{M / 4} )

z _{2 x M / 4} to z _{3 x M / 4-1} = conj (x ₀ to x _{M / 4} )

z _{3 x M / 4} to z _{4 x M / 4-1} = - (x ₀ to x _{M / 4} )

을 인덱스로 하는 z_L로 매핑하여, 출력 비트들을 non-uniform constellation 방식으로 성성점에 맵핑할 수 있다. 이러한 방식에 따라 non-uniform constellation 방식에 따른 성상도의 일 예는 도 15 내지 도 19와 같다.Therefore, the modulating unit 130 outputs the output bits [y ₀ , ..., y ₀ ) output from the demultiplexer , y _{m -1} ]

To an index z _L to map output bits to sexual points in a non-uniform constellation scheme. An example of the constellation according to the non-uniform constellation scheme according to this scheme is shown in FIGS. 15 to 19. FIG.

Meanwhile, an example of a concrete method of performing modulation in a non-uniform constellation scheme without modulating in the modulator 130 is shown in Tables 59 to 64 below. That is, according to one embodiment of the present invention, the property points existing in the first quadrant are defined through Tables 59 to 64, the property points existing in the remaining quadrants are defined by the above method, and the non-uniform constellation method Modulation can be performed.

In these Tables 59 to 64, Table 59 shows non-uniform 16-QAM, Tables 60 to 62 show non-uniform 64-QAM, Table 63 and Table 64 show non-uniform 256-QAM, It can be seen that different mapping schemes can be applied.

On the other hand, when non-uniform constellation is designed to simulate the x-axis and the y-axis, it can be expressed similarly to the uniform QAM, and an example is shown in Tables 65 to 68 below.

In Tables 65 to 68, Table 65 and Table 66 are tables for determining the real component Re (z _q ) and the imaginary component Im (z _q ) in the case of performing modulation by the non-uniform 1024-QAM method. That is, Table 65 shows the real part of 1024-QAM, and Table 66 shows the imaginary part of 1024-QAM. Tables 67 and 68 show examples of performing modulation using the non-uniform 1024-QAM method, and show x _i values in Table 65 and Table 66.

As described above, in the non-uniform constellation scheme, the modulation symbols mapped to the property points may have different demodulation performances in that the modulation symbols can be mapped to the property points without being symmetric. That is, the bits constituting the modulation symbol may have different performances.

For example, non-uniform if 64-QAM, see FIG. 15 showing an example of the case of performing modulation in such a manner, the modulation symbols (10) _{(y 0, y 1, y} 2, y 3, y 4, y ₅₎ may be of a = (0,0,1,0,1,0), the modulation performance of the bits configuring the symbol 10 (e.g., capacity) is _{C (y 0)> C (} y 1 )> C (y ₂ )> C (y ₃ )> C (y ₄ )> C (y ₅ )

On the other hand, the constellation in the uniform constellation scheme and the non-uniform constellation scheme can be rotated and / or scaled (where the scaling factors applied to the real and imaginary axes can be the same or different from each other) It is self-evident that it can be applied. In addition, the constellation shown represents the relative position of the constellation point, which may be derived by rotation, scaling and / or other suitable transformations.

In this manner, the modulator 130 can map the modulation symbols to the ST points using a uniform constellation scheme and a non-uniform constellation scheme. In this case, the performance of the bits constituting the modulation symbol may be different from each other as described above.

Meanwhile, the LDPC codeword bits may have different codeword characteristics according to the structure of the parity check matrix. That is, the LDPC codeword bits may have different codeword characteristics according to the number of 1s in the column of the parity check matrix, that is, the column order.

Accordingly, in the present invention, the interleaver 120 performs interleaving so that LDPC codeword bits can be mapped to modulation symbols considering both the codeword characteristics of the LDPC codeword bits and the reliability of the bits constituting the modulation symbol.

In particular, when non-uniform QAM is used, since the bits constituting the modulation symbol are different from each other, the number of columns of the block interleaver 124 is made equal to the number of bits constituting the modulation symbol, So that one of the plurality of groups can be mapped to a bit existing at the same position in each modulation symbol.

That is, when mapping the LDPC codeword bits having excellent decoding performance to the bits having high reliability among the bits constituting the modulation symbol, the decoding performance may be improved at the receiving side, but the LDPC codeword bits A problem that can not be solved can occur. When the LDPC codeword bits having excellent decoding performance are mapped to the bits having poor reliability among the bits constituting the modulation symbol, the initial reception performance is excellent and the overall performance may be excellent. However, Error propagation may occur.

Therefore, when mapping LDPC codeword bits to modulation symbols, LDPC codeword bits having specific codeword characteristics are considered in consideration of both the codeword characteristics of the LDPC codeword bits and the reliability of the bits constituting the modulation symbol. Mapped to a specific bit in the modulation symbol and transmitted to the receiving side. Thus, it is possible to achieve both excellent reception performance and decoding performance on the receiving side.

In this case, in the present invention, the LDPC codeword is divided into groups each consisting of M (= 360) bits having the same codeword characteristics, and the bits are mapped to the bits at specific positions of the modulation symbols on a group basis. It is possible to effectively map the bits having a specific codeword characteristic to a specific position in the modulation symbol. In addition, as described above, the number of bits constituting the group can be a divisor of M. However, for convenience of explanation, the number of codeword bits constituting the group is limited to M.

That is, the modulator 130 may map at least one bit included in a predetermined group among a plurality of groups constituting the LDPC codeword to predetermined bits in the modulation symbol. Here, each of the plurality of groups may be composed of M (= 360) bits.

For example, in case of 16-QAM, at least one bit included in a predetermined group among a plurality of groups may be mapped to the first bit in the modulation symbol, or may be mapped to the first bit and the second bit.

The reason why the modulator 130 maps at least one bit included in a predetermined group among a plurality of groups to a predetermined bit in a modulation symbol is as follows.

As described above, the block interleaver 124 interleaves a plurality of groups constituting the LDPC codeword group by group, a demultiplexer (not shown) demultiplexes the bits output from the block interleaver 124, 130 sequentially map demultiplexed bits (i.e., cells) to modulation symbols.

Therefore, the group interleaver 122 disposed before the block interleaver 124 may be configured such that groups including bits to be mapped to bits in a specific position in the modulation symbol are allocated to the block interleaver 124 (FIG. 1), considering the demultiplexing operation performed in the demultiplexer The LDPC codeword is interleaved on a group basis.

Specifically, the group interleaver 122 rearranges the order of the plurality of groups so that at least one group including the bits mapped to the same positions of the different modulation symbols are arranged in order adjacent to each other, So that the block interleaver 124 writes the predetermined group into the predetermined column. That is, the group interleaver 122 interleaves a plurality of groups constituting the LDPC codeword on a group basis based on the above-mentioned Tables 28 to 43 and outputs at least one Groups are adjacent to each other, and the block interleaver 124 performs interleaving by writing at least one adjacent group to the same column.

Accordingly, the modulator 130 may generate a modulation symbol by mapping the bits output from the predetermined column of the block interleaver 124 to predetermined bits in the modulation symbol. In this case, the bits included in one group may be mapped to one of the bits constituting the modulation symbol or may be mapped to two of the bits constituting the modulation symbol.

For the sake of more detailed explanation, a case of modulating an LDPC codeword having a length of 16200 with a non-uniform 64-QAM will be described as an example.

The group interleaver 122 divides the LDPC codeword into 16200/360 = 45 groups, and performs interleaving of a plurality of groups on a group basis.

In this case, the group interleaver 122 determines the number of groups that can be written in each column of the block interleaver 124 based on the number of columns of the block interleaver 124, and determines a plurality of groups based on the determined number of groups Interleaving can be performed on a group basis.

Here, since the group written in the same column in the block interleaver 124 is mapped to a specific one bit or two specific bits among the bits constituting the modulation symbol according to the number of columns of the block interleaver 124, the group interleaver 122 Takes into account the bit attribute of the modulation symbol, arranges the groups including the bits that need to be mapped to the corresponding bits adjacent to each other, and arranges the plurality of groups so that the array units adjacent to each other are sequentially arranged. Lt; / RTI &gt; In this case, the group interleaver 122 can use Table 29 described above.

Accordingly, the groups adjacent to each other in the interleaved LDPC codeword group can be written in the same column of the block interleaver 124, and the bits written in the same column can be modulated by a modulation unit 130 into a specific one or It is mapped to two bits.

For example, it is assumed that the block interleaver 124 includes as many columns as the number of bits constituting the modulation symbol, i.e., includes six columns. In this case, as shown in Table 44 or Table 48, each column of the block interleaver 124 can be divided into a first part including 2520 rows and a second part including 180 rows.

Accordingly, the group interleaver 122 includes 2520/360 = 7 groups written in the first part of each column of the block interleaver 124 among the plurality of groups and adjacent to each other, Are sequentially arranged. Accordingly, the block interleaver 124 can write the first bits of each column in seven groups, and write the bits included in the remaining three groups into the second part of each column.

Thereafter, the block interleaver 124 may read the bits written in each row of the first part of the plurality of columns in the row direction and read the bits written to each row of the second part of the plurality of columns in the row direction.

That is, the block interleaver 124 writes the bits written in the respective rows of the plurality of columns in the order of the bits written in the first row of the first column to the first row of the sixth column (q ₀ , q ₁ , q ₂ , q ₃ , q ₄ , q ₅ , q ₆ , q ₇ , q ₈ , q ₉ , q ₁₀ , q ₁₁ , ...).

In this case, when the demultiplexer (not shown) is not used or the order of the input bits is not changed in the demultiplexer (not shown), the LDPC codeword bits q ₀ , _{q 1, q 2, q 3} , q 4, q 5), (q 6, q 7, q 8, q 9, q 10, q 11), ... it is modulated by the modulation unit 130. the Q ₆ , q ₇ , q ₈ , q ₉ , q ₁₀ (q ₀ , q ₁ , q ₂ , q ₃ , q ₄ , q ₅ ) output from the block interleaver 124, , q _11), ... are respectively the cells _{(y 0, 0, y 1} , 0, ..., y 5, 0), (y 0, 1, y 1, 1, ..., y 5, 1) ,. And the modulator 130 may generate modulation symbols by mapping the cells to the property points.

Accordingly, the modulator 130 may map the bits output from the same column of the block interleaver 124 to a specific one of the bits constituting the modulation symbol. For example, the modulation unit 130 maps the bits (q ₀ , q ₆ , ...) included in the group written in the first column in the block interleaver 124 to the first bit in the modulation symbol And the bits written in the first column may be the bits determined to be mapped to the first bit of each modulation symbol according to the codeword characteristics of the LDPC codeword bits and the reliability of the bits constituting the modulation symbol.

As described above, the group interleaver 122 divides a plurality of groups constituting the LDPC codeword into groups such that groups including bits to be mapped to one bit at a specific position in the modulation symbol are written in a specific column of the block interleaver 124 Interleaving.

On the other hand, it is assumed that the block interleaver 124 includes the number of bits that constitute the modulation symbol, that is, the number of bits, that is, three columns. In this case, as shown in Table 47, each column of the block interleaver 124 is not divided into parts, and 5400 bits can be written in each column.

Accordingly, in the group interleaver 122, 5400/360 = 15 groups written in each column of the block interleaver 124 among the plurality of groups are adjacent to each other, and the group interleaving is performed so that the array units each composed of 15 groups are sequentially arranged. . Accordingly, the block interleaver 124 can write to each column by 15 groups.

The block interleaver 124 may then read the bits written in each row of the plurality of columns in the row direction.

That is, the block interleaver 124 writes the bits (q ₀ , q ₁ , q (n)) written in each row of the plurality of columns in the order of bits written in the first row of the first column to the first row of the third column ₂ , q ₃ , q ₄ , q ₅ , q ₆ , q ₇ , q ₈ , q ₉ , q ₁₀ , q ₁₁ , ...).

In this case, the demultiplexer (not shown) and on the basis of the table 50 demultiplexes of the LDPC codeword bit output from the block interleaver _{(124) (y 0, 0} , y 1, 0, ..., y 5, 0) = ( _{q 0, q 2, q 4} , q 1, q 3, q 5), (y 0, 1, y 1, 1, ..., y 5, 1) = (q 6, q 8, q 10, q 7 , q ₉ , q ₁₁ ), and the modulator 130 may generate modulation symbols by mapping the cells to the property points.

Accordingly, the modulator 130 may map the bits output from the same column of the block interleaver 124 to specific two bits among the bits constituting the modulation symbol. For example, the modulator 130 is the bits contained in the first column that was light group in the block interleaver 124, the _{(q 0, q 3, q} 6, q 9, ...) from (q _0, q ₆ , ...) to the first bit in the modulation symbol and (q ₃ , q ₉ , ...) to the fifth bit in the modulation symbol, and the bits written in the first column are mapped to the LDPC codeword Bits determined to be mapped to the first and fifth bits of each modulation symbol according to the codeword characteristics of the bits and the reliability of the bits constituting the modulation symbol. Here, the first bit in the modulation symbol is a bit that determines the sign of the real component Re (z _q ) of the mobility point to which the modulation symbol is mapped, and the fifth bit in the modulation symbol is the relative position of the mobility point to which the modulation symbol is mapped It is a bit that determines the small size.

As described above, the group interleaver 122 groups a plurality of groups constituting the LDPC codeword so that groups including bits to be mapped to two bits at a specific position in the modulation symbol are written in a specific column of the block interleaver 124, Interleaving.

Hereinafter, the encoding unit 110 generates LDPC codewords (N _ldpc = 16200) composed of 16200 bits by performing LDPC encoding with code rates of 10/15, 11/15, 12/15, and 13/15, Unit 130 uses a non-uniform 16-QAM modulation scheme corresponding to the coding rate based on Table 59. [

The present invention will be described in more detail by way of specific examples.

For example, the coding unit 110 generates LDPC codewords (N _ldpc = 16200) composed of 16200 bits by performing LDPC coding with coding rates of 10/15, 11/15, 12/15, and 13/15, It is assumed that the modulation unit 130 uses a non-uniform 16-QAM modulation scheme corresponding to the coding rate based on Table 59.

In this case, the group interleaver 122 may perform group interleaving using Equation (11) and Table 28. On the other hand, according to Table 44 or Table 48, the number of columns is 4, the number of rows of the first part is 3960 (= 360 x 11), and the number of rows of the second part is 90 is used .

Accordingly, the eleven groups (X ₃₅ , X ₃₁ , X ₃₉ , X ₁₉ , X ₂₉ , X ₂₀ , X ₃₆ , X ₀ , X ₉ , X ₁₃ , and X ₅ ) constituting the LDPC codeword are connected to the block interleaver (X ₃₇ , X ₁₇ , X ₄₃ , X ₂₁ , X ₄₁ , X ₂₅ , X ₁ , X ₃₃ , X ₂₄ , X ₁₂ , and X ₃₀ ) two is input to the first part-th column of the block interleaver 124, 11 groups _{(X 16, X 32, X} 10, X 28, X 4, X 26, X 8, X 40, X 42, X 3 , X ₆₎ X _2, (three are input to the first part-th column, the 11 groups of the block interleaver _{(124) X 38, X 14} , X 34, X 22, X 18, X 27, X 23, X ₇ , X ₁₁ , and X ₁₅ are input to the first part of the fourth column of the block interleaver 124.

Then, the group X ₄₄ is input to the second part of the block interleaver 124. Specifically, the bits constituting the group X ₄₄ are sequentially input into the rows of the first column of the second part, sequentially input to the rows of the second column, sequentially input to the rows of the third column, Are sequentially input to the rows of the column. In this case, since the group X ₄₄ is composed of 360 bits, 90 bits can be input to the second part of each column.

The block interleaver 124 may successively output the bits input from the first row to the last row of each column and the bits output from the block interleaver 124 may be sequentially input to the modulator 130 . In this case, the demultiplexer (not shown) may be omitted or the demultiplexer (not shown) may sequentially output the input bits without changing the order of the input bits.

Accordingly, one modulation symbol is constituted by one bit included in each of the group X ₃₅ , the group X ₃₇ , the group X _16, and the group X ₂ .

In one embodiment of the present invention, one bit included in each of group X ₃₅ , group X ₃₇ , group X _16, and group X ₂ based on group interleaving and block interleaving includes configuring one modulation symbol , Other methods in which one modulation symbol is composed of one bit included in each of the group X ₃₅ , the group X ₃₇ , the group X _16, and the group X _{2 in} addition to the above-described method may also be included within the scope of the present invention.

On the other hand, in the case of using Equation 11, when the value of? (J) defined by Tables 28 to 35 is applied to the index of the input group and when Equation 12 is used,? (J) Are inversely related to each other in that they are applied as indices of this output group.

On the other hand, the transmitting apparatus 100 can modulate the signal mapped to the constellation and transmit it to the receiving apparatus (e.g., 2700 in Fig. 24). For example, the transmitting apparatus 100 may map a signal mapped to constellation to an OFDM frame using an Orthogonal Frequency Division Multiplexing (OFDM) scheme, and transmit the mapped signal to the receiving apparatus 2700 through the allocated channel.

To this end, the transmitting apparatus 100 includes a frame mapper (not shown) for mapping a signal mapped to constellation to an OFDM frame and a transmitter (not shown) for transmitting an OFDM frame type signal to the receiving apparatus 2700 As shown in FIG.

block- low Interleaver  When to use

In another embodiment of the present invention, the interleaver 120 interleaves the LDPC codeword by a method other than the above-mentioned method, and determines whether bits included in a predetermined group among a plurality of groups constituting the interleaved LDPC codeword are within the modulation symbol To be mapped to a predetermined bit. Reference is made to Fig. 20 for a detailed description.

20, the interleaver 120 includes a parity interleaver 121, a group interleaver (or a group-wise interleaver 122), a group twist interleaver 123 and a block-row interleaver 125 do. Here, the parity interleaver 121 and the group twist interleaver 123 perform the same functions as those described in the first embodiment, so that a detailed description of these components will be omitted.

The group interleaver 122 may classify the parity interleaved LDPC codewords into a plurality of groups, and rearrange the order of the plurality of groups into groups.

In this case, the operation of dividing the parity-interleaved LDPC codewords into a plurality of groups is the same as that in the above-described embodiment, and a detailed description thereof will be omitted.

Meanwhile, the group interleaver 122 interleaves the LDPC codeword group by group. That is, the group interleaver 122 can rearrange the order of a plurality of groups in the LDPC codeword group by changing positions of a plurality of groups constituting the LDPC codeword.

Here, the group interleaver 122 may rearrange the order of the plurality of groups so that the groups including the bits mapped to the same modulation symbol among the plurality of groups are sequentially arranged.

In this case, the group interleaver 122 maps to the same modulation symbol considering the number of rows and columns constituting the block-row interleaver 124, the number of groups constituting the LDPC codeword, the number of bits included in each group, The order of the plurality of groups may be rearranged in units of groups such that the groups including the bits are sequentially arranged.

For this purpose, the group interleaver 122 can interleave the LDPC codewords on a group basis using Equation (13).

Here, X _j denotes the j-th group before the group interleaving, Y _j represents the j th group after group interleaving. Further,? (J) is a parameter indicating an interleaving sequence and may be determined by at least one of the length, the coding rate and the modulation method of the LDPC codeword.

Therefore, X _(j) represents the group of π (j) before group interleaving, and Equation (13) means that the group π (j) before interleaving is interleaved into the jth group after interleaving.

Meanwhile, a concrete example of? (J) according to an embodiment of the present invention can be defined as shown in Tables 69 to 76 below.

In this case,? (J) is defined according to the length and coding rate of the LDPC codeword, and the parity check matrix is also defined according to the length and coding rate of the LDPC codeword. Therefore, when LDPC coding is performed based on a specific parity check matrix according to the length and the coding rate of the LDPC codeword, the LDPC codeword is divided into a group of the LDPC codewords based on? (J) satisfying the length and the coding rate of the LDPC codeword, Lt; / RTI &gt;

For example, when the encoding unit 110 performs LDPC encoding with a coding rate of 10/15 to generate an LDPC codeword having a length of 16,200, the group interleaver 122 performs the LDPC encoding on the basis of Tables 69 to 76 The interleaving can be performed using? (J) defined by the length of the LDPC codeword of 16200 and the coding rate of 10/15.

For example, when the length of the LDPC codeword is 16200, the coding rate is 10/15, and the modulation scheme is 16-QAM, the group interleaver 122 performs interleaving using? (J) defined as Table 69 can do.

On the other hand, a concrete example of? (J) is as follows.

For example, when the LDPC codeword length _Nldpc is 16200 and the coding rates are 10/15, 11/15, 12/15, and 13/15 and the modulation scheme is 16-QAM, π (j) Can be defined as follows.

For Table 69, the equation (13) is _{Y 0 = X π (0)} = X 7, Y 1 = X π (1) = X 42, Y 2 = X π (2) = X 37, ..., Y _{43 = X π (43) =} X 13, can be expressed as _{Y 44 = X π (44)} = X 44. Accordingly, the group interleaver 122 sets the seventh group to the 0th, the 42nd group to the 1st, the 37th to the 2nd, ..., the 13th group to the 43rd, the 44th group to 44 The order of a plurality of groups can be rearranged in a group unit by changing the order.

As another example, when the LDPC codeword length _Nldpc is 16200 and the coding rates are 6/15, 7/15, 8/15, 9/15 and the modulation scheme is 64-QAM, π (j) Can be defined as follows.

For Table 70, the equation (13) is _{Y 0 = X π (0)} = X 32, Y 1 = X π (1) = X 39, Y 2 = X π (2) = X 8, ..., Y ₄₃ = X ₍₄₃₎ = X ₄₃ , Y ₄₄ = X ₍₄₄₎ = X ₄₄ . Accordingly, the group interleaver 122 sets the 32nd group to the 0th, the 39th group to the 1st, the 8th group to the 2nd, the 43rd group to the 43rd, the 44th group to 44 The order of a plurality of groups can be rearranged in a group unit by changing the order.

As another example, when the LDPC codeword length _Nldpc is 16200 and the coding rates are 10/15, 11/15, 12/15, 13/15 and the modulation scheme is 256-QAM,? (J) Can be defined as follows.

For Table 71, the equation (13) is _{Y 0 = X π (0)} = X 28, Y 1 = X π (1) = X 22, Y 2 = X π (2) = X 7, ..., Y ₄₃ = X ₍₄₃₎ = X ₄₃ , Y ₄₄ = X ₍₄₄₎ = X ₄₄ . Accordingly, the group interleaver 122 sets the 28th group to the 0th, the 22nd group to the 1st, the 7th group to the 2nd, the 43rd group to the 43rd, the 44th group to 44 The order of a plurality of groups can be rearranged in a group unit by changing the order.

As another example, when the LDPC codeword length _Nldpc is 16200 and the coding rates are 6/15, 7/15, 8/15, 9/15 and the modulation scheme is 1024-QAM,? (J) Can be defined as follows.

For Table 72, the equation (13) is _{Y 0 = X π (0)} = X 16, Y 1 = X π (1) = X 24, Y 2 = X π (2) = X 32, ..., Y43 = X _{? (43)} = X ₄₃ , Y ₄₄ = X _{? (44)} = X ₄₄ . Accordingly, the group interleaver 122 sets the 16th group to 0, the 24th group to 1, the 32nd to the 2 nd, the 43rd group to the 43rd, the 44th group to 44 The order of a plurality of groups can be rearranged in a group unit by changing the order.

As another example, when the LDPC codeword length _Nldpc is 64800 and the coding rates are 6/15, 7/15, 8/15, 9/15 and the modulation scheme is 256-QAM,? (J) Can be defined as follows.

For Table 73, the equation (13) is _{Y 0 = X π (0)} = X 48, Y 1 = X π (1) = X 152, Y 2 = X π (2) = X 156, ..., Y ₁₇₈ = X _{17 (178)} = X ₁₇₈ , Y ₁₇₉ = X _{17 (179)} = X ₁₇₉ . Accordingly, the group interleaver 122 sets the 48th group to the 0th, the 152th group to the 1st, the 156th group to the 2nd, ..., the 178th group to 178th, the 179th group to 179 The order of a plurality of groups can be rearranged in a group unit by changing the order.

As another example, when the LDPC codeword length _Nldpc is 64,800 and the coding rates are 6/15, 7/15, 8/15, 9/15 and the modulation scheme is 16-QAM,? (J) Can be defined as follows.

For Table 74, the equation (13) is _{Y 0 = X π (0)} = X 121, Y 1 = X π (1) = X 65, Y 2 = X π (2) = X 152, ..., Y ₁₇₈ = X ₍₁₇₈₎ = X ₁₄₆ , Y ₁₇₉ = X ₍₁₇₉₎ = X ₉₆ . Accordingly, the group interleaver 122 divides the 121st group into 0, 65th, 1 st, 152th, ..., 146th, 178th, 176th, The order of a plurality of groups can be rearranged in a group unit by changing the order.

As another example, when the LDPC codeword length _Nldpc is 64,800 and the coding rates are 10/15, 11/15, 12/15, 13/15 and the modulation scheme is 64-QAM,? (J) Can be defined as follows.

For Table 75, the equation (13) is _{Y 0 = X π (0)} = X 49, Y 1 = X π (1) = X 69, Y 2 = X π (2) = X 61, ..., Y ₁₇₈ = X ₍₁₇₈₎ = X ₁₅ , Y ₁₇₉ = X ₍₁₇₉₎ = X ₁₇₆ . Accordingly, the group interleaver 122 sets the 49th group to the 0th, the 69th group to the 1st, the 61st group to the 2nd, ..., the 15th group to 178th, the 176th group to 179 The order of a plurality of groups can be rearranged in a group unit by changing the order.

As another example, when the LDPC codeword length _Nldpc is 64800 and the coding rates are 10/15, 11/15, 12/15, and 13/15 and the modulation scheme is 1024-QAM,? (J) Can be defined as follows.

For Table 76, the equation (13) is _{Y 0 = X π (0)} = X 45, Y 1 = X π (1) = X 46, Y 2 = X π (2) = X 71, ..., Y ₁₇₈ = X ₍₁₇₈₎ = X ₁₆₆ , Y ₁₇₉ = X ₍₁₇₉₎ = X ₁₆₅ . Accordingly, the group interleaver 122 sets the 45th group to the 0th, the 46th group to the 1st, the 71st group to the 2nd, ..., the 166th group to 178th, the 165th group to 179 The order of a plurality of groups can be rearranged in a group unit by changing the order.

In this way, the group interleaver 122 can rearrange the order of the plurality of groups into groups using Equation (13) and Table 69 to Table 76. [

Meanwhile, the group interleaver 122 may interleave the LDPC codewords group by group using Equation (14).

Here, X _j denotes the j-th group before the group interleaving, Y _j represents the j th group after group interleaving. Further,? (J) is a parameter indicating an interleaving sequence and may be determined by at least one of the length, the coding rate and the modulation method of the LDPC codeword.

Accordingly, Y _{? (J)} represents the? (J) th group after the group interleaving, and Equation (14) means that the jth group before interleaving is interleaved into? (J) th group after interleaving.

Meanwhile, a specific example of? (J) according to an embodiment of the present invention can be defined as shown in Tables 77 to 84 below.

In this case,? (J) is defined according to the length and coding rate of the LDPC codeword, and the parity check matrix is also defined according to the length and coding rate of the LDPC codeword. Therefore, when LDPC coding is performed based on a specific parity check matrix according to the length and the coding rate of the LDPC codeword, the LDPC codeword is divided into a group of the LDPC codewords based on? (J) satisfying the length and the coding rate of the LDPC codeword, Lt; / RTI &gt;

For example, when the encoding unit 110 performs LDPC encoding with a coding rate of 10/15 in order to generate an LDPC codeword having a length of 16,200, the group interleaver 122 performs the LDPC encoding in the following Tables 77 to 84 The interleaving can be performed using? (J) defined by the length of the LDPC codeword of 16200 and the coding rate of 10/15.

For example, if the length of the LDPC codeword is 16200, the coding rate is 10/15, and the modulation scheme is 16-QAM, the group interleaver 122 performs interleaving using? (J) defined as Table 77 can do.

On the other hand, a concrete example of? (J) is as follows.

For example, when the LDPC codeword length _Nldpc is 16200 and the coding rates are 10/15, 11/15, 12/15, and 13/15 and the modulation scheme is 16-QAM, π (j) Can be defined as follows.

For Table 77, Equation 14 _{X 0 = Y π (0)} = Y 11, X 1 = Y π (1) = Y 38, X 2 = Y π (2) = Y 27, ..., X ₄₃ = Y _{π (43)} = Y ₁₃ , X ₄₄ = Y _{π (44)} = Y ₄₄ . Accordingly, the group interleaver 122 sets the 0th group to 11th, the 1st group to 38th, the 2nd group to 27th, the 43rd group to 17th, the 44th group to 44 The order of a plurality of groups can be rearranged in a group unit by changing the order.

In another example, when the LDPC codeword length _Nldpc is 16200 and the coding rates are 6/15, 7/15, 8/15, 9/15 and the modulation scheme is 64-QAM,? (J) Can be defined as follows.

For Table 78, Equation 14 _{X 0 = Y π (0)} = Y 26, X 1 = Y π (1) = Y 22, X 2 = Y π (2) = Y 41, ..., X ₄₃ = Y _{? 43} = Y ₄₃ , X ₄₄ = Y _{? 44} = Y ₄₄ . Accordingly, the group interleaver 122 sets the 0th group to 26th, the 1 st group to 22nd, the 2 nd group to the 41st, ..., the 43rd group to the 43rd, the 44th group to 44 The order of a plurality of groups can be rearranged in a group unit by changing the order.

As another example, when the LDPC codeword length _Nldpc is 16200 and the coding rates are 10/15, 11/15, 12/15, and 13/15 and the modulation scheme is 256-QAM, π (j) Can be defined as follows.

For Table 79, Equation 14 _{X 0 = Y π (0)} = Y 32, X 1 = Y π (1) = Y 26, X 2 = Y π (2) = Y 14, ..., X ₄₃ = Y _{? 43} = Y ₄₃ , X ₄₄ = Y _{? 44} = Y ₄₄ . Accordingly, the group interleaver 122 sets the 0th group to 32nd, the 1 st group to 26th, the 2 nd group to 14th, ..., the 43rd group to the 43rd, the 44th group to 44 The order of a plurality of groups can be rearranged in a group unit by changing the order.

As another example, when the LDPC codeword length N _ldpc is 16200 and the coding rates are 6/15, 7/15, 8/15, 9/15 and the modulation method is 1024-QAM, π (j) Can be defined as follows.

For Table 80, Equation 14 _{X 0 = Y π (0)} = Y 22, X 1 = Y π (1) = Y 20, X 2 = Y π (2) = Y 7, ..., X ₄₃ = Y _{? 43} = Y ₄₃ , X ₄₄ = Y _{? 44} = Y ₄₄ . Accordingly, the group interleaver 122 sets the 0th group to 22nd, the 1st group to the 20th, the 2nd group to the 7th, ..., the 43rd group to the 43rd, the 44th group to 44 The order of a plurality of groups can be rearranged in a group unit by changing the order.

As another example, when the LDPC codeword length N _ldpc is 64800 and the coding rates are 6/15, 7/15, 8/15, 9/15 and the modulation method is 256-QAM, π (j) Can be defined as follows.

For Table 81, Equation 14 _{X 0 = Y π (0)} = Y 72, X 1 = Y π (1) = Y 48, X 2 = Y π (2) = Y 55, ..., X ₁₇₈ = Y _{17 (178)} = Y ₁₇₈ , X ₁₇₉ = Y _{17 (179)} = Y ₁₇₉ . Accordingly, the group interleaver 122 sets the 0th group to 72nd, the 1st group to 48th, the 2nd group to 55th, ..., the 178th group to 178th, the 179th group to 179 The order of a plurality of groups can be rearranged in a group unit by changing the order.

As another example, when the LDPC codeword length _Nldpc is 64,800 and the coding rates are 6/15, 7/15, 8/15, 9/15 and the modulation scheme is 16-QAM, π (j) Can be defined as follows.

For Table 82, Equation 14 _{X 0 = Y π (0)} = Y 3, X 1 = Y π (1) = Y 45, X 2 = Y π (2) = Y 175, ..., X ₁₇₈ = Y ₍₁₇₈₎ = Y ₁₁ , X ₁₇₉ = Y ₍₁₇₉₎ = Y ₁₀₄ . Accordingly, the group interleaver 122 sets the 0th group to the 3rd, the 1st group to the 45th, the 2nd group to the 175th, ..., the 178th group to the 11th, the 179th group to 104 The order of a plurality of groups can be rearranged in a group unit by changing the order.

As another example, when the LDPC codeword length _Nldpc is 64,800 and the coding rates are 10/15, 11/15, 12/15, 13/15 and the modulation scheme is 64-QAM, π (j) Can be defined as follows.

For Table 83, Equation 14 _{X 0 = Y π (0)} = Y 112, X 1 = Y π (1) = Y 161, X 2 = Y π (2) = Y 147, ..., X ₁₇₈ = Y ₍₁₇₈₎ = Y ₃₅ , and X ₁₇₉ = Y ₍₁₇₉₎ = Y ₆₄ . Accordingly, the group interleaver 122 sets the 0th group to 112, the 1 st group to 161, the 2 nd group to 147, ..., the 178th group to the 35th, the 179th group to 64 The order of a plurality of groups can be rearranged in a group unit by changing the order.

As another example, when the LDPC codeword length _Nldpc is 64800 and the coding rates are 10/15, 11/15, 12/15, and 13/15 and the modulation scheme is 1024-QAM, π (j) Can be defined as follows.

For Table 84, Equation 14 _{X 0 = Y π (0)} = Y 120, X 1 = Y π (1) = Y 141, X 2 = Y π (2) = Y 130, ..., X ₁₇₈ = Y ₍₁₇₈₎ = Y ₉₈ , X ₁₇₉ = Y ₍₁₇₉₎ = Y ₁₉ . Accordingly, the group interleaver 122 sets the 0th group to 120th, the 1st group to 141st, the 2 nd group to 130th, ..., the 178th group to 98th, the 179th group to 19 The order of a plurality of groups can be rearranged in a group unit by changing the order.

In this way, the group interleaver 122 can rearrange the order of the plurality of groups into groups using Equation (14) and Table 77 to Table 84. [

The groups constituting the LDPC codeword are rearranged in groups by the group interleaver 122 and then block interleaved by a block interleaver 124 to be described later. In Table 69 to Table 84, π (j ) With respect to " Order of bits group to be block interleaved ".

In the case of performing group interleaving based on Table 69 to Table 84, the order of the groups constituting the group interleaved LDPC codeword is different from the groups constituting the group interleaved LDPC codeword on the basis of Tables 28 to 43 do.

This is because the block-row interleaver 125 is used instead of the block interleaver 124 in this embodiment. That is, since the interleaving scheme used in the block interleaver 124 is different from the interleaving scheme used in the block-row interleaver 125, the group interleaver 122 in the present embodiment performs LDPC The order of the plurality of groups constituting the codeword is rearranged.

Specifically, the group interleaver 122 may rearrange the order of the plurality of groups so that the at least one group including the bits mapped to the same modulation symbol is repeatedly arranged in units of groups.

That is, the group interleaver 122 may include one of a plurality of first groups including bits mapped to a specific first position of the modulation symbol, a plurality of second groups including bits mapped to a specific second position of the modulation symbol One of a plurality of nth groups including a bit mapped to a specific n-th position of the modulation symbol, ..., and the remaining groups may be repeatedly arranged in the same manner.

The block-row interleaver 125 interleaves a plurality of ordered reordering groups. In this case, the block-row interleaver 125 may interleave a plurality of ordered reordering groups using at least one row of a plurality of columns. Refer to Figs. 21 to 23 for a more detailed description.

FIGS. 21 to 23 are diagrams for explaining the structure and interleaving method of a block-row interleaver according to an embodiment of the present invention.

First, when N _group / m is an integer, the block-row interleaver 125 includes an interleaver 125-1 composed of m rows each including M columns as shown in FIG. 21, and a block-row interleaver 125-1 125 may perform interleaving using N _group / m interleavers 125-1 having the structure as shown in FIG.

Here, N _group is the total number of groups constituting the LDPC codeword. M is the number of bits included in one group, and may be 360, for example. M may be equal to the number of bits constituting the modulation symbol or may be 1/2 of the number of bits constituting the modulation symbol have. For example, when non-uniform QAM is used, since the bits constituting the modulation symbol are different from each other, the value of m is made equal to the number of bits constituting the modulation symbol, To be mapped to one bit.

Specifically, the block-row interleaver 125 writes each of the plurality of groups constituting the LDPC codeword in the row direction on each row in the group unit, and writes each column of the plurality of rows written in the plurality of groups in the group It is possible to perform interleaving by reading in the column direction.

For example, as shown in FIG. 21, the block-row interleaver 125 writes m consecutive groups out of a plurality of groups in row direction to each of m rows constituting the interleaver 125-1, Each row of the m number of rows can be read in the column direction. In this case, a quotient obtained by dividing the number of groups by the number of rows, that is, N _group / m interleavers 125-1 can be used.

In this manner, when the number of groups constituting the LDPC codeword is an integral multiple of the number of rows, the block-row interleaver 125 can perform interleaving by sequentially writing groups as many as the number of rows among a plurality of groups .

On the other hand, when the number of groups constituting the LDPC codeword does not become an integer multiple of the number of rows, the block-row interleaver 125 outputs N (N is an integer of 2 or more) interleavers including a different number of columns So that interleaving can be performed.

×m이고,

는 N_group/m 이하의 가장 큰 정수를 나타낸다.For example, as shown in FIGS. 22 and 23, the block-row interleaver 125 includes a first interleaver 125-2 including m rows each including M columns, and a first interleaver 125-2 including a × M / Interleaving can be performed using a second interleaver 125-3 including m rows. Here, a is an N _group -

X m,

_Represents the largest integer of N _group / m or less.

개가 이용될 수 있고, 제2 인터리버(125-3)는 1 개가 이용될 수 있다. In this case, the first interleaver 125-2

And one of the second interleaver 125-3 can be used.

×m 개 그룹 각각을 그룹 단위로 각 행에 행 방향으로 라이트하고,

×m 개 그룹이 그룹 단위로 라이트된 복수의 행의 각 열을 열 방향으로 리드하여 인터리빙을 수행할 수 있다.Specifically, the block-row interleaver 125 selects one of a plurality of groups constituting the LDPC codeword

X m groups are written in the row direction in each row in groups,

X m groups can be interleaved by reading each column of a plurality of rows written in group units in the column direction.

×m 개 그룹 중에서 행의 개수와 동일한 개수의 연속된 m 개의 그룹을 제1 인터리버(125-2)의 각 행에 행 방향으로 라이트하고, m 개의 그룹이 라이트된 제1 인터리버(125-2)의 복수의 행의 각 열을 열 방향으로 리드할 수 있다. 이 경우, 도 22 및 도 23과 같은 구조를 갖는 제1 인터리버(125-2)가

개만큼 이용될 수 있다.For example, as shown in FIGS. 22 and 23, the block-row interleaver 125

M consecutive groups of the same number as the number of rows among the m groups are written in each row of the first interleaver 125-2 in the row direction and the first interleaver 125-2 in which m groups are written, Each column of the plurality of rows of columns can be read in the column direction. In this case, the first interleaver 125-2 having the structure as shown in Figs. 22 and 23

&Lt; / RTI &gt;

Also, m may be a product of the number of bits constituting the modulation scheme and the number of antennas in a system using multiple antennas.

Thereafter, the block-row interleaver 125 divides the bits included in the remaining groups except for the group written in the first interleaver 125-2, and writes the bits in the row direction in each row of the second interleaver 125-3 . At this time, the same number of bits can be written in each row of the second interleaver 125-3. That is, one bit group may be input to a plurality of rows of the second interleaver 125-3.

For example, as shown in FIG. 22, the block-row interleaver 125 converts the bits included in the remaining groups except the group written in the first interleaver 125-2 into m M × m / m in the row direction for each row, and each column of m rows of the second interleaver 125-3 in which the bits are written can be read in the column direction. In this case, one second interleaver 125-3 having the structure as shown in Fig. 22 can be used.

However, according to another embodiment of the present invention, as shown in FIG. 23, the block-row interleaver 125 writes bits in the same manner as described in FIG. 22 for the first interleaver 125-2 And the second interleaver 125-3 may write the bits in a manner different from the method described with reference to FIG.

That is, the block-row interleaver 125 can write the bits in the column direction to the second interleaver 125-3.

For example, as shown in FIG. 23, the block-row interleaver 125 converts the bits included in the remaining groups except for the group written in the first interleaver 125-2 into the bits constituting the second interleaver 125-3 it is possible to write the bits in each column of m rows consisting of a 占 M / m columns in the column direction and to read each column of m rows of the bits of the second interleaver 125-3 in the column direction. In this case, one second interleaver 125-3 having the structure as shown in FIG. 23 may be used.

23, the block-row interleaver 125 writes the bits to the second interleaver in the column direction, reads the bits in the column direction, and performs interleaving. Accordingly, the bits included in the group interleaved by the second interleaver are read in the written order and output to the modulation unit 130. [ Accordingly, the bits included in the group belonging to the second interleaver can be sequentially mapped to the modulation symbols without being rearranged in order by the block-row interleaver 125. As such, the block-row interleaver 125 may perform interleaving for at least some of the plurality of groups and not for interleaving for the remaining groups. Specifically, the block-row interleaver 125 sequentially writes LDPC codewords constituting at least some of the plurality of groups into a plurality of rows and reads them in the column direction to perform interleaving, but interleaves the remaining groups I can not. That is, since the block-row interleaver 125 writes and reads the bits included in the remaining groups in the same direction, the bits included in the remaining groups can be output without changing the order.

Also, in the above example, the bits included in the remaining group are written and read in the column direction, but this is merely an example. That is, the block-row interleaver 125 may write and read the bits included in the remaining group in the row direction. In this case, the bits included in the remaining groups can be output without changing the order.

As described above, the block-row interleaver 125 can interleave a plurality of groups using the method described in FIGS. 21 to 23. FIG.

In accordance with such a scheme, the output of the block-row interleaver 125 may be the same as the output of the block interleaver 124. Specifically, when the block-row interleaver 125 performs interleaving as shown in FIG. 21, it outputs the same value as the block interleaver 124 performing the interleaving as shown in FIG. 8, and the block-row interleaver 125 outputs 9, interleaving is performed as shown in FIG. 9, and the block-row interleaver 125 outputs the same value as the block interleaver 124 performing interleaving as shown in FIG. 9. When the block-row interleaver 125 performs interleaving as shown in FIG. 23, And outputs the same value as the block interleaver 124 to be performed.

Specifically, if the group interleaver 122 is used and the block interleaver 124 is used based on Equation (11), the output groups of the group interleaver 122 are denoted by Y _i (0? J <N _group ) When the group interleaver 122 is used and the block-row interleaver 125 is used, if the output groups of the group interleaver 122 are Z _i (0? J &lt; N _group ) The relationship between Z _i and Y _i can be expressed as Equation (15) and Equation (16) below, so that the same value can be output in the block interleaver (124).

로, 블록 인터리버(124)를 사용할 경우 제 1 파트의 하나의 열에 입력되는 그룹의 개수를 의미하며,

는 N_group/m 이하의 가장 큰 정수이다. 그리고, m은 변조 심볼을 구성하는 비트의 개수와 동일하거나, 변조 심볼을 구성하는 비트의 절반일 수 있다. 또한, m은 블록 인터리버(124)의 열의 개수를 의미하고, m은 블록-로우 인터리버(125)의 행의 개수를 의미한다.Here, α =

Means the number of groups input to one column of the first part when the block interleaver 124 is used,

Is the largest integer less than or equal to N _group / m. And, m may be equal to the number of bits constituting the modulation symbol, or may be one-half of the bits constituting the modulation symbol. M denotes the number of rows of the block interleaver 124, and m denotes the number of rows of the block-row interleaver 125. [

Accordingly, the modulator 130 can map the bits output from the block-row interleaver 125 to the modulation symbols in the same manner as using the block interleaver 124. [

4, the bit interleaving method proposed in the present invention is composed of a parity interleaver 121, a group interleaver 122, a group twisted interleaver 123 and a block interleaver 124 , The parity interleaver 121, or the group twisted interleaver 123 may be omitted). However, the present invention is not limited to the above-described three modules or four modules.

For example, in the present invention, when a block interleaver is used and a group interleaving method expressed by Equation (13) is used, bit groups X _j (0? _J <N _group ) defined as Equation (9) with respect to, the m number of bit groups, for _{example, {X π (i),} X π (α + i), ..., X π ((m-1) × α + i)} (0≤i <α) So that the bits belonging to the modulation symbol constitute one modulation symbol.

이다. 그리고, m은 블록 인터리버의 열의 개수를 의미하며, 이는 변조 심볼을 구성하는 비트의 개수 또는 변조 심볼을 구성하는 비트의 개수의 절반일 수 있다.Here,? Is the number of bit groups constituting the first part of the block interleaver,? =

to be. And m denotes the number of columns of the block interleaver, which may be half the number of bits constituting the modulation symbol or the number of bits constituting the modulation symbol.

Thus, one embodiment, with respect to interleaved parity bits _{u i, {u π (i} ) + j, u π (α + i) + j, ..., u π ((m-1) × α + i _{) + j} } (0 <i? m, 0 < _j ? M) can constitute one modulation symbol. As described above, there are various methods for constructing one modulation symbol.

20, the bit interleaving scheme proposed by the present invention includes a parity interleaver 121, a group interleaver 122, and a group twisted interleaver 123 block-row interleaver 125 as shown in FIG. 20 Accordingly, the group twisted interleaver 123 may be omitted). However, the present invention is not limited to the above-described three or four modules.

For example, in the present invention, when a block-row interleaver is used and a group interleaving scheme expressed by Equation 12 is used, bit groups X _j (0? _J < N with respect to the _group), m bits of the group, for _{example, {X π (m × i} ), X π (m × i + 1), ..., X π (m × i + (m-1))} (0 &Lt; i &lt; a) constitute one modulation symbol.

이다. 그리고, m은 블록 인터리버의 열의 개수를 의미하며, 이는 변조 심볼을 구성하는 비트의 개수 또는 변조 심볼을 구성하는 비트의 개수의 절반일 수 있다.Here,? Is the number of bit groups constituting the first part of the block interleaver,? =

to be. And m denotes the number of columns of the block interleaver, which may be half the number of bits constituting the modulation symbol or the number of bits constituting the modulation symbol.

Thus, one embodiment, with respect to the parity interleaved bits _{u i, {u π (m} × i) + j, u π (m × i + 1) + j, ..., u π (m × i + (m _{-1)) + j} } (0 <i? M, 0 < _j ? M) can constitute one modulation symbol. As described above, there are various methods for constructing one modulation symbol.

Meanwhile, in the present invention, the transmission apparatus 100 may use an interleaving scheme differently according to a set including at least one of a coding rate, an LDPC codeword length, and a modulation scheme.

For example, the transmitting apparatus 100 may perform interleaving using a block interleaver 124 in a first set including a specific coding rate, a length of an LDPC codeword, and a modulation scheme, In the second set including the specific code rate, the length of the LDPC codeword, and the modulation scheme, interleaving can be performed using the block-row interleaver 125.

24 is a block diagram illustrating a configuration of a receiving apparatus according to an embodiment of the present invention. 24, a receiving apparatus 2700 includes a demodulator 2710, a multiplexer 2720, a deinterleaver 2730, and a decoder 2740.

The demodulation unit 2710 receives and demodulates the signal transmitted from the transmission apparatus 100. Specifically, the demodulator 2710 demodulates the received signal to generate a value corresponding to the LDPC codeword, and outputs the value to the multiplexer 2720. In this case, the demodulator 2710 can perform demodulation so as to correspond to the modulation scheme used in the transmitter 100.

To this end, the transmitting apparatus 100 may transmit information on the modulation scheme to the receiving apparatus 2700, or the transmitting apparatus 100 may transmit the information on the modulation scheme to the receiving apparatus 2700 using modulation schemes pre- Can be performed.

Here, the value corresponding to the LDPC codeword can be expressed by the channel value for the received signal. There are various methods for determining the channel value, for example, a method of determining a log likelihood ratio (LLR) value.

The LLR value can be represented by a value obtained by taking a log as a ratio of the probability that the bits transmitted from the transmitting apparatus 100 are 0 and the probability of one day. Alternatively, the LLR value may be a bit value determined according to a hard decision, and the LLR value may be a representative value determined according to a period in which the probability that the bit transmitted from the transmitting apparatus 100 is 0 or 1 .

The multiplexer 2720 multiplexes the output value of the demodulator 2710 and outputs it to the deinterleaver 2730.

Specifically, the multiplexer 2720 is a component corresponding to a demultiplexer (not shown) included in the transmission apparatus 100, and performs an operation corresponding to a demultiplexer (not shown). Therefore, when the demultiplexer (not shown) is omitted from the transmitting apparatus 100, the multiplexer 2720 of the receiving apparatus 2700 can be omitted.

That is, the multiplexer 2720 can perform cell-to-bit conversion of the output value of the demodulator 2710 and output the LLR value in units of bits.

In this case, when the demultiplexer (not shown) does not change the order of the LDPC codeword bits as shown in FIG. 13, the multiplexer 2720 does not change the order of the LLR values corresponding to the bits constituting the cell, LLR values can be sequentially output. Alternatively, the multiplexer 2720 may rearrange the order of the LLR values corresponding to the bits that make up the cell to be the inverse of the demultiplexing operation performed in the demultiplexer (not shown) based on Table 50. [ Information on whether or not the demultiplexing operation is performed may be provided from the transmission apparatus 100 or may be stored in advance between the transmission apparatus 100 and the reception apparatus 2700.

The deinterleaver 2730 deinterleaves the output value of the multiplexer 2720 and outputs it to the decoding unit 2740.

Specifically, the deinterleaver 2730 corresponds to the interleaver 120 of the transmission apparatus 100, and performs an operation corresponding to the interleaver 120. FIG. That is, the deinterleaver 2730 deinterleaves the LLR value by performing the interleaving operation performed by the interleaver 120 inversely.

To this end, the deinterleaver 2730 may include components as shown in FIG. 25 and FIG.

25, the deinterleaver 2730 may include a block deinterleaver 2731, a group twist deinterleaver 2732, a group deinterleaver 2733, and a parity deinterleaver 2734.

The block deinterleaver 2731 deinterleaves the output of the multiplexer 2720 and outputs it to the group twist deinterleaver 2732.

Specifically, the block deinterleaver 2731 is a component corresponding to the block interleaver 124 included in the transmitting apparatus 100, and can perform the interleaving operation performed in the block interleaver 124 inversely.

That is, the block deinterleaver 2731 writes the LLR value output from the multiplexer 2720 in each row in the row direction, using at least one row composed of a plurality of columns, It is possible to perform deinterleaving by reading the column in the column direction.

In this case, when the block interleaver 124 divides a column into two parts and performs interleaving, the block deinterleaver 2731 can perform deinterleaving by dividing a row into two parts.

When the block interleaver 124 writes and reads in a row direction to a group not belonging to the first part, the block deinterleaver 2731 writes the value corresponding to the group not belonging to the first part in the row direction, And perform the de-interleaving.

Hereinafter, the block deinterleaver 2731 will be described with reference to FIG. However, this is merely an example, and it goes without saying that the block deinterleaver 2731 can be implemented by other methods.

,

이다.The input LLR v _i (0? I <N _ldpc ) is written to the r _i row, c _i column of the block deinterleaver 2431. From here,

,

to be.

,

이다.On the other hand, the output LLR q _i (0? I <N _c × N _r1 ) is read from the c _i column and the r _i row of the first part of the block deinterleaver 2431. From here,

,

to be.

,

이다.The output _{LLR q i (N c × N} r1 ≤i <N ldpc) is lead from the second part of the column c _i, r _i the row of the block deinterleaver (2431). From here,

,

to be.

The group twist deinterleaver 2732 deinterleaves the output value of the block deinterleaver 2431 and outputs it to the group deinterleaver 2733.

Specifically, the group twist deinterleaver 2732 is a component corresponding to the group twist interleaver 123 provided in the transmission apparatus 100, and can inversely perform the interleaving operation performed in the group twist interleaver 123 .

That is, the group twist deinterleaver 2732 can rearrange the LLR values in the same group by changing the order of the LLR values existing in the same group. On the other hand, if the group twist operation is not performed in the transmitting apparatus 100, the group twist deinterleaver 2732 may be omitted.

The group deinterleaver 2733 (or group-wise deinterleaver) deinterleaves the output value of the group twist deinterleaver 2732 and outputs it to the parity deinterleaver 2734.

Specifically, the group deinterleaver 2733 is a component corresponding to the group interleaver 122 provided in the transmitting apparatus 100, and can perform the interleaving operation performed in the group interleaver 122 inversely.

That is, the group deinterleaver 2733 can rearrange the order of the plurality of groups into groups. In this case, the group deinterleaver 2733 may reverse the interleaving scheme of Tables 28 to 43 according to the length, modulation scheme, and coding rate of the LDPC codeword so that the order of the plurality of groups can be rearranged in groups.

On the other hand, as described above, the order of the column groups in the parity check matrix having the form of FIG. 2 and FIG. 3 can be changed, and the column group corresponds to the bit group. Accordingly, when the order of the column groups of the parity check matrix is changed, the sequence of the bit groups may be changed to correspond to the sequence of the bit groups, and the group deinterleaver 2733 may rearrange the order of the plurality of groups into groups.

The parity deinterleaver 2734 performs parity deinterleaving on the output value of the group deinterleaver 2733 and outputs it to the decoding unit 2740.

Specifically, the parity deinterleaver 2734 is a component corresponding to the parity interleaver 121 provided in the transmitting apparatus 100, and can perform the interleaving operation performed in the parity interleaver 121 inversely. That is, the parity deinterleaver 2734 can deinterleave the LLR values corresponding to the parity bits among the LLR values output from the group deinterleaver 2733. In this case, the parity deinterleaver 2734 can deinterleave the LLR values corresponding to the parity bits inverse to the parity interleaving method of Equation (8). However, the parity deinterleaver 2734 may be omitted according to the decoding method and implementation of the decoding unit 2740.

The deinterleaver 2730 of FIG. 24 may be composed of three or four components as shown in FIG. 25, but the operation of the components may be performed by one component. For example, a bit group of X _a, X _b, X _c, if one of the bits belonging to each bit group to form one modulation symbol with respect to the X _d, a received one in the deinterleaver (2730) for Based on the modulation symbols, to positions corresponding to the bit groups.

For example, when the coding rate is 12/15 and the modulation scheme is 16-QAM, the group deinterleaver 2733 can perform deinterleaving based on Table 28. [

In this case, one bit included in each of the bit groups X ₃₅ , X ₃₇ , X ₁₆ , and X ₂ constitutes one modulation symbol. One bit in the bit groups X ₃₅ , X ₃₇ , X ₁₆ , and X ₂ constitutes one modulation symbol. Therefore, the deinterleaver 2730 generates bit groups X ₃₅ and X ₃₇ , X ₁₆ , and X ₂ , respectively.

27, the deinterleaver 2730 may include a block-low deinterleaver 2735, a group twist deinterleaver 2732, a group deinterleaver 2733, and a parity deinterleaver 2734. In this case, since the group twist deinterleaver 2732 and the parity deinterleaver 2734 perform the same functions as those of FIG. 25, a detailed description of the overlapping portions will be omitted.

The block-row deinterleaver 2735 deinterleaves the output value of the multiplexer 2720 and outputs it to the group twist deinterleaver 2732.

Specifically, the block-low deinterleaver 2735 is a component corresponding to the block-row interleaver 125 included in the transmitting apparatus 100, and performs the interleaving operation performed in the block-row interleaver 125 inversely can do.

That is, the block-row deinterleaver 2735 writes the LLR value output from the multiplexer 2720 in the column direction in the column direction, using at least one column of the plurality of rows, It is possible to carry out deinterleaving by reading each row in the column direction.

However, if the block-row interleaver 125 writes and reads in the column direction for a group not belonging to the first part, the block-row deinterleaver 2735 outputs the value corresponding to the group not belonging to the first part as a column Lt; RTI ID = 0.0 &gt; and / or &lt; / RTI &gt;

The group deinterleaver 2733 deinterleaves the output value of the group twist deinterleaver 2732 and outputs it to the parity deinterleaver 2734.

Specifically, the group deinterleaver 2733 is a component corresponding to the group interleaver 122 provided in the transmitting apparatus 100, and can perform the interleaving operation performed in the group interleaver 122 inversely.

That is, the group deinterleaver 2733 can rearrange the order of the plurality of groups into groups. In this case, the group deinterleaver 2733 may rearrange the order of the plurality of groups in units of groups by applying the interleaving scheme of Table 69 to Table 84 inversely according to the length, modulation method, and coding rate of the LDPC codeword.

On the other hand, the deinterleaver 2730 of FIG. 24 may be composed of three or four components as shown in FIG. 27, but the operation of the components may be performed by one component. For example, a bit group of X _a, X _b, X _c, if one of the bits belonging to each bit group to form one modulation symbol with respect to the X _d, a deinterleaver (2730) the received single Based on the modulation symbols, to positions corresponding to the bit groups.

To this end, the transmitting apparatus 100 transmits various kinds of information used for performing the interleaving in the interleaver 120 to the receiving apparatus 2700, or the transmitting apparatus 100 transmits the information to the receiving apparatus 2700 in a predetermined manner To perform interleaving.

The decoding unit 2740 can perform LDPC decoding using the output value of the deinterleaver 2730. For this, the decoding unit 2740 may include an LDPC decoder (not shown) for performing LDPC decoding.

More specifically, the decoding unit 2740 is a component corresponding to the encoding unit 110 of the transmission apparatus 100 and performs LDPC decoding using the LLR value output from the deinterleaver 2730 to correct errors have

For example, the decoding unit 2740 may perform LDPC decoding using iterative decoding based on a sum-product algorithm. Here, the summing algorithm is a kind of message passing algorithm, and the message passing algorithm is a method of exchanging messages (e.g., LLR values) via edges on a bipartite graph, It shows an algorithm for calculating and updating an output message from input messages.

 Meanwhile, the decoding unit 2740 may use a parity check matrix for LDPC decoding. In this case, the information word sub-matrix in the parity check matrix is defined as shown in Tables 4 to 27 according to the code rate and the length of the LDPC codeword, and the parity sub-matrix may have a double diagonal structure.

Information on the parity check matrix used in the LDPC decoding, information on the coding rate, and the like may be stored in the receiving apparatus 2700 or may be provided from the transmitting apparatus 100.

28 is a flowchart for explaining a signal processing method of a transmitting apparatus according to an embodiment of the present invention.

First, LDPC coding is performed to generate an LDPC codeword (S3010).

Thereafter, the LDPC codeword is interleaved (S3020). For example, when the length Nldpc of the LDPC codeword is 16200 and the coding rates are 10/15, 11/15, 12/15, and 13/15 and the modulation scheme is 16-QAM In this case,? (J) can be defined as shown in Table 28 below. The interleaved LDPC codeword is modulated according to a modulation scheme to generate a modulation symbol (S3030).

In step S3020, the LDPC codewords are grouped into a plurality of groups, the order of the plurality of groups is rearranged in units of groups, and a plurality of columns each including a plurality of rows are used to convert the modulation order A plurality of groups may be separated and interleaved.

In this case, each of the plurality of columns is divided into a first part and a second part, and a plurality of groups are sequentially written into a plurality of columns constituting the first part in units of a bit group, It is possible to divide the bit groups into bit groups each consisting of a predetermined number of bits based on the number of columns and sequentially write the divided bit groups into a plurality of columns constituting the second part to perform interleaving.

Here, the number of the plurality of columns has the same value as the modulation order according to the modulation method, and each of the plurality of columns can be constituted by a row corresponding to a value obtained by dividing the number of bits constituting the LDPC codeword by the number of the plurality of columns.

In the first part, in each of the plurality of columns, a bit group is assigned to each of a plurality of columns of the plurality of bit groups constituting the LDPC codeword according to the number of the plurality of columns, the number of bit groups, And the second part is constituted by a plurality of rows in each of a plurality of columns, and each of the plurality of columns comprises a plurality of columns, And may be composed of a row excluding a number of rows as many as the number of bits included in at least some bit groups as far as possible.

In this case, the number of rows of the second part may have the same value as the quotient of dividing the number of bits included in all bit groups except the bit group corresponding to the first part by the number of the plurality of columns.

Meanwhile, in step S3020, the bits included in at least some bit groups writable in units of bit groups are sequentially written into each of the plurality of columns constituting the first part, and the remaining bits excluding at least some bit groups in the plurality of bit groups The bits included in the bit group can be divided based on the number of the plurality of columns and sequentially written into each of the plurality of columns constituting the second part.

In this case, in step S3020, bits included in the remaining bit groups are divided into a plurality of columns, each of the divided bits is written in a column direction in each of a plurality of columns constituting the second part, A plurality of columns constituting the two parts can be read in the row direction and interleaving can be performed.

Meanwhile, the modulation order may be 2, 4, 6, 8, 10, or 12 when the modulation method is QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM or 4096-QAM.

Meanwhile, a non-transitory computer readable medium may be provided in which a program for sequentially performing the signal processing method according to the present invention is stored.

A non-transitory readable medium is a medium that stores data for a short period of time, such as a register, cache, memory, etc., but semi-permanently stores data and is readable by the apparatus. In particular, various applications or programs may be stored on non-volatile readable media such as CD, DVD, hard disk, Blu-ray disk, USB, memory card, ROM,

Although the buses are not shown in the above-described block diagrams for the transmitting apparatus and the receiving apparatus, the communication between the respective elements in each apparatus may be performed via the bus. Further, each apparatus may further include a processor such as a CPU, a microprocessor, or the like that performs the various steps described above.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the present invention.

100: transmitting apparatus 110:
120: interleaver 130:

Claims (14)

In the transmitting apparatus,
An encoding unit for performing LDPC encoding to generate an LDPC codeword;
An interleaver for interleaving the LDPC codeword; And
And a modulator for modulating the interleaved LDPC codeword according to a modulation scheme to generate a modulation symbol,
The interleaver includes:
A group interleaver for grouping the LDPC codewords into a plurality of bit groups and rearranging the order of the plurality of bit groups in group units; And
And a block interleaver configured by a plurality of columns each including a plurality of rows and for interleaving the plurality of rearranged bit groups based on a modulation order determined according to the modulation scheme,
Wherein the block interleaver comprises:
Wherein each of the plurality of bits is divided into a first part and a second part, and the plurality of bit groups are sequentially written into a plurality of columns constituting the first part in units of a bit group, Wherein the plurality of bit groups are divided into a bit group composed of a predetermined number of bits based on the number of the plurality of columns and the divided bit groups are sequentially written into a plurality of columns constituting the second part to perform interleaving. The method according to claim 1,
Wherein the number of the plurality of columns has the same value as the modulation order according to the modulation method,
Wherein each of the plurality of columns comprises:
And the number of bits constituting the LDPC codeword is divided by the number of the plurality of columns. The method according to claim 1,
The first part,
Wherein in each of the plurality of columns, in each of the plurality of columns constituting the LDPC codeword according to the number of the plurality of columns, the number of bit groups, and the number of bits constituting each bit group, And the number of bits included in at least a part of the bit groups which can be written,
The second part comprises:
And a row in each of the plurality of columns excluding rows corresponding to the number of bits included in at least a part of bit groups that can be written in each bit group in each of the plurality of columns in a row constituting each of the plurality of columns . The method of claim 3,
Wherein the number of rows of the second part,
Wherein a number of bits included in all bit groups except a bit group corresponding to the first part is equal to a quotient obtained by dividing the number of bits included in the block interleaver by the number of columns constituting the block interleaver. The method of claim 3,
Wherein the block interleaver comprises:
And writes the bits included in at least a part of the bit groups writable in units of the bit groups sequentially into each of the plurality of columns constituting the first part, And sequentially writes the bits included in the second part into each of the plurality of columns constituting the second part by dividing the included bits based on the number of the plurality of columns. In the fifth aspect,
Wherein the block interleaver comprises:
Dividing the bits included in the remaining bit group into the number of the plurality of columns and writing each of the divided bits in a column direction to each of a plurality of columns constituting the second part, And the interleaving is performed by reading a plurality of columns constituting the two parts in the row direction. 3. The method of claim 2,
The modulation order is expressed by:
Wherein when the modulation scheme is QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM, A signal processing method of a transmitting apparatus,
Performing LDPC coding to generate an LDPC codeword;
Interleaving the LDPC codeword; And
Modulating the interleaved LDPC codeword according to a modulation scheme to generate a modulation symbol,
Wherein the interleaving comprises:
Grouping the LDPC codewords into a plurality of groups and rearranging the order of the plurality of groups into groups; And
And dividing and rearranging the plurality of reordering groups based on a modulation order determined according to the modulation scheme using a plurality of columns each including a plurality of rows,
Wherein the grouping and interleaving of the plurality of reordering groups comprises:
Wherein each of the plurality of groups is divided into a first part and a second part, and the plurality of groups are sequentially written into a plurality of columns constituting the first part in units of a bit group, And the interleaving is performed by sequentially writing the divided bit groups to a plurality of columns constituting the second part. 9. The method of claim 8,
Wherein the number of the plurality of columns has the same value as the modulation order according to the modulation method,
Wherein each of the plurality of columns comprises:
And the number of bits constituting the LDPC codeword is divided by the number of the plurality of columns. 9. The method of claim 8,
The first part,
Wherein in each of the plurality of columns, in each of the plurality of columns constituting the LDPC codeword according to the number of the plurality of columns, the number of bit groups, and the number of bits constituting each bit group, And the number of bits included in at least a part of the bit groups which can be written,
The second part comprises:
And a row in each of the plurality of columns excluding rows corresponding to the number of bits included in at least a part of bit groups that can be written in each bit group in each of the plurality of columns in a row constituting each of the plurality of columns . 11. The method of claim 10,
Wherein the number of rows of the second part,
Wherein the number of bits included in all bit groups except for the bit group corresponding to the first part is the same as a quotient obtained by dividing the number of bits by the number of the plurality of columns. 11. The method of claim 10,
Wherein the interleaving comprises:
And writes the bits included in at least a part of the bit groups writable in units of the bit groups sequentially into each of the plurality of columns constituting the first part, Dividing the included bits based on the number of the plurality of columns, and sequentially writing the divided bits to each of the plurality of columns constituting the second part. 13. The method according to claim 12,
Wherein the interleaving comprises:
Dividing the bits included in the remaining bit group into the number of the plurality of columns and writing each of the divided bits in a column direction to each of a plurality of columns constituting the second part, Wherein a plurality of columns constituting the two parts are read in the row direction and interleaving is performed. 10. The method of claim 9,
The modulation order is expressed by:
Wherein when the modulation method is QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM, the signal processing method is 2, 4, 6, 8, 10 and 12.

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