KR102493349B1 - Transmitting apparatus and signal processing method thereof - Google Patents

Abstract

A transmission device is started. The transmitter includes an encoder that performs LDPC encoding to generate an LDPC codeword, an interleaver that interleaves the LDPC codeword, and a modulator that modulates the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. A group interleaver that groups LDPC codewords into a plurality of bit groups and rearranges the order of the plurality of bit groups in units of groups, each composed of a plurality of columns including a plurality of rows, and a modulation order determined according to a modulation method and a block interleaver for separating and interleaving a plurality of bit groups rearranged based on the basis of the above, wherein the block interleaver divides each of a plurality of columns into a first part and a second part, and divides the plurality of bit groups into a plurality of plurality constituting the first part. Sequentially written in units of bit groups in the columns of , dividing the bits constituting the remaining bit groups into bit groups each consisting of a predetermined number of bits based on the number of a plurality of columns, and dividing the divided bit groups into a plurality of groups constituting the second part. Performs interleaving by sequentially writing to the columns of .

Description

Transmission device and its signal processing method { TRANSMITTING APPARATUS AND SIGNAL PROCESSING METHOD THEREOF }

The present invention relates to a transmitting device and a signal processing method thereof, and more particularly, to a transmitting device for processing and transmitting data and a signal processing method thereof.

In a communication/broadcasting system, link performance may significantly deteriorate due to various noise and fading phenomena of channels and inter-symbol interference (ISI). Therefore, in order to implement high-speed digital communication/broadcasting systems that require high data throughput and reliability, such as next-generation mobile communication, digital broadcasting, and portable Internet, it is required to develop techniques for overcoming noise, fading, and inter-symbol interference. . As part of research to overcome noise, etc., research on error-correcting codes has recently been actively conducted as a method for increasing reliability of communication by efficiently restoring distortion of information.

The LDPC (Low Density Parity Check) code, first introduced by Gallager in the 1960s, has been forgotten for a long time due to the complexity that was difficult to implement at the technical level at the time. However, as the turbo code proposed by Berrou, Glavieux, and Thitimajshima in 1993 showed performance approaching Shannon's channel capacity, many interpretations were made on the performance and characteristics of the turbo code, resulting in iterative decoding. A lot of research has been conducted on iterative decoding and graph-based channel coding. With this as an opportunity, as LDPC codes were re-researched in the late 1990s, decoding was performed by applying iterative decoding based on the sum-product algorithm on the Tanner graph corresponding to the LDPC codes. It was found to have performance approaching that of the discussion channel capacity.

When an LDPC code is transmitted using a higher-order modulation method, performance may vary depending on a method of mapping codeword bits to higher-order modulation bits. Therefore, a method of mapping the LDPC codeword bits to higher order modulation bits is required for an LDPC code having excellent performance.

The present invention has been made in accordance with the above-described needs, and an object of the present invention is a transmitter capable of mapping bits included in a preset group among a plurality of groups constituting an LDPC codeword to preset bits in a modulation symbol and transmitting the same, and a signal thereof It is to provide a processing method.

In order to achieve the above object, a transmitter according to an embodiment of the present invention includes an encoder for generating an LDPC codeword by performing LDPC encoding, an interleaver for interleaving the LDPC codeword, and the interleaved LDPC according to a modulation method. A modulator for modulating codewords to generate modulation symbols, wherein the interleaver groups the LDPC codeword into a plurality of bit groups and rearranges the order of the plurality of bit groups in a group unit; and a block interleaver configured of a plurality of columns including rows, and classifying and interleaving the rearranged plurality of bit groups based on a modulation order determined according to the modulation method, wherein the block interleaver separates each of the plurality of columns. Divided into a first part and a second part, the plurality of bit groups are sequentially written in bit group units to a plurality of columns constituting the first part, and the bits constituting the remaining bit groups are written according to the number of the plurality of columns. and interleaving is performed by sequentially writing the divided bit groups into a plurality of columns constituting the second part.

Here, the number of the plurality of columns has the same value as the modulation order according to the modulation method, and each of the plurality of columns has rows equal to the value obtained by dividing the number of bits constituting the LDPC codeword by the number of the plurality of columns can be configured.

In addition, the first part may include the plurality of bit groups constituting the LDPC codeword according to the number of the plurality of columns, the number of bit groups, and the number of bits constituting each bit group in each of the plurality of columns. It consists of as many rows as the number of bits included in at least some bit groups that can be written in units of bit groups in each of the columns of , and the second part is in each of the plurality of columns, in a row constituting each of the plurality of columns. Each of the plurality of columns may include rows excluding as many rows as the number of bits included in at least some bit groups that can be written in units of bit groups.

Here, the number of rows of the second part may have a value equal to a quotient obtained by dividing the number of bits included in all bit groups except for the bit group corresponding to the first part by the number of columns constituting the block interleaver. there is.

In addition, the block interleaver sequentially writes the bits included in at least some of the bit groups that can be written in units of bit groups to each of a plurality of columns constituting the first part, and at least some of the bit groups in the plurality of bit groups. The bits included in the remaining bit groups except for may be divided based on the number of the plurality of columns and sequentially written to each of the plurality of columns constituting the second part.

Here, the block interleaver divides the bits included in the remaining bit group by the number of the plurality of columns, and writes each of the divided bits to each of the plurality of columns constituting the second part in a column direction; Interleaving may be performed by reading a plurality of columns constituting the first part and the second part in a row direction.

Meanwhile, the modulation order may be 2, 4, 6, 8, 10, or 12 when the modulation scheme is QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, or 4096-QAM.

Meanwhile, a signal processing method of a transmitter according to an embodiment of the present invention includes generating an LDPC codeword by performing LDPC encoding, interleaving the LDPC codeword, and converting the interleaved LDPC codeword according to a modulation scheme. Modulating to generate modulation symbols, wherein the interleaving includes grouping the LDPC codewords into a plurality of groups, rearranging the order of the plurality of groups in units of groups, and including a plurality of rows, respectively. and interleaving the rearranged plurality of groups by using a plurality of columns based on a modulation order determined according to the modulation method, wherein the rearranged plurality of groups are separated and interleaved. Each of a plurality of columns is divided into a first part and a second part, the plurality of groups are sequentially written in units of bit groups to the plurality of columns constituting the first part, and the bits constituting the remaining groups are written in the plurality of columns. Based on the number of columns, each bit group is divided into a predetermined number of bits, and the divided bit groups are sequentially written to a plurality of columns constituting the second part to perform interleaving.

Here, the number of the plurality of columns has the same value as the modulation order according to the modulation method, and each of the plurality of columns consists of rows equal to the value obtained by dividing the number of bits constituting the LDPC codeword by the number of the plurality of columns It can be.

In addition, the first part may include the plurality of bit groups constituting the LDPC codeword according to the number of the plurality of columns, the number of bit groups, and the number of bits constituting each bit group in each of the plurality of columns. It consists of as many rows as the number of bits included in at least some bit groups that can be written in units of bit groups in each of the columns of , and the second part is in each of the plurality of columns, in a row constituting each of the plurality of columns. Each of the plurality of columns may include rows excluding as many rows as the number of bits included in at least some bit groups that can be written in units of bit groups.

Here, the number of rows of the second part may have a value equal to a quotient obtained by dividing the number of bits included in all bit groups except for the bit group corresponding to the first part by the number of columns.

In addition, the interleaving step may include sequentially writing the bits included in at least some of the bit groups that can be written on a bit group basis to each of a plurality of columns constituting the first part, and at least some of the bits in the plurality of bit groups. Bits included in the remaining bit groups excluding the group may be divided based on the number of the plurality of columns and sequentially written in each of the plurality of columns constituting the second part.

Here, the step of interleaving divides the bits included in the remaining bit group by the number of the plurality of columns, writes each of the divided bits to each of the plurality of columns constituting the second part in a column direction, , Interleaving may be performed by reading a plurality of columns constituting the first part and the second part in a row direction.

Meanwhile, the modulation order may be 2, 4, 6, 8, 10, or 12 when the modulation scheme is QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, or 4096-QAM.

According to various embodiments of the present invention, better decoding and reception performance can be provided.

1 is a block diagram for explaining the configuration of a transmission device according to an embodiment of the present invention;
2 and 3 are diagrams for explaining the structure of a parity check matrix according to an embodiment of the present invention;
4 is a block diagram for explaining the structure of an interleaver according to an embodiment of the present invention;
5 to 7 are diagrams showing how LDPC codewords are processed in groups according to an embodiment of the present invention;
8 to 11 are diagrams for explaining the structure and interleaving method of a block interleaver according to an embodiment of the present invention;
12 and 13 are diagrams for explaining the operation of a demultiplexer according to an embodiment of the present invention;
14 is a diagram for explaining an example of a uniform constellation modulation scheme according to an embodiment of the present invention;
15 to 19 are diagrams for explaining an example of a non uniform constellation modulation scheme according to an embodiment of the present invention;
20 is a block diagram for explaining the structure of an interleaver according to another embodiment of the present invention;
21 and 23 are diagrams for explaining the structure and interleaving method of a block-row interleaver according to an embodiment of the present invention;
24 is a block diagram for explaining the configuration of a receiving device according to an embodiment of the present invention;
25 and 27 are block diagrams for explaining the structure of a deinterleaver according to an embodiment of the present invention;
26 is a diagram for explaining a block deinterleaver according to an embodiment of the present invention;
28 is a flowchart for explaining a signal processing method according to an embodiment of the present invention.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

1 is a block diagram for explaining the configuration of a transmission device according to a first embodiment of the present invention. According to FIG. 1 , a transmitter 100 includes an encoder 110, an interleaver 120, and a modulator 130 (or may be referred to as a 'constellation mapper').

The encoder 110 performs LDPC (Low Density Parity Check) encoding to generate an LDPC codeword. To this end, the encoder 110 may include an LDPC encoder (not shown) that performs LPDC encoding.

Specifically, the encoder 110 may generate an LDPC codeword composed of information word bits and parity bits (ie, LDPC parity bits) by performing LDPC encoding on input bits into information word bits. . In this case, since the LPDC code is a systematic code, information word bits may be included in the LDPC codeword as it is.

In this case, the LDPC codeword is composed of information word bits and parity bits. For example, the _LDPC codeword is composed of N ldpc bits and may include information word bits composed of K _ldpc bits and parity bits composed of N _parity =N _ldpc -K _ldpc bits.

In this case, the encoder 110 may generate an LDPC codeword by performing LDPC encoding based on a parity check matrix (PCM). That is, since the process of performing LDPC encoding is a process of generating LDPC codewords to satisfy H·C ^T =0, the encoder 110 may use a parity check matrix during LDPC encoding. Here, H represents a parity check matrix and C represents an LDPC codeword.

To this end, the transmitting device 100 may have a separate memory to store various types of parity check matrices in advance.

For example, the transmitting device 100 may use DVB-C2 (Digital Video Broadcasting-Cable version 2), DVB-S2 (Digital Video Broadcasting-Satellite-Second Generation), DVB-T2 (Digital Video Broadcasting-Second Generation Terrestria), and the like. A parity check matrix defined in the standard may be pre-stored, or a parity check matrix defined in the North American Digital Broadcasting Standard System ATSC (Advanced Television Systems Committee) 3.0 standard currently being standardized may be pre-stored. However, this is only an example, and the transmitter 100 may pre-store parity check matrices of various types in addition to this.

Hereinafter, the structure of the parity check matrix will be described in detail with reference to FIGS. 2 and 3 .

Referring to FIG. 2 , a parity check matrix 200 is composed of an information word sub-matrix 210, which is a sub-matrix corresponding to information word bits, and a parity sub-matrix 220, which is a sub-matrix corresponding to parity bits. An element of the parity check matrix 200 excluding 1 is 0.

The information submatrix 210 includes K _ldpc columns, and the parity submatrix 220 includes N _parity =N _ldpc -K _ldpc columns. Meanwhile, the number of rows of the parity check matrix 200 is equal to the number of columns of the parity submatrix 220, N _parity =N _ldpc -K _ldpc .

Also, in the parity check matrix 200, N ldpc represents the length of an _LDPC codeword, K _ldpc represents the length of information word bits, and N _parity =N _ldpc -K _ldpc represents the length of parity bits. Here, the lengths of the LDPC codeword, information word bits, and parity bits mean the number of bits included in each of the LDPC codeword, information word bits, and parity bits.

Hereinafter, structures of the information submatrix 210 and the parity submatrix 220 will be described.

The information submatrix 210 is a matrix including K _ldpc columns (ie, 0-th column to K _ldpc -1-th column), and follows the following rules.

First, K _ldpc columns constituting the information word submatrix 210 belong to the same group by M each, and are divided into a total of K _ldpc /M column groups. Columns belonging to the same column group have a relationship in which they are cyclically shifted by Q _ldpc .

Here, M is an interval at which a column pattern is repeated in the information word submatrix 210 (eg, M=360), and Q _ldpc is a size at which each column in the information word submatrix 210 is cyclically shifted. M and Q _ldpc are integers, and are determined such that Q _ldpc =(N _ldpc -K _ldpc )/M holds. At this time, K _ldpc /M also becomes an integer. Meanwhile, M and Q _ldpc may have various values according to the length and code rate of the LDPC codeword.

For example, when M = 360 and the length N ldpc of the _LDPC codeword is 64800, Q _ldpc is defined as shown in Table 1 below, and when M = 360 and the length N ldpc of the _LDPC codeword is 16200, Q _ldpc is It can be defined as shown in Table 2 of

이라 하면, i 번째 열 그룹 내의 j 번째 열에서 k 번째 무게-1(weight-1)이 위치한 행의 인덱스

(즉, i 번째 열 그룹 내의 j 번째 열에서 k 번째 1이 위치한 행의 인덱스)는 하기의 수학식 1과 같이 결정된다.Second, the degree of the 0th column of the ith (i=0,1,..,K _ldpc /M-1) column group (here, the degree is the number of 1 values present in the column, The degree of all columns belonging to it is the same) is D _i , and the position (or index) of each row with 1 in the 0-th column of the i-th column group is

, the index of the row where the k-th weight-1 is located in the j-th column in the i-th column group

(That is, the index of the row where the k-th 1 is located in the j-th column in the i-th column group) is determined as in Equation 1 below.

Here, k=0,1,2,..,Di-1, _i =0,1,.., _Kldpc /M-1, j=1,2,...,M-1.

Meanwhile, Equation 1 may be expressed as in Equation 2 below.

Here, k=0,1,2,..,Di-1, _i =0,1,.., _Kldpc /M-1, j=1,2,...,M-1.

는 i 번째 열 그룹 내의 j 번째 열에서 k 번째 무게-1이 위치한 행의 인덱스, N_ldpc는 LDPC 부호어의 길이, K_ldpc는 정보어 비트들의 길이, D_i는 i 번째 열 그룹에 속하는 열들의 차수, M은 하나의 열 그룹에 속하는 열의 개수, Q_ldpc는 각 열이 시클릭 쉬프트되는 크기를 의미한다.In these equations,

is the index of the row where the k weight-1 is located in the j column in the i column group, N _ldpc is the length of the LDPC codeword, K _ldpc is the length of information word bits, D _i is the number of columns belonging to the i column group The degree, M, is the number of columns belonging to one column group, and Q _ldpc is the size at which each column is cyclically shifted.

값만을 알면 i 번째 열 그룹 내의 j 번째 열에서 k 번째 무게-1이 있는 행의 인덱스

를 알 수 있게 된다. 그러므로, 각각의 열 그룹 내의 첫 번째 열에서 k 번째 무게-1이 있는 행의 인덱스 값을 저장하면, 도 2의 구조를 갖는 패리티 검사 행렬(200)(즉, 패리티 검사 행렬(200)의 정보어 부분 행렬(210))에서 무게-1이 있는 열과 행의 위치가 파악될 수 있다.Finally, referring to these equations,

The index of the row with the k weight-1 in the j column within the i column group, if only the value is known.

will be able to know Therefore, if the index value of the row having the k-th weight-1 is stored in the first column of each column group, the parity check matrix 200 having the structure of FIG. 2 (ie, the information word of the parity check matrix 200) In the sub-matrix 210), the position of a column and a row having weight-1 can be identified.

According to the above-described rules, all the orders of columns belonging to the i-th column group are equal to D _i . Accordingly, an LDPC code storing information about a parity check matrix according to the above rules can be briefly expressed as follows.

For example, when N _ldoc is 30, K _ldpc is 15, and Q _ldpc is 3, the positional information of the row where weight-1 is located in the 0th column of the 3 column group is expressed as a sequence as shown in Equation 3 below , which may be referred to as a 'weight-1 position sequence'.

는 i번째 열 그룹 내의 j번째 열에서 k번째 무게-1이 있는 행의 인덱스를 의미한다.From here,

Means the index of the row with the k-th weight-1 in the j-th column in the i-th column group.

Weight-1 position sequences such as Equation 3 representing the index of the row where 1 is located in the 0th column of each column group can be more simply expressed as shown in Table 3 below.

Table 3 shows the position of an element having weight-1, that is, a value of 1, in the parity check matrix. represented by indices.

Based on the foregoing, the information submatrix 210 of the parity check matrix according to an embodiment of the present invention may be defined by Tables 4 to 27 below.

Specifically, Tables 4 to 27 show indexes of rows where 1 is located in the 0th column of the i th column group of the information submatrix 210 . That is, the information submatrix 210 is composed of a plurality of column groups each including M columns, and the position of 1 in the 0th column of each of the plurality of column groups can be defined by Tables 4 to 27. .

Here, indices of rows where 1 is located in the 0th column of the ith column group mean “addresses of parity bit accumulators”. Meanwhile, since “addresses of parity bit accumulators” have the same meaning as defined in standards such as DVB-C2/S2/T2 or the ATSC 3.0 standard currently being standardized, a detailed description thereof will be omitted.

For example, when the length N ldpc of the _LDPC codeword is 16200, the code rate is 5/15, and M is 360, the indexes of rows where 1 is located in the 0th column of the i-th column group of the information word submatrix 210 are It is shown in Table 4 below.

As another example, when the length N ldpc of the _LDPC codeword is 16200, the code rate is 6/15, and M is 360, the indexes of rows where 1 is located in the 0th column of the i-th column group of the information submatrix 210 are It is shown in Table 5 below.

As another example, when the length N ldpc of the _LDPC codeword is 16200, the code rate is 7/15, and M is 360, the index of the row where 1 is located in the 0th column of the i-th column group of the information submatrix 210 They are shown in Table 6 below.

As another example, if the length N ldpc of the _LDPC codeword is 16200, the code rate R is 8/15, and M is 360, the row where 1 is located in the 0th column of the i-th column group of the information word submatrix 210 The indices are as shown in Table 7, Table 8 or Table 9 below.

As another example, when the length N ldpc of the _LDPC codeword is 16200, the code rate is 9/15, and M is 360, the index of the row where 1 is located in the 0th column of the i-th column group of the information submatrix 210 They are shown in Table 10 below.

As another example, when the length N ldpc of the _LDPC codeword is 16200, the code rate is 10/15, and M is 360, the index of the row where 1 is located in the 0th column of the i-th column group of the information submatrix 210 These are shown in Table 11, Table 12 or Table 13 below.

As another example, when the length N ldpc of the _LDPC codeword is 16200, the code rate is 11/15, and M is 360, the index of the row where 1 is located in the 0th column of the i-th column group of the information word submatrix 210 These are shown in Table 14 below.

As another example, when the length N ldpc of the _LDPC codeword is 16200, the code rate is 12/15, and M is 360, the index of the row where 1 is located in the 0th column of the ith column group of the information submatrix 210 These are shown in Table 15 or Table 16 below.

As another example, when the length N ldpc of the _LDPC codeword is 16200, the code rate is 13/15, and M is 360, the index of the row where 1 is located in the 0th column of the i-th column group of the information word submatrix 210 They are shown in Table 17 below.

As another example, when the length N ldpc of the _LDPC codeword is 64800, the code rate is 5/15, and M is 360, the index of the row where 1 is located in the 0th column of the i-th column group of the information submatrix 210 They are shown in Table 18 below.

As another example, if the length N ldpc of the _LDPC codeword is 64800, the code rate is 6/15, and M is 360, the index of the row where 1 is located in the 0th column of the i-th column group of the information word submatrix 210 They are shown in Table 19 below.

As another example, when the length N ldpc of the _LDPC codeword is 64800, the code rate is 7/15, and M is 360, the index of the row where 1 is located in the 0th column of the i-th column group of the information word submatrix 210 These are shown in Table 20 or Table 21 below.

As another example, when the length N ldpc of the _LDPC codeword is 64800, the code rate is 8/15, and M is 360, the index of the row where 1 is located in the 0th column of the i-th column group of the information word submatrix 210 These are shown in Table 22 below.

As another example, when the length N ldpc of the _LDPC codeword is 64800, the code rate is 9/15, and M is 360, the index of the row where 1 is located in the 0th column of the i-th column group of the information submatrix 210 They are shown in Table 23 below.

As another example, when the length N ldpc of the _LDPC codeword is 64800, the code rate is 10/15, and M is 360, the index of the row where 1 is located in the 0th column of the i-th column group of the information word submatrix 210 They are shown in Table 24 below.

As another example, if the length N ldpc of the _LDPC codeword is 64800, the code rate is 11/15, and M is 360, the index of the row where 1 is located in the 0th column of the i-th column group of the information submatrix 210 These are shown in Table 25 below.

As another example, when the length N ldpc of the _LDPC codeword is 64800, the code rate is 12/15, and M is 360, the index of the row where 1 is located in the 0th column of the i-th column group of the information submatrix 210 They are shown in Table 26 below.

As another example, when the length N ldpc of the _LDPC codeword is 64800, the code rate is 13/15, and M is 360, the index of the row where 1 is located in the 0th column of the i-th column group of the information word submatrix 210 They are shown in Table 27 below.

In the above-described Tables 4 to 27, in that the parity check matrix has the same sign even if the order of numbers in the sequence corresponding to each i-th column group is changed, the order in the sequence corresponding to each i-th column group in Tables 4 to 27 A case where is changed may also be an example of a code considered in the present invention.

In addition, since the algebraic characteristics such as cycle characteristics and order distribution on the graph of codes do not change even if the order of the sequences corresponding to each column group in Tables 4 to 27 is changed, the order of the sequences shown in Tables 4 to 27 is A case in which it is changed may also be an example.

In addition, as a result of adding multiples of Q _ldpc equally for sequences corresponding to any column group in Tables 4 to 27, since algebraic characteristics such as cycle characteristics or order distribution on the graph of codes do not change, Table 4 For the sequences shown in Table 27 to Table 27, the result of adding multiples of Q _ldpc identically can also be an example. The point to be aware of here is that when adding a multiple of Q _ldpc to a given sequence, if the value is greater than (N _ldpc -K _ldpc ), a modulo operation is performed on the value (N _ldpc -K _ldpc ). It means that it should be applied by changing it to the applied value.

Meanwhile, as shown in Tables 4 to 27, when the position of a row in which 1 exists is defined in the 0th column of the ith column group of the information word submatrix 210, it is cyclically shifted by Q _ldpc to determine the other values of each column group. The position of a row where a 1 exists in a column can be defined.

For example, in the case of Table 4, in the case of the 0th column of the 0th column group of the information word submatrix 210, the 245th row, 449th row, 491st row, . . . 1 exists in

In this case, since Q _ldpc =(N _ldpc -K ldpc )/M=( _16200-5400 )/360=30, the index of the row where 1 is located in the 1st column of the 0th column group is 275 (=245+30) , 479(=449+30), 521(=491+30),… , and the index of the row where 1 is located in the second column of the 0th column group can be 305 (= 275 + 30), 509 (= 479 + 30), 551 (= 521 + 30), ...

In this way, the index of the row where 1 is located in all rows of each column group can be defined.

Meanwhile, in the parity check matrix 200 shown in FIG. 2 , the parity sub-matrix 220 may be defined as follows.

The parity submatrix 220 is a submatrix including N _ldpc -K _ldpc columns (ie, K _ldpc th column to N _ldpc −1 th column) and has a dual diagonal or staircase structure. Therefore, among the columns included in the parity submatrix 220, the order of all columns except for the last column (ie, the N _{ldpc -1th} column) is 2, and the order of the last column is 1.

Consequently, in the parity check matrix 200, the information submatrix 210 is defined by Tables 4 to 27, and the parity submatrix 220 may have a double diagonal structure.

Meanwhile, if the columns and rows of the parity check matrix 200 shown in FIG. 2 are permuted based on Equations 4 and 5 below, the parity check matrix 200 shown in FIG. It can be represented in the form of a parity check matrix 300 shown in

A method of performing permutation based on Equations 4 and 5 is as follows. Here, since the same principle applies to row permutation and column permutation, row permutation will be described as an example.

In the case of row permutation, i and j that satisfy X = Q _ldpc ×i + j are calculated for the X row, and the calculated i and j are substituted into M × j + i to obtain a row in which the X row is permuted. will yield For example, in the case of the 7th row, since i and j satisfying 7=2×i+j become 3 and 1, respectively, the 7th row is permuted into 10×1+3=13th row.

If row permutation and column permutation are performed in this way, the parity check matrix of FIG. 2 can be expressed as shown in FIG. 3 .

Referring to FIG. 3, the parity check matrix 300 divides the parity check matrix 300 into a plurality of partial blocks, and each of the partial blocks has a quasi-cyclic pattern of size M×M. It has a form that corresponds to a matrix.

Accordingly, the parity check matrix 300 having the structure shown in FIG. 3 is configured in units of matrices of size M×M. That is, the parity check matrix 300 is formed by arranging partial matrices having a size of M×M in a plurality of partial blocks.

In this way, since the parity check matrix 300 is composed of quasi-circulant matrix units of size M×M, M columns may be referred to as column-blocks and M rows may be referred to as row-blocks. there is. Accordingly, the parity check matrix 300 having the structure shown in FIG. 3 used in the present invention is composed of N _{qc _ column} =N _ldpc /M column blocks and N _{qc _ row} =N _parity /M row blocks can be seen as

Hereinafter, a partial matrix having a size of M×M will be described.

First, the (N _{qc _ column} -1)th column block of the 0th row block has the form of Equation 6 below.

As such, A (330) is an M × M matrix, the values of the 0th row and the (M-1)th column are all '0', and for 0≤i≤(M-2), the values of the i-th column (i+ 1) The first row is '1' and all other values are '0'.

Second, for _0≤i≤ (N ldpc -K _ldpc )/M-1 in the parity submatrix 320, the ith row block of the (K _ldpc /M+i) th column block is an identity matrix I _{M ×M} ( 340). In addition, for _0≤i≤ (N ldpc -K _ldpc )/M-2, the (i+1)th row block of the (K _ldpc /M+i)th column block is an identity matrix I _{M ×M} (340) It consists of

또는, 순환 행렬 P가 시클릭 쉬프트된 행렬

이 합해진 형태(또는, 중첩된 형태)가 될 수 있다. Third, the block 350 constituting the information submatrix 310 is a cyclic matrix P in the form of a cyclic shift.

Alternatively, a matrix in which the circulant matrix P is cyclically shifted

This combined form (or superimposed form) can be.

For example, a form in which the circulant matrix P is cyclically shifted by 1 in the right direction can be expressed as in Equation 7 below.

The circulant matrix P is a square matrix having a size of M×M. The circulant matrix P represents a matrix in which each of the M rows has a weight of 1 and each of the M columns has a weight of 1 as well. And, the circulant matrix P is when the superscript a _ij is 0, that is, P ⁰ represents an identity matrix I _{M × M} , and when the superscript a _ij is ∞, that is, P ^∞ represents a zero matrix.

가 될 수 있다. 따라서, i와 j는 정보어 부분에 해당하는 부분 블록들의 행 블록과 열 블록의 개수를 나타낸다. 따라서, 패리티 검사 행렬(300)은 전체 열의 개수가 N_ldpc=M×N_{qc _ column}이고, 전체 행의 개수가 N_parity=M×N_{qc _ row}가 된다. 즉, 패리티 검사 행렬(300)은 N_{qc _ column} 개의 "열 블록"과 N_{qc _ row} 개의 "행 블록"으로 구성된다.Meanwhile, in FIG. 3, a partial matrix existing at a point where the ith row block and the jth column block of the parity check matrix 300 intersect is

can be Accordingly, i and j represent the number of row blocks and column blocks of partial blocks corresponding to the information word portion. Accordingly, in the parity check matrix 300, the total number of columns is N _ldpc =M×N _{qc _ column} , and the total number of rows is N _parity =M×N _{qc _ row} . That is, _the parity check matrix 300 is _{composed of N qc_column "column blocks" and N qc_row " row blocks "} .

Returning to FIG. 1, the encoder 110 uses various codes such as 5/15, 6/15, 7/15, 8/15, 9/15, 10/15, 11/15, 12/15, 13/15, etc. LDPC encoding may be performed using a rate. Also, the encoder 110 may generate LDPC codewords having various lengths, such as 16200 or 64800, based on the length and code rate of information word bits.

In this case, the encoder 110 may perform LDPC encoding using the parity check matrix, and the detailed structure of the parity check matrix has been described above with reference to FIGS. 2 and 3 .

Also, the encoder 110 may perform Bose, Chaudhuri, Hocquenghem (BCH) encoding as well as LDPC encoding. To this end, the encoder 110 may further include a BCH encoder (not shown) that performs BCH encoding.

In this case, the encoder 110 may perform encoding in the order of BCH encoding and LDPC encoding. Specifically, the encoder 110 performs BCH encoding on input bits to add BCH parity bits, performs LDPC encoding on the bits to which the BCH parity bits are added as information word bits, and generates an LDPC codeword You may.

The interleaver 120 interleaves the LDPC codewords. That is, the interleaver 120 may receive the LDPC codeword from the encoder 110 and interleave the LDPC codeword based on various interleaving rules.

In particular, the interleaver 120 maps the LDPC codeword so that bits included in a predetermined group among a plurality of groups (or a plurality of bit groups or a plurality of blocks) constituting the LDPC codeword are mapped to predetermined bits in the modulation symbol. can be interleaved. Accordingly, the modulator 130 may map bits included in a preset group among a plurality of groups constituting the LDPC codeword to preset bits in the modulation symbol.

Hereinafter, the interleaving rules used by the interleaver 120 will be described in more detail by dividing the cases.

block interleaver When to use

According to an embodiment of the present invention, the interleaver 120 interleaves the LDPC codeword through the following method so that bits included in a predetermined group among a plurality of groups constituting the interleaved LDPC codeword are interleaved in the modulation symbol. It can be mapped to a preset bit. For a detailed description, refer to FIG. 4 .

4 is a block diagram for explaining the structure of an interleaver according to an embodiment of the present invention. According to FIG. 4, the interleaver 120 includes a parity interleaver 121, a group interleaver (or group-wise interleaver, 122), a group twist interleaver 123, and a block interleaver 124.

The parity interleaver 121 interleaves parity bits constituting the LDPC codeword.

Specifically, when the LDPC codeword is generated based on the parity check matrix 200 having the structure shown in FIG. 2, the parity interleaver 121 interleaves only parity bits among the LDPC codeword using Equation 8 below can

)에 대해 패리티 인터리빙을 수행하여 U=(u₀,u₁,…,

)를 출력할 수 있다.Here, M is the interval at which a column pattern is repeated in the information word submatrix 210, that is, the number of columns included in the column group (for example, M=360), and Q _ldpc is each The amount by which the column is cyclically shifted. That is, the parity interleaver 121 converts the LDPC codeword c=(c ₀ ,c ₁ ,...,

) by performing parity interleaving on U=(u ₀ ,u ₁ ,…,

) can be output.

On the other hand, when the LDPC codeword encoded based on the parity check matrix 200 as shown in FIG. 2 is parity-interleaved based on Equation 8, the parity-interleaved LDPC codeword is coded using the parity check matrix 300 as shown in FIG. It is the same as the LDPC codeword. Accordingly, when the LDPC codeword is generated based on the parity check matrix 300 as shown in FIG. 3, the parity interleaver 121 can be omitted.

Meanwhile, an LDPC codeword coded based on the parity check matrix 200 having the form of FIG. 2 and then parity interleaved and an LDPC codeword coded based on the parity check matrix 300 having the form of FIG. 3 have a certain number of Consecutive bits may be configured to have similar decoding characteristics (eg, cycle distribution, sequence order, etc.).

For example, the LDPC codeword may have the same characteristics in units of M consecutive bits. Here, M is an interval at which a pattern of a column is repeated in the information word submatrix, and may be, for example, 360.

Specifically, the product of the LDPC codeword bits and the parity check matrix must be '0', which means that i is the i th LDPC codeword bit c _i from 0 to N _ldpc -1 (i=0,1,..., N _ldpc -1) and the column of the ith parity check matrix. Accordingly, the i-th LDPC codeword bit can be regarded as corresponding to the i-th column of the parity check matrix.

On the other hand, in the case of the parity check matrix 200 as shown in FIG. 2, each information word submatrix 210 belongs to the same group by M columns and has the same characteristics per column group (for example, within the same column group The columns have the same order distribution and the same cycle characteristics).

In this case, since M consecutive bits of the information word bits correspond to the same column group of the information word submatrix 210, the information word bits may be composed of consecutive M bits having the same codeword characteristics. . Meanwhile, if the parity bits of the LDPC codeword are interleaved by the parity interleaver 121, the parity bits of the LDPC codeword may also be composed of M consecutive bits having the same codeword characteristics.

Meanwhile, in the case of the parity check matrix 300 as shown in FIG. 3, the information word submatrix 310 and the parity submatrix 320 of the parity check matrix 300 by row and column permutation include M columns Since each column group has the same characteristics, information word bits and parity bits of the LDPC codeword encoded based on the parity check matrix 300 may be composed of M consecutive bits having the same codeword characteristics. .

Here, row permutation does not affect algebraic characteristics of the LDPC code itself, such as cycle characteristics, order distribution, or minimum distance, in that it merely rearranges the order of rows in the parity check matrix. In addition, in the case of column permutation, LDPC encoded by the parity check matrix 300 as shown in FIG. The parity bits of the codeword may be composed of M consecutive bits like the parity bits of the LDPC codeword encoded by the parity check matrix 200 as shown in FIG. 2 .

In this way, bits constituting the LDPC codeword may have the same characteristics in units of M consecutive bits.

The group interleaver 122 may divide the LDPC codewords into a plurality of groups and rearrange the order of the plurality of groups group wise. Alternatively, the group interleaver 122 may divide the parity-interleaved LDPC codewords into a plurality of groups and rearrange the order of the plurality of groups group wise.

That is, the group interleaver 122 may interleave a plurality of groups in group units.

To this end, the group interleaver 122 divides the parity-interleaved LDPC codewords into a plurality of groups using Equation 9 or Equation 10 below.

는 k/360 이하의 가장 큰 정수를 나타낸다. In these equations, N _group denotes the total number of groups, X _j denotes the j th group, and u _k denotes the k th LDPC codeword bit input to the group interleaver 122. and,

represents the largest integer less than or equal to k/360.

Meanwhile, 360 in these equations represents an example of M, which is an interval at which a pattern of a column is repeated in the information word submatrix, so 360 in these equations can be changed to M.

Meanwhile, LDPC codewords classified into a plurality of groups can be represented as shown in FIG. 5 .

Referring to FIG. 5, it can be seen that the LDPC codeword is divided into a plurality of groups, and each group is composed of M consecutive bits. Here, when M is 360, each of the plurality of groups may consist of 360 bits. Accordingly, each group may be composed of bits corresponding to each column group of the parity check matrix.

Specifically, since the LDPC codeword is divided into M consecutive bits, K _ldpc information bits are divided into (K _ldpc /M) groups and N _ldpc -K _ldpc parity bits are (N _ldpc -K _ldpc ) / It is divided into M groups. Accordingly, LDPC codewords can be divided into a total of (N _ldpc /M) groups. For example, if M=360, if the length N ldpc of the _LDPC codeword is 64800, the number of groups N _group is 180, and if the length N ldpc of the _LDPC codeword is 16200, the number of groups N _group is 45. can

The reason why the group interleaver 122 divides the LDPC codewords into the same group by M consecutive bits is that, as described above, the LDPC codewords have the same codeword characteristics in units of M consecutive bits. Accordingly, when the LDPC codeword is divided into M consecutive bits, bits having the same codeword characteristics may be included in the same group.

Meanwhile, in the above example, it has been described that the number of bits constituting each group is M, but this is only an example, and the number of bits constituting each group can be variously changed.

For example, the number of bits constituting each group may be a divisor of M. That is, the number of bits constituting each group may be a divisor of the number of columns constituting the column group of the information submatrix of the parity check matrix. In this case, each group may be composed of multiple bits of M. For example, when the number of columns constituting the column group of the information word submatrix is 360, that is, when M=360, the group interleaver 122 determines that the number of bits constituting each group is one of the divisors of 360. As much as possible, LDPC codewords can be divided into a plurality of groups.

However, in the following, for convenience of description, only a case where the number of bits constituting a group is M will be described.

Then, the group interleaver 122 interleaves the LDPC codewords in groups. Specifically, the group interleaver 122 may group LDPC codewords into a plurality of groups and rearrange the plurality of groups in group units. That is, the group interleaver 122 may rearrange the order of the plurality of groups constituting the LDPC codeword by group by changing the positions of the plurality of groups constituting the LDPC codeword.

Here, the group interleaver 122 may rearrange the order of the plurality of groups on a group basis so that groups including bits mapped to the same modulation symbol among the plurality of groups are spaced apart by a predetermined interval.

In this case, the group interleaver 122 considers the number of rows and columns constituting the block interleaver 124, the number of groups constituting the LDPC codeword and the number of bits included in each group, etc. The order of the plurality of groups may be rearranged in group units so that the groups including the are spaced apart by a predetermined interval.

To this end, the group interleaver 122 may rearrange the order of the plurality of groups in units of groups using Equation 11 below.

Here, X _j represents the j-th group before group interleaving, and Y _j represents the j-th group after group interleaving. Further, π(j) is a parameter indicating an interleaving order, and may be determined by at least one of the length of an LDPC codeword, a code rate, and a modulation scheme.

Accordingly, X _π(j) represents the π(j)-th group before group interleaving, and Equation 11 means that the π(j)-th group before interleaving is interleaved into the j-th group after interleaving.

Meanwhile, specific examples of π(j) according to an embodiment of the present invention may be defined as shown in Tables 28 to 35 below.

In this case, π(j) is defined according to the length and code rate of the LDPC codeword, and the parity check matrix is also defined according to the length and code rate of the LDPC codeword. Therefore, when LDPC encoding is performed based on a specific parity check matrix according to the length and code rate of the LDPC codeword, the LDPC codeword is group-based based on π(j) that satisfies the length and code rate of the LDPC codeword. can be interleaved with

For example, when the encoder 110 performs LDPC encoding at a code rate of 10/15 to generate an LDPC codeword having a length of 16200, the group interleaver 122 performs the following Tables 28 to 35 Interleaving may be performed using π(j), in which the length of the LDPC codeword is 16200 and the code rate is defined at 10/15.

For example, when the length of the LDPC codeword is 16200, the code rate is 10/15, and the modulation method is 16-QAM (quadrature amplitude modulation), the group interleaver 122 obtains π(j) defined as shown in Table 28. Interleaving can be performed using

Meanwhile, a specific example of π(j) is as follows.

For example, when the length N ldpc of the _LDPC codeword is 16200, the code rates are 10/15, 11/15, 12/15, and 13/15, and the modulation method is 16-QAM, π(j) is Table 28 below can be defined as

For Table 28, Equation 11 is Y ₀ =X _π(0) =X ₇ , Y ₁ =X _π(1) =X ₁₇ , Y ₂ =X _π(2) =X ₃₃ ,..., Y ₄₃ =X _π(43) =X ₁₃ , Y ₄₄ =X _π(44) =X ₄₄ Accordingly, the group interleaver 122 converts the 7th group to 0, the 17th group to 1st, the 33rd group to 2nd, ..., the 13th group to 43rd, and the 44th group to 44th. Second, the order of a plurality of groups may be rearranged in group units by changing the order.

As another example, when the length N ldpc of the _LDPC codeword is 16200, the code rates are 6/15, 7/15, 8/15, and 9/15, and the modulation method is 64-QAM, π(j) is shown in Table 29 below. can be defined as

For Table 29, Equation 11 is Y ₀ =X _π(0) =X ₃₂ , Y ₁ =X _π(1) =X ₄ , Y ₂ =X _π(2) =X ₂₃ ,..., Y ₄₃ =X _π(43) =X ₄₃ , Y ₄₄ =X _π(44) =X ₄₄ Accordingly, the group interleaver 122 converts the 32nd group to 0, the 4th group to 1st, the 23rd group to 2nd, ..., the 43rd group to 43rd, and the 44th group to 44th. Second, the order of a plurality of groups may be rearranged in group units by changing the order.

As another example, when the length N ldpc of the _LDPC codeword is 16200, the code rates are 10/15, 11/15, 12/15, and 13/15, and the modulation method is 256-QAM, π(j) is shown in Table 30 below can be defined as

For Table 30, Equation 11 is Y ₀ =X _π(0) =X ₂₈ , Y ₁ =X _π(1) =X ₆ , Y ₂ =X _π(2) =X ₁₅ ,..., Y ₄₃ =X _π(43) =X ₄₃ , Y ₄₄ =X _π(44) =X ₄₄ Accordingly, the group interleaver 122 converts the 28th group to 0, the 6th group to 1st, the 15th group to 2nd, ..., the 43rd group to 43rd, and the 44th group to 44th. Second, the order of a plurality of groups may be rearranged in group units by changing the order.

As another example, when the length N ldpc of the _LDPC codeword is 16200, the code rates are 6/15, 7/15, 8/15, and 9/15, and the modulation method is 1024-QAM, π(j) is Table 31 below can be defined as

For Table 31, Equation 11 is Y ₀ =X _π(0) =X ₁₆ , Y ₁ =X _π(1) =X ₁₃ , Y ₂ =X _π(2) =X ₁ ,..., Y ₄₃ =X _π(43) =X ₄₃ , Y ₄₄ =X _π(44) =X ₄₄ Accordingly, the group interleaver 122 converts the 16th group to 0, the 13th group to 1st, the 1st group to 2nd, ..., the 43rd group to 43rd, and the 44th group to 44th. Second, the order of a plurality of groups may be rearranged in group units by changing the order.

As another example, when the length N ldpc of the _LDPC codeword is 64800, the code rates are 6/15, 7/15, 8/15, and 9/15, and the modulation method is 256-QAM, π(j) is shown in Table 32 below can be defined as

For Table 32, Equation 11 is Y ₀ =X _π(0) =X ₄₈ , Y ₁ =X _π(1) =X ₄ , Y ₂ =X _π(2) =X ₁₅ ,..., Y ₁₇₈ =X _π(178) =X ₁₇₈ , Y ₁₇₉ =X _π(179) =X ₁₇₉ Accordingly, the group interleaver 122 converts the 48th group to 0, the 4th group to 1st, the 15th group to 2nd, ..., the 178th group to 178th, and the 179th group to 179th. Second, the order of a plurality of groups may be rearranged in group units by changing the order.

As another example, when the length Nldpc of the LDPC codeword is 64800, the code rates are 6/15, 7/15, 8/15, and 9/15, and the modulation method is 16-QAM, π(j) is can be defined as

For Table 33, Equation 11 is Y ₀ =X _π(0) =X ₁₂₁ , Y ₁ =X _π(1) =X ₃₉ , Y ₂ =X _π(2) =X ₁₃₉ ,..., Y ₁₇₈ =X _π(178) =X ₂ , Y ₁₇₉ =X _π(179) =X ₉₆ Accordingly, the group interleaver 122 converts the 121st group to 0, the 39th group to 1st, the 139th group to 2nd, ..., the 2nd group to 178th, and the 96th group to 179th. Second, the order of a plurality of groups may be rearranged in group units by changing the order.

As another example, when the length N ldpc of the _LDPC codeword is 64800, the code rates are 10/15, 11/15, 12/15, and 13/15, and the modulation method is 64-QAM, π(j) is shown in Table 34 below can be defined as

For Table 34, Equation 11 is Y ₀ =X _π(0) =X ₄₉ , Y ₁ =X _π(1) =X ₁₀₅ , Y ₂ =X _π(2) =X ₁₀₄ ,..., Y ₁₇₈ =X _π(178) =X ₁₆₄ , Y ₁₇₉ =X _π(179) =X ₁₇₆ Accordingly, the group interleaver 122 converts the 49th group to 0, the 105th group to 1st, the 104th group to 2nd, ..., the 164th group to 178th, and the 176th group to 179th. Second, the order of a plurality of groups may be rearranged in group units by changing the order.

As another example, when the length N ldpc of the _LDPC codeword is 64800, the code rates are 10/15, 11/15, 12/15, and 13/15, and the modulation method is 1024-QAM, π(j) is shown in Table 35 below can be defined as

For Table 35, Equation 11 is Y ₀ =X _π(0) =X ₄₅ , Y ₁ =X _π(1) =X ₃₇ , Y ₂ =X _π(2) =X ₃₁ ,..., Y ₁₇₈ =X _π(178) =X ₁₉ , Y ₁₇₉ =X _π(179) =X ₁₆₅ . Accordingly, the group interleaver 122 converts the 45th group to 0, the 37th group to 1st, the 31st group to 2nd, ..., the 19th group to 178th, and the 165th group to 179th. Second, the order of a plurality of groups may be rearranged in group units by changing the order.

As such, the group interleaver 12 may rearrange the order of the plurality of groups in units of groups using Equation 11 and Tables 28 to 35.

Meanwhile, the group interleaver 122 may rearrange the order of a plurality of groups on a group basis by using Equation 12 below.

Here, X _j represents the j-th group before group interleaving, and Y _j represents the j-th group after group interleaving. Further, π(j) is a parameter indicating an interleaving order, and may be determined by at least one of the length of an LDPC codeword, a code rate, and a modulation scheme.

Accordingly, Y _π(j) denotes a π(j)-th group after group interleaving, and Equation 12 means that the j-th group before interleaving is interleaved into a π(j)-th group after interleaving.

Meanwhile, specific examples of π(j) according to an embodiment of the present invention may be defined as Tables 36 to 43 below.

In this case, π(j) is defined according to the length and code rate of the LDPC codeword, and the parity check matrix is also defined according to the length and code rate of the LDPC codeword. Therefore, when LDPC encoding is performed based on a specific parity check matrix according to the length and code rate of the LDPC codeword, the LDPC codeword is group-based based on π(j) that satisfies the length and code rate of the LDPC codeword. can be interleaved with

For example, when the encoder 110 performs LDPC encoding at a code rate of 10/15 to generate an LDPC codeword having a length of 16200, the group interleaver 122 performs the following Tables 36 to 43 Interleaving can be performed using π(j), in which the length of the LDPC codeword is 16200 and the code rate is defined at 10/15.

For example, when the length of the LDPC codeword is 16200, the code rate is 10/15, and the modulation method is 16-QAM, the group interleaver 122 performs interleaving using π(j) defined as shown in Table 36 can do.

Meanwhile, a specific example of π(j) is as follows.

For example, when the length N ldpc of the _LDPC codeword is 16200, the code rates are 10/15, 11/15, 12/15, and 13/15, and the modulation method is 16-QAM, π(j) is Table 36 below can be defined as

For Table 36, Equation 12 is X ₀ =Y _π(0) =Y ₃₅ , X ₁ =Y _π(1) =Y ₃₁ , X ₂ =Y _π(2) =Y ₃₉ ,..., X ₄₃ =Y _π(43) =Y ₁₅ , X ₄₄ =Y _π(44) =Y ₄₄ . Accordingly, the group interleaver 122 converts the 0th group to the 35th, the 1st group to the 31st, the 2nd group to the 39th, ..., the 43rd group to the 15th, and the 44th group to the 44th. Second, the order of a plurality of groups may be rearranged in group units by changing the order.

As another example, when the length N ldpc of the _LDPC codeword is 16200, the code rates are 6/15, 7/15, 8/15, and 9/15, and the modulation method is 64-QAM, π(j) is shown in Table 37 below can be defined as

For Table 37, Equation 12 is X ₀ =Y _π(0) =Y ₁₈ , X ₁ =Y _π(1) =Y ₃₁ , X ₂ =Y _π(2) =Y ₄₁ ,..., X ₄₃ =Y _π(43) =Y ₄₃ , X ₄₄ =Y _π(44) =Y ₄₄ . Accordingly, the group interleaver 122 converts the 0th group to the 18th, the 1st group to the 31st, the 2nd group to the 41st, ..., the 43rd group to the 43rd, and the 44th group to the 44th. Second, the order of a plurality of groups may be rearranged in group units by changing the order.

As another example, when the length N ldpc of the _LDPC codeword is 16200, the code rates are 10/15, 11/15, 12/15, and 13/15, and the modulation method is 256-QAM, π(j) is shown in Table 38 below can be defined as

For Table 38, Equation 12 is X ₀ =Y _π(0) =Y ₄ , X ₁ =Y _π(1) =Y ₁₃ , X ₂ =Y _π(2) =Y ₃₁ ,..., X ₄₃ =Y _π(43) =Y ₄₃ , X ₄₄ =Y _π(44) =Y ₄₄ . Accordingly, the group interleaver 122 converts the 0th group to the 4th, the 1st group to the 13th, the 2nd group to the 31st, ..., the 43rd group to the 43rd, and the 44th group to the 44th. Second, the order of a plurality of groups may be rearranged in group units by changing the order.

As another example, when the length N ldpc of the _LDPC codeword is 16200, the code rates are 6/15, 7/15, 8/15, and 9/15, and the modulation method is 1024-QAM, π(j) is shown in Table 39 below can be defined as

For Table 39, Equation 12 is X ₀ =Y _π(0) =Y ₁₀ , X ₁ =Y _π(1) =Y ₂ , X ₂ =Y _π(2) =Y ₂₈ ,..., X ₄₃ =Y _π(43) =Y ₄₃ , X ₄₄ =Y _π(44) =Y ₄₄ . Accordingly, the group interleaver 122 converts the 0th group to the 10th, the 1st group to the 2nd, the 2nd group to the 28th, ..., the 43rd group to the 43rd, and the 44th group to the 44th. Second, the order of a plurality of groups may be rearranged in group units by changing the order.

As another example, when the length N ldpc of the _LDPC codeword is 64800, the code rates are 6/15, 7/15, 8/15, and 9/15, and the modulation method is 256-QAM, π(j) is shown in Table 40 below can be defined as

For Table 40, Equation 12 is X ₀ =Y _π(0) =Y ₉ , X ₁ =Y _π(1) =Y ₆ , X ₂ =Y _π(2) =Y ₁₆₀ ,..., X ₁₇₈ =Y _π(178) =Y ₁₇₇ , X ₁₇₉ =Y _π(179) =Y ₁₇₆ . Accordingly, the group interleaver 122 converts the 0th group to the 9th, the 1st group to the 6th, the 2nd group to the 160th, ..., the 178th group to the 177th, and the 179th group to the 176th. Second, the order of a plurality of groups may be rearranged in group units by changing the order.

As another example, when the length N ldpc of the _LDPC codeword is 64800, the code rates are 6/15, 7/15, 8/15, and 9/15, and the modulation method is 16-QAM, π(j) is shown in Table 41 below. can be defined as

For Table 41, Equation 12 is X ₀ =Y _π(0) =Y ₁₃₅ , X ₁ =Y _π(1) =Y ₅₆ , X ₂ =Y _π(2) =Y ₁₇₈ ,..., X ₁₇₈ =Y _π(178) =Y ₁₃₇ , X ₁₇₉ =Y _π(179) =Y ₂₆ . Accordingly, the group interleaver 122 converts the 0th group to the 135th, the 1st group to the 56th, the 2nd group to the 178th, ..., the 178th group to the 137th, and the 179th group to the 26th. Second, the order of a plurality of groups can be rearranged in group units by changing the order.

As another example, when the length N ldpc of the _LDPC codeword is 64800, the code rates are 10/15, 11/15, 12/15, and 13/15, and the modulation method is 64-QAM, π(j) is shown in Table 42 below. can be defined as

For Table 42, Equation 12 is X ₀ =Y _π(0) =Y ₁₃₈ , X ₁ =Y _π(1) =Y ₁₇₆ , X ₂ =Y _π(2) =Y ₁₁₄ ,..., X ₁₇₈ =Y _π(178) =Y ₁₅₅ , X ₁₇₉ =Y _π(179) =Y ₁₃₀ . Accordingly, the group interleaver 122 converts the 0th group to the 138th, the 1st group to the 176th, the 2nd group to the 114th, ..., the 178th group to the 155th, and the 179th group to the 130th. Second, the order of a plurality of groups may be rearranged in group units by changing the order.

As another example, when the length N ldpc of the _LDPC codeword is 64800, the code rates are 10/15, 11/15, 12/15, and 13/15, and the modulation method is 1024-QAM, π(j) is shown in Table 43 below. can be defined as

For Table 43, Equation 12 is X ₀ =Y _π(0) =Y ₁₂ , X ₁ =Y _π(1) =Y ₃₂ , X ₂ =Y _π(2) =Y ₁₃ ,..., X ₁₇₈ =Y _π(178) =Y ₁₅₃ , X ₁₇₉ =Y _π(179) =Y ₁₆₃ . Accordingly, the group interleaver 122 converts the 0th group to the 12th, the 1st group to the 32nd, the 2nd group to the 13th, ..., the 178th group to the 153rd, and the 179th group to the 163rd. Second, the order of a plurality of groups can be rearranged in group units by changing the order.

As such, the group interleaver 12 may rearrange the order of the plurality of groups in a group unit using Equation 12 and Tables 36 to 43.

Meanwhile, in Tables 28 to 43, π(j ) was described as "Order of bits group to be block interleaved".

According to the above method, the group interleaved LDPC codeword is shown in FIG. 6. When the LDPC codeword shown in FIG. 6 is compared with the LDPC codeword shown in FIG. 5 before group interleaving, it can be seen that the order of a plurality of groups constituting the LDPC codeword has been rearranged.

That is, as shown in FIGS. 5 and 6, the LDPC codewords have group X ₀ , group X ₁ , ... before group interleaving. , group X is arranged in the order of _{Ngroup -1} , then group interleaved, group Y ₀ , group Y ₁ , . . . , group Y can be arranged in the order of _{Ngroup -1} . In this case, the order in which each group is arranged by group interleaving may be determined based on Tables 28 to 43.

Group twist interleaver 123 interleaves the bits within the same group. That is, the group twist interleaver 123 may rearrange the order of bits in the same group by changing the order of bits in the same group.

In this case, the group twist interleaver 123 may rearrange the order of bits in the same group by cyclically shifting bits in the same group by a predetermined number of bits.

For example, as shown in FIG. 7 , the group twist interleaver 123 may cyclically shift bits included in group Y ₁ by 1 bit in the right direction. In this case, as shown in FIG. 7, the 0th, 1st, 2nd, . . . in group Y ₁ , 358th and 359th bits are cyclically shifted to the right by 1 bit, so that the 359th bit before cyclic shift is located at the front in group Y ₁ and 0 before cyclic shift 1st, 1st, 2nd,… , 358 bits are sequentially shifted to the right by 1 bit.

In addition, the group twist interleaver 123 may rearrange the order of bits in each group by cyclically shifting a different number of bits for each group.

For example, the group twist interleaver 123 may cyclically shift bits included in group Y ₁ by 1 bit in the right direction and cyclic shift bits included in group Y ₂ by 3 bits in the right direction. .

However, the aforementioned group twist interleaver 123 may be omitted in some cases.

Also, in the above example, the group twist interleaver 123 is described as being disposed after the group interleaver 122, but this is also only an example. That is, the group twist interleaver 123 may be placed before the group interleaver 122 in that it only changes the order of bits constituting the corresponding group within the group and does not change the order of the group itself.

The block interleaver 124 interleaves the plurality of groups whose order is rearranged. Specifically, the block interleaver 124 is composed of a plurality of columns each including a plurality of rows, and performs interleaving by classifying a plurality of rearranged groups based on a modulation order determined according to a modulation scheme. can be done

In this case, a plurality of groups whose order is rearranged by the group interleaver 122 may be interleaved in a group unit. Specifically, the block interleaver 124 may interleave the first part (part 1) and the second part (part 2) may be used to classify and interleave a plurality of rearranged groups according to modulation orders.

Specifically, the block interleaver 124 divides each of a plurality of columns into a first part and a second part, sequentially writes a plurality of groups into a plurality of columns constituting the first part in units of groups, and writes the remaining columns in units of groups. The bits constituting the group are divided into groups each consisting of a predetermined number of bits (or sub bit groups) based on the number of a plurality of columns, and the divided groups are sequentially divided into a plurality of columns constituting the second part. Interleaving can be performed by writing.

Here, the number of groups interleaved in a group unit may be determined according to at least one of the number of rows and columns constituting the block interleaver 124, the number of groups, and the number of bits included in each group. That is, the block interleaver 124 determines a group to be interleaved in a group unit among a plurality of groups by considering at least one of the number of rows and columns constituting the block interleaver 124, the number of groups, and the number of bits included in each group. Then, the corresponding group may be interleaved on a group basis, and the remaining groups may be divided and interleaved. For example, the block interleaver 124 may interleave at least some of the plurality of groups in group units using the first part, and divide and interleave the remaining groups using the second part.

Meanwhile, being interleaved in a group unit means that bits included in the same group are written in the same column. That is, the block interleaver 124 writes the bits included in the same group to the same column without dividing them in the case of groups interleaved in group units, and in the case of groups not interleaved in group units, divides the bits included in the corresponding group to each other. You can perform interleaving by writing to different columns.

Accordingly, the number of rows constituting the first part may be a multiple of the number of bits included in one group (eg, 360), and the number of rows constituting the second part may be less than the number of bits included in one group. there is.

In addition, all groups interleaved by the first part are interleaved by writing bits included in the same group to the same column of the first part, and at least one group interleaved by the second part is at least two groups constituting the second part. It can be divided into two columns and lit.

Details of this interleaving method will be described later.

Meanwhile, interleaving performed by the group twist interleaver 123 only changes the order of bits within a group, and the order of the group itself is not changed by interleaving. Accordingly, the order of groups interleaved in the block interleaver 124, that is, the order of groups input to the block interleaver 124 may be determined by the group interleaver 122. For example, the order of blocks interleaved by the block interleaver 124 may be determined by π(j) defined in Tables 28 to 43.

As described above, the block interleaver 124 may be composed of a plurality of columns each including a plurality of rows, and may interleave the LDPC codeword by dividing the plurality of columns into at least two parts.

For example, the block interleaver 124 may divide each of a plurality of columns into a first part and a second part to interleave a plurality of groups constituting the LDPC codeword.

In this case, the block interleaver 124 assigns N each of the plurality of columns according to whether the number of groups constituting the LDPC codeword is an integer multiple of the number of columns constituting the block interleaver 124 (N is an integer greater than or equal to 2). Interleaving may be performed by dividing into parts of .

First, when the number of groups constituting the LDPC codeword is an integer multiple of the number of columns constituting the block interleaver 124, the block interleaver 124 constructs the LDPC codeword without dividing each of the plurality of columns into parts. A plurality of groups may be interleaved on a group basis.

Specifically, the block interleaver 124 writes a plurality of groups constituting the LDPC codeword in a column direction to each column in a group unit, and reads each row of a plurality of columns in which the plurality of groups are written in a group unit in a row direction (read) to perform interleaving.

In this case, the block interleaver 124 divides the number of groups constituting the LDPC codeword by the number of columns constituting the block interleaver 124, and divides the bits included in the groups by the quotient in each of a plurality of columns in the column direction. , and interleaving may be performed by reading each row of a plurality of columns in which bits are written in a row direction.

Hereinafter, for convenience of description, a group located at the j position after being interleaved by the group interleaver 122 is referred to as a group Y _j .

For example, it is assumed that the block interleaver 124 is composed of C columns each including R ₁ rows. And, it is assumed that the LDPC codeword is composed of Y _group groups, and the number of groups, Y _group , is a multiple of C.

In this case, since the quotient of dividing the number Ygroup, the number of groups constituting the LDPC codeword, by the number C, the number of columns constituting the block interleaver 124, is Y group/C, the block interleaver 124 assigns Y _group /C groups to each column. Interleaving may be performed by sequentially writing in a column direction and reading the written bits in each column in a row direction.

For example, as shown in FIG. 8 , the block interleaver 124 assigns a group (Y ₀ ), a group (Y ₁ ), ..., a group (Y _{p -1} ) to the first row of the _first column to the first R row. ), and writes the bits included in each of the groups (Y _p ), groups (Y _{p +1} ),..., groups (Y _{q -1} ) from the 1st row of the 2nd column to the _1st row of R Write included bits, ..., group (Y _z ), group (Y _{z +1} ),..., group (Y _{Ngroup -1} ) from the 1st row of the C-th column to the _1st row of R, respectively Bits included in may be written, and the written bits in each row of a plurality of columns may be read in a row direction.

Accordingly, the block interleaver 124 interleaves all groups constituting the LDPC codeword in units of groups.

However, when the number of groups constituting the LDPC codeword is not an integer multiple of the number of columns constituting the block interleaver 124, the block interleaver 124 divides each of a plurality of columns into two parts to obtain the LDPC codeword. Some of the plurality of groups may be interleaved on a group basis, and the remaining groups may be divided and interleaved. In this case, the bits included in the remaining groups, that is, the bits included in the remaining groups when the number of groups constituting the LDPC codeword is divided by the number of columns, are not interleaved in units of groups, but the number of columns Depending on the number, each column may be divided and interleaved.

Specifically, the block interleaver 124 may interleave the LDPC codeword by dividing each of a plurality of columns into two parts.

In this case, the block interleaver 124 converts a plurality of columns into a first part and a plurality of columns based on the number of columns constituting the block interleaver 124, the number of groups constituting the LDPC codeword, and the number of bits constituting each of the plurality of groups. It can be divided into the second part.

Here, each of the plurality of groups may consist of 360 bits. The number of groups constituting the LDPC codeword is determined according to the length of the LDPC codeword and the number of bits included in each group. For example, if an LDPC codeword with a length of 16200 is divided so that each group consists of 360 bits, an LDPC codeword is divided into 45 groups, and an LDPC codeword with a length of 64800 is divided so that each group consists of 360 bits. DPC codewords can be divided into 180 groups. Also, the number of columns constituting the block interleaver 124 may be determined according to a modulation method, and a specific example related to this will be described later.

Accordingly, the number of rows constituting each of the first part and the second part is based on the number of columns constituting the block interleaver 124, the number of groups constituting the LDPC codeword, and the number of bits constituting each of the plurality of groups. can be determined by

Specifically, the first part includes a plurality of columns constituting the LDPC codeword according to the number of columns constituting the block interleaver 124, the number of groups constituting the LDPC codeword, and the number of bits constituting each group in each of the plurality of columns. Each of a plurality of columns among the groups of may include as many rows as the number of bits included in at least one group that can be written in group units.

In addition, the second part may be composed of rows excluding as many rows as the number of bits included in at least some groups that can be written in group units in each of the plurality of columns from the rows constituting each of the plurality of columns. there is. Specifically, the number of rows of the second part may have a value equal to the quotient obtained by dividing the number of bits included in all bit groups except for the group corresponding to the first part by the number of columns constituting the block interleaver 124. . That is, the number of rows of the second part may have the same value as the quotient obtained by dividing the number of bits included in the remaining groups after being written in the first part among the groups constituting the LDPC codeword by the number of columns.

On the other hand, the block interleaver 124 divides each of the plurality of columns into a first part including rows as many as the number of bits included in the group that can be written to each column in a group unit and a second part including the remaining rows. Each column can be distinguished.

Accordingly, the first part may be composed of rows as many as integer multiples of the number of bits included in the group, that is, M. However, as described above, since the number of codeword bits constituting each group can be a divisor of M, the first part may consist of rows as many as integer multiples of the number of bits constituting each group. there is.

In this case, the block interleaver 124 may perform interleaving by writing and reading LDPC codewords in the first part and the second part in the same manner.

Specifically, the block interleaver 124 writes the LDPC codeword in a column direction to a plurality of columns constituting the first part and the second part, respectively, and writes the LDPC codeword to the plurality of columns constituting the written first part and the second part, respectively. Interleaving may be performed by reading the columns of in the row direction.

That is, the block interleaver 124 sequentially writes bits included in at least some groups that can be written in groups in each of a plurality of columns to each of a plurality of columns constituting the first part, and writes at least some of the bits in each of the plurality of groups. The bits included in the remaining groups excluding the group are divided and written to each of the plurality of columns constituting the second part in the column direction, and the written bits to each of the plurality of columns constituting the first part and the second part are written in rows. Interleaving may be performed by leading in the direction.

In this case, the block interleaver 124 may perform interleaving by dividing remaining groups other than at least some of the plurality of groups based on the number of columns constituting the block interleaver 124 .

Specifically, the block interleaver 124 divides the bits included in the remaining groups into a plurality of columns, writes each of the divided bits to each of the plurality of columns constituting the second part in a column direction, and writes the divided bits Interleaving may be performed by reading in a row direction a plurality of columns constituting the second part in which the fields are written.

That is, the block interleaver 124 writes the first part of the plurality of groups constituting the LDPC codeword and the remaining groups, that is, the number of groups constituting the LDPC codeword divided by the number of columns, the remainder (remainder) The bits included in the group of may be divided into the number of columns, and the divided bits may be sequentially written in the column direction in each column of the second part.

For example, it is assumed that the block interleaver 124 is composed of C columns each including R ₁ rows. Also, it is assumed that the LDPC codeword is composed of Y _group groups, the number of groups, Y _group , is not a multiple of C, and A×C+1=Y _group (A is an integer greater than 0). That is, it is assumed that when the number of groups constituting the LDPC codeword is divided by the number of columns, the quotient is A and the remainder is 1.

In this case, the block interleaver 124 can be divided into a first part including R ₁ rows in each column and a second part including R ₂ rows, as shown in FIGS. 9 and 10 . In this case, R ₁ may be as many as the number of bits included in groups that can be written in groups in each column, and R ₂ may be a value excluding R ₁ from the number of rows constituting each column.

That is, in the above example, the number of groups that can be written in each column is A, and the first part of each column can be composed of the number of bits included in the A groups, that is, A×M rows.

In this case, the block interleaver 124 writes the bits included in groups that can be written in groups in each column, that is, groups A, in the column direction to the first part of each column.

That is, the block interleaver 124, as shown in FIGS. 9 and ₁₀ , groups (Y ₀ ), groups (Y ₁ ), ..., The bits included in each group (Y _{n -1} ) are written, and the groups (Y _n ) and groups (Y _{n +1} ) in the first row from the 1st row to the R _1st row constituting the first part of the second column. .., write the bits included in _each group (Y _{m -1} ), ..., group (Y _e ), group ( Y _{e +1} ),..., Writes the bits included in each group (Y _{Ngroup -2} ).

In this way, the block interleaver 124 writes bits included in groups that can be written to each column in group units to the first part of each column in group units.

That is, in the above example, the bits included in each of the group (Y ₀ ), group (Y ₁ ), ..., group (Y _{n -1} ) are all written in the first column without being divided, and the group (Y _n ), group (Y _{n +1} ), ..., the bits included in each group (Y _{m -1} ) are not divided and all are written in the second column, ..., group (Y _e ), group (Y _{e +1} ),... , bits included in each of the groups (Y _{Ngroup -2} ) may all be written to the C-th column without being divided. In this way, all groups interleaved by the first part can be viewed as bits included in the same group being written in the same column of the first part.

Thereafter, the block interleaver 124 may divide the bits included in the groups other than the groups written to the first part of each column among the plurality of groups and write the second part of each column in a column direction. At this time, the block interleaver 124 divides the bits included in the remaining groups excluding the group written in the first part of each column by the number of columns so that the same number of bits are written in the second part of each column, and each of the divided bits can be written in the column direction in each column of the second part.

Here, each of the divided bits based on the number of columns can be named a sub bit group, and in this case, each sub bit group can be regarded as being written in each column of the second part.

In the above example, since A×C+1=Y _group is satisfied, when the groups constituting the LDPC codeword are sequentially written in the first part, the last group of the LDPC codeword (Y _Ngroup-1 ) is the first It is not written to 1 part and remains. Accordingly, the block interleaver 124 divides the bits included in the group (Y _{Ngroup -1} ) into C pieces as shown in _{FIG .} bits as many as the quotient of dividing by C) may be sequentially written in the second part of each column.

Here, each of the divided bits based on the number of columns may be referred to as a sub-bit group, and in this case, each sub-bit group may be considered to be written in each column of the second part. That is, bits included in the bit group may be divided to form a sub bit group.

That is, the block interleaver 124 writes bits from the 1st row to the R2nd row constituting the _second part of the first column, and from the 1st row to the R2nd row constituting the _second part of the second column. Bits can be written up to ..., and bits can be written from the 1st row constituting the second part of the C-th column to the _2nd row R. In this case, the block interleaver 124 may write bits to the second part of each column in a column direction as shown in FIG. 9 .

That is, in the second part, the bits constituting the bit group may not be written in the same column, but may be written in a plurality of columns. That is, in the above example, since the last group (Y _{Ngroup -1} ) consists of M bits, the bits included in the last group (Y _{Ngroup -1} ) can be divided by M/C and written to each column. . That is, the bits included in the last group (Y _{Ngroup -1} ) are divided into M/C units, sub-bit groups are formed by each segmented M/C, and each sub-bit group can be written in each column of the second part. .

Accordingly, in at least one group interleaved by the second part, the bits included in the at least one group may be divided into at least two columns constituting the second part and written.

Meanwhile, in the above example, the block interleaver 124 has been described as writing bits in the column direction to the second part, but this is only an example. That is, the block interleaver 124 may write bits to a plurality of columns of the second part in a row direction. In this case, the block interleaver 124 may write bits for the first part in the same manner as described above.

Specifically, referring to FIG. 10, the block interleaver 124 writes bits from the first row constituting the second part in the first column to the first row constituting the second part in the C-th column, and Write bits from the 2nd row constituting the second part to the C-th column to the 2nd row constituting the second part, ..., R constituting the second part in the first column from the _2nd row to the 2nd row constituting the second part Bits can be written from column C to the _second row of R constituting the second part.

Meanwhile, the block interleaver 124 sequentially reads the bits written in each row of each part in the row direction. That is, the block interleaver 124 sequentially reads the bits written in each row of the first part of the plurality of columns in the row direction as shown in FIGS. 9 and 10, and the bits written in each row of the second part of the plurality of columns. can be read sequentially in the row direction.

Accordingly, the block interleaver 124 may perform interleaving by interleaving some of the plurality of groups constituting the LDPC codeword in units of groups and dividing the remaining parts. That is, the block interleaver 124 writes LDPC codewords constituting a predetermined number of groups among a plurality of groups into a plurality of columns constituting the first part in group units, and writes the LDPC codewords constituting the remaining groups into the second part. Interleaving may be performed by dividing and writing each column constituting the part and reading a plurality of columns constituting the first and second parts in a row direction.

As such, the block interleaver 124 may interleave a plurality of groups using the method described in FIGS. 8 to 10 .

In particular, in the case of FIG. 9, the order of bits included in groups not belonging to the first part is redefined in that the bits included in the groups not belonging to the first part are written in the column direction and read in the row direction in the second part. It can be. In this way, bit error rate (BER)/frame error rate (FER) performance can be improved compared to the case where interleaving is not performed in that bits included in groups not belonging to the first part are interleaved.

However, as shown in FIG. 10, groups not belonging to the first part may not be interleaved. That is, as shown in FIG. 10, in that the block interleaver 124 writes and reads the bits included in the group not belonging to the first part to the second part in the row direction, the bits included in the group not belonging to the first part are They may be sequentially output to the modulator 130 without changing the order. In this case, bits included in groups not belonging to the first part may be sequentially output and mapped to modulation symbols.

Meanwhile, in FIGS. 9 and 10, it has been described that the last one of the plurality of groups is written in the second part, but this is only an example, and the number of groups written in the second part is the number of groups constituting the LDPC codeword Of course, it can be variously changed according to the total number of , the number of columns and rows, the number of transmit antennas, and the like.

Meanwhile, the block interleaver 124 may have a different structure depending on whether bits included in the same group are mapped to one bit in a modulation symbol or bits included in the same group are mapped to two bits in a modulation symbol. .

On the other hand, in the case of a transmission/reception system using a plurality of antennas, the number of columns constituting the block interleaver 124 may be determined by simultaneously considering the number of bits constituting a modulation symbol and the number of used antennas. For example, in the case of a system in which bits included in the same group are mapped to one bit in a modulation symbol and two antennas are used, the block interleaver 124 sets the number of columns to twice the number of bits constituting the modulation symbol. can decide

First, when bits included in the same group are mapped to one bit in a modulation symbol, the block interleaver 124 may have structures as shown in Tables 44 and 45 below.

Here, C (or N _c ) is the number of columns constituting the block interleaver 124, R ₁ is the number of rows constituting the first part in each column, and R ₂ is the second part in each column. is the number of rows

Referring to Tables 44 and 45, the number of columns has the same value as the modulation order according to the modulation method, and each of the plurality of columns divides the number of bits constituting the LDPC codeword by the number of columns. It can be seen that it consists of

For example, when the length of the LDPC codeword is Nldpc = 64800 and modulation is performed in the 16-QAM method, since the modulation order is 4 in the case of 16-QAM, the block interleaver 124 consists of 4 columns, each column It can be seen that R1 + R2 = 16200 (= 64800/4) rows.

Meanwhile, referring to Tables 44 and 45, when the number of groups constituting the LDPC codeword is an integer multiple of the number of columns, the block interleaver 124 performs interleaving without distinguishing _each column. It becomes the number of rows constituting the column, and R ₂ =0. In addition, when the number of groups constituting the LDPC codeword is not an integer multiple of the number of columns, the block interleaver 124 divides each column into a first part composed of R ₁ rows and a second part composed of R ₂ rows. Interleaving is performed by dividing into parts.

Meanwhile, as shown in Tables 44 and 45, when the number of columns of the block interleaver 124 is the same as the number of bits constituting the modulation symbol, the bits included in the same group may be mapped to one bit in the modulation symbol.

For example, when N _ldpc =64800 and the modulation scheme is 16-QAM, the block interleaver 124 may be configured with 4 columns each including 16200 rows. In this case, a plurality of groups are written in four columns in group units, and bits written in the same row in each column are sequentially output. In this case, since 4 bits constitute one modulation symbol when the modulation method is 16-QAM, bits included in the same group, that is, bits output from one column may be mapped to one bit in the modulation symbol. there is. For example, bits included in a group written in the first column may be mapped to the first bit of each modulation symbol.

Meanwhile, when bits included in the same group are mapped to two bits in a modulation symbol, the block interleaver 124 may have structures as shown in Tables 46 and 47 below.

Here, C (or N _c ) is the number of columns constituting the block interleaver 124, R ₁ is the number of rows constituting the first part in each column, and R ₂ is the second part in each column. is the number of rows

Referring to Tables 46 and 47, when the number of groups constituting the LDPC codeword is an integer multiple of the number of columns, the block interleaver 124 performs interleaving without distinguishing each column, so that R ₁ constitutes each column is the number of rows, and R ₂ =0. In addition, when the number of groups constituting the LDPC codeword is not an integer multiple of the number of columns, the block interleaver 124 divides each column into a first part composed of R ₁ rows and a second part composed of R ₂ rows. Interleaving is performed by dividing into parts.

As shown in Tables 46 and 47, when the number of columns of the block interleaver 124 is half of the number of bits constituting the modulation symbol, bits included in the same group may be mapped to two bits in the modulation symbol.

For example, when N _ldpc =64800 and the modulation scheme is 16-QAM, the block interleaver 124 may be composed of two columns each including 32400 rows. In this case, a plurality of groups are written in two columns in group units, and bits written in the same row in each column are sequentially output. Meanwhile, since 4 bits constitute one modulation symbol when the modulation method is 16-QAM, bits output from two rows constitute one modulation symbol. Accordingly, bits included in the same group, that is, bits output from one column may be mapped to two bits in a modulation symbol. For example, the bits included in the group written in the first column may be mapped to bits present in two arbitrary positions in the modulation symbol.

Meanwhile, referring to Tables 44 to 47, it can be seen that the total number of rows of the block interleaver 124, that is, R ₁ +R ₂ is N _ldpc /C.

이고, 제2 파트의 행의 개수인 R₂는 N_ldpc/C-R₁이 될 수 있다. 여기에서,

는 N_group/C 이하의 가장 큰 정수를 나타낸다. 이와 같이, R₁은 각 그룹에 포함된 비트의 개수인 M의 정수 배가 된다는 점에서 R₁에는 그룹 단위의 비트들이 라이트될 수 있다. And, R ₁ , the number of rows of the first part, is an integer multiple of M (eg, M=360), the number of bits included in each group.

, and the number of rows of the second part, R ₂ , may be N _ldpc /CR ₁ . From here,

represents the largest integer less than or equal to N _group /C. In this way, since R ₁ is an integer multiple of M, which is the number of bits included in each group, bits in units of groups can be written in R ₁ .

Also, referring to Tables 44 to 47, when the number of groups constituting the LDPC codeword is not a multiple of the number of columns, the block interleaver 124 divides each column into two parts and interleaving is performed. can

Specifically, a value obtained by dividing the length of the LDPC codeword by the number of columns becomes the total number of rows included in each column. In this case, when the number of groups constituting the LDPC codeword is a multiple of the number of columns, each column is not divided into two parts. However, when the number of groups constituting the LDPC codeword is not a multiple of the number of columns, each column may be divided into two parts.

For example, as shown in Table 44, it is assumed that the number of columns of the block interleaver 124 is equal to the number of bits constituting the modulation symbol and the LDPC codeword is composed of 64800 bits. At this time, each group constituting the LDPC codeword is composed of 360 bits, and the LDPC codeword is composed of 64800/360 = 180 groups.

Meanwhile, when the modulation method is 16-QAM, the block interleaver 124 is composed of 4 columns, and each column may be composed of 64800/4 = 16200 rows.

In this case, since the value obtained by dividing the number of groups constituting the LDPC codeword by the number of columns is 180/4 = 45, bits can be written in groups in each column without dividing each column into two parts. That is, bits included in 45 groups, that is, 45×360=16200 bits, which are the quotient obtained by dividing the number of groups constituting the LDPC codeword by the number of columns, can be written in each column.

However, when the modulation method is 256-QAM, the block interleaver 124 is composed of 8 columns, and each column may be composed of 64800/8 = 8100 rows.

At this time, since the value obtained by dividing the number of groups constituting the LDPC codeword by the number of columns is 180/8 = 22.5, the number of groups constituting the LDPC codeword is not an integer multiple of the number of columns. Accordingly, the block interleaver 124 divides each of the eight columns into two parts in order to perform interleaving on a group basis.

At this time, since bits must be written in group units in the first part of each column, the number of groups that can be written in group units in the first part of each column is the number of groups constituting the LDPC codeword divided by the number of columns The quotient is 22, and accordingly, the first part of each column can be composed of 22 × 360 = 7920 rows. Accordingly, 7920 bits included in 22 groups may be written in the first part of each column.

On the other hand, the second part of each column is composed of rows excluding rows constituting the first part from all rows of each column. Accordingly, the second part of each column may consist of 8100-7920 = 180 rows.

At this time, in the second part of each column, bits included in the remaining groups not written in the first part may be divided and written.

Specifically, since 22 × 8 = 176 groups are written in the first part, the number of groups written in the second part is 180-176 = 4 (eg, groups (Y ₀ ) constituting the LDPC codeword, groups (Y ₁ ), group (Y ₂ ),..., group (Y ₁₇₈ ), group (Y ₁₇₉ ) group (Y ₁₇₆ ), group (Y ₁₇₇ ), group (Y ₁₇₈ ), group (Y ₁₇₉ ) can be).

Accordingly, the block interleaver 124 may write the first part among the groups constituting the LDPC codeword and sequentially write the remaining four groups to the second part of each column.

That is, the block interleaver 124 writes 180 bits among the 360 bits included in the group (Y ₁₇₆ ) in the column direction from the 1st row to the 180th row of the second part of the 1st column, and writes the remaining 180 bits It is possible to light in the column direction from the 1st row to the 180th row of the second part of the 2nd column. Then, the block interleaver 124 writes 180 bits among the 360 bits included in the group (Y ₁₇₇ ) in the column direction from the first row to the 180th row of the second part of the third column, and writes the remaining 180 bits It is possible to light in the column direction from the 1st row to the 180th row of the second part of the 4th column. Then, the block interleaver 124 writes 180 bits among the 360 bits included in the group (Y ₁₇₈ ) in the column direction from the 1st row to the 180th row of the second part of the 5th column, and writes the remaining 180 bits It is possible to light in the column direction from the 1st row to the 180th row of the second part of the 6th column. Then, the block interleaver 124 writes 180 bits among the 360 bits included in the group (Y ₁₇₉ ) in the column direction from the 1st row to the 180th row of the second part of the 7th column, and writes the remaining 180 bits It is possible to light in the column direction from the 1st row to the 180th row of the second part of the 8th column.

Accordingly, the bits included in the remaining groups after being written in the first part may not be written in the same column in the second part, but may be divided and written in a plurality of columns.

Hereinafter, a specific example of the block interleaver of FIG. 4 will be described in more detail with reference to FIG. 11 .

)는 V={Y₀,Y₁,…,

}과 같이 Y_j가 연속적으로 배치될 수 있다. Group interleaved LDPC codeword (v ₀ ,v ₁ ,…,

) is V={Y ₀ ,Y ₁ ,… ,

}, Y _j can be arranged consecutively.

After group interleaving, the LDPC codewords may be interleaved by the block interleaver 124 as shown in FIG. In this case, the block interleaver 124 may divide the plurality of columns into a first part and a second part based on the number of columns constituting the block interleaver 124 and the number of bits of the group. In this case, bits constituting a group may be written in the same column in the first part, and bits constituting a group may be written in a plurality of columns in the second part.

Specifically, the input bit v _i is sequentially written column wise starting from the first part to the second part, and sequentially written row wise from the first part to the second part. lead Accordingly, bits included in the same group in the first part may be mapped to one bit in each modulation symbol.

)은 360의 배수이므로, 복수의 비트 그룹이 제1 파트에 라이트될 수 있다. In this case, the number of columns and the number of rows of the first part and the second part of the block interleaver 124 according to the modulation method and the length (ie, code length) of the LDPC codeword may be as shown in Table 48 below. Here, the number of columns of the block interleaver 124 may be equal to the number of bits constituting the modulation symbol. Also, the sum of N _r1 , the number of rows of the first part, and N _r2 , the number of rows of the second part, is equal to N _ldpc /N _c (here, N _c is the number of columns). And, N _r1 (=

) is a multiple of 360, so a plurality of bit groups can be written to the first part.

Hereinafter, the operation of the block interleaver 124 will be described in more detail.

, r_i=(i mod N_r1)와 같다.Specifically, as shown in FIG. 11 , the input bit v _i (0≤i<N _c ×N _r1 ) is written to row r _i of column c _i of the first part of the block interleaver 124 . Here, c _i and r _i are respectively

, equal to r _i =(i mod N _r1 ).

, r_i=N_r1+{(i-N_c×N_r1) mod N_r2}와 같다.Then, the input bit v _i (N _c ×N _r1 ≤ i<N _ldpc ) is written to row r _i of column c _i of the second part of the block interleaver 124 . Here, c _i and r _i are respectively

, r _i = N _r1 + {(iN _c × N _r1 ) mod N _r2 }.

, c_j=(j mod N_c)와 같다.On the other hand, the output bit q _j (0≤j<N _ldpc ) is read from the c _j column of the r _j row. Here, c _j and r _j are respectively

, equal to c _j = (j mod N _c ).

For example, when the length N ldpc of the _LDPC codeword is 64800 and the modulation method is 256-QAM, the order of bits output from the block interleaver 124 is (q ₀ ,q ₁ ,q ₂ ,..., q ₆₃₃₅₇ ,q ₆₃₃₅₈ ,q ₆₃₃₅₉ ,q ₆₃₃₆₀ ,q ₆₃₃₆₁ ,...,q ₆₄₇₉₉ )= (v ₀ ,v ₇₉₂₀ ,v ₁₅₈₄₀ ,...,v ₄₇₅₁₉ ,v ₅₅₄₃₉ ,v ₆₃₃₅₉ ,v ₆₃₃₆₀ ,v ₆₃₅₄₀ ,...,v ₆₄₇₉₉ ). Here, the indices in the right column are expressed in more detail for all eight columns: 0, 7920, 15840, 23760, 31680, 39600, 47520, 55440, 1, 7921, 15841, 23761, 31681, 39601, 47521, 55441, ... … , 7919, 15839, 23759, 31679, 39599, 47519, 55439, 63359, 63360, 63540, 63720, 63900, 64080, 64260, 64440, 64620, … … , 63539, 63719, 63899, 64079, 64259, 64439, 64619, 64799.

Meanwhile, in the above example, it has been described that the number of columns constituting the block interleaver 124 has the same value as the modulation order or has a value equal to half of the modulation order, but this is only an example, and the block interleaver 124 The number of constituting columns may be a multiple value of the modulation order. In this case, the number of rows constituting each column may be a value obtained by dividing the length of the LDPC codeword by the number of columns.

For example, when the modulation method is QPSK (ie, the modulation order is 2), the number of columns constituting the block interleaver 124 may be 4 instead of 2. In this case, when the length N ldpc of the LDPC codeword is 16200, the number of rows constituting each column may be 4050 (= 16200/4).

Meanwhile, the block interleaver 124 may perform interleaving in the same manner as when the number of columns has the same value as the modulation order or has a value equal to half of the modulation order even when the number of columns has a value that is a multiple of the modulation order. In that it can be, a detailed description thereof will be omitted.

In this case, since the number of columns constituting the block interleaver 124 may have the same value as the modulation order or may be an integer multiple of the modulation order, the number of rows of the second part excluding the group corresponding to the first part It may have the same value as the quotient obtained by dividing the number of bits included in all bit groups by the modulation order or multiple of the modulation order.

Returning to FIG. 1 , the modulator 130 modulates the interleaved LDPC codeword according to a modulation scheme to generate modulation symbols. Specifically, the modulator 130 may generate modulation symbols by demultiplexing the interleaved LDPC codeword, modulating the demultiplexed LDPC codeword, and mapping the modulated LDPC codeword to a constellation.

In this case, the modulator 130 may generate a modulation symbol using bits included in each of a plurality of groups.

That is, as described above, bits included in different groups are written to each column of the block interleaver 124, and the block interleaver 124 reads the bits written to each column in a row direction. In this case, the modulator 130 generates a modulation symbol by mapping bits read from each column of the block interleaver 124 to each bit of the modulation symbol. Accordingly, each bit of the modulation symbol may be a bit included in different groups.

For example, it is assumed that a modulation symbol is composed of C bits. In this case, in that the bits read from each row of C columns of the block interleaver 124 can be mapped to each bit of the modulation symbol, each bit of the modulation symbol composed of C numbers of bits is assigned to C different groups. Bits can be included.

Hereinafter, this will be described in more detail.

First, the modulator 130 may demultiplex the interleaved LDPC codeword. To this end, the modulator 130 may include a demultiplexer (not shown) for demultiplexing the interleaved LDPC codewords.

A demultiplexer (not shown) demultiplexes the interleaved LDPC codewords. Specifically, the demultiplexer (not shown) performs serial-to-parallel conversion on the interleaved LDPC codeword, and converts the interleaved LDPC codeword into cells having a certain number of bits ( Alternatively, demultiplexing may be performed to data cells.

For example, as shown in FIG. 12, the demultiplexer (not shown) receives the LDPC codeword Q=(q ₀ ,q ₁ ,q ₂ ,...) output from the interleaver 120, and inputs The LDPC codeword bits may be sequentially output to one of a plurality of sub-streams, and the input LDPC codeword bits may be converted into cells and output.

Here, the number of substreams N _substreams is equal to the number of bits constituting a modulation symbol η _MOD , and the number of bits constituting a cell may be equal to N _ldpc /η _MOD . Meanwhile, the number of cells generated according to η _MOD according to the modulation scheme and the length N ldpc of the _LDPC codeword may be shown in Table 49 below.

Meanwhile, bits having the same index in each of a plurality of sub streams may constitute the same cell. That is, in FIG. 12, each cell is (y _{0,0 ,} y _{1 ,0} ,...,y _{η MOD -1,0} ), (y _0,1 ,y _1,1 ,..., y _{η MOD} It can be expressed as _-1,1 ),...

Meanwhile, a method of demultiplexing input LDPC codeword bits by a demultiplexer (not shown) may be various. That is, the demultiplexer (not shown) may change the order of LDPC codeword bits and output them to each of a plurality of sub streams, or may sequentially output them to each of a plurality of streams without changing the order of LDPC codeword bits. This operation may be determined according to the number of columns used for interleaving in the block interleaver 124.

Specifically, when the block interleaver 124 includes half as many columns as the number of bits constituting the modulation symbol, the demultiplexer (not shown) changes the order of input LDPC codeword bits to each of a plurality of sub-streams. It can be output, and an example of how to change the order is shown in Table 50 below.

In Table 50 as described above, taking the case where the modulation method is 16-QAM as an example, in the case of 16-QAM, since the number of bits constituting the modulation symbol is 4, the number of sub-streams is 4. In this case, the demultiplexer (not shown) outputs bits for which index i satisfies i mod 4 = 0 among sequentially input bits as the 0th sub-stream, and bits for which index i satisfies i mod 4 = 1 output to the second sub-stream, output bits for which index i satisfies i mod 4 = 2 to the first sub-stream, and bits for which index i satisfies i mod 4 = 3 to the third sub-stream. there is.

Accordingly, the LDPC codeword bits (q ₀ ,q ₁ ,q ₂ ,...) input to the demultiplexer (not shown) are (y _{0 ,0} ,y _{1 ,0} ,y _{2 ,0} ,y _{3 , 0} )=(q ₀ ,q ₂ ,q ₁ ,q ₃ ), (y _0,1 ,y _1,1 ,y _2,1 ,y _3,1 )=(q ₄ ,q ₆ ,q ₅ ,q ₇ ), ... can be output as cells.

On the other hand, when the block interleaver 124 includes the same number of columns as the number of bits constituting the modulation symbol, the demultiplexer (not shown) does not change the order of input LDPC codeword bits and sequentially outputs each of a plurality of streams. can be output to That is, as shown in FIG. 13, the demultiplexer (not shown) sequentially outputs the input LDPC codeword bits (q ₀ , q ₁ , q ₂ , ...) to each sub-stream. Accordingly, Each cell is (y _0,0 ,y _1,0 ,…,y _{η MOD -1,0} )=(q ₀ ,q ₁ ,…,q _{η MOD -1} ), (y _{0 ,1} ,y _{1 , 1} ,…,y _{η MOD -1,1} )=(q _{η MOD} ,q _{η MOD +1} ,…,q _{2 ×ηMOD-1} ),...

Meanwhile, in the above example, it has been described that the demultiplexer (not shown) does not change the order of input LDPC codeword bits and sequentially outputs them to each of a plurality of streams, but this is only an example. That is, according to an embodiment of the present invention, when the block interleaver 124 includes the same number of columns as the number of bits constituting the modulation symbol, the demultiplexer (not shown) may be omitted.

Meanwhile, the modulator 130 may map the demultiplexed LDPC codeword to modulation symbols. However, as described above, when the demultiplexer (not shown) is omitted, the modulator 130 may map the LDPC codeword bits output from the interleaver 120, that is, the block-interleaved LDPC codeword bits to modulation symbols there is.

Specifically, the modulator 130 modulates the bits (ie, cells) output from the demultiplexer (not shown) in various ways such as QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM. It can be modulated using this method. Here, when the modulation schemes are QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM, respectively, the number of bits constituting the modulation symbol η _MOD (ie, modulation order) is 2, respectively. ,4,6,8,10,12 can be.

In this case, since each cell output from the demultiplexer (not shown) is composed of as many bits as the number constituting the modulation symbol, the modulator 130 sequentially assigns each cell output from the demultiplexer (not shown) to a constellation point. A modulation symbol may be generated by mapping. Here, the modulation symbol corresponds to a constellation point in a constellation.

However, when the demultiplexer (not shown) is omitted, the modulator 130 may generate modulation symbols by sequentially dividing interleaved bits by a predetermined number of bits and mapping them to constellation points. In this case, the modulator 130 may generate a modulation symbol by sequentially using η _MOD bits according to a modulation scheme.

Meanwhile, the modulator 130 may perform modulation by mapping cells output from a demultiplexer (not shown) to constellation points using a uniform constellation (UC) method.

Here, the uniform constellation method means a method of mapping modulation symbols to constellation points so that the real component Re(z _q ) and the imaginary component Im(z _q ) of the constellation point have symmetry and the modulation symbols are formed at equal intervals. Accordingly, in the uniform constellation method, at least two modulation symbols among modulation symbols mapped to a constellation may have the same demodulation performance.

Meanwhile, in an embodiment of the present invention, an example of a method for generating modulation symbols using a uniform constellation method may be shown in Tables 51 to 58 below, and an example of a case of uniform constellation 64-QAM is shown in FIG. shown

Here, Table 51 and Table 52 are used to determine the real component Re(z _q ) and the imaginary component Im(z _q ) in the case of performing modulation by the QPSK method, respectively, and Table 53 and Table 54 are respectively 16- It is used to determine the real component Re(z _q ) and the imaginary component Im(z _q ) when modulation is performed by the QAM method, and Tables 55 and 56 show the real component when modulation is performed by the 64-QAM method. It is used to determine Re (z _q ) and the imaginary component Im (z _q ), and Tables 57 and 58 show the real component Re (z _q ) and the imaginary component Im (z q ) in the case of performing modulation in the 256-QAM scheme. _q ) is used to determine

Referring to Tables 51 to 58 described above, performance (eg, reliability) varies depending on whether the plurality of bits constituting the modulation symbol correspond to the most significant byte (MSB) and the least significant bit (LSB). Able to know.

For example, in the case of 16-QAM, each of the first bit and the second bit among the four bits constituting the modulation symbol is the real component Re(z _q ) and the imaginary component Im(z) of a constellation point to which the modulation symbol is mapped. _q ) are bits that determine each sign, and the third and fourth bits are bits that determine the size of a constellation point to which a modulation symbol is mapped.

In this case, among the four bits constituting the modulation symbol, it can be seen that the first bit and the second bit, which determine the code, are more reliable than the third and fourth bits, which are size-determining bits.

As another example, in the case of 64-QAM, each of the first bit and the second bit among the six bits constituting the modulation symbol represents the real component Re(zq) and the imaginary component Im(zq) of a constellation point to which the modulation symbol is mapped, respectively. These are the bits that determine the sign of . In addition, the third to sixth bits are bits that determine the size of the constellation point to which the modulation symbol is mapped, and among them, the third and fourth bits determine a relatively large size, and the fifth and sixth bits determines a relatively small size (e.g., the third bit determines whether the size of a constellation point to which a modulation symbol is mapped belongs to (-7, -5) or (-3, -1), If (-7, -5) is determined by the third bit, whether it is -7 or -5 is determined by the fourth bit).

In this case, among the six bits constituting the modulation symbol, the first and second bits that determine the sign have the highest reliability, and the third and fourth bits that determine the relatively large size are relatively It can be considered to be more reliable than the fifth and sixth bits, which are bits that determine the small size.

As such, in the case of the uniform constellation method, each of the bits constituting the modulation symbol may have a different reliability according to a mapped position within the modulation symbol.

Meanwhile, the modulator 130 may perform modulation by mapping cells output from a demultiplexer (not shown) to constellation points using a non-uniform constellation (NUC) method.

Specifically, the modulator 130 converts the bits output from the demultiplexer (not shown) into non-uniform 16-QAM, non-uniform 64-QAM, non-uniform 256-QAM, non-uniform 1024-QAM, and non-uniform Modulation can be performed using various modulation schemes such as 4096-QAM.

Hereinafter, a method for generating modulation symbols using a non-uniform constellation method according to an embodiment of the present invention will be described.

First, the characteristics of the non-uniform constellation scheme will be briefly described as follows.

Unlike the uniform constellation method, constellation points may not be regularly arranged in the non-uniform constellation method. Therefore, when the non-uniform constellation method is used, performance for an SNR of a specific value or less can be improved compared to the uniform constellation method, and a high SNR gain can be obtained.

Meanwhile, characteristics of a constellation may be determined by one or more parameters such as an interval between constellation points. Since the constellation points in the uniform constellation scheme are regularly distributed, the number of parameters required to specify the uniform constellation scheme can be 1. On the other hand, in the case of the non-uniform constellation scheme, the number of parameters required to specify the non-uniform constellation scheme can be 1. It is relatively large, and the number of parameters may increase as the constellation (eg, the number of constellation points) increases.

Meanwhile, in the case of a non-uniform constellation, the x-axis and the y-axis may be designed symmetrically or non-symmetrically. A non-symmetric design can guarantee better performance, but decoding complexity may increase.

Hereinafter, an example of non-symmetrical design will be presented. In this case, if only constellation points in the first quadrant are defined, positions of constellation points in the other third quadrants can be determined by the following method. For example, if X is the set of constellation points defined for the first quadrant, -conj(X) for the second quadrant, conj(X) for the third quadrant, and -(X) for the fourth quadrant. .

That is, if the first quadrant is defined, the other quadrants can be expressed as follows.

1 Quarter = X

2 Quarter = -conj(X)

3 Quarter = conj(X)

4 Quarter = -X

Specifically, when non-uniform M-QAM is used, M constellation points can be defined as z={z ₀ , z ₁ ,..., z _{M -1} }. At this time, constellation points existing in the first quadrant are {x ₀ , x ₁ , x ₂ , . . . , x _{M /4-1} }, z can be defined as follows.

z ₀ to z _{M /4-1} = x ₀ to x _{M /4}

z _{M /4} to z _{2 ×M/4-1} = -conj(x ₀ to x _{M /4} )

z _{2 ×M/4} to z _{3 ×M/4-1} = conj(x ₀ to x _{M /4} )

z _{3 × M/4} to z _{4 × M/4-1} = -(x ₀ to x _{M /4} )

을 인덱스로 하는 z_L로 매핑하여, 출력 비트들을 non-uniform constellation 방식으로 성성점에 맵핑할 수 있다. 이러한 방식에 따라 non-uniform constellation 방식에 따른 성상도의 일 예는 도 15 내지 도 19와 같다.Therefore, the modulator 130 is an output bit output from a demultiplexer (not shown) [y ₀ , . . . ,y _{m -1} ]

By mapping z _L as an index, output bits can be mapped to constellation points in a non-uniform constellation method. According to this scheme, examples of constellations according to the non-uniform constellation scheme are shown in FIGS. 15 to 19.

Meanwhile, an example of a specific method of performing modulation in a non-uniform constellation manner in the modulator 130 in a non-symmetric manner is shown in Tables 59 to 64 below. That is, according to an embodiment of the present invention, constellation points present in the first quadrant are defined through Tables 59 to 64, and constellation points present in the other quadrants are defined by the above-described method, thereby providing a non-uniform constellation. modulation can be performed.

In Tables 59 to 64, Table 59 shows non-uniform 16-QAM, Tables 60 to 62 show non-uniform 64-QAM, and Tables 63 and 64 show non-uniform 256-QAM. It can be seen that different mapping schemes can be applied.

On the other hand, when the non-uniform constellation is designed so that the x-axis and the y-axis are symmetric, it can be expressed similarly to uniform QAM, and one example is shown in Tables 65 to 68 below.

In Tables 65 to 68, Tables 65 and 66 are tables for determining the real component Re(z _q ) and the imaginary component Im(z _q ) when modulation is performed in a non-uniform 1024-QAM scheme. That is, Table 65 shows the real part of 1024-QAM, and Table 66 shows the imaginary part of 1024-QAM. Tables 67 and 68 show an example of performing modulation in a non-uniform 1024-QAM method, and show values of x _i in Tables 65 and 66.

As described above, since the non-uniform constellation method can map modulation symbols to constellation points in a non-symmetric manner, modulation symbols mapped to constellation points can have different demodulation performance. That is, bits constituting a modulation symbol may have different performance.

For example, referring to FIG. 15 showing an example of a case in which modulation is performed in a non-uniform 64-QAM method, the modulation symbol 10 is (y ₀ ,y ₁ ,y ₂ ,y ₃ ,y ₄ , y ₅ )=(0,0,1,0,1,0), and the performance (eg, capacity) of bits constituting the modulation symbol 10 is C(y ₀ )>C(y ₁ )>C(y ₂ )>C(y ₃ )>C(y ₄ )>C(y ₅ ).

On the other hand, constellations in the uniform constellation method and in the non-uniform constellation method may be rotated and / or scaled (here, scaling factors applied to the real axis and the imaginary axis may be the same or different), and other modifications It is obvious that this can be applied. Also, the illustrated constellations indicate the relative positions of constellation points, from which other constellations may be derived by rotation, scaling, and/or other appropriate transformations.

As such, the modulator 130 may map modulation symbols to constellation points using a uniform constellation method or a non-uniform constellation method. In this case, as described above, the performance of bits constituting the modulation symbol may be different.

Meanwhile, LDPC codeword bits may have different codeword characteristics according to the structure of the parity check matrix. That is, LDPC codeword bits may have different codeword characteristics depending on the number of 1s present in a column of the parity check matrix, that is, the column order.

Therefore, in the present invention, the interleaver 120 performs interleaving so that the LDPC codeword bits can be mapped to the modulation symbol considering both the codeword characteristics of the LDPC codeword bits and the reliability of the bits constituting the modulation symbol.

In particular, when non-uniform QAM is used, since the performance of all bits constituting the modulation symbol is different, the number of columns of the block interleaver 124 is configured equal to the number of bits constituting the modulation symbol to configure the LDPC codeword One of a plurality of groups can be mapped to a bit present in the same position in each modulation symbol.

That is, when LDPC codeword bits with excellent decoding performance are mapped to bits with excellent reliability among bits constituting a modulation symbol, decoding performance may be improved at the receiving side, but LDPC codeword bits with excellent decoding performance are received Problems that cannot be solved may arise. In addition, when LDPC codeword bits having excellent decoding performance are mapped to bits having poor reliability among bits constituting a modulation symbol, overall performance may be excellent due to excellent initial reception performance, but a bit that is difficult to decode If many are received, error propagation may occur.

Therefore, in the present invention, when mapping LDPC codeword bits to modulation symbols, LDPC codeword bits having specific codeword characteristics are obtained by considering both the codeword characteristics of the LDPC codeword bits and the reliability of the bits constituting the modulation symbol. It is mapped to a specific bit in the modulation symbol and transmitted to the receiving side. Accordingly, it is possible to achieve both excellent reception performance and decoding performance at the receiving side.

At this time, in the present invention, the LDPC codeword is divided into groups consisting of M (= 360) bits each having the same codeword characteristics, and the bits are mapped to bits at specific positions of the modulation symbol in units of groups. Bits having specific codeword characteristics can be efficiently mapped to specific positions within a modulation symbol. Also, as described above, the number of bits constituting a group may be a divisor of M. However, for convenience of description, the description will be limited to the case where the number of codeword bits constituting a group is M.

That is, the modulator 130 may map at least one bit included in a preset group among a plurality of groups constituting the LDPC codeword to a preset bit in the modulation symbol. Here, each of the plurality of groups may be composed of M (=360) bits.

For example, in the case of 16-QAM, at least one bit included in a preset group among a plurality of groups may be mapped to a first bit or mapped to a first bit and a second bit in a modulation symbol.

In this way, the reason why the modulator 130 can map at least one bit included in a preset group among a plurality of groups to a preset bit in a modulation symbol is as follows.

As described above, the block interleaver 124 interleaves a plurality of groups constituting the LDPC codeword in group units, a demultiplexer (not shown) demultiplexes bits output from the block interleaver 124, and a modulator ( 130) sequentially maps the demultiplexed bits (i.e. cells) to modulation symbols.

Therefore, the group interleaver 122 disposed before the block interleaver 124 considers the demultiplexing operation performed by the demultiplexer (not shown) so that groups including bits to be mapped to bits at specific positions in the modulation symbol are grouped into the block interleaver 124. ), LDPC codewords are interleaved in groups so that they can be written in the same column.

Specifically, the group interleaver 122 rearranges the order of a plurality of groups in a group unit such that arrangement units in which at least one group including bits mapped to the same position of different modulation symbols are arranged adjacent to each other are sequentially arranged. In this way, the block interleaver 124 may write a preset group to a preset column. That is, the group interleaver 122 interleaves a plurality of groups constituting the LDPC codeword in group units based on Tables 28 to 43 described above, and obtains at least one bit each including bits mapped to the same position of each modulation symbol. The groups are adjacent to each other, and the block interleaver 124 performs interleaving by writing at least one adjacent group to the same column.

Accordingly, the modulator 130 may generate a modulation symbol by mapping bits output from a preset column of the block interleaver 124 to preset bits within the modulation symbol. In this case, bits included in one group may be mapped to one of the bits constituting the modulation symbol or mapped to two of the bits constituting the modulation symbol.

For more detailed description, a case in which an LDPC codeword having a length of 16200 is modulated by non-uniform 64-QAM will be described as an example.

The group interleaver 122 divides LDPC codewords into 16200/360 = 45 groups and performs interleaving on a plurality of groups in group units.

In this case, the group interleaver 122 determines the number of groups that can be written to each column of the block interleaver 124 based on the number of columns of the block interleaver 124, and selects a plurality of groups based on the determined number of groups. Interleaving can be performed on a group basis.

Here, groups written in the same column in the block interleaver 124 are mapped to one specific bit or two specific bits among bits constituting the modulation symbol according to the number of columns of the block interleaver 124, so the group interleaver 122 ) considers the bit properties of the modulation symbol and arranges a plurality of groups in group units such that groups including bits that need to be mapped to the corresponding bits are arranged adjacent to each other, and arrangement units in which the corresponding groups are arranged adjacent to each other are sequentially arranged. interleave with In this case, the group interleaver 122 may use Table 29 described above.

Accordingly, groups positioned adjacent to each other in the LDPC codeword interleaved in group units can be written to the same column of the block interleaver 124, and the bits written to the same column are selected by the modulator 130 as a specific one in the modulation symbol or It is mapped to two bits.

For example, it is assumed that the block interleaver 124 includes as many columns as the number of bits constituting the modulation symbol, that is, includes 6 columns. In this case, as shown in Table 44 or Table 48, each column of the block interleaver 124 may be divided into a first part including 2520 rows and a second part including 180 rows.

Accordingly, in the group interleaver 122, 2520/360=7 groups written in the first part of each column of the block interleaver 124 are adjacent to each other from among a plurality of groups, and each of the 7 adjacent groups is an arrangement unit. Group interleaving is performed so that are sequentially arranged. Accordingly, the block interleaver 124 may write seven groups to the first part of each column, divide the bits included in the remaining three groups, and write the second part of each column.

Then, the block interleaver 124 may read bits written in each row of the first part of the plurality of columns in a row direction, and read bits written in each row of the second part of the plurality of columns in a row direction.

That is, the block interleaver 124 stores the written bits in each row of the plurality of columns in the order from the bit written in the first row of the first column to the bit written in the first row of the sixth column (q ₀ ,q ₁ ,q ₂ ,q ₃ ,q ₄ ,q ₅ ,q ₆ ,q ₇ ,q ₈ ,q ₉ ,q ₁₀ ,q ₁₁ ,... ).

In this case, when a demultiplexer (not shown) is not used or when input bits are sequentially output without changing the order of the demultiplexer (not shown), the LDPC codeword bits output from the block interleaver 124 (q ₀ , q ₁ , q ₂ , q ₃ , q ₄ , q ₅ ), (q ₆ , q ₇ , q ₈ , q ₉ , q ₁₀ , q ₁₁ ), ... are modulated by the modulator 130 . That is, the LDPC codeword bits output from the block interleaver 124 (q ₀ ,q ₁ ,q ₂ ,q ₃ ,q ₄ ,q ₅ ), (q ₆ ,q ₇ ,q ₈ ,q ₉ ,q _{10 . _ _ _ _ _ _ _ _ _ _ _ _} .., and the modulator 130 may generate modulation symbols by mapping cells to constellation points.

Accordingly, the modulator 130 may map bits output from the same column of the block interleaver 124 to one specific bit among bits constituting the modulation symbol. For example, the modulator 130 may map the bits included in the group written in the first column in the block interleaver 124, that is, (q ₀ , q ₆ ,...) to the first bit in the modulation symbol. The bits written in the first column may be bits determined to be mapped to the first bit of each modulation symbol according to codeword characteristics of LDPC codeword bits and reliability of bits constituting the modulation symbol.

In this way, the group interleaver 122 groups a plurality of groups constituting the LDPC codeword in units of groups such that groups including bits to be mapped to one bit at a specific position in the modulation symbol are written to a specific column of the block interleaver 124. can be interleaved.

Meanwhile, it is assumed that the block interleaver 124 includes half as many columns as the number of bits constituting the modulation symbol, that is, three columns. In this case, as shown in Table 47, each column of the block interleaver 124 is not divided into parts, and 5400 bits can be written in each column.

Accordingly, the group interleaver 122 conducts group interleaving so that 5400/360 = 15 groups written in each column of the block interleaver 124 are adjacent to each other, and arrangement units consisting of each of the 15 groups are sequentially arranged. Do it. Accordingly, the block interleaver 124 can write 15 groups in each column.

Then, the block interleaver 124 may read the bits written in each row of the plurality of columns in a row direction.

That is, the block interleaver 124 stores the written bits in each row of the plurality of columns in the order from the bit written in the first row of the first column to the bit written in the first row of the third column (q ₀ ,q ₁ ,q ₂ ,q ₃ ,q ₄ ,q ₅ ,q ₆ ,q ₇ ,q ₈ ,q ₉ ,q ₁₀ ,q ₁₁ ,... ).

In this case, the demultiplexer (not shown) demultiplexes the LDPC codeword bits output from the block interleaver 124 based on Table 50 to obtain (y _{0 ,0} ,y _{1 ,0} ,...,y _{5 ,0} )=( q ₀ ,q ₂ ,q ₄ ,q ₁ ,q ₃ ,q ₅ ), (y _{0 ,1} ,y _{1 ,1} ,…,y _{5 ,1} )=(q ₆ ,q ₈ ,q ₁₀ ,q ₇ ,q ₉ ,q ₁₁ )..., and the modulator 130 may generate a modulation symbol by mapping the cells to constellation points.

Accordingly, the modulator 130 may map bits output from the same column of the block interleaver 124 to specific two bits among bits constituting the modulation symbol. For example, the modulator 130 performs (q ₀ , q among bits (q ₀ ,q ₃ ,q ₆ ,q ₉ ,...) included in the group written in the first column in the block interleaver 124. ₆ ,...) can be mapped to the first bit in the modulation symbol, and (q ₃ ,q ₉ ,...) can be mapped to the fifth bit in the modulation symbol, and the bits written in the first column are LDPC codewords. It may be bits determined to be mapped to the first bit and the fifth bit of each modulation symbol according to the codeword characteristics of the bits and the reliability of the bits constituting the modulation symbol. Here, the first bit in the modulation symbol is a bit that determines the sign of the real component Re(z _q ) of the constellation point to which the modulation symbol is mapped, and the fifth bit in the modulation symbol is the relative value of the constellation point to which the modulation symbol is mapped. It is the bit that determines the small size.

In this way, the group interleaver 122 groups a plurality of groups constituting the LDPC codeword in group units such that groups including bits to be mapped to two bits at a specific position in the modulation symbol are written to a specific column of the block interleaver 124. can be interleaved.

Hereinafter, the encoder 110 performs LDPC encoding at code rates of 10/15, 11/15, 12/15, and 13/15 to generate an LDPC codeword (N _ldpc = 16200) composed of 16200 bits, and modulates Unit 130 assumes a case in which a non-uniform 16-QAM modulation scheme corresponding to a code rate is used based on Table 59.

The present invention will be described in more detail through specific examples.

For example, the encoder 110 performs LDPC encoding at code rates of 10/15, 11/15, 12/15, and 13/15 to generate an LDPC codeword (N _ldpc = 16200) composed of 16200 bits, It is assumed that the modulator 130 uses a non-uniform 16-QAM modulation scheme corresponding to the code rate based on Table 59.

In this case, the group interleaver 122 may perform group interleaving using Equation 11 and Table 28. Meanwhile, according to Table 44 or Table 48, a block interleaver 124 with 4 columns, 3960 (= 360 × 11) rows of the first part, and 90 rows of the second part will be used. can

Accordingly, 11 groups (X ₃₅ , X ₃₁ , X ₃₉ , X ₁₉ , X ₂₉ , X ₂₀ , X ₃₆ , X ₀ , X ₉ , X ₁₃ , X ₅ ) constituting the LDPC codeword are block interleaver ( 124), 11 groups (X ₃₇ , X ₁₇ , X ₄₃ , X ₂₁ , X ₄₁ , X ₂₅ , X ₁ , X ₃₃ , X ₂₄ , X ₁₂ , X ₃₀ ) It is input to the first part of the second column of the block interleaver 124, and 11 groups (X ₁₆ , X ₃₂ , X ₁₀ , X ₂₈ , X ₄ , X ₂₆ , X ₈ , X ₄₀ , X ₄₂ , X ₃ , X ₆ ) is input to the first part of the third column of the block interleaver 124, and 11 groups (X ₂ , X ₃₈ , X ₁₄ , X ₃₄ , X ₂₂ , X ₁₈ , X ₂₇ , X ₂₃ , X ₇ , X ₁₁ , X ₁₅ ) are input to the first part of the fourth column of the block interleaver 124 .

Then, group X ₄₄ is input to the second part of the block interleaver 124. Specifically, the bits constituting the group X ₄₄ are sequentially input to the rows of the first column of the second part, then sequentially input to the rows of the second column, then sequentially input to the rows of the third column, and finally to the fourth column. Columns are entered sequentially in rows. In this case, since group X ₄₄ consists of 360 bits, 90 bits can be input to the second part of each column.

The block interleaver 124 may sequentially output bits input from the first row to the last row of each column, and the bits output from the block interleaver 124 may be sequentially input to the modulator 130. . In this case, the demultiplexer (not shown) may be omitted, or the demultiplexer (not shown) may sequentially output bits without changing the order of input bits.

Accordingly, one bit included in each of the group X ₃₅ , the group X ₃₇ , the group X ₁₆ , and the group X ₂ constitutes one modulation symbol.

According to an embodiment of the present invention, based on group interleaving and block interleaving, one bit included in each of group X ₃₅ , group X ₃₇ , group X ₁₆ , and group X ₂ constitutes one modulation symbol. , In addition to the above method, other methods in which one bit included in each of group X ₃₅ , group X ₃₇ , group X ₁₆ and group X ₂ constitutes one modulation symbol may also be included within the scope of the present invention.

On the other hand, when using Equation 11, the π(j) value defined by Tables 28 to 35 is applied as the index of the input group, and when using Equation 12, the π(j) value defined by Tables 36 to 43 In that they are applied as the index of this output group, they are inverse to each other.

Meanwhile, the transmitting device 100 may modulate a signal mapped to a constellation and transmit the modulated signal to the receiving device (eg, 2700 of FIG. 24 ). For example, the transmitter 100 may map a signal mapped to a constellation to an OFMD frame using an orthogonal frequency division multiplexing (OFDM) scheme and transmit the signal to the receiver 2700 through an assigned channel.

To this end, the transmitter 100 includes a frame mapper (not shown) for mapping a signal mapped to a constellation to an OFDM frame and a transmitter (not shown) for transmitting a signal in the form of an OFDM frame to the receiver 2700. may further include.

block- low interleaver When to use

As another embodiment of the present invention, the interleaver 120 interleaves the LDPC codeword through a method other than the above-described method, so that bits included in a predetermined group among a plurality of groups constituting the interleaved LDPC codeword are interleaved in a modulation symbol. It can be mapped to a preset bit. For a detailed description, reference is made to FIG. 20 .

According to FIG. 20, the interleaver 120 includes a parity interleaver 121, a group interleaver (or group-wise interleaver, 122), a group twist interleaver 123, and a block-row interleaver 125. do. Here, since the parity interleaver 121 and the group twist interleaver 123 perform the same functions as those described in the first embodiment, detailed descriptions of these components will be omitted.

The group interleaver 122 may divide parity-interleaved LDPC codewords into a plurality of groups and rearrange the order of the plurality of groups in units of groups.

In this case, since the operation of classifying the parity-interleaved LDPC codewords into a plurality of groups is the same as in the above-described embodiment, a detailed description thereof will be omitted.

Meanwhile, the group interleaver 122 interleaves the LDPC codewords in groups. That is, the group interleaver 122 may rearrange the order of a plurality of groups within the LDPC codeword in units of groups by changing positions of a plurality of groups constituting the LDPC codeword.

Here, the group interleaver 122 may rearrange the order of the plurality of groups on a group basis so that groups including bits mapped to the same modulation symbol among the plurality of groups are sequentially disposed.

In this case, the group interleaver 122 maps to the same modulation symbol considering the number of rows and columns constituting the block-row interleaver 124, the number of groups constituting the LDPC codeword, and the number of bits included in each group. The order of a plurality of groups may be rearranged in group units so that groups including bits that are

To this end, the group interleaver 122 may interleave the LDPC codewords in groups using Equation 13 below.

Here, X _j represents the j-th group before group interleaving, and Y _j represents the j-th group after group interleaving. Further, π(j) is a parameter indicating an interleaving order, and may be determined by at least one of the length of an LDPC codeword, a code rate, and a modulation scheme.

Accordingly, X _π(j) denotes the π(j)-th group before group interleaving, and Equation 13 means that the π(j)-th group before interleaving is interleaved into the j-th group after interleaving.

Meanwhile, specific examples of π(j) according to an embodiment of the present invention may be defined as Tables 69 to 76 below.

In this case, π(j) is defined according to the length and code rate of the LDPC codeword, and the parity check matrix is also defined according to the length and code rate of the LDPC codeword. Therefore, when LDPC encoding is performed based on a specific parity check matrix according to the length and code rate of the LDPC codeword, the LDPC codeword is group-based based on π(j) that satisfies the length and code rate of the LDPC codeword. can be interleaved with

For example, when the encoder 110 performs LDPC encoding at a code rate of 10/15 to generate an LDPC codeword having a length of 16200, the group interleaver 122 performs the following Tables 69 to 76 Interleaving may be performed using π(j), in which the length of the LDPC codeword is 16200 and the code rate is defined at 10/15.

For example, when the length of the LDPC codeword is 16200, the code rate is 10/15, and the modulation method is 16-QAM, the group interleaver 122 performs interleaving using π(j) defined as shown in Table 69 can do.

Meanwhile, a specific example of π(j) is as follows.

For example, when the length N ldpc of the _LDPC codeword is 16200, the code rates are 10/15, 11/15, 12/15, and 13/15, and the modulation method is 16-QAM, π(j) is shown in Table 69 below. can be defined as

For Table 69, Equation 13 is Y ₀ =X _π(0) =X ₇ , Y ₁ =X _π(1) =X ₄₂ , Y ₂ =X _π(2) =X ₃₇ ,..., Y ₄₃ =X _π(43) =X ₁₃ , Y ₄₄ =X _π(44) =X ₄₄ Accordingly, the group interleaver 122 converts the 7th group to 0, the 42nd group to 1st, the 37th group to 2nd, ..., the 13th group to 43rd, and the 44th group to 44th. Second, the order of a plurality of groups may be rearranged in group units by changing the order.

As another example, when the length N ldpc of the _LDPC codeword is 16200, the code rates are 6/15, 7/15, 8/15, and 9/15, and the modulation method is 64-QAM, π(j) is shown in Table 70 below. can be defined as

For Table 70, Equation 13 is Y ₀ =X _π(0) =X ₃₂ , Y ₁ =X _π(1) =X ₃₉ , Y ₂ =X _π(2) =X ₈ ,..., Y ₄₃ =X _π(43) =X ₄₃ , Y ₄₄ =X _π(44) =X ₄₄ Accordingly, the group interleaver 122 converts the 32nd group to 0, the 39th group to 1st, the 8th group to 2nd, ..., the 43rd group to 43rd, and the 44th group to 44th. Second, the order of a plurality of groups may be rearranged in group units by changing the order.

As another example, when the length N ldpc of the _LDPC codeword is 16200, the code rates are 10/15, 11/15, 12/15, and 13/15, and the modulation method is 256-QAM, π(j) is shown in Table 71 below. can be defined as

For Table 71, Equation 13 is Y ₀ =X _π(0) =X ₂₈ , Y ₁ =X _π(1) =X ₂₂ , Y ₂ =X _π(2) =X ₇ ,..., Y ₄₃ =X _π(43) =X ₄₃ , Y ₄₄ =X _π(44) =X ₄₄ Accordingly, the group interleaver 122 converts the 28th group to 0, the 22nd group to 1st, the 7th group to 2nd, ..., the 43rd group to 43rd, and the 44th group to 44th. Second, the order of a plurality of groups may be rearranged in group units by changing the order.

As another example, when the length N ldpc of the _LDPC codeword is 16200, the code rates are 6/15, 7/15, 8/15, and 9/15, and the modulation method is 1024-QAM, π(j) is shown in Table 72 below can be defined as

For Table 72, Equation 13 is Y ₀ =X _π(0) =X ₁₆ , Y ₁ =X _π(1) =X ₂₄ , Y ₂ =X _π(2) =X ₃₂ ,..., Y43 =X _π(43) =X ₄₃ , Y ₄₄ =X _π(44) =X ₄₄ . Accordingly, the group interleaver 122 converts the 16th group to 0, the 24th group to 1st, the 32nd group to 2nd, ..., the 43rd group to 43rd, and the 44th group to 44th. Second, the order of a plurality of groups may be rearranged in group units by changing the order.

As another example, when the length N ldpc of the _LDPC codeword is 64800, the code rates are 6/15, 7/15, 8/15, and 9/15, and the modulation method is 256-QAM, π(j) is shown in Table 73 below. can be defined as

For Table 73, Equation 13 is Y ₀ =X _π(0) =X ₄₈ , Y ₁ =X _π(1) =X ₁₅₂ , Y ₂ =X _π(2) =X ₁₅₆ ,..., Y ₁₇₈ =X _π(178) =X ₁₇₈ , Y ₁₇₉ =X _π(179) =X ₁₇₉ Accordingly, the group interleaver 122 converts the 48th group to 0, the 152nd group to 1st, the 156th group to 2nd, ..., the 178th group to 178th, and the 179th group to 179th. Second, the order of a plurality of groups may be rearranged in group units by changing the order.

As another example, when the length N ldpc of the _LDPC codeword is 64800, the code rates are 6/15, 7/15, 8/15, and 9/15, and the modulation method is 16-QAM, π(j) is shown in Table 74 below. can be defined as

For Table 74, Equation 13 is Y ₀ =X _π(0) =X ₁₂₁ , Y ₁ =X _π(1) =X ₆₅ , Y ₂ =X _π(2) =X ₁₅₂ ,..., Y ₁₇₈ =X _π(178) =X ₁₄₆ , Y ₁₇₉ =X _π(179) =X ₉₆ . Accordingly, the group interleaver 122 converts the 121st group to 0, the 65th group to 1st, the 152nd group to 2nd, ..., the 146th group to 178th, and the 96th group to 179th. Second, the order of a plurality of groups may be rearranged in group units by changing the order.

As another example, when the length N ldpc of the _LDPC codeword is 64800, the code rates are 10/15, 11/15, 12/15, and 13/15, and the modulation method is 64-QAM, π(j) is shown in Table 75 below. can be defined as

For Table 75, Equation 13 is Y ₀ =X _π(0) =X ₄₉ , Y ₁ =X _π(1) =X ₆₉ , Y ₂ =X _π(2) =X ₆₁ ,..., Y ₁₇₈ =X _π(178) =X ₁₅ , Y ₁₇₉ =X _π(179) =X ₁₇₆ Accordingly, the group interleaver 122 converts the 49th group to 0, the 69th group to 1st, the 61st group to 2nd, ..., the 15th group to 178th, and the 176th group to 179th. Second, the order of a plurality of groups may be rearranged in group units by changing the order.

As another example, when the length N ldpc of the _LDPC codeword is 64800, the code rates are 10/15, 11/15, 12/15, and 13/15, and the modulation method is 1024-QAM, π(j) is shown in Table 76 below can be defined as

For Table 76, Equation 13 is Y ₀ =X _π(0) =X ₄₅ , Y ₁ =X _π(1) =X ₄₆ , Y ₂ =X _π(2) =X ₇₁ ,..., Y ₁₇₈ =X _π(178) =X ₁₆₆ , Y ₁₇₉ =X _π(179) =X ₁₆₅ Accordingly, the group interleaver 122 converts the 45th group to 0, the 46th group to 1st, the 71st group to 2nd, ..., the 166th group to 178th, and the 165th group to 179th. Second, the order of a plurality of groups may be rearranged in group units by changing the order.

As such, the group interleaver 122 may rearrange the order of the plurality of groups in a group unit using Equation 13 and Tables 69 to 76.

Meanwhile, the group interleaver 122 may interleave the LDPC codewords in groups using Equation 14 below.

Here, X _j represents the j-th group before group interleaving, and Y _j represents the j-th group after group interleaving. Further, π(j) is a parameter indicating an interleaving order, and may be determined by at least one of the length of an LDPC codeword, a code rate, and a modulation scheme.

Accordingly, Y _π(j) denotes a π(j)-th group after group interleaving, and Equation 14 means that the j-th group before interleaving is interleaved into a π(j)-th group after interleaving.

Meanwhile, specific examples of π(j) according to an embodiment of the present invention may be defined as Tables 77 to 84 below.

In this case, π(j) is defined according to the length and code rate of the LDPC codeword, and the parity check matrix is also defined according to the length and code rate of the LDPC codeword. Therefore, when LDPC encoding is performed based on a specific parity check matrix according to the length and code rate of the LDPC codeword, the LDPC codeword is group-based based on π(j) that satisfies the length and code rate of the LDPC codeword. can be interleaved with

For example, when the encoder 110 performs LDPC encoding at a code rate of 10/15 to generate an LDPC codeword having a length of 16200, the group interleaver 122 performs the following Tables 77 to 84 Interleaving can be performed using π(j), in which the length of the LDPC codeword is 16200 and the code rate is defined at 10/15.

For example, when the length of the LDPC codeword is 16200, the code rate is 10/15, and the modulation method is 16-QAM, the group interleaver 122 performs interleaving using π(j) defined as shown in Table 77 can do.

Meanwhile, a specific example of π(j) is as follows.

For example, when the length N ldpc of the _LDPC codeword is 16200, the code rates are 10/15, 11/15, 12/15, and 13/15, and the modulation method is 16-QAM, π(j) is shown in Table 77 below. can be defined as

For Table 77, Equation 14 is X ₀ =Y _π(0) =Y ₁₁ , X ₁ =Y _π(1) =Y ₃₈ , X ₂ =Y _π(2) =Y ₂₇ ,..., X ₄₃ =Y _π(43) =Y ₁₃ , X ₄₄ =Y _π(44) =Y ₄₄ . Accordingly, the group interleaver 122 converts the 0th group to the 11th, the 1st group to the 38th, the 2nd group to the 27th, ..., the 43rd group to the 17th, and the 44th group to the 44th. Second, the order of a plurality of groups may be rearranged in group units by changing the order.

As another example, when the length N ldpc of the _LDPC codeword is 16200, the code rates are 6/15, 7/15, 8/15, and 9/15, and the modulation method is 64-QAM, π(j) is shown in Table 78 below. can be defined as

For Table 78, Equation 14 is X ₀ =Y _π(0) =Y ₂₆ , X ₁ =Y _π(1) =Y ₂₂ , X ₂ =Y _π(2) =Y ₄₁ ,..., X ₄₃ =Y _π(43) =Y ₄₃ , X ₄₄ =Y _π(44) =Y ₄₄ . Accordingly, the group interleaver 122 converts the 0th group to the 26th, the 1st group to the 22nd, the 2nd group to the 41st, ..., the 43rd group to the 43rd, and the 44th group to the 44th. Second, the order of a plurality of groups may be rearranged in group units by changing the order.

As another example, when the length N ldpc of the _LDPC codeword is 16200, the code rates are 10/15, 11/15, 12/15, and 13/15, and the modulation method is 256-QAM, π(j) is shown in Table 79 below. can be defined as

For Table 79, Equation 14 is X ₀ =Y _π(0) =Y ₃₂ , X ₁ =Y _π(1) =Y ₂₆ , X ₂ =Y _π(2) =Y ₁₄ ,..., X ₄₃ =Y _π(43) =Y ₄₃ , X ₄₄ =Y _π(44) =Y ₄₄ . Accordingly, the group interleaver 122 converts the 0th group to the 32nd, the 1st group to the 26th, the 2nd group to the 14th, ..., the 43rd group to the 43rd, and the 44th group to the 44th. Second, the order of a plurality of groups may be rearranged in group units by changing the order.

As another example, when the length N ldpc of the _LDPC codeword is 16200, the code rates are 6/15, 7/15, 8/15, and 9/15, and the modulation method is 1024-QAM, π(j) is shown in Table 80 below. can be defined as

For Table 80, Equation 14 is X ₀ =Y _π(0) =Y ₂₂ , X ₁ =Y _π(1) =Y ₂₀ , X ₂ =Y _π(2) =Y ₇ ,..., X ₄₃ =Y _π(43) =Y ₄₃ , X ₄₄ =Y _π(44) =Y ₄₄ . Accordingly, the group interleaver 122 converts the 0th group to the 22nd, the 1st group to the 20th, the 2nd group to the 7th, ..., the 43rd group to the 43rd, and the 44th group to the 44th. Second, the order of a plurality of groups may be rearranged in group units by changing the order.

As another example, when the length N ldpc of the _LDPC codeword is 64800, the code rates are 6/15, 7/15, 8/15, and 9/15, and the modulation method is 256-QAM, π(j) is shown in Table 81 below can be defined as

For Table 81, Equation 14 is X ₀ =Y _π(0) =Y ₇₂ , X ₁ =Y _π(1) =Y ₄₈ , X ₂ =Y _π(2) =Y ₅₅ ,..., X ₁₇₈ =Y _π(178) =Y ₁₇₈ , X ₁₇₉ =Y _π(179) =Y ₁₇₉ Accordingly, the group interleaver 122 converts the 0th group to the 72nd, the 1st group to the 48th, the 2nd group to the 55th, ..., the 178th group to the 178th, and the 179th group to the 179th. Second, the order of a plurality of groups may be rearranged in group units by changing the order.

As another example, when the length N ldpc of the _LDPC codeword is 64800, the code rates are 6/15, 7/15, 8/15, and 9/15, and the modulation method is 16-QAM, π(j) is shown in Table 82 below. can be defined as

For Table 82, Equation 14 is X ₀ =Y _π(0) =Y ₃ , X ₁ =Y _π(1) =Y ₄₅ , X ₂ =Y _π(2) =Y ₁₇₅ ,..., X ₁₇₈ =Y _π(178) =Y ₁₁ , X ₁₇₉ =Y _π(179) =Y ₁₀₄ . Accordingly, the group interleaver 122 converts the 0th group to the 3rd, the 1st group to the 45th, the 2nd group to the 175th, ..., the 178th group to the 11th, and the 179th group to the 104th. Second, the order of a plurality of groups may be rearranged in group units by changing the order.

As another example, when the length N ldpc of the _LDPC codeword is 64800, the code rates are 10/15, 11/15, 12/15, and 13/15, and the modulation method is 64-QAM, π(j) is shown in Table 83 below. can be defined as

For Table 83, Equation 14 is X ₀ =Y _π(0) =Y ₁₁₂ , X ₁ =Y _π(1) =Y ₁₆₁ , X ₂ =Y _π(2) =Y ₁₄₇ ,..., X ₁₇₈ =Y _π(178) =Y ₃₅ , X ₁₇₉ =Y _π(179) =Y ₆₄ . Accordingly, the group interleaver 122 converts the 0th group to the 112th, the 1st group to the 161st, the 2nd group to the 147th, ..., the 178th group to the 35th, and the 179th group to the 64th. Second, the order of a plurality of groups may be rearranged in group units by changing the order.

As another example, when the length N ldpc of the _LDPC codeword is 64800, the code rates are 10/15, 11/15, 12/15, and 13/15, and the modulation method is 1024-QAM, π(j) is shown in Table 84 below. can be defined as

For Table 84, Equation 14 is X ₀ =Y _π(0) =Y ₁₂₀ , X ₁ =Y _π(1) =Y ₁₄₁ , X ₂ =Y _π(2) =Y ₁₃₀ ,..., X ₁₇₈ =Y _π(178) =Y ₉₈ , X ₁₇₉ =Y _π(179) =Y ₁₉ . Accordingly, the group interleaver 122 converts the 0th group to the 120th, the 1st group to the 141st, the 2nd group to the 130th, ..., the 178th group to the 98th, and the 179th group to the 19th. Second, the order of a plurality of groups may be rearranged in group units by changing the order.

As such, the group interleaver 122 may rearrange the order of the plurality of groups in a group unit using Equation 14 and Tables 77 to 84.

Meanwhile, groups constituting the LDPC codeword are rearranged in group units by the group interleaver 122 and then block interleaved by the block interleaver 124 to be described later. In Tables 69 to 84, π(j ) was described as "Order of bits group to be block interleaved".

When group interleaving is performed based on Tables 69 to 84, the order of the groups constituting the group-interleaved LDPC codewords is different from the group constituting the group-interleaved LDPC codewords based on Tables 28 to 43. do.

This is because the block-row interleaver 125 is used instead of the block interleaver 124 in this embodiment. That is, since the interleaving method used by the block interleaver 124 and the interleaving method used by the block-row interleaver 125 are different, the group interleaver 122 in this embodiment uses LDPC based on Tables 69 to 84 The order of a plurality of groups constituting the codeword is rearranged.

Specifically, the group interleaver 122 may rearrange the order of the plurality of groups in a group unit such that an arrangement unit in which at least one group including bits mapped to the same modulation symbol is sequentially arranged in a group unit is repeated.

That is, the group interleaver 122 is one of a plurality of first groups including bits mapped to a specific first position of the modulation symbol, and a plurality of second groups including bits mapped to a specific second position of the modulation symbol. One, ..., one of a plurality of n-th groups including bits mapped to a specific n-th position of a modulation symbol may be sequentially arranged, and the remaining groups may be repeatedly arranged in the same manner.

The block-row interleaver 125 interleaves the plurality of rearranged groups. In this case, the block-row interleaver 125 may interleave the plurality of groups whose order is rearranged using at least one row composed of a plurality of columns. 21 to 23 are referred to for a more detailed description.

21 to 23 are diagrams for explaining a structure of a block-row interleaver and an interleaving method according to an embodiment of the present invention.

First, when N _group /m is an integer, the block-row interleaver 125 includes an interleaver 125-1 composed of m rows each including M columns as shown in FIG. 21, and the block-row interleaver ( 125) may perform interleaving using N _groups /m interleavers 125-1 having the structure shown in FIG.

Here, N _group is the total number of groups constituting the LDPC codeword. And, M is the number of bits included in one group, for example, 360, m may be equal to the number of bits constituting the modulation symbol or 1/2 of the number of bits constituting the modulation symbol. there is. For example, when non-uniform QAM is used, since the performance of bits constituting a modulation symbol is all different, the value m is configured equal to the number of bits constituting a modulation symbol so that one group constitutes a modulation symbol. so that it can be mapped to one bit.

Specifically, the block-row interleaver 125 writes each of a plurality of groups constituting the LDPC codeword in a row direction on each row in a group unit, and writes each column of a plurality of rows in which the plurality of groups are written in a group unit Interleaving may be performed by reading in the column direction.

For example, as shown in FIG. 21, the block-row interleaver 125 writes m consecutive groups among a plurality of groups in the row direction to each of the m rows constituting the interleaver 125-1, and writes the bits. Each column of the m number of rows can be read in the column direction. In this case, a quotient obtained by dividing the number of groups by the number of rows, that is, as many as N _groups /m interleaver 125-1 may be used.

As such, when the number of groups constituting the LDPC codeword is an integer multiple of the number of rows, the block-row interleaver 125 can perform interleaving by sequentially writing as many groups as the number of rows among a plurality of groups. .

Meanwhile, when the number of groups constituting the LDPC codeword is not an integer multiple of the number of rows, the block-row interleaver 125 uses N (N is an integer greater than or equal to 2) interleavers including different numbers of columns. Interleaving can be performed using

×m이고,

는 N_group/m 이하의 가장 큰 정수를 나타낸다.For example, as shown in FIGS. 22 and 23, the block-row interleaver 125 includes a first interleaver 125-2 composed of m rows each including M columns and each a×M/m columns. Interleaving may be performed using the second interleaver 125-3 composed of m rows. Here, a is N _group -

×m,

represents the largest integer less than or equal to N _group /m.

개가 이용될 수 있고, 제2 인터리버(125-3)는 1 개가 이용될 수 있다. In this case, the first interleaver 125-2

A dog may be used, and one second interleaver 125-3 may be used.

×m 개 그룹 각각을 그룹 단위로 각 행에 행 방향으로 라이트하고,

×m 개 그룹이 그룹 단위로 라이트된 복수의 행의 각 열을 열 방향으로 리드하여 인터리빙을 수행할 수 있다.Specifically, the block-row interleaver 125 among a plurality of groups constituting the LDPC codeword

Each of the ×m groups is lit in the row direction in each row by group unit,

Interleaving may be performed by reading each column of a plurality of rows in which ×m groups are written in a group unit in a column direction.

×m 개 그룹 중에서 행의 개수와 동일한 개수의 연속된 m 개의 그룹을 제1 인터리버(125-2)의 각 행에 행 방향으로 라이트하고, m 개의 그룹이 라이트된 제1 인터리버(125-2)의 복수의 행의 각 열을 열 방향으로 리드할 수 있다. 이 경우, 도 22 및 도 23과 같은 구조를 갖는 제1 인터리버(125-2)가

개만큼 이용될 수 있다.For example, as shown in FIGS. 22 and 23, the block-row interleaver 125

The first interleaver 125-2 in which the number of consecutive m groups equal to the number of rows among x m groups is written in the row direction to each row of the first interleaver 125-2, and m groups are written Each column of a plurality of rows of can be read in the column direction. In this case, the first interleaver 125-2 having the structure shown in FIGS. 22 and 23

Can be used as much as dogs.

Also, m may be the product of the number of bits constituting the modulation scheme and the number of antennas in a system using multiple antennas.

Thereafter, the block-row interleaver 125 divides the bits included in the remaining groups except for the group written in the first interleaver 125-2 and writes them to each row of the second interleaver 125-3 in a row direction. can In this case, the same number of bits may be written to each row of the second interleaver 125-3. That is, one bit group may be input to multiple rows of the second interleaver 125-3.

For example, as shown in FIG. 22, the block-row interleaver 125 converts the bits included in the remaining groups except for the group written to the first interleaver 125-2 to m constituting the second interleaver 125-3. Each a×M/m number of rows may be written in a row direction, and each column of the m rows of the second interleaver 125-3 in which bits are written may be read in a column direction. In this case, one second interleaver 125-3 having a structure as shown in FIG. 22 may be used.

However, according to another embodiment of the present invention, as shown in FIG. 23, the block-row interleaver 125 writes bits to the first interleaver 125-2 in the same manner as described in FIG. , bits may be written to the second interleaver 125-3 in a method different from the method described in FIG. 22.

That is, the block-row interleaver 125 may write bits to the second interleaver 125-3 in a column direction.

For example, as shown in FIG. 23, the block-row interleaver 125 transfers the bits included in the remaining groups except for the group written to the first interleaver 125-2 to each of those constituting the second interleaver 125-3. Bits may be written in a column direction in each column of m rows composed of a×M/m columns, and each column of m rows of the second interleaver 125-3 in which bits are written may be read in a column direction. In this case, one second interleaver 125-3 having a structure as shown in FIG. 23 may be used.

Meanwhile, in the case of the method shown in FIG. 23, the block-row interleaver 125 performs interleaving by writing bits to the second interleaver in a column direction and then reading them in a column direction. Accordingly, the bits included in the group interleaved by the second interleaver are read in the order in which they are written and output to the modulator 130 . Accordingly, bits included in groups belonging to the second interleaver may be sequentially mapped to modulation symbols without rearranging the order by the block-row interleaver 125 . As such, the block-row interleaver 125 may perform interleaving on at least some of the plurality of groups, and may not perform interleaving on the remaining groups. Specifically, the block-row interleaver 125 performs interleaving by sequentially writing LDPC codewords constituting at least some of a plurality of groups into a plurality of rows and reading them in a column direction, but interleaving is performed on the remaining groups may not That is, since the block-row interleaver 125 writes and reads the bits included in the remaining groups in the same direction, the bits included in the remaining groups may be output without changing their order.

Also, in the above example, it has been described that the bits included in the remaining groups are written and read in the column direction, but this is only an example. That is, the block-row interleaver 125 may write and read bits included in the remaining groups in a row direction, and even in this case, the bits included in the remaining groups may be output without changing their order.

As such, the block-row interleaver 125 may interleave a plurality of groups using the method described with reference to FIGS. 21 to 23 .

According to this method, the output of the block-row interleaver 125 may be the same as the output of the block interleaver 124. Specifically, when the block-row interleaver 125 performs interleaving as shown in FIG. 21, it outputs the same value as the block interleaver 124 performing interleaving as shown in FIG. When interleaving is performed as shown in FIG. 9, the same value as that of the block interleaver 124 performing interleaving is output, and when the block-row interleaver 125 performs interleaving as shown in FIG. 23, interleaving is performed as shown in FIG. 10. It may output the same value as the block interleaver 124 performing.

Specifically, when the group interleaver 122 is used and the block interleaver 124 is used based on Equation 11, output groups of the group interleaver 122 are Y _i (0≤j<N _group ), and Equation 13 When the group interleaver 122 is used based on and the block-row interleaver 125 is used, when the output groups of the group interleaver 122 are Z _i (0≤j<N _group ), the output group after group interleaving The relationship between Z _i and Y _i can be expressed as Equations 15 and 16 below, and eventually, the same value can be output from the block interleaver 124.

로, 블록 인터리버(124)를 사용할 경우 제 1 파트의 하나의 열에 입력되는 그룹의 개수를 의미하며,

는 N_group/m 이하의 가장 큰 정수이다. 그리고, m은 변조 심볼을 구성하는 비트의 개수와 동일하거나, 변조 심볼을 구성하는 비트의 절반일 수 있다. 또한, m은 블록 인터리버(124)의 열의 개수를 의미하고, m은 블록-로우 인터리버(125)의 행의 개수를 의미한다.where α =

, which means the number of groups input to one column of the first part when using the block interleaver 124,

is the largest integer less than or equal to N _group /m. And, m may be the same as the number of bits constituting the modulation symbol, or may be half of the bits constituting the modulation symbol. Also, m denotes the number of columns of the block interleaver 124, and m denotes the number of rows of the block-row interleaver 125.

Accordingly, the modulator 130 may map bits output from the block-row interleaver 125 to modulation symbols in the same manner as in the case of using the block interleaver 124 .

Meanwhile, the bit interleaving method proposed in the present invention is composed of a parity interleaver 121, a group interleaver 122, a group twist interleaver 123, and a block interleaver 124 as shown in FIG. , the parity interleaver 121 or the group twist interleaver 123 can be omitted), which is only an example and does not need to be limited to being composed of three modules or four modules as described above.

For example, when a block interleaver is used in the present invention and a group interleaving method expressed as in Equation 13 is used, bit groups X _j defined as in Equation 9 and Equation 10 (0≤j<N _group ) For m bit groups such as {X _π(i) , X _π(α+i) ,...,X _{π((m-1)×α+i)} } (0≤i<α) Bits belonging to constitute one modulation symbol.

이다. 그리고, m은 블록 인터리버의 열의 개수를 의미하며, 이는 변조 심볼을 구성하는 비트의 개수 또는 변조 심볼을 구성하는 비트의 개수의 절반일 수 있다.Here, α is the number of bit groups constituting the first part of the block interleaver, and α =

am. And, m means the number of columns of the block interleaver, which may be half of the number of bits constituting the modulation symbol or the number of bits constituting the modulation symbol.

Therefore, as an example, for parity interleaved bits u _i , {u _π(i)+j , u _π(α+i)+j ,...,u _{π((m-1)×α+i ) + j} } (0<i≤m, 0<j≤M) may constitute one modulation symbol. In this way, there may be various methods of constructing one modulation symbol.

In addition, the bit interleaving method proposed in the present invention is composed of a parity interleaver 121, a group interleaver 122, a group twist interleaver 123, and a block-row interleaver 125 as shown in FIG. Accordingly, the group twist interleaver 123 can be omitted), which is only an example and does not need to be limited to being composed of 3 modules or 4 modules as described above.

For example, when a block-row interleaver is used in the present invention and a group interleaving method expressed as in Equation 12 is used, bit groups X _j defined as in Equation 9 and Equation 10 (0≤j<N _group ), m bit groups such as {X _π(m×i) , X _π(m×i+1) ,...,X _{π(m×i+(m-1))} } (0 Bits belonging to ≤i<α constitute one modulation symbol.

이다. 그리고, m은 블록 인터리버의 열의 개수를 의미하며, 이는 변조 심볼을 구성하는 비트의 개수 또는 변조 심볼을 구성하는 비트의 개수의 절반일 수 있다.Here, α is the number of bit groups constituting the first part of the block interleaver, and α =

am. And, m means the number of columns of the block interleaver, which may be half of the number of bits constituting the modulation symbol or the number of bits constituting the modulation symbol.

Therefore, as an example, for parity interleaved bits u _i , {u _π(m×i)+j , u _π(m×i+1)+j ,...,u _{π(m×i+(m -1)) + j} } (0<i≤m, 0<j≤M) may constitute one modulation symbol. In this way, there may be various methods of constructing one modulation symbol.

Meanwhile, in the present invention, the transmitter 100 may use an interleaving method differently according to a set including at least one of a code rate, a length of an LDPC codeword, and a modulation method.

For example, the transmitter 100 may perform interleaving using the block interleaver 124 in the first set including the specific code rate, the length of the LDPC codeword, and the modulation method, and different from the first set. Interleaving may be performed using the block-row interleaver 125 in the second set including the specific code rate, the length of the LDPC codeword, and the modulation method.

24 is a block diagram for explaining the configuration of a receiving device according to an embodiment of the present invention. Referring to FIG. 24 , a receiving apparatus 2700 includes a demodulator 2710, a multiplexer 2720, a deinterleaver 2730, and a decoder 2740.

The demodulator 2710 receives and demodulates the signal transmitted from the transmitter 100 . Specifically, the demodulator 2710 demodulates the received signal to generate a value corresponding to the LDPC codeword, and outputs it to the multiplexer 2720. In this case, the demodulator 2710 may perform demodulation to correspond to the modulation method used in the transmitter 100 .

To this end, the transmitter 100 may transmit information on the modulation scheme to the receiver 2700, or the transmitter 100 may perform modulation using a predefined modulation scheme between the transmitter 2700 and the receiver 2700. can be performed.

Here, a value corresponding to the LDPC codeword may be expressed as a channel value for the received signal. There may exist various methods for determining the channel value, and for example, a method for determining a Log Likelihood Ratio (LLR) value may be used.

The LLR value may be expressed as a value obtained by taking Log of a ratio of a probability that a bit transmitted from the transmitter 100 is 0 and a probability that it is 1. Alternatively, the LLR value may be a bit value itself determined according to a hard decision, and also, the LLR value is a representative value determined according to a section to which the probability that the bit transmitted by the transmitting device 100 is 0 or 1 belongs. It could be.

The multiplexer 2720 multiplexes the output value of the demodulator 2710 and outputs it to the deinterleaver 2730.

Specifically, the multiplexer 2720 is a component corresponding to a demultiplexer (not shown) included in the transmitter 100 and performs an operation corresponding to the demultiplexer (not shown). Accordingly, when a demultiplexer (not shown) is omitted in the transmitter 100, the multiplexer 2720 of the receiver 2700 may be omitted.

That is, the multiplexer 2720 may perform cell-to-bit conversion on the output value of the demodulator 2710 and output an LLR value in bit units.

In this case, when the demultiplexer (not shown) does not change the order of the LDPC codeword bits as shown in FIG. 13, the multiplexer 2720 does not change the order of the LLR values corresponding to the bits constituting the cell and LLR values can be output sequentially. Alternatively, the multiplexer 2720 may rearrange the order of the LLR values corresponding to the bits constituting the cell to be the reverse of the demultiplexing operation performed by the demultiplexer (not shown) based on Table 50. Meanwhile, information on whether or not the demultiplexing operation is performed may be provided from the transmitter 100 or pre-stored between the transmitter 100 and the receiver 2700 .

The deinterleaver 2730 deinterleaves the output value of the multiplexer 2720 and outputs it to the decoder 2740.

Specifically, the deinterleaver 2730 is a component corresponding to the interleaver 120 of the transmitter 100 and performs an operation corresponding to the interleaver 120 . That is, the deinterleaver 2730 reversely performs the interleaving operation performed by the interleaver 120 to deinterleave the LLR values.

To this end, the deinterleaver 2730 may include components as shown in FIGS. 25 and 27 .

First, as shown in FIG. 25 , the deinterleaver 2730 may include a block deinterleaver 2731, a group twist deinterleaver 2732, a group deinterleaver 2733, and a parity deinterleaver 2734.

The block deinterleaver 2731 deinterleaves the output of the multiplexer 2720 and outputs it to the group twist deinterleaver 2732.

Specifically, the block deinterleaver 2731 is a component corresponding to the block interleaver 124 provided in the transmitter 100, and may reversely perform the interleaving operation performed by the block interleaver 124.

That is, the block deinterleaver 2731 writes the LLR values output from the multiplexer 2720 to each row in a row direction using at least one row composed of a plurality of columns, and writes each of the plurality of rows in which the LLR values are written. Deinterleaving may be performed by leading columns in a column direction.

In this case, when the block interleaver 124 divides a column into two parts and performs interleaving, the block deinterleaver 2731 divides a row into two parts and performs deinterleaving.

In addition, when the block interleaver 124 writes and reads the groups not belonging to the first part in the row direction, the block deinterleaver 2731 writes and reads the values corresponding to the groups not belonging to the first part in the row direction. Deinterleaving may be performed by reading.

Hereinafter, the block deinterleaver 2731 will be described with reference to FIG. 26 . However, this is only an example, and the block deinterleaver 2731 may be implemented in other ways, of course.

,

이다.The input LLR v _i (0≤i<N _ldpc ) is written to row r _i and column c _i of the block deinterleaver 2431. From here,

,

am.

,

이다.On the other hand, the output LLR q _i (0≤i<N _c ×N _r1 ) is read from column c _i and row r _i of the first part of the block deinterleaver 2431 . From here,

,

am.

,

이다.Then, the output LLR q _i (N _c ×N _r1 ≤ i<N _ldpc ) is read from column c _i and row r _i of the second part of the block deinterleaver 2431 . From here,

,

am.

The group twist deinterleaver 2732 deinterleaves the output value of the block deinterleaver 2431 and outputs it to the group deinterleaver 2733.

Specifically, the group twist deinterleaver 2732 is a component corresponding to the group twist interleaver 123 provided in the transmitter 100, and may reversely perform the interleaving operation performed by the group twist interleaver 123. .

That is, the group twist deinterleaver 2732 may rearrange LLR values within the same group by changing the order of LLR values existing within the same group. Meanwhile, when the group twist operation is not performed in the transmitter 100, the group twist deinterleaver 2732 may be omitted.

The group deinterleaver 2733 (or group-wise deinterleaver) deinterleaves the output value of the group twist deinterleaver 2732 and outputs it to the parity deinterleaver 2734.

Specifically, the group deinterleaver 2733 is a component corresponding to the group interleaver 122 provided in the transmitter 100, and may reversely perform the interleaving operation performed by the group interleaver 122.

That is, the group deinterleaver 2733 may rearrange the order of the plurality of groups on a group basis. In this case, the group deinterleaver 2733 may reversely apply the interleaving methods of Tables 28 to 43 according to the length of the LDPC codeword, the modulation method, and the code rate, and rearrange the order of the plurality of groups into groups.

Meanwhile, as described above, in the parity check matrices shown in FIGS. 2 and 3, the order of column groups can be changed, and the column groups correspond to bit groups. Accordingly, when the order of the column groups of the parity check matrix is changed, the order of the bit groups may also be changed to correspond thereto, and the group deinterleaver 2733 may rearrange the order of the plurality of groups group by group with reference to this.

The parity deinterleaver 2734 performs parity deinterleaving on the output value of the group deinterleaver 2733 and outputs it to the decoder 2740.

Specifically, the parity deinterleaver 2734 is a component corresponding to the parity interleaver 121 provided in the transmitter 100, and may reversely perform the interleaving operation performed by the parity interleaver 121. That is, the parity deinterleaver 2734 may deinterleave LLR values corresponding to parity bits among the LLR values output from the group deinterleaver 2733. In this case, the parity deinterleaver 2734 may deinterleave the LLR values corresponding to the parity bits in reverse of the parity interleaving method of Equation 8. However, the parity deinterleaver 2734 may be omitted depending on the decoding method and implementation of the decoding unit 2740.

Meanwhile, the deinterleaver 2730 of FIG. 24 may be composed of three or four components as shown in FIG. 25, but the operation of the components may be performed by one component. For example, when one bit belonging to each of the bit groups X _a , X _b , X _c , and X _d constitutes one modulation symbol, the deinterleaver 2730 transmits one received Deinterleaving may be performed at positions corresponding to bit groups based on modulation symbols.

For example, when the code rate is 12/15 and the modulation method is 16-QAM, the group deinterleaver 2733 may perform deinterleaving based on Table 28.

In this case, one bit included in each of the bit groups X ₃₅ , X ₃₇ , X ₁₆ , and X ₂ constitutes one modulation symbol. Since one bit each of the bit groups X ₃₅ , X ₃₇ , X ₁₆ , and X ₂ constitutes one modulation symbol, the deinterleaver 2730 converts the bit groups X ₃₅ and X ₃₇ based on the received one modulation symbol. , X ₁₆ , and X ₂ may be mapped to initial decoding values.

Meanwhile, as shown in FIG. 27 , the deinterleaver 2730 may include a block-row deinterleaver 2735, a group twist deinterleaver 2732, a group deinterleaver 2733, and a parity deinterleaver 2734. In this case, since the group twist deinterleaver 2732 and the parity deinterleaver 2734 perform the same functions as those of FIG. 25, detailed descriptions of overlapping parts are omitted.

The block-row deinterleaver 2735 deinterleaves the output value of the multiplexer 2720 and outputs it to the group twist deinterleaver 2732.

Specifically, the block-row deinterleaver 2735 is a component corresponding to the block-row interleaver 125 provided in the transmitter 100, and performs the interleaving operation performed in the block-row interleaver 125 inversely. can do.

That is, the block-row deinterleaver 2735 writes the LLR values output from the multiplexer 2720 in the column direction to each column using at least one column composed of a plurality of rows, and writes the LLR values of the plurality of columns in which the LLR values are written. Deinterleaving may be performed by reading each row in a column direction.

However, when the block-row interleaver 125 writes and reads the groups not belonging to the first part in the column direction, the block-row deinterleaver 2735 returns values corresponding to the groups not belonging to the first part. Deinterleaving may be performed by writing and reading in the same direction.

The group deinterleaver 2733 deinterleaves the output value of the group twist deinterleaver 2732 and outputs it to the parity deinterleaver 2734.

Specifically, the group deinterleaver 2733 is a component corresponding to the group interleaver 122 provided in the transmitter 100, and may reversely perform the interleaving operation performed by the group interleaver 122.

That is, the group deinterleaver 2733 may rearrange the order of the plurality of groups on a group basis. In this case, the group deinterleaver 2733 may reversely apply the interleaving schemes of Tables 69 to 84 according to the length of the LDPC codeword, the modulation scheme, and the code rate to rearrange the order of the plurality of groups group by group.

Meanwhile, the deinterleaver 2730 of FIG. 24 may be composed of three or four components as shown in FIG. 27, but the operation of the components may be performed by one component. For example, for the bit groups X _a , X _b , X _c , and X _d , when one bit belonging to each bit group constitutes one modulation symbol, the deinterleaver 2730 converts one received Deinterleaving may be performed at positions corresponding to bit groups based on modulation symbols.

To this end, the transmitter 100 transmits various types of information used for interleaving in the interleaver 120 to the receiver 2700, or the transmitter 100 transmits information between the receiver 2700 and the receiver 2700 in a predefined manner. Interleaving can be performed using

The decoder 2740 may perform LDPC decoding using the output value of the deinterleaver 2730. To this end, the decoder 2740 may include an LDPC decoder (not shown) for performing LDPC decoding.

Specifically, the decoder 2740 is a component corresponding to the encoder 110 of the transmitter 100, and can correct an error by performing LDPC decoding using the LLR value output from the deinterleaver 2730. there is

For example, the decoder 2740 may perform LDPC decoding by iterative decoding based on a sum-product algorithm. Here, the multiplication algorithm is a kind of message passing algorithm, and the message passing algorithm means to exchange messages (eg, LLR values) through edges on a bipartite graph, and to variable nodes or check nodes. It represents an algorithm that calculates and updates an output message from input messages.

Meanwhile, the decoder 2740 may use a parity check matrix during LDPC decoding. In this case, information word submatrices in the parity check matrix are defined as shown in Tables 4 to 27 according to the code rate and the length of LDPC codewords, and the parity submatrices may have a double diagonal structure.

In addition, information on a parity check matrix used in LDPC decoding and information on a code rate may be previously stored in the receiving device 2700 or may be provided from the transmitting device 100.

28 is a flowchart for explaining a signal processing method of a transmitter according to an embodiment of the present invention.

First, LDPC encoding is performed to generate an LDPC codeword (S3010).

Then, the LDPC codeword is interleaved (S3020), and, for example, the length Nldpc of the LDPC codeword is 16200, the code rates are 10/15, 11/15, 12/15, 13/15, and the modulation scheme is 16-QAM In this case, π(j) may be defined as shown in Table 28 below. Modulation symbols are generated by modulating the interleaved LDPC codeword according to a modulation scheme (S3030).

Here, step S3020 groups the LDPC codewords into a plurality of groups, rearranges the order of the plurality of groups in units of groups, and uses a plurality of columns each including a plurality of rows, the modulation order determined according to the modulation scheme It is possible to distinguish and interleave a plurality of rearranged groups based on .

In this case, each of a plurality of columns is divided into a first part and a second part, the plurality of groups are sequentially written in units of bit groups to the plurality of columns constituting the first part, and the bits constituting the remaining groups are sequentially written in a plurality of columns. Interleaving may be performed by dividing into bit groups each having a predetermined number of bits based on the number of columns and sequentially writing the divided bit groups to a plurality of columns constituting the second part.

Here, the number of the plurality of columns has the same value as the modulation order according to the modulation method, and each of the plurality of columns may include rows equal to a value obtained by dividing the number of bits constituting the LDPC codeword by the number of the plurality of columns.

In addition, the first part is a bit group in each of a plurality of columns among a plurality of bit groups constituting the LDPC codeword according to the number of columns, the number of bit groups, and the number of bits constituting each bit group in each of the plurality of columns. It consists of as many rows as the number of bits included in at least some of the bit groups that can be written as a unit, and the second part is written in units of bit groups in each of the plurality of columns and in the rows constituting each of the plurality of columns. It may be composed of rows excluding rows as many as the number of bits included in at least some possible bit groups.

In this case, the number of rows of the second part may have the same value as the quotient obtained by dividing the number of bits included in all bit groups except for the bit groups corresponding to the first part by the number of columns.

Meanwhile, in step S3020, the bits included in at least some of the bit groups that can be written in bit group units are sequentially written to each of a plurality of columns constituting the first part, and the remainder except for at least some of the bit groups in the plurality of bit groups. The bits included in the bit group may be divided based on the number of the plurality of columns and sequentially written in each of the plurality of columns constituting the second part.

In this case, step S3020 divides the bits included in the remaining bit groups into a plurality of columns, writes each of the divided bits in the column direction to each of the plurality of columns constituting the second part, and Interleaving may be performed by reading a plurality of columns constituting two parts in a row direction.

Meanwhile, the modulation order may be 2, 4, 6, 8, 10, or 12 when the modulation scheme is QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, or 4096-QAM.

Meanwhile, a non-transitory computer readable medium storing a program for sequentially performing the signal processing method according to the present invention may be provided.

A non-transitory readable medium is not a medium that stores data for a short moment, such as a register, cache, or memory, but a medium that stores data semi-permanently and can be read by a device. Specifically, various applications or programs may be stored and provided in a non-transitory readable medium such as a CD, DVD, hard disk, Blu-ray disk, USB, memory card, or ROM.

In addition, although a bus is not shown in the above-described block diagram showing the transmitting device and the receiving device, communication between components in each device may be performed through a bus. In addition, each device may further include a processor such as a CPU, a microprocessor, etc. that performs the various steps described above.

In addition, although the preferred embodiments of the present invention have been shown and described above, the present invention is not limited to the specific embodiments described above, and the technical field to which the present invention belongs without departing from the gist of the present invention claimed in the claims. Of course, various modifications are possible by those skilled in the art, and these modifications should not be individually understood from the technical spirit or perspective of the present invention.

100: transmission device 110: encoder
120: interleaver 130: modulator

Claims (5)

In the transmission method,
encoding information word bits to generate parity bits;
dividing a codeword including the information word bits and the parity bits into a plurality of bit groups;
interleaving the plurality of bit groups on a bit group basis;
interleaving bits of the plurality of interleaved bit groups using a plurality of columns; and
Mapping the interleaved bits to constellation points;
Each of the plurality of columns includes a first part and a second part,
Some bit groups of the plurality of interleaved bit groups are interleaved in a first part of the plurality of columns, and the remaining bit groups of the plurality of interleaved bit groups are interleaved in a second part of the plurality of columns;
The transmission method of claim 1 , wherein bits of the partial bit groups and bits of the remaining bit groups are written in a column direction and read in a row direction. According to claim 1,
Each of the plurality of bit groups includes 360 bits. According to claim 1,
Interleaving the parity bits; further comprising,
In the step of distinguishing,
A transmission method of dividing a codeword including the information word bits and the interleaved parity bits into a plurality of bit groups. In the receiving method,
demodulating a signal received from a transmitting device to generate values;
writing the generated values to a plurality of columns, and deinterleaving the generated values by reading the written values from the plurality of columns;
classifying the deinterleaved values into a plurality of groups;
deinterleaving the plurality of groups on a group basis; and
decoding the deinterleaved values of the plurality of groups;
Each of the plurality of columns includes a first part and a second part,
Some of the generated values are read in a second direction after being written in a first direction in the first part of the plurality of columns,
The remaining values among the generated values are read in the second direction after being written in the second part of the plurality of columns in the first direction. According to claim 4,
Each of the plurality of groups includes 360 values.

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