CA3022281A1 - Improvements in or relating to packaging for integrated circuits - Google Patents
Improvements in or relating to packaging for integrated circuits Download PDFInfo
- Publication number
- CA3022281A1 CA3022281A1 CA3022281A CA3022281A CA3022281A1 CA 3022281 A1 CA3022281 A1 CA 3022281A1 CA 3022281 A CA3022281 A CA 3022281A CA 3022281 A CA3022281 A CA 3022281A CA 3022281 A1 CA3022281 A1 CA 3022281A1
- Authority
- CA
- Canada
- Prior art keywords
- layer
- film
- assay device
- sensing
- passivation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N27/00—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
- G01N27/26—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating electrochemical variables; by using electrolysis or electrophoresis
- G01N27/403—Cells and electrode assemblies
- G01N27/414—Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS
- G01N27/4148—Integrated circuits therefor, e.g. fabricated by CMOS processing
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N27/00—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
- G01N27/26—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating electrochemical variables; by using electrolysis or electrophoresis
- G01N27/403—Cells and electrode assemblies
- G01N27/414—Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Microelectronics & Electronic Packaging (AREA)
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Health & Medical Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Electrochemistry (AREA)
- Pathology (AREA)
- Molecular Biology (AREA)
- Analytical Chemistry (AREA)
- Biochemistry (AREA)
- General Health & Medical Sciences (AREA)
- Immunology (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Apparatus Associated With Microorganisms And Enzymes (AREA)
- Micromachines (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Investigating Or Analyzing Materials By The Use Of Fluid Adsorption Or Reactions (AREA)
- Measuring Or Testing Involving Enzymes Or Micro-Organisms (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB1608758.7 | 2016-05-18 | ||
| GBGB1608758.7A GB201608758D0 (en) | 2016-05-18 | 2016-05-18 | Improvements in or relating to packaging for integrated circuits |
| PCT/GB2017/051352 WO2017199009A1 (en) | 2016-05-18 | 2017-05-15 | Improvements in or relating to packaging for integrated circuits |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA3022281A1 true CA3022281A1 (en) | 2017-11-23 |
Family
ID=56320613
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA3022281A Abandoned CA3022281A1 (en) | 2016-05-18 | 2017-05-15 | Improvements in or relating to packaging for integrated circuits |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US10634642B2 (enExample) |
| EP (1) | EP3458851A1 (enExample) |
| JP (1) | JP6870003B2 (enExample) |
| CN (1) | CN109416340B (enExample) |
| CA (1) | CA3022281A1 (enExample) |
| GB (1) | GB201608758D0 (enExample) |
| WO (1) | WO2017199009A1 (enExample) |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5676042A (en) * | 1979-11-28 | 1981-06-23 | Shindengen Electric Mfg Co Ltd | Field effect transistor for ion sensor |
| GB2096825A (en) | 1981-04-09 | 1982-10-20 | Sibbald Alastair | Chemical sensitive semiconductor field effect transducer |
| JPS6056247A (ja) * | 1983-09-07 | 1985-04-01 | Mitsubishi Electric Corp | 半導体イオンセンサの絶縁法 |
| JPS6073352A (ja) * | 1983-09-30 | 1985-04-25 | Hitachi Ltd | 化学fetセンサ |
| JP2988020B2 (ja) * | 1991-07-03 | 1999-12-06 | 日本電気株式会社 | 半導体イオンセンサ |
| JP4450031B2 (ja) * | 2007-08-22 | 2010-04-14 | 株式会社デンソー | 半導体部品 |
| US7759135B2 (en) * | 2008-09-30 | 2010-07-20 | Infineon Technologies Ag | Method of forming a sensor node module |
| DE102009002060B4 (de) * | 2009-03-31 | 2023-08-03 | Endress+Hauser Conducta Gmbh+Co. Kg | Ionensensitiver Sensor mit Mehrfachschichtaufbau im sensitiven Bereich sowie Verfahren zur Herstellung eines solchen Sensors |
| FR2991053B1 (fr) * | 2012-05-25 | 2014-06-06 | Hemodia | Capteur isfet avec dispositif de controle integre. |
| EP2677307B1 (en) * | 2012-06-21 | 2016-05-11 | Nxp B.V. | Integrated circuit with sensors and manufacturing method |
| GB2508582A (en) * | 2012-10-12 | 2014-06-11 | Dna Electronics Ltd | ISFET with Titanium Nitride layer |
| US9395326B2 (en) * | 2013-11-01 | 2016-07-19 | Taiwan Semiconductor Manufacturing Company Limited | FET sensing cell and method of improving sensitivity of the same |
| TWI600901B (zh) * | 2015-09-14 | 2017-10-01 | 友達光電股份有限公司 | 離子感測場效電晶體 |
| US9470652B1 (en) * | 2015-09-15 | 2016-10-18 | Freescale Semiconductor, Inc. | Sensing field effect transistor devices and method of their manufacture |
-
2016
- 2016-05-18 GB GBGB1608758.7A patent/GB201608758D0/en not_active Ceased
-
2017
- 2017-05-15 WO PCT/GB2017/051352 patent/WO2017199009A1/en not_active Ceased
- 2017-05-15 CA CA3022281A patent/CA3022281A1/en not_active Abandoned
- 2017-05-15 US US16/302,359 patent/US10634642B2/en active Active
- 2017-05-15 CN CN201780026589.4A patent/CN109416340B/zh active Active
- 2017-05-15 JP JP2018560621A patent/JP6870003B2/ja active Active
- 2017-05-15 EP EP17724429.0A patent/EP3458851A1/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| EP3458851A1 (en) | 2019-03-27 |
| CN109416340A (zh) | 2019-03-01 |
| US10634642B2 (en) | 2020-04-28 |
| JP6870003B2 (ja) | 2021-05-12 |
| US20190302051A1 (en) | 2019-10-03 |
| CN109416340B (zh) | 2021-08-27 |
| JP2019516992A (ja) | 2019-06-20 |
| WO2017199009A1 (en) | 2017-11-23 |
| GB201608758D0 (en) | 2016-06-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI480545B (zh) | 生物場效電晶體裝置與生物場效電晶體的製造方法 | |
| US10381277B2 (en) | Method for producing a plurality of measurement regions on a chip, and chip with measurement regions | |
| CN110943040B (zh) | 切割衬底的方法和用于形成半导体芯片的分离方法 | |
| US9493347B2 (en) | Method of forming a semiconductor device | |
| CN110709350B (zh) | 利用ALGe的共晶键合 | |
| US9766195B2 (en) | Integrated circuit with sensor and method of manufacturing such an integrated circuit | |
| US8581239B2 (en) | Package structure and semiconductor structure thereof | |
| US10374093B2 (en) | Method of fabricating a flexible substrate and the flexible substrate fabricated thereby | |
| US8772153B2 (en) | Semiconductor device with air gap therein and manufacturing method thereof | |
| US12191258B2 (en) | Semiconductor device having integral alignment marks with decoupling features and method for fabricating the same | |
| US20230178493A1 (en) | Semiconductor device with alignment marks and method for fabricating the same | |
| US20170108464A1 (en) | System and method for forming microwells | |
| US10634642B2 (en) | Packaging for integrated circuits | |
| WO2014008927A1 (en) | Method for encapsulating an optoelectronic device and light-emitting diode chip | |
| US20140045330A1 (en) | Methods of in-situ vapor phase deposition of self-assembled monolayers as copper adhesion promoters and diffusion barriers | |
| JP2019516992A5 (enExample) | ||
| US20080064214A1 (en) | Semiconductor processing including etched layer passivation using self-assembled monolayer | |
| US20160181197A1 (en) | Reliable passivation layers for semiconductor devices | |
| EP1282164A2 (en) | Method to improve the adhesion of dielectric layers to copper | |
| CN102016558A (zh) | 废气适用的、高温传感器的保护层 | |
| US8865563B2 (en) | Film embedding method and semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request |
Effective date: 20220114 |
|
| EEER | Examination request |
Effective date: 20220114 |
|
| EEER | Examination request |
Effective date: 20220114 |
|
| EEER | Examination request |
Effective date: 20220114 |
|
| FZDE | Discontinued |
Effective date: 20240325 |