CA2939202C - High performance standard cell - Google Patents

High performance standard cell Download PDF

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Publication number
CA2939202C
CA2939202C CA2939202A CA2939202A CA2939202C CA 2939202 C CA2939202 C CA 2939202C CA 2939202 A CA2939202 A CA 2939202A CA 2939202 A CA2939202 A CA 2939202A CA 2939202 C CA2939202 C CA 2939202C
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CA
Canada
Prior art keywords
gate
cell
region
continuous
dummy gate
Prior art date
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Active
Application number
CA2939202A
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English (en)
French (fr)
Other versions
CA2939202A1 (en
Inventor
Xiangdong Chen
Ohsang Kwon
Foua Vang
Animesh Datta
Seid Hadi Rasouli
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Qualcomm Inc
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Qualcomm Inc
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Filing date
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Publication of CA2939202A1 publication Critical patent/CA2939202A1/en
Application granted granted Critical
Publication of CA2939202C publication Critical patent/CA2939202C/en
Active legal-status Critical Current
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10Integrated device layouts
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135Manufacturing their gate conductors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0149Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90Masterslice integrated circuits
    • H10D84/903Masterslice integrated circuits comprising field effect technology
    • H10D84/907CMOS gate arrays
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90Masterslice integrated circuits
    • H10D84/903Masterslice integrated circuits comprising field effect technology
    • H10D84/907CMOS gate arrays
    • H10D84/909Microarchitecture
    • H10D84/929Isolations
    • H10D84/931FET isolation
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90Masterslice integrated circuits
    • H10D84/903Masterslice integrated circuits comprising field effect technology
    • H10D84/907CMOS gate arrays
    • H10D84/909Microarchitecture
    • H10D84/959Connectability characteristics, i.e. diffusion and polysilicon geometries
    • H10D84/961Substrate and well contacts
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90Masterslice integrated circuits
    • H10D84/903Masterslice integrated circuits comprising field effect technology
    • H10D84/907CMOS gate arrays
    • H10D84/909Microarchitecture
    • H10D84/959Connectability characteristics, i.e. diffusion and polysilicon geometries
    • H10D84/966Gate electrode terminals or contacts
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/031Manufacture or treatment of conductive parts of the interconnections
    • H10W20/0698Local interconnections
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0128Manufacturing their channels
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0151Manufacturing their isolation regions

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
CA2939202A 2014-03-03 2015-02-19 High performance standard cell Active CA2939202C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/195,525 US9318476B2 (en) 2014-03-03 2014-03-03 High performance standard cell with continuous oxide definition and characterized leakage current
US14/195,525 2014-03-03
PCT/US2015/016690 WO2015134202A1 (en) 2014-03-03 2015-02-19 High performance standard cell

Publications (2)

Publication Number Publication Date
CA2939202A1 CA2939202A1 (en) 2015-09-11
CA2939202C true CA2939202C (en) 2017-08-29

Family

ID=52598835

Family Applications (1)

Application Number Title Priority Date Filing Date
CA2939202A Active CA2939202C (en) 2014-03-03 2015-02-19 High performance standard cell

Country Status (9)

Country Link
US (1) US9318476B2 (enExample)
EP (2) EP3998630A1 (enExample)
JP (1) JP6100981B1 (enExample)
KR (1) KR101724362B1 (enExample)
CN (2) CN106068557B (enExample)
BR (1) BR112016020239B1 (enExample)
CA (1) CA2939202C (enExample)
ES (1) ES2905416T3 (enExample)
WO (1) WO2015134202A1 (enExample)

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US20150311122A1 (en) * 2014-04-28 2015-10-29 Globalfoundries Inc. Forming gate tie between abutting cells and resulting device
US9634026B1 (en) * 2016-07-13 2017-04-25 Qualcomm Incorporated Standard cell architecture for reduced leakage current and improved decoupling capacitance
KR102469885B1 (ko) 2017-09-11 2022-11-22 삼성전자주식회사 반도체 장치
CN109524394B (zh) * 2017-09-18 2021-08-10 联华电子股份有限公司 具有虚置标准单元的集成电路
US10600866B2 (en) * 2018-02-01 2020-03-24 Qualcomm Incorporated Standard cell architecture for gate tie-off
US11068633B2 (en) * 2018-08-31 2021-07-20 Taiwan Semiconductor Manufacturing Company, Ltd. Fault diagnostics
US11030381B2 (en) * 2019-01-16 2021-06-08 Taiwan Semiconductor Manufacturing Co., Ltd. Leakage analysis on semiconductor device
KR102893583B1 (ko) * 2019-11-29 2025-12-01 삼성전자주식회사 표준셀을 포함하는 집적 회로 및 그 레이아웃 방법
US12575187B2 (en) * 2022-03-09 2026-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit and method of forming the same
WO2024135324A1 (ja) * 2022-12-22 2024-06-27 株式会社ソシオネクスト 半導体集積回路装置

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Also Published As

Publication number Publication date
JP6100981B1 (ja) 2017-03-22
KR20160121589A (ko) 2016-10-19
EP3114708B1 (en) 2021-12-29
WO2015134202A1 (en) 2015-09-11
ES2905416T3 (es) 2022-04-08
BR112016020239B1 (pt) 2022-03-08
EP3998630A1 (en) 2022-05-18
KR101724362B1 (ko) 2017-04-07
CA2939202A1 (en) 2015-09-11
EP3114708A1 (en) 2017-01-11
CN106068557B (zh) 2020-07-10
CN106068557A (zh) 2016-11-02
BR112016020239A2 (enExample) 2017-08-15
US9318476B2 (en) 2016-04-19
JP2017510069A (ja) 2017-04-06
US20150249076A1 (en) 2015-09-03
CN111326508A (zh) 2020-06-23

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