CA2408597A1 - Procede et appareil permettant de reduire le temps de verrouillage d'une boucle a asservissement de phase - Google Patents

Procede et appareil permettant de reduire le temps de verrouillage d'une boucle a asservissement de phase Download PDF

Info

Publication number
CA2408597A1
CA2408597A1 CA002408597A CA2408597A CA2408597A1 CA 2408597 A1 CA2408597 A1 CA 2408597A1 CA 002408597 A CA002408597 A CA 002408597A CA 2408597 A CA2408597 A CA 2408597A CA 2408597 A1 CA2408597 A1 CA 2408597A1
Authority
CA
Canada
Prior art keywords
frequency
vco
voltage
frequency synthesizer
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002408597A
Other languages
English (en)
Inventor
Keith Gallardo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2408597A1 publication Critical patent/CA2408597A1/fr
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/08—Modifications of the phase-locked loop for ensuring constant frequency when the power supply fails or is interrupted, e.g. for saving power
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/18—Temporarily disabling, deactivating or stopping the frequency counter or divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0802—Details of the phase-locked loop the loop being adapted for reducing power consumption

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Transceivers (AREA)

Abstract

L'invention concerne un procédé et un appareil permettant de réduire le temps de verrouillage dans un synthétiseur de fréquence à boucle à asservissement de phase possédant un mode actif et un mode veille. En mode actif, le synthétiseur de fréquence sert à maintenir une sortie en fréquence stable. Le mode veille ou sommeil sert à réduire la consommation lorsque le synthétiseur de fréquence n'a pas à fournir de sortie en fréquence. Lorsque le synthétiseur fonctionne en mode veille, la valeur la plus récente de la tension de syntonisation de l'oscillateur commandé en tension (VCO) est maintenue sur la ligne témoin de syntonisation de l'oscillateur VCO du synthétiseur de fréquence. Dans les synthétiseurs de fréquence à circuit intégré, la tension est maintenue au niveau de la fiche de sortie permettant la syntonisation de l'oscillateur VCO. L'erreur de tension au niveau de la fiche de syntonisation du VCO est ainsi minimisée, ce qui permet de minimiser le temps d'asservissement du synthétiseur de fréquence.
CA002408597A 2000-05-09 2001-05-08 Procede et appareil permettant de reduire le temps de verrouillage d'une boucle a asservissement de phase Abandoned CA2408597A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/567,802 US6731146B1 (en) 2000-05-09 2000-05-09 Method and apparatus for reducing PLL lock time
US09/567,802 2000-05-09
PCT/US2001/014992 WO2001086815A2 (fr) 2000-05-09 2001-05-08 Procede et appareil permettant de reduire le temps de verrouillage d'une boucle a asservissement de phase

Publications (1)

Publication Number Publication Date
CA2408597A1 true CA2408597A1 (fr) 2001-11-15

Family

ID=24268707

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002408597A Abandoned CA2408597A1 (fr) 2000-05-09 2001-05-08 Procede et appareil permettant de reduire le temps de verrouillage d'une boucle a asservissement de phase

Country Status (9)

Country Link
US (1) US6731146B1 (fr)
EP (1) EP1290797A2 (fr)
JP (1) JP2004516692A (fr)
KR (1) KR20030028467A (fr)
CN (1) CN1462508A (fr)
AU (1) AU2001259679A1 (fr)
CA (1) CA2408597A1 (fr)
MX (1) MXPA02011007A (fr)
WO (1) WO2001086815A2 (fr)

Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7558557B1 (en) * 1991-11-12 2009-07-07 Broadcom Corporation Low-power messaging in a network supporting roaming terminals
US6374311B1 (en) * 1991-10-01 2002-04-16 Intermec Ip Corp. Communication network having a plurality of bridging nodes which transmit a beacon to terminal nodes in power saving state that it has messages awaiting delivery
US7415548B2 (en) 1991-05-13 2008-08-19 Broadcom Corporation Communication network having a plurality of bridging nodes which transmits a polling message with backward learning technique to determine communication pathway
EP0606396B1 (fr) * 1991-10-01 2002-06-12 Norand Corporation Reseau local a radiofrequences
US7917145B2 (en) * 1992-11-02 2011-03-29 Broadcom Corporation Radio frequency local area network
US8509260B2 (en) 1993-08-31 2013-08-13 Broadcom Corporation Modular, portable data processing terminal for use in a communication network
US6061551A (en) * 1998-10-21 2000-05-09 Parkervision, Inc. Method and system for down-converting electromagnetic signals
US7515896B1 (en) 1998-10-21 2009-04-07 Parkervision, Inc. Method and system for down-converting an electromagnetic signal, and transforms for same, and aperture relationships
US6370371B1 (en) * 1998-10-21 2002-04-09 Parkervision, Inc. Applications of universal frequency translation
US7236754B2 (en) 1999-08-23 2007-06-26 Parkervision, Inc. Method and system for frequency up-conversion
US6542722B1 (en) * 1998-10-21 2003-04-01 Parkervision, Inc. Method and system for frequency up-conversion with variety of transmitter configurations
US7039372B1 (en) 1998-10-21 2006-05-02 Parkervision, Inc. Method and system for frequency up-conversion with modulation embodiments
US6853690B1 (en) 1999-04-16 2005-02-08 Parkervision, Inc. Method, system and apparatus for balanced frequency up-conversion of a baseband signal and 4-phase receiver and transceiver embodiments
US6879817B1 (en) * 1999-04-16 2005-04-12 Parkervision, Inc. DC offset, re-radiation, and I/Q solutions using universal frequency translation technology
US7693230B2 (en) 1999-04-16 2010-04-06 Parkervision, Inc. Apparatus and method of differential IQ frequency up-conversion
US7065162B1 (en) 1999-04-16 2006-06-20 Parkervision, Inc. Method and system for down-converting an electromagnetic signal, and transforms for same
US7110444B1 (en) 1999-08-04 2006-09-19 Parkervision, Inc. Wireless local area network (WLAN) using universal frequency translation technology including multi-phase embodiments and circuit implementations
US8295406B1 (en) 1999-08-04 2012-10-23 Parkervision, Inc. Universal platform module for a plurality of communication protocols
US7010286B2 (en) 2000-04-14 2006-03-07 Parkervision, Inc. Apparatus, system, and method for down-converting and up-converting electromagnetic signals
US7454453B2 (en) 2000-11-14 2008-11-18 Parkervision, Inc. Methods, systems, and computer program products for parallel correlation and applications thereof
JP3884914B2 (ja) * 2001-01-30 2007-02-21 株式会社ルネサステクノロジ 半導体装置
US7072427B2 (en) 2001-11-09 2006-07-04 Parkervision, Inc. Method and apparatus for reducing DC offsets in a communication system
US7379883B2 (en) 2002-07-18 2008-05-27 Parkervision, Inc. Networking methods and systems
US7460584B2 (en) * 2002-07-18 2008-12-02 Parkervision, Inc. Networking methods and systems
JP2004171104A (ja) * 2002-11-18 2004-06-17 Fujitsu Ltd コンピュータのユーザ認証システム、その方法およびそのためのプログラム
US7038508B2 (en) * 2004-04-30 2006-05-02 Intel Corporation Methods and apparatuses for detecting clock loss in a phase-locked loop
DE102004032130B4 (de) * 2004-07-01 2010-12-16 Krohne Messtechnik Gmbh Frequenzsynthesizer und Verfahren zum Betrieb eines Frequenzsynthesizers
JP2007027981A (ja) * 2005-07-13 2007-02-01 Futaba Corp 発振装置およびその制御方法
JP2008042810A (ja) * 2006-08-10 2008-02-21 Fujitsu Ltd Ｐｌｌ回路
KR101316788B1 (ko) 2007-01-08 2013-10-11 삼성전자주식회사 반도체 집적 회로 장치
KR100956639B1 (ko) 2007-08-31 2010-05-11 전자부품연구원 컴퓨팅 디바이스의 전력 감소 장치 및 그 방법
JP5102603B2 (ja) * 2007-12-21 2012-12-19 ルネサスエレクトロニクス株式会社 半導体集積回路
US7595699B1 (en) * 2008-03-04 2009-09-29 Freescale Semiconductor, Inc. Look loop circuit and method having improved lock time
US7667545B2 (en) * 2008-03-04 2010-02-23 Freescale Semiconductor, Inc. Automatic calibration lock loop circuit and method having improved lock time
KR101034617B1 (ko) * 2009-12-29 2011-05-12 주식회사 하이닉스반도체 지연 고정 루프
CN102104411B (zh) * 2010-12-29 2013-06-05 浙江大学 一种用于皮卫星的接收机电路
TWI437820B (zh) * 2010-12-31 2014-05-11 鈺創科技股份有限公司 電壓保持電路
AT513104B1 (de) * 2012-07-10 2015-11-15 Felix Dipl Ing Dr Himmelstoss Vorrichtung zur Konstanthaltung der Frequenz eines spannungsgesteuerten Oszillators
US9060735B2 (en) 2012-12-14 2015-06-23 Sharp Laboratories Of America, Inc. Classification of segments of acoustic physiological signal captured during sleep using phase-locked loop array
US8760202B1 (en) * 2013-05-15 2014-06-24 Freescale Semiconductor, Inc. System for generating clock signal
US9258001B1 (en) 2013-09-03 2016-02-09 Cirrus Logic, Inc. Dual-input oscillator for redundant phase-locked loop (PLL) operation
US20180340803A1 (en) * 2017-05-25 2018-11-29 Renesas Electronics Corporation Detection system, sensor and microcomputer
KR101938674B1 (ko) * 2017-11-27 2019-01-15 주식회사 아나패스 위상 고정 루프 및 지연 고정 루프
US11074210B2 (en) * 2018-12-08 2021-07-27 Apple Inc. Bus protocol for multiple chipsets

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56136037A (en) 1980-03-26 1981-10-23 Nec Corp Phase synchronizing oscillator
US4521918A (en) * 1980-11-10 1985-06-04 General Electric Company Battery saving frequency synthesizer arrangement
JPH0787366B2 (ja) * 1986-03-14 1995-09-20 株式会社日立製作所 位相同期発振器
CA1282464C (fr) 1985-10-23 1991-04-02 Masanori Ienaka Oscillateur a phase asservie
JPS6297429A (ja) * 1985-10-23 1987-05-06 Hitachi Ltd 位相同期発振器
CH677298A5 (en) 1989-04-17 1991-04-30 Koechler Erika Fa Frequency synthesiser circuit for portable radio receiver - has switch interrupting voltage to frequency divider and phase detector for reduced battery requirement
JP2995923B2 (ja) * 1991-04-11 1999-12-27 ソニー株式会社 同期クロック発生回路
US5528307A (en) * 1991-07-18 1996-06-18 Canon Kabushiki Kaisha Clock generator
JPH08125527A (ja) * 1994-10-21 1996-05-17 Mitsubishi Electric Corp 位相同期ループ回路
US6223061B1 (en) * 1997-07-25 2001-04-24 Cleveland Medical Devices Inc. Apparatus for low power radio communications
US6150891A (en) * 1998-05-29 2000-11-21 Silicon Laboratories, Inc. PLL synthesizer having phase shifted control signals
US6114888A (en) * 1998-09-25 2000-09-05 Conexant Systems, Inc. Digital phase lock loop divider cycling method, apparatus, and communication system incorporating the same

Also Published As

Publication number Publication date
US6731146B1 (en) 2004-05-04
WO2001086815A2 (fr) 2001-11-15
KR20030028467A (ko) 2003-04-08
JP2004516692A (ja) 2004-06-03
WO2001086815A3 (fr) 2002-04-04
EP1290797A2 (fr) 2003-03-12
AU2001259679A1 (en) 2001-11-20
MXPA02011007A (es) 2003-04-25
CN1462508A (zh) 2003-12-17

Similar Documents

Publication Publication Date Title
US6731146B1 (en) Method and apparatus for reducing PLL lock time
EP1931051B1 (fr) Procédé et système pour WLAN à puce unique et radios Bluetooth sur un substrat CMOS unique
EP0937338B1 (fr) Procede et appareil de reduction du courant en mode de veille dans un equipement de telecommunications
US7031662B2 (en) Wireless communication circuit, wireless communication terminal and method, recording medium, and program
US7209720B2 (en) Multiband and multimode transmitter and method
JP2002050963A (ja) デジタル情報送受信装置の電気消費量を減少させるプロセスおよび装置
JP4503512B2 (ja) 無線通信装置及び電力変換器の動作周波数制御方法
CN103199859A (zh) 时钟产生器及移动设备
US6799028B2 (en) Mobile radio receiver with integrated broadcast receiver that fills broadcast gaps during mobile band communication
US6185411B1 (en) Apparatus and method for enabling elements of a phase locked loop
US20070164827A1 (en) Circuit and method for controlling an oscillation loop
JP2001007714A (ja) 温度補正回路及び温度補正機能を備えた電子機器
EP1469606A1 (fr) Méthode pour appliquer un signal de puissance d' un tétéphone mobile
KR100266414B1 (ko) Rf­모듈의 전원 인가장치
EP1354407A2 (fr) Boucle a verrouillage de phase
KR20020006759A (ko) 이동통신 단말기에서 전압제어 발진기의 제어 장치 및 방법
EP1061661A2 (fr) Architecture d'un émetteur-recepteur cellulaire à deux bandes
JP3572028B2 (ja) 移動無線端末装置
JP3092538B2 (ja) 通信装置
JPH06276094A (ja) 発振周波数調整方式
KR100626527B1 (ko) 무선통신 단말기에서 전계에 따른 수신신호처리부의이득상태 저장 방법
JPH0218773B2 (fr)
JP2000013251A (ja) 送信回路
JPH07212291A (ja) 移動無線装置
WO2001097393A1 (fr) Dispositif de communication sans fil mobile

Legal Events

Date Code Title Description
FZDE Dead