CA2150151A1 - First-in first-out memory - Google Patents

First-in first-out memory

Info

Publication number
CA2150151A1
CA2150151A1 CA002150151A CA2150151A CA2150151A1 CA 2150151 A1 CA2150151 A1 CA 2150151A1 CA 002150151 A CA002150151 A CA 002150151A CA 2150151 A CA2150151 A CA 2150151A CA 2150151 A1 CA2150151 A1 CA 2150151A1
Authority
CA
Canada
Prior art keywords
memory
signal
write
address
state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002150151A
Other languages
English (en)
French (fr)
Inventor
John H. Baldwin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp filed Critical AT&T Corp
Publication of CA2150151A1 publication Critical patent/CA2150151A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/16—Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
  • Memory System (AREA)
  • Information Transfer Systems (AREA)
CA002150151A 1994-08-05 1995-05-25 First-in first-out memory Abandoned CA2150151A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US28733394A 1994-08-05 1994-08-05
US287,333 1994-08-05

Publications (1)

Publication Number Publication Date
CA2150151A1 true CA2150151A1 (en) 1996-02-06

Family

ID=23102441

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002150151A Abandoned CA2150151A1 (en) 1994-08-05 1995-05-25 First-in first-out memory

Country Status (5)

Country Link
EP (1) EP0695988A2 (cg-RX-API-DMAC7.html)
JP (1) JPH0863954A (cg-RX-API-DMAC7.html)
KR (1) KR960008829A (cg-RX-API-DMAC7.html)
CN (1) CN1147676A (cg-RX-API-DMAC7.html)
CA (1) CA2150151A1 (cg-RX-API-DMAC7.html)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1185573C (zh) * 1999-03-31 2005-01-19 皇家菲利浦电子有限公司 数据处理装置,处理数据的方法和存储器系统
US6772311B2 (en) * 2002-06-24 2004-08-03 Texas Instruments Incorporated ATAPI device unaligned and aligned parallel I/O data transfer controller
US7467242B2 (en) * 2003-05-13 2008-12-16 Via Technologies, Inc. Method and system for dynamic FIFO flow control
CN100409201C (zh) * 2005-04-29 2008-08-06 哈尔滨工业大学 基于ram及fpga的先进先出型存储器及其控制方法
JP4351292B2 (ja) 2006-02-27 2009-10-28 富士通株式会社 データ制御装置、データ制御方法およびデータ制御プログラム
KR101854232B1 (ko) * 2010-11-09 2018-05-04 삼성전자주식회사 디-엠퍼시스 기능을 갖는 의사 오픈 드레인 방식의 출력 드라이버, 반도체 메모리 장치 및 그것의 제어 방법
JP6359491B2 (ja) * 2015-06-12 2018-07-18 東芝メモリ株式会社 半導体記憶装置
JP7211676B2 (ja) * 2019-03-25 2023-01-24 ラピスセミコンダクタ株式会社 半導体装置
CN111752525A (zh) * 2020-06-22 2020-10-09 深圳鲲云信息科技有限公司 一种模块间通信方法及系统
CN115527579A (zh) * 2022-09-16 2022-12-27 山东云海国创云计算装备产业创新中心有限公司 Fifo存储器读写数据的方法、装置、芯片及介质
CN115604198B (zh) * 2022-11-29 2023-03-10 珠海星云智联科技有限公司 一种网卡控制器、网卡控制方法、设备及介质

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3646526A (en) * 1970-03-17 1972-02-29 Us Army Fifo shift register memory with marker and data bit storage
JPS6057090B2 (ja) * 1980-09-19 1985-12-13 株式会社日立製作所 データ記憶装置およびそれを用いた処理装置
JPS59177782A (ja) * 1983-03-25 1984-10-08 Nec Corp バツフアメモリ制御方式
US4843544A (en) * 1987-09-25 1989-06-27 Ncr Corporation Method and apparatus for controlling data transfers through multiple buffers
DE69032757T2 (de) * 1989-10-03 1999-06-24 Advanced Micro Devices, Inc., Sunnyvale, Calif. Speichervorrichtung

Also Published As

Publication number Publication date
KR960008829A (ko) 1996-03-22
CN1147676A (zh) 1997-04-16
EP0695988A3 (cg-RX-API-DMAC7.html) 1996-03-13
JPH0863954A (ja) 1996-03-08
EP0695988A2 (en) 1996-02-07

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