CA2050658A1 - Commutation de canaux et de contextes dans un processeur graphique - Google Patents

Commutation de canaux et de contextes dans un processeur graphique

Info

Publication number
CA2050658A1
CA2050658A1 CA2050658A CA2050658A CA2050658A1 CA 2050658 A1 CA2050658 A1 CA 2050658A1 CA 2050658 A CA2050658 A CA 2050658A CA 2050658 A CA2050658 A CA 2050658A CA 2050658 A1 CA2050658 A1 CA 2050658A1
Authority
CA
Canada
Prior art keywords
task
channel
hardware
context switching
graphics processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2050658A
Other languages
English (en)
Other versions
CA2050658C (fr
Inventor
John M. Peaslee
Jeffrey C. Malacarne
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Raytheon Co
Original Assignee
John M. Peaslee
Jeffrey C. Malacarne
Hughes Aircraft Company
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by John M. Peaslee, Jeffrey C. Malacarne, Hughes Aircraft Company filed Critical John M. Peaslee
Publication of CA2050658A1 publication Critical patent/CA2050658A1/fr
Application granted granted Critical
Publication of CA2050658C publication Critical patent/CA2050658C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/48Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806Task transfer initiation or dispatching
    • G06F9/4812Task transfer initiation or dispatching by interrupt, e.g. masked
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/1423Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00Aspects of the architecture of display systems
    • G09G2360/04Display device controller operating with a plurality of display units
CA002050658A 1990-09-14 1991-09-04 Commutation de canaux et de contextes dans un processeur graphique Expired - Fee Related CA2050658C (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US58270990A 1990-09-14 1990-09-14
US582,709 1990-09-14

Publications (2)

Publication Number Publication Date
CA2050658A1 true CA2050658A1 (fr) 1992-03-15
CA2050658C CA2050658C (fr) 1997-01-28

Family

ID=24330218

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002050658A Expired - Fee Related CA2050658C (fr) 1990-09-14 1991-09-04 Commutation de canaux et de contextes dans un processeur graphique

Country Status (4)

Country Link
US (1) US5371849A (fr)
EP (1) EP0475421A3 (fr)
JP (1) JPH04299389A (fr)
CA (1) CA2050658C (fr)

Families Citing this family (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2509192A (en) * 1991-08-21 1993-03-16 Digital Equipment Corporation Address method for computer graphics system
US5321810A (en) * 1991-08-21 1994-06-14 Digital Equipment Corporation Address method for computer graphics system
US5388841A (en) * 1992-01-30 1995-02-14 A/N Inc. External memory system having programmable graphics processor for use in a video game system or the like
US5394524A (en) * 1992-08-07 1995-02-28 International Business Machines Corporation Method and apparatus for processing two graphics data streams in parallel
US5596749A (en) * 1992-09-21 1997-01-21 Texas Instruments Incorporated Arbitration request sequencer
US5613126A (en) * 1994-05-31 1997-03-18 Advanced Micro Devices, Inc. Timer tick auto-chaining technique within a symmetrical multiprocessing system
US5768626A (en) * 1994-06-24 1998-06-16 Intel Corporation Method and apparatus for servicing a plurality of FIFO's in a capture gate array
DE69615431T2 (de) * 1995-03-15 2002-05-23 Koninkl Philips Electronics Nv Datenverarbeitungssystem zur Ausführung von Aufgaben verschiedener Prioritäten und dieses System enthaltendes Modem
US5812150A (en) * 1995-04-28 1998-09-22 Ati Technologies Inc. Device synchronization on a graphics accelerator
US5794037A (en) * 1995-05-01 1998-08-11 Intergraph Corporation Direct access to slave processing by unprotected application using context saving and restoration
US5760792A (en) * 1995-05-01 1998-06-02 Intergraph Corporation Fifo logical addresses for control and error recovery
US5659750A (en) * 1995-05-15 1997-08-19 Nvidia Corporation Apparatus for context switching of input/output devices in responses to commands from unprivileged application programs
US5673416A (en) * 1995-06-07 1997-09-30 Seiko Epson Corporation Memory request and control unit including a mechanism for issuing and removing requests for memory access
US5696940A (en) * 1995-09-29 1997-12-09 Intel Corporation Apparatus and method for sharing first-in first-out memory space between two streams of data
US5896141A (en) * 1996-07-26 1999-04-20 Hewlett-Packard Company System and method for virtual device access in a computer system
US6247040B1 (en) 1996-09-30 2001-06-12 Lsi Logic Corporation Method and structure for automated switching between multiple contexts in a storage subsystem target device
US6148326A (en) * 1996-09-30 2000-11-14 Lsi Logic Corporation Method and structure for independent disk and host transfer in a storage subsystem target device
US6081849A (en) * 1996-10-01 2000-06-27 Lsi Logic Corporation Method and structure for switching multiple contexts in storage subsystem target device
US5949994A (en) * 1997-02-12 1999-09-07 The Dow Chemical Company Dedicated context-cycling computer with timed context
JP3530360B2 (ja) * 1997-10-27 2004-05-24 株式会社ルネサステクノロジ データ処理装置及びデータ処理システム
US6145033A (en) * 1998-07-17 2000-11-07 Seiko Epson Corporation Management of display FIFO requests for DRAM access wherein low priority requests are initiated when FIFO level is below/equal to high threshold value
US6243770B1 (en) 1998-07-21 2001-06-05 Micron Technology, Inc. Method for determining status of multiple interlocking FIFO buffer structures based on the position of at least one pointer of each of the multiple FIFO buffers
US6119207A (en) * 1998-08-20 2000-09-12 Seiko Epson Corporation Low priority FIFO request assignment for DRAM access
US6252600B1 (en) 1998-10-02 2001-06-26 International Business Machines Corporation Computer graphics system with dual FIFO interface
US6339427B1 (en) * 1998-12-15 2002-01-15 Ati International Srl Graphics display list handler and method
US7233331B2 (en) * 2000-03-16 2007-06-19 Square Enix Co., Ltd. Parallel object task engine and processing method
US6557083B1 (en) * 2000-06-30 2003-04-29 Intel Corporation Memory system for multiple data types
US6724391B1 (en) * 2000-06-30 2004-04-20 Intel Corporation Mechanism for implementing Z-compression transparently
US7196710B1 (en) * 2000-08-23 2007-03-27 Nintendo Co., Ltd. Method and apparatus for buffering graphics data in a graphics system
US6624815B1 (en) 2000-08-31 2003-09-23 National Semiconductor Corporation System, method, and apparatus for creating character boxes for on screen displays
JP2004140575A (ja) * 2002-10-17 2004-05-13 Sony Corp データ処理装置、データ処理方法、および情報記憶媒体、並びにコンピュータ・プログラム
JP4094931B2 (ja) * 2002-10-29 2008-06-04 三菱電機株式会社 トランシーバ集積回路及び通信モジュール
KR20040062311A (ko) * 2003-01-02 2004-07-07 삼성전자주식회사 파일 리스트 디스플레이 영상 및 음성 기록/재생 장치 및방법
EP3522163A1 (fr) * 2003-01-02 2019-08-07 Samsung Electronics Co., Ltd. Appareil multimédia avec sortie audio accompagnée d'un diaporama
US7673304B2 (en) 2003-02-18 2010-03-02 Microsoft Corporation Multithreaded kernel for graphics processing unit
US7701949B1 (en) * 2003-06-24 2010-04-20 Cisco Technology, Inc. System and method for switching high priority traffic with low latency
JP4190476B2 (ja) * 2004-09-22 2008-12-03 株式会社ソニー・コンピュータエンタテインメント グラフィックプロセッサ、制御用プロセッサおよび情報処理装置
US20070070067A1 (en) * 2005-04-29 2007-03-29 Modviz, Inc. Scene splitting for perspective presentations
US7716387B2 (en) * 2005-07-14 2010-05-11 Canon Kabushiki Kaisha Memory control apparatus and method
US7583268B2 (en) * 2005-11-10 2009-09-01 Via Technologies, Inc. Graphics pipeline precise interrupt method and apparatus
US7545381B2 (en) * 2005-11-10 2009-06-09 Via Technologies, Inc. Interruptible GPU and method for context saving and restoring
US7580040B2 (en) 2005-11-10 2009-08-25 Via Technologies, Inc. Interruptible GPU and method for processing multiple contexts and runlists
US7590774B2 (en) * 2005-12-01 2009-09-15 Kabushiki Kaisha Toshiba Method and system for efficient context swapping
US7340557B2 (en) * 2005-12-15 2008-03-04 Via Technologies, Inc. Switching method and system for multiple GPU support
US7325086B2 (en) * 2005-12-15 2008-01-29 Via Technologies, Inc. Method and system for multiple GPU support
US8243069B1 (en) * 2006-11-03 2012-08-14 Nvidia Corporation Late Z testing for multiple render targets
US8854381B2 (en) * 2009-09-03 2014-10-07 Advanced Micro Devices, Inc. Processing unit that enables asynchronous task dispatch
DE102011119004A1 (de) * 2011-11-19 2013-05-23 Diehl Aerospace Gmbh Grafikverarbeitungsvorrichtung, Anzeigevorrichtung für ein Flugzeugcockpit sowie Verfahren zur Anzeige von Grafikdaten
US9361116B2 (en) * 2012-12-28 2016-06-07 Intel Corporation Apparatus and method for low-latency invocation of accelerators
US10140129B2 (en) 2012-12-28 2018-11-27 Intel Corporation Processing core having shared front end unit
US9417873B2 (en) 2012-12-28 2016-08-16 Intel Corporation Apparatus and method for a hybrid latency-throughput processor
US10346195B2 (en) 2012-12-29 2019-07-09 Intel Corporation Apparatus and method for invocation of a multi threaded accelerator
US10026142B2 (en) * 2015-04-14 2018-07-17 Intel Corporation Supporting multi-level nesting of command buffers in graphics command streams at computing devices
US10503457B2 (en) 2017-05-05 2019-12-10 Nvidia Corporation Method and apparatus for rendering perspective-correct images for a tilted multi-display environment
US11335296B2 (en) 2020-09-14 2022-05-17 Apple Inc. Low-latency context switch systems and methods

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3962684A (en) * 1971-08-31 1976-06-08 Texas Instruments Incorporated Computing system interface using common parallel bus and segmented addressing
DE2659662C3 (de) * 1976-12-30 1981-10-08 Ibm Deutschland Gmbh, 7000 Stuttgart Prioritätsstufengesteuerte Unterbrechungseinrichtung
US4398244A (en) * 1980-05-07 1983-08-09 Fairchild Camera & Instrument Corporation Interruptible microprogram sequencing unit and microprogrammed apparatus utilizing same
US4430707A (en) * 1981-03-05 1984-02-07 Burroughs Corporation Microprogrammed digital data processing system employing multi-phase subroutine control for concurrently executing tasks
JPS6039234A (ja) * 1983-08-10 1985-03-01 Mitsubishi Electric Corp Crtタ−ミナル装置
DE3473665D1 (en) * 1984-06-25 1988-09-29 Ibm Graphical display apparatus with pipelined processors
US4858107A (en) * 1985-03-11 1989-08-15 General Electric Company Computer device display system using conditionally asynchronous memory accessing by video display controller
US4744048A (en) * 1985-10-09 1988-05-10 American Telephone And Telegraph Company Display context switching arrangement
JPS62184560A (ja) * 1986-02-07 1987-08-12 Matsushita Electric Ind Co Ltd 入出力バツフア制御装置
US4862392A (en) * 1986-03-07 1989-08-29 Star Technologies, Inc. Geometry processor for graphics display system
US4839800A (en) * 1986-08-29 1989-06-13 Bull Hn Information Systems Inc. Data processing system with a fast interrupt
US4916301A (en) * 1987-02-12 1990-04-10 International Business Machines Corporation Graphics function controller for a high performance video display system
US5138702A (en) * 1987-04-17 1992-08-11 Minolta Camera Co., Ltd. External image input/output device connectable image processing system
US5010515A (en) * 1987-07-28 1991-04-23 Raster Technologies, Inc. Parallel graphics processor with workload distributing and dependency mechanisms and method for distributing workload
US4928247A (en) * 1987-08-13 1990-05-22 Digital Equipment Corporation Method and apparatus for the continuous and asynchronous traversal and processing of graphics data structures
JPH0727571B2 (ja) * 1987-10-26 1995-03-29 テクトロニックス・インコーポレイテッド ラスタ走査表示装置及び図形データ転送方法
US4958303A (en) * 1988-05-12 1990-09-18 Digital Equipment Corporation Apparatus for exchanging pixel data among pixel processors
JPH01318140A (ja) * 1988-06-20 1989-12-22 Canon Inc マルチプロセッサシステム
US5127098A (en) * 1989-04-12 1992-06-30 Sun Microsystems, Inc. Method and apparatus for the context switching of devices

Also Published As

Publication number Publication date
EP0475421A2 (fr) 1992-03-18
EP0475421A3 (en) 1993-02-03
CA2050658C (fr) 1997-01-28
JPH04299389A (ja) 1992-10-22
US5371849A (en) 1994-12-06

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