CA2036162A1 - Synchronisation de signaux numeriques utilisant une seule memoire elastique - Google Patents

Synchronisation de signaux numeriques utilisant une seule memoire elastique

Info

Publication number
CA2036162A1
CA2036162A1 CA2036162A CA2036162A CA2036162A1 CA 2036162 A1 CA2036162 A1 CA 2036162A1 CA 2036162 A CA2036162 A CA 2036162A CA 2036162 A CA2036162 A CA 2036162A CA 2036162 A1 CA2036162 A1 CA 2036162A1
Authority
CA
Canada
Prior art keywords
clock signal
gaps
smooth
elastic store
data signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2036162A
Other languages
English (en)
Other versions
CA2036162C (fr
Inventor
Erik J. Kramer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Publication of CA2036162A1 publication Critical patent/CA2036162A1/fr
Application granted granted Critical
Publication of CA2036162C publication Critical patent/CA2036162C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0623—Synchronous multiplexing systems, e.g. synchronous digital hierarchy/synchronous optical network (SDH/SONET), synchronisation with a pointer process

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Hardware Design (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Time-Division Multiplex Systems (AREA)
CA002036162A 1990-05-30 1991-02-12 Synchronisation de signaux numeriques utilisant une seule memoire elastique Expired - Fee Related CA2036162C (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US530,774 1990-05-30
US07/530,774 US5119406A (en) 1990-05-30 1990-05-30 Digital signal synchronization employing single elastic store

Publications (2)

Publication Number Publication Date
CA2036162A1 true CA2036162A1 (fr) 1991-12-01
CA2036162C CA2036162C (fr) 1995-02-21

Family

ID=24114909

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002036162A Expired - Fee Related CA2036162C (fr) 1990-05-30 1991-02-12 Synchronisation de signaux numeriques utilisant une seule memoire elastique

Country Status (6)

Country Link
US (1) US5119406A (fr)
EP (1) EP0459686B1 (fr)
JP (1) JP2563691B2 (fr)
KR (1) KR0175662B1 (fr)
CA (1) CA2036162C (fr)
DE (1) DE69123785T2 (fr)

Families Citing this family (40)

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US5420893A (en) * 1989-02-16 1995-05-30 International Business Machines Corporation Asynchronous data channel for information storage subsystem
DE4027967A1 (de) * 1990-09-04 1992-03-05 Philips Patentverwaltung Stopfentscheidungsschaltung fuer eine anordnung zur bitratenanpassung
JP2600496B2 (ja) * 1990-12-20 1997-04-16 日本電気株式会社 セル位相乗換回路
US5638411A (en) * 1991-05-23 1997-06-10 Mitsubishi Denki Kabushiki Kaisha Stuff bit synchronization system
US5268936A (en) * 1991-07-08 1993-12-07 At&T Bell Laboratories Synchronous digital signal to asynchronous digital signal desynchronizer
US5268935A (en) * 1991-12-20 1993-12-07 At&T Bell Laboratories Synchronous digital signal to asynchronous digital signal desynchronizer
ES2046106B1 (es) * 1992-02-18 1996-11-16 Estandard Electrica S A Metodo de realizacion de circuitos alineadores inmunes a los deslizamientos ocurridos en la memoria elastica de recepcion.
JP2888022B2 (ja) * 1992-04-02 1999-05-10 三菱電機株式会社 通信制御装置
US5717693A (en) * 1992-05-21 1998-02-10 Alcatel Network Systems, Inc. Sonet payload pointer processing and architecture
ES2121979T3 (es) * 1992-05-27 1998-12-16 Ericsson Telefon Ab L M Procedimiento y dispositivo de escritura-lectura en una memoria.
EP0578315A1 (fr) * 1992-07-09 1994-01-12 Philips Patentverwaltung GmbH Système de transmission synchrone
US5885489A (en) * 1992-11-03 1999-03-23 Eta Process Plant Limited Packing elements
CH686465A5 (de) * 1993-01-26 1996-03-29 Royale Consultants Ltd Verfahren und Einrichtung zur bidirektionalen Informationsuebertragung (Full-Duplex).
FI94812C (fi) * 1993-05-18 1995-10-25 Nokia Telecommunications Oy Menetelmä ja laite tasauspäätöksen aikaansaamiseksi synkronisen digitaalisen tietoliikennejärjestelmän solmupisteessä
US5457717A (en) * 1993-11-29 1995-10-10 Dsc Communications Corporation Apparatus and method for eliminating mapping jitter
US5548534A (en) * 1994-07-08 1996-08-20 Transwitch Corporation Two stage clock dejitter circuit for regenerating an E4 telecommunications signal from the data component of an STS-3C signal
KR0177733B1 (ko) * 1994-08-26 1999-05-15 정장호 데이타 전송장치의 클럭동기 회로
JP3408652B2 (ja) * 1995-02-03 2003-05-19 沖電気工業株式会社 ビット位相同期回路
US5583894A (en) * 1995-03-20 1996-12-10 Vlsi Technology, Inc. Slip buffer for synchronizing data transfer between two devices
US5699391A (en) * 1995-05-31 1997-12-16 Dsc Communications Corporation Digital desynchronizer
US5761203A (en) * 1996-04-04 1998-06-02 Lucent Technologies Inc. Synchronous and asynchronous recovery of signals in an ATM network
GB2312353B (en) * 1996-04-16 2000-12-06 Gpt Ltd Digital telecommunications transmision systems
US6064706A (en) * 1996-05-01 2000-05-16 Alcatel Usa, Inc. Apparatus and method of desynchronizing synchronously mapped asynchronous data
JPH10210503A (ja) * 1997-01-17 1998-08-07 Sony Corp 信号変換装置
US5990713A (en) * 1998-02-05 1999-11-23 Harris Corporation Adjustable phase clock circuit using the same and related methods
EP0935362A3 (fr) * 1998-02-06 2005-02-02 Alcatel Dispositif de synchronisation d'un système de transmission numérique et procédé de génération un signal de sortie synchrone
EP1068765B1 (fr) * 1998-04-07 2008-05-07 Nokia Siemens Networks Gmbh & Co. Kg Procede et dispositif pour le couplage d'une couche de communication mta a plusieurs connexions de communication a multiplexage dans le temps
US6289066B1 (en) * 1998-06-11 2001-09-11 Hewlett-Packard Company Method and apparatus for recentering an elasticity FIFO when receiving 1000BASE-X traffic using minimal information
US6501809B1 (en) * 1999-03-19 2002-12-31 Conexant Systems, Inc. Producing smoothed clock and data signals from gapped clock and data signals
JP3419345B2 (ja) * 1999-05-28 2003-06-23 日本電気株式会社 パルススタッフ同期方式における低次群信号のクロック再生方法および回路
US6956873B2 (en) * 2001-05-21 2005-10-18 General Instrument Corporation Arrangement for deriving a local clock in a packet cable telephony modem
US6882662B2 (en) * 2001-06-07 2005-04-19 Applied Micro Circuits Corporation Pointer adjustment wander and jitter reduction apparatus for a desynchronizer
KR100443014B1 (ko) * 2001-12-24 2004-08-04 엘지전자 주식회사 듀얼포트램을 이용한 상이위상 클럭간 데이터 전송 장치
US7606269B1 (en) * 2004-07-27 2009-10-20 Intel Corporation Method and apparatus for detecting and managing loss of alignment in a virtually concatenated group
US8867682B2 (en) * 2010-08-30 2014-10-21 Exar Corporation Dejitter (desynchronize) technique to smooth gapped clock with jitter/wander attenuation using all digital logic
US8666011B1 (en) 2011-04-20 2014-03-04 Applied Micro Circuits Corporation Jitter-attenuated clock using a gapped clock reference
US8855258B1 (en) 2011-04-20 2014-10-07 Applied Micro Circuits Corporation Transmitters and receivers using a jitter-attenuated clock derived from a gapped clock reference
US9673963B1 (en) * 2016-04-12 2017-06-06 Keyssa Systems, Inc. Multi-protocols and multi-data rates communications
US10056890B2 (en) 2016-06-24 2018-08-21 Exar Corporation Digital controlled oscillator based clock generator for multi-channel design
US10063365B1 (en) 2017-03-10 2018-08-28 Keyssa Systems, Inc. Re-timer network insertion

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1532444A (en) * 1975-03-26 1978-11-15 Micro Consultants Ltd Synchronising data for digital storage systems
US4347620A (en) * 1980-09-16 1982-08-31 Northern Telecom Limited Method of and apparatus for regenerating a signal frequency in a digital signal transmission system
JPS61281635A (ja) * 1985-05-29 1986-12-12 Kenwood Corp 時分割多重信号分離方式
CA1262173A (fr) * 1986-05-29 1989-10-03 James Angus Mceachern Synchronisation de signaux de donnees asynchrones
US4928275A (en) * 1989-05-26 1990-05-22 Northern Telecom Limited Synchronization of asynchronous data signals
DE3942885A1 (de) * 1989-12-23 1991-06-27 Philips Patentverwaltung Schaltungsanordnung zur bitratenanpassung

Also Published As

Publication number Publication date
EP0459686A3 (en) 1992-08-26
KR0175662B1 (ko) 1999-05-15
EP0459686B1 (fr) 1996-12-27
KR910021068A (ko) 1991-12-20
US5119406A (en) 1992-06-02
DE69123785T2 (de) 1997-04-17
DE69123785D1 (de) 1997-02-06
JP2563691B2 (ja) 1996-12-11
JPH04233348A (ja) 1992-08-21
EP0459686A2 (fr) 1991-12-04
CA2036162C (fr) 1995-02-21

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