GB2279522A - Pointer jitter suppression in a desynchronizer - Google Patents

Pointer jitter suppression in a desynchronizer

Info

Publication number
GB2279522A
GB2279522A GB9416172A GB9416172A GB2279522A GB 2279522 A GB2279522 A GB 2279522A GB 9416172 A GB9416172 A GB 9416172A GB 9416172 A GB9416172 A GB 9416172A GB 2279522 A GB2279522 A GB 2279522A
Authority
GB
United Kingdom
Prior art keywords
desynchronizer
phase
read
data buffer
controlled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB9416172A
Other versions
GB2279522B (en
GB9416172D0 (en
Inventor
Reino Urala
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Oyj
Original Assignee
Nokia Telecommunications Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Telecommunications Oy filed Critical Nokia Telecommunications Oy
Publication of GB9416172D0 publication Critical patent/GB9416172D0/en
Publication of GB2279522A publication Critical patent/GB2279522A/en
Application granted granted Critical
Publication of GB2279522B publication Critical patent/GB2279522B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q11/00Selecting arrangements for multiplex systems
    • H04Q11/04Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478Provisions for broadband connections
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/06Synchronising arrangements
    • H04J3/07Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
    • H04J3/076Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J2203/00Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
    • H04J2203/0001Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
    • H04J2203/0089Multiplexing, e.g. coding, scrambling, SONET

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

The invention relates to an arrangement for suppressing pointer justification jitter in a desynchronizer in a digital transmission system, the desynchronizer comprising a data buffer (1); a data buffer write address counter (2) controlled by a write clock (CLK1); a data buffer read address counter (3) controlled by a read clock (CLK2); and a phase-locked loop comprising a phase comparator (4), a loop filter (A1) and a voltage-controlled oscillator (5) for adjusting said read clock on the basis of the phase difference between the read and write clocks. According to the invention, the arrangement comprises means (A2, 71, 81) for positively controlling the phase-locked loop so as to limit, in synchronization with the time of occurrence of each pointer justification, the maximum amplitude of the phase jitter induced in an output signal (DATA OUT) of the desynchronizer by said pointer justification. <IMAGE>
GB9416172A 1992-02-14 1993-02-12 Pointer jitter suppression in a desynchronizer Expired - Fee Related GB2279522B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FI920643A FI90709C (en) 1992-02-14 1992-02-14 Arrangement for damping pointer vibration in a desynchronizer
PCT/FI1993/000045 WO1993016535A1 (en) 1992-02-14 1993-02-12 Pointer jitter suppression in a desynchronizer

Publications (3)

Publication Number Publication Date
GB9416172D0 GB9416172D0 (en) 1994-10-05
GB2279522A true GB2279522A (en) 1995-01-04
GB2279522B GB2279522B (en) 1995-10-25

Family

ID=8534632

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9416172A Expired - Fee Related GB2279522B (en) 1992-02-14 1993-02-12 Pointer jitter suppression in a desynchronizer

Country Status (6)

Country Link
AU (1) AU3500693A (en)
DE (1) DE4390463T1 (en)
FI (1) FI90709C (en)
GB (1) GB2279522B (en)
SE (1) SE518361C2 (en)
WO (1) WO1993016535A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5457717A (en) * 1993-11-29 1995-10-10 Dsc Communications Corporation Apparatus and method for eliminating mapping jitter
ES2102938B1 (en) * 1994-03-28 1998-04-16 Alcatel Standard Electrica PHASE FLUCTUATION REDUCTION SYSTEM IN DIGITAL DEMULTIPLEXERS.
US6064706A (en) * 1996-05-01 2000-05-16 Alcatel Usa, Inc. Apparatus and method of desynchronizing synchronously mapped asynchronous data
SE509186C2 (en) * 1996-06-25 1998-12-14 Ericsson Telefon Ab L M Device and method for processing redundancy signals and a telecommunication system comprising the same
FI965072A (en) 1996-12-17 1998-08-13 Nokia Telecommunications Oy Method for damping transients caused by smoothing events in a desynchronizer
DE19653470C2 (en) * 1996-12-20 1998-10-08 Siemens Ag Method and arrangement for clock recovery from a digital signal

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4996698A (en) * 1989-10-23 1991-02-26 Rockwell International Corporation Clock signal resynchronizing apparatus
EP0435383A2 (en) * 1989-12-23 1991-07-03 Philips Patentverwaltung GmbH Circuit for bit adaptation
WO1991012678A1 (en) * 1990-02-16 1991-08-22 Siemens Aktiengesellschaft Process and device for beat recovery
US5052025A (en) * 1990-08-24 1991-09-24 At&T Bell Laboratories Synchronous digital signal to asynchronous digital signal desynchronizer
EP0450269A2 (en) * 1990-03-14 1991-10-09 Alcatel N.V. Phase locked loop arrangement
EP0491054A1 (en) * 1990-07-04 1992-06-24 Fujitsu Limited Circuit for extracting asynchronous signal

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4996698A (en) * 1989-10-23 1991-02-26 Rockwell International Corporation Clock signal resynchronizing apparatus
EP0435383A2 (en) * 1989-12-23 1991-07-03 Philips Patentverwaltung GmbH Circuit for bit adaptation
WO1991012678A1 (en) * 1990-02-16 1991-08-22 Siemens Aktiengesellschaft Process and device for beat recovery
EP0450269A2 (en) * 1990-03-14 1991-10-09 Alcatel N.V. Phase locked loop arrangement
EP0491054A1 (en) * 1990-07-04 1992-06-24 Fujitsu Limited Circuit for extracting asynchronous signal
US5052025A (en) * 1990-08-24 1991-09-24 At&T Bell Laboratories Synchronous digital signal to asynchronous digital signal desynchronizer

Also Published As

Publication number Publication date
SE9402708D0 (en) 1994-08-12
SE9402708L (en) 1994-08-12
GB2279522B (en) 1995-10-25
AU3500693A (en) 1993-09-03
WO1993016535A1 (en) 1993-08-19
SE518361C2 (en) 2002-10-01
FI90709B (en) 1993-11-30
DE4390463T1 (en) 1995-01-26
FI920643A0 (en) 1992-02-14
FI920643A (en) 1993-08-15
FI90709C (en) 1994-03-10
GB9416172D0 (en) 1994-10-05

Similar Documents

Publication Publication Date Title
CA2036135C (en) Phase locked loop including non-integer multiple frequency reference signal
EP0549125B1 (en) Synchronous digital signal to asynchronous digital signal desynchronizer
US5367545A (en) Asynchronous signal extracting circuit
CA2036162A1 (en) Digital signal synchronization employing single elastic store
ATE192616T1 (en) INCREMENTAL PHASE SMOOTHING DESYNCHRONIZER AND COMPUTING ARRANGEMENT
JPH04142812A (en) Phase locked loop circuit
CA2254651A1 (en) Method and apparatus for coupled phase locked loops
US5276688A (en) Circuit arrangement for bit rate adjustment
JPH06102964A (en) Information processing system
GB2279522A (en) Pointer jitter suppression in a desynchronizer
ES2102938A1 (en) Jitter reduction system in digital demultiplexers.
RU97120125A (en) SYNCHRONIZATION RECOVERY DEVICE FOR SYNCHRONOUS DIGITAL HIERARCHICAL DATA TRANSMISSION SYSTEM
DE3374829D1 (en) Phase-locked clock
US5339338A (en) Apparatus and method for data desynchronization
US5960331A (en) Device and method for maintaining synchronization and frequency stability in a wireless telecommunication system
KR100242424B1 (en) Several network sink clock generator
JPH01180151A (en) Self-running frequency stability compensation type pll circuit
JP2630057B2 (en) Destuffing circuit of digital synchronous network.
JPH1117669A (en) Phase-locked loop circuit
KR0120030Y1 (en) Frame length varying system
JPH05130064A (en) Destuffing circuit
US6084442A (en) Digital oscillator for generating two fixed pulse signals from one clock
JPH0548561A (en) Destuff circuit
JP3097737B2 (en) Memory circuit for burst clock
JPS63308427A (en) Speed converting circuit

Legal Events

Date Code Title Description
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20040212