SE9402708D0 - Attenuation of pointers in a desynchronizer - Google Patents

Attenuation of pointers in a desynchronizer

Info

Publication number
SE9402708D0
SE9402708D0 SE9402708A SE9402708A SE9402708D0 SE 9402708 D0 SE9402708 D0 SE 9402708D0 SE 9402708 A SE9402708 A SE 9402708A SE 9402708 A SE9402708 A SE 9402708A SE 9402708 D0 SE9402708 D0 SE 9402708D0
Authority
SE
Sweden
Prior art keywords
desynchronizer
phase
read
data buffer
controlled
Prior art date
Application number
SE9402708A
Other languages
Swedish (sv)
Other versions
SE9402708L (en
SE518361C2 (en
Inventor
Reino Urala
Original Assignee
Nokia Telecommunications Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Telecommunications Oy filed Critical Nokia Telecommunications Oy
Publication of SE9402708L publication Critical patent/SE9402708L/en
Publication of SE9402708D0 publication Critical patent/SE9402708D0/en
Publication of SE518361C2 publication Critical patent/SE518361C2/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478—Provisions for broadband connections
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
    • H04J3/076—Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
    • H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
    • H04J2203/0089—Multiplexing, e.g. coding, scrambling, SONET

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

The invention relates to an arrangement for suppressing pointer justification jitter in a desynchronizer in a digital transmission system, the desynchronizer comprising a data buffer (1); a data buffer write address counter (2) controlled by a write clock (CLK1); a data buffer read address counter (3) controlled by a read clock (CLK2); and a phase-locked loop comprising a phase comparator (4), a loop filter (A1) and a voltage-controlled oscillator (5) for adjusting said read clock on the basis of the phase difference between the read and write clocks. According to the invention, the arrangement comprises means (A2, 71, 81) for positively controlling the phase-locked loop so as to limit, in synchronization with the time of occurrence of each pointer justification, the maximum amplitude of the phase jitter induced in an output signal (DATA OUT) of the desynchronizer by said pointer justification. <IMAGE>
SE9402708A 1992-02-14 1994-08-12 Attenuation of pointer jitters in a desynchronizer SE518361C2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FI920643A FI90709C (en) 1992-02-14 1992-02-14 Arrangement for damping pointer vibration in a desynchronizer
PCT/FI1993/000045 WO1993016535A1 (en) 1992-02-14 1993-02-12 Pointer jitter suppression in a desynchronizer

Publications (3)

Publication Number Publication Date
SE9402708L SE9402708L (en) 1994-08-12
SE9402708D0 true SE9402708D0 (en) 1994-08-12
SE518361C2 SE518361C2 (en) 2002-10-01

Family

ID=8534632

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9402708A SE518361C2 (en) 1992-02-14 1994-08-12 Attenuation of pointer jitters in a desynchronizer

Country Status (6)

Country Link
AU (1) AU3500693A (en)
DE (1) DE4390463T1 (en)
FI (1) FI90709C (en)
GB (1) GB2279522B (en)
SE (1) SE518361C2 (en)
WO (1) WO1993016535A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5457717A (en) * 1993-11-29 1995-10-10 Dsc Communications Corporation Apparatus and method for eliminating mapping jitter
ES2102938B1 (en) * 1994-03-28 1998-04-16 Alcatel Standard Electrica PHASE FLUCTUATION REDUCTION SYSTEM IN DIGITAL DEMULTIPLEXERS.
US6064706A (en) * 1996-05-01 2000-05-16 Alcatel Usa, Inc. Apparatus and method of desynchronizing synchronously mapped asynchronous data
SE509186C2 (en) * 1996-06-25 1998-12-14 Ericsson Telefon Ab L M Device and method for processing redundancy signals and a telecommunication system comprising the same
FI965072A (en) 1996-12-17 1998-08-13 Nokia Telecommunications Oy Method for damping transients caused by smoothing events in a desynchronizer
DE19653470C2 (en) * 1996-12-20 1998-10-08 Siemens Ag Method and arrangement for clock recovery from a digital signal

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4996698A (en) * 1989-10-23 1991-02-26 Rockwell International Corporation Clock signal resynchronizing apparatus
DE3942885A1 (en) * 1989-12-23 1991-06-27 Philips Patentverwaltung BITRATE ADJUSTMENT CIRCUIT
EP0515376B1 (en) * 1990-02-16 1994-08-17 Siemens Aktiengesellschaft Process and device for beat recovery
EP0450269B1 (en) * 1990-03-14 2000-06-07 Alcatel Phase locked loop arrangement
JP2777929B2 (en) * 1990-07-04 1998-07-23 富士通株式会社 Asynchronous signal extraction circuit
US5052025A (en) * 1990-08-24 1991-09-24 At&T Bell Laboratories Synchronous digital signal to asynchronous digital signal desynchronizer

Also Published As

Publication number Publication date
GB2279522B (en) 1995-10-25
FI920643A (en) 1993-08-15
GB9416172D0 (en) 1994-10-05
AU3500693A (en) 1993-09-03
SE9402708L (en) 1994-08-12
FI90709B (en) 1993-11-30
DE4390463T1 (en) 1995-01-26
GB2279522A (en) 1995-01-04
FI90709C (en) 1994-03-10
SE518361C2 (en) 2002-10-01
WO1993016535A1 (en) 1993-08-19
FI920643A0 (en) 1992-02-14

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