CA1307062C - Methode et structure de fabrication de matrices de transistors en couches minces pour afficheurs a cristaux liquides
- Google Patents
Methode et structure de fabrication de matrices de transistors en couches minces pour afficheurs a cristaux liquides
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Publication number
CA1307062C
CA1307062CCA000568390ACA568390ACA1307062CCA 1307062 CCA1307062 CCA 1307062CCA 000568390 ACA000568390 ACA 000568390ACA 568390 ACA568390 ACA 568390ACA 1307062 CCA1307062 CCA 1307062C
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Canada
Prior art keywords
layer
disposed
aluminum
gate
insulative
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General Electric Co
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General Electric Co
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Application filed by General Electric CofiledCriticalGeneral Electric Co
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Publication of CA1307062CpublicationCriticalpatent/CA1307062C/fr
CA000568390A1987-11-301988-06-02Methode et structure de fabrication de matrices de transistors en couches minces pour afficheurs a cristaux liquides
Expired - Fee RelatedCA1307062C
(fr)
Dual dielectric field effect transistors for protected gate structures for improved yield and performance in thin film transistor matrix addressed liquid crystal displays
Dual dielectric field effect transistors for protected gate structures for improved yield and performance in thin film transistor matrix addressed liquid crystal displays