CA1237170A

CA1237170A - A.c. solid state relay circuit and thyristor structure

Info

Publication number: CA1237170A
Application number: CA000443824A
Authority: CA
Inventors: Thomas Herman; Oliver Williams
Original assignee: International Rectifier Corp USA
Current assignee: Infineon Technologies Americas Corp
Priority date: 1982-12-21
Filing date: 1983-12-20
Publication date: 1988-05-24
Also published as: GB2133641A; SE8306952L; SE8306952D0; GB2174242A; IT1194526B; GB2133641B; IL70462A; MX155562A; GB8604263D0; GB8333998D0; IT8324285A0; NL8304376A; IT8324285A1; DE3345449C2; CH664861A5; KR840007203A; FR2538170B1; KR900004197B1; IL70462A0; GB2174242B

Abstract

A.C. SOLID STATE RELAY CIRCUIT AND THYRISTOR STRUCTURE

ABSTRACT OF THE DISCLOSURE
A solid state a.c. relay has two separate and iden-tical power thyristors connected in anti-parallel arrangement.
The power thyristors are each optically switched, lateral con-duction devices with anode and cathode electrodes on the same surface. Both are switched by illuminating their surface by reflected illumination from an LED. Each thyristor is pro-vided with a respective control circuit which includes a MOS-FET transistor for clamping its respective thyristor gate whenever the voltage across the thyristor exceeds a given absolute value or whenever there is a high dV/dt transient across the thyristor. The control circuit for the control transistor includes a capacitance divider, one element of which is the distributed capacitance of the control transis-tor; a resistor and a zener diode. The control circuit com-ponents are integrated into the thyristor chips. Each of the two identical power chips and the LED chip are spaced from one another and mounted on an alumina substrate. Two lead wires are stitch-bonded to the electrode pads of the two chips to connect them in anti-parallel relation, and are then stitch-bonded to two respective conductive sections on the alumina substrate. Each thyristor consists of a plural-ity of individual lateral thyristor elements connected in parallel. Each element has an active base region which con-tains a respective cathode region. Each of the base regions is carried in a common conductivity type body. Extending fingers of a continuous anode electrode partly enclose each individual base region to enable the parallel connection of the individual devices. The thyristor base and emitter zones are surrounded by an auxiliary P region which is resistively connected to a field plate and the cathode electrode to im-prove emitter collection efficiency. The cathode electrode and anode electrode are interdigitated. The cathode electrode is connected to spaced, parallel, generally rectangular emit-ter regions which are disposed in respective bases between loops of the cathode electrode.

Description

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A.C. SOLID STATE REI.AY CIRCUIT AND THYRISTOR STRUCTVRE

~ACKGROUND OF THE INVENTION
This invention relates to a.c. solid sta-te relays, and to a novel thyristor which can be used in a solid state relay.
Solid state a.c. relays are well known. Such relays, - with optical isolation between input and output, are also well known. In existin~ devices, many discrete components - are commonly required to cornplete the a.c. circuit. Thus, it may take thirty or more discrete thyristors, transistors, resistors and capacitors to ManuEacture a single device.
Attempts have been made to in-tegrate the various parts oE
the entire solid state relay, but these have met only limi-ted~success due to the mix o~ high voltage and high power components .
Solid state relays made in the past have also em-ployed zero voltage crossing circuits to ensure turn on of the thyristor only when the a.c. voltage is within some small "windo~v". These circuits have also been relatively complex ànd dif:Eicult to integrate into the main power chip.
Thus, zero cross firin~ circuits have required the use of a discrete resistor connected across the power terminals.
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These resistors have not been easily integrated into a sin-gle chip because oE the di~ficulty oE Eormin~ this resistor on the chip surEace.

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It has a]so been difEicult -to provide so call~d "snubberless" operatiorl for the relay under any Lnduc-tive or resistlve load. Thus, ~hile solid s-tate relays may operate well under resistive or sli~h-tly inductive loads, they may tend to "half wave" or "chatter", which is a condition wherein a relay turns on only for one-half of a cycle, under a hi~hly inductive load. This has occurred in -the p~st because the relays are comlnonly provided with conditioning circuits for suppressing fast turn on of -the circuit under some fas-t transien-t or hi~h dV/dt condition. When the device is oper-ated under a very hi~hly inductive load, however, voltage transients are commonly generated repetitively durin~ device turn on. When the signal conditioning circuit misin-teEprets this as a -transient si~nal, it shuts off the power output 1~ durin~ a particular hal:E phase of the operation. The circuit will then appear to turn to normal during the next half wave alld the relay will turn on. This condition repeats so that the relay turns on only during one or another of the half waves of the full cycle. To avoid this condition, relays of the past have been formed with reduced firing sensitivity and this has required reduction of sensitivity to optical firin~.
Since prior art relays have been relatively complex, they have required substantial volume for their housings.
~oreover, solid state relays of the past have been llmited to a maximu1n temperature rise o~ about 110C., thus limiting their current-handling capability. Finally, solid state relays of the past have ~een relatively expensive in view of the need for lar~e numbers of discrete components and large houslngs .
Optlcally iired lateral thyristor devices which can be used alone or in such relays are also known. Such devices, however, are expensive and have a relatively hi~h forward drop and are relatlvely insensitive to input radiation. One thyristor devlce of this type lS shown, ~or example, in U.S.
Patent ~,3S5,320, dated October 19, 198~, entitled LIGHT-CONT~OLLED T~NSISTOR.

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~I~IE~' DF~,~CRIP'r ON_OIi' Ttl13 INVE'NTION
In accorclance with the presen-t inventLon, two iden-tical and novel thyris-tor power chips are provided ~or an a.c. relay wherein the power chips are both of lateral con-s-truction with both cathode and anode electrodes at one sur-face of each device and wherein each o~ the chips can be optically fired and has an optically sensitive upper surface which, when illuminated, will permit -the device to become conductive between its anode and cathode elec-trodes.
The ~ate circuit of each o~ the thyristors is con-nected to a novel control circuit, formed either o~ discrete - components or of components merged within the body of the semiconductor material forming the thyristor. The con~rol circuit is operable to prevent turn on, even`though the surface is illuminated, when the voltage across the device exceeds a value greater than some predetermined window value, or when high dV/dt transients appear across the device. This - control circuit includes a clamping transistor which can be turned on to clamp the gate of its respective thyristor and a capacitive divider circuit connected across the main power electrodes. The capacitive divider applies a control s`igna]
to the control transistor.
One of the capacitors of the capacitive divider in-cludes the distributed capacitance of the control transistor.
So lon~ as the control transistor is on, its respective power thyristor cannot turn on even though its surface is illu~
nated. The capacitive divider is arranged so that the con-trol transistor is normally turned on ~or all absolute vol-ta~es across the main device greater than some relatively small window value. Thus, the power thyris-tor cannot turn on outside of this small window value or zero cross value.
The novel capacitance divider, in combination with the control transistor, will now operate to suppress both fast transients and still allow the device to function under its normal load conditlon. Thus, voltage -transients which ;,............ ' ' ~ ' ' ' are ~enerate(l re~)etitively durin~ de~vlce -turn on under highly inductive loacl conclitions will no-t be mlsin-terprel;ecl as a fast transient and the power thyristor chip will be permitted to turn on in its normal manner under even highly inductive load.s.
The novel si~nal conditioner of the invention also allows for substantial improvement in optical sensitivity oE
the device without misfiring. Note that currently available optically isolated triac drivers and the like are always limited either in dV/dt capability or op-tical sensi-tivity because of -their inability to separate low level command si~nals from transients.
A novel housin~ is provided for the two chip arrange-ment in which the two chips are easily and inexpensive]y con-nected in parallel with one another and are protected from the outer environment. An alumina substrate or other suit-- able heat conductive but electrically insulative substrate is provided with suitable conductive patterns thereon for ~eceivin~ the various chips of the switch and Por connecting the chip electrodes to suitable output leads. The two iden-tical thyristor chips which are to be connected in anti-par-allel are symmetrically secured to respective conductive pads on the substrate and are in alignment wi-th one ao-ther and with the terminal ends of two conductive patterns on the substrate. Two continuous wires are then sti-tch-bonded to the thyristor pads and conductivè leads in such a manner that one lead wire is elec-trically connected to the anode pad of one chip, the cathode pad of the second chip and one of the conduc-tive patterns which is connected to an input a.c.
lead. The other wire is similarly connected to the other electrodes and conductive pattern to conduct the thyristors in anti-parallel.
A small LED chip is also connected to -the alumina substrate at the same time the power chips are connected.
The LED is connected appropriately to two input leads which are well insulated from the a.c. output leads.

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plast:ic cap covered by a white illumin~tion re-~lecting ~aterial then is secured to the s~bs-trate and covers the re~ion O:e the subst:rate contain:ing the L~n and the -two power chips. The cap may consist of a -transparent silicone which encloses and encapsulates the surfaces of the chips and their inter-connecting leads with a white silicone painted outer surface.
I-f the cGntrol circuit for the power transistor is carried out in discrete form, the discrete componen-ts may also be suitably connected to this substrate. Pre~erably, however, these components are integrated in-to the individual power chips so that the entire solid state relay will consist of two power chips and their controls, the LED chip and the various support structures previously described.
15- Each thyristor of the relay has a novel structure and is formed in a single chip which has a low ~orward vol-tage drop and a relatively hi~h current capacity and is highly sensitive to input radiation so that a noncritical LED trig~ering source can be provided to cause the thyristor to conduct. The relay circuit control components including . parallel connected control MOSFETs, a resistor, zener diode and capacitor may also be provided in the single chip. The relay control components permit thyristor turn-on only when the anode-to-cathode volta~e is less than a given value~
Moreover, ~alse turn-on due to a transient is prevented under all circuit conditions, if the LED is off.
I~ accordance with the invention, a plurality of individual lateral thyristors, each of which may be optically fired, are connected in parallel with one another within a single chip. Each lateral thyristor has a respective base with emitter elements ~ormed in the base. A novel anode region consisting of a plurality of spaced anode region fingers which envelope the end and two sides of each base make parallel connection o- the elements easily possible.

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The thyris-tor base zone contains space~d parallel emitter re~ions and -ttle base zone is surrourlded by an auxi]iary P region. An allxiliary region for a lateral optically trig-~ered thyristor is shown in Patent 4,355,320. The novel auxiliary regions of the lnvention, however, loop around and fully enclose the individual base regions and are resistive]y connected to a conductive polysilicon field plate which is solidly connected to the metallic cathode electrode.
The novel resistive connection may be obtained by making spaced connections frorn the field plate to the auxil~
iary region. By using a resistive connection in this manner, more carriers which are injected from the anode region and which travel laterally toward the emit-ter will reach the emitter. This improves the forward drop of the devi~e by a significan-t amount (for example, from 1.45 volts to 1,15 volts) which si~nificantly decreases power dissipation durin~
the operation of the device.
In accordance with further features of the inven-tion, the anode region may be relatively heavily doped in comparison to the emitter dopin~ to further reduce the Eorward drop. The emitter doping concentration at the emitter region surface is also controlled to a point found to be optimum for improvin~ injection efficiency. In particular, very ~ood operation is obtained when using a surface concentration o~` 1 x 102 to 6 x 102 phosphorus ions/cc at the emit~er surface.
Finally, in making the surface contacts -for the device, thin lines of relatively thick aluminum are used to expose a maximum amount of silicon~

BRIEF DESCRIPTION OF THE DRAWINGS
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Figure 1 is a cross-sectional view of the junction pattern of a sin~le lateral thyristor which emp]oys some features of the present invention.

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Flgure 2 is a plan vlew O:e the rne-tallizing pa-t-tern on the surEace O:e a sLngle chip which employs the lat~ral -thyris-tor oE the pre,Yent invention.
Figure 3 is a plan view of the ~ilicon surface of -the chip o~` F'i~ure 2 and shows the junction pat-terns which come to the device surface.
Fi~ure 4 is an enlarged view of one of the parallel elements or loops of Fi~ure 3.
Figure 5 is a cross-sectional view o-E Figure 3 taken across the section line 5-5 in Fi~ure 3.
Fi~ure 6 is a cross-sectional view of Figure 4 taken across section line 6-6 in Figure 4.
Figure 7 is a cross-sectional view of Figure 3 taken across section line 7-7 in Figure 3.
Figure 8 is a cross-sectional view oE the polysilicon resistor which is shown in Figure 3.
Figure 9 is a circuit diagram of the thyristor and its control circuit as produced by the junction pattern and interconnections of the device of Figures 2 through 8.
Figure 10 is a circuit diagram of the novel a.c.
relay of the present invention.
Figure 11 illus-trates the two power thyristor chips o~` Figure 10 and an LED mounted on a ceramic substrate.
Figure 12 is a side view of Figure 11.
Figure 13 is an elevation view of the assembly o-f Figure 11 with an enclosing cap for enclosing the LED and ~ower chi~s.
Figure 14 is a top view of Figure 13.
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DETAILED DESCRIPTION OF THE DRAWINGS
Referring first to Figure l, there is shown therein in cross-section the junction pattern and metallizing of a -l~teral thyristor chip which is manufactured in accordance with some of -the principles of the present invention.- The chip containin~ the lateral thyris-tor of Figure l can have .

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any desired size and c:onLigllra-tion, and i9 a chip of mono-crys-tallLne siLicon.
The various junc-tions shown in ~igure 1 are ~ormed in N(--) layer 20. Layer 20 may have a resistivity of about 20 ohm-centimeters. Spaced P type regions 21, 22 and 23 are ~ormed in the upper surface of chip 20 by any desired process.
A fur-ther P type region 23a, which is inactive, may enclose the periphery of region 23. Regions 21, 22, 23 and 23a can be boron-dif~used regions o-E su~eicient concentration so that the sheet resistance oi the P regions will be about 1,600 ohms per square at the chip surface. They may also be formed, for example, by an ion implantation and drive-diffusion process employing 5 x 10-~13 boron atoms per square centimeter dose so that it is relatively lightly doped. Region 21 is prefer-ably more heavily doped than -the other P regions. Regions 21, 22, 23 and 23a may have the same depth of approximately 4 microns. P type region 23 contains an N(-~) region 24 to com~lete the laterally spaced junctions of the lateral thy-ristor.
The facin~ edges of regions 21 and 23 should he as close together as possible while still being able to block a selected vol-tage. In the present application, the device preferably blocks about ~00 to 500 volts and a spacing of 105 microns is used.
Region 21 is the anode re~ion, region 23 is the ~ate or base region, re~ion 24 i5 the emi~ter or cathode re~ion while the N(--) body 20 is the main blocking region of the thyristor shown in Figure 1. Re~ion 22 is a known type of floating ~uard region which permits an increase in trle blockin~ voltage between junctions 21 and 23 to as high as ~00 to 500 volts without dan~er oi brea~down at the surface of the chip.
The upper chip surface is covered by a thin silicon dioxide layer 30 which can have a thickness, for example, of a~out 1 micron. Polysillco- eield plates 31 and 32 are iormed .

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a-to~ the oxLde layer 30 as shown, usin~ conven-tional polysili-con de~osltion and masking technlques. The entire uppcr sur-face oE Ctlip, includin~ the polysLlicon ~ielcl plates, and the oxide 30 is covered wLth a conventional glassy, phosphorus doped silicon dioxide layer 35. Spaced gaps 36 and 37 of known structure may be placed on either side of -the floating guard region 22 to prevent lateral polarization eEfects within the phosphorus doped oxide layer 35 ~rorn interfering with -the field dis-tribu-tion at the sur~ace of region 20 adJacen-t the floating guard region 22.
Sui-table openin~s are formed in the oxide layers 30 and 35 above emitter re~ion 24 and anode region 21 to permit contact to the various regions and field plates. Thus, aluminum cathode electrode 40 and anode electrode 41 are a~plied to emitter region 24 and anode region 21, respec-tively, as shown. Other openings which are formed in the oxide layer 35 permit connection from the cathode 40 to the field plate 31 and from the anode 41 to the field plate 32.
Both cathode electrode 40 and anode electrode 41 are rela-tively thin and can, for example, be about 4 microns in thickness.
Re~ion 23a is preferably resistively connected to the cathode 40. Thus, region 23a can be connected to cathode 40 only at spaced points along their peripheries.
The lateral thyristor o~ Figure 1 is turned on by inJection of carriers from emitter region 24 into ~ate region 23. Suitable inJeCtion can be obtained by applying radiation to the upper surPace of the device which will generate car-riers (holes) in the body 20. These holes drift to region ~3 and are collected by the emitter junction between regions 23 and 24 to act as a base drive to turn the device on. A
suitable source of radiation can be the schematically illus-trated LED 45 which is arranged to illuminate the surface of the device.

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:1.0 It has been Eound that a device employing the s-truc--ture O:e ~ gul e 1 is capable Oe blocking ~rorn ~00 to 600 volts. Durin~ forwarcl conduction, the forward voltage drop was about 1.15 Vol-ts at about 1.5 amperes forward current.
The arrangernen-t of the lateral thyristor of Figure can be implemerlted in any number of desired geometries.
particularly efficient geometry is that disclosed in Figures

2 to 9 which are now described and show an arrangement in which a plurality of devices, such as tha-t of Figure 1, are connected in parallel.
~eferring to Figures 2 and 3, there is shown a plan view of a single chip containing a single thyristor device and its control circuit components. The C}lip of Figures 2 and 3 is one of a large number of chips on a common wafer which are separated after common processing is completed.
The chip is shown in Figure 2 after metallizing o~ the cathode and anode terminal electrodes. The junction pa-tterns on the chip surface are shown in Fi~ure 3. As will be described in detailj a plurality of separate thyristor elements are con-nected in parallel, using novel junction patterns for the anode, base and emi-tter regions (Figures 3 and 4) w~ich e~tend along a path hereinafter designated ei-ther a serpen-tine or interdigitated path, so that they will have the lon~est possible length, thus permitting a high current c~pacity for the device.
In the embodiment of Figures 2 and 3, the chip may have a width of 8~ mils, a leng~th of 113 mils and will have a foxward current-carryin~ rating of 1.5 amperes with a 1.15 volts forward voltage drop. The bisymmetrical blocking vol-tage capability of the device is about 500 volts peak. There-fore, the thyristor chip of the invention can be employed with an identical anti-parallel connected thyristor chip and used in a solid state relay for controlling an a.c. circuit which might have an ~MS voltage of up to 280 volts.

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The basic rnetaLliz~n~ pa-tte-rn of FiKure ~ employs -the cathode 50 and anocle 5l conei~urecl as shown. ~ control circuit, not shown in Fi~ure 2, i9 contaLned within -the chi~
body. The circuit is shown in Figure 9. Metallized sections ~0 and 61 in Fi~ure 3 are electrodes of two respective capa-citors shown in Figure 9. Capacitor 60 will be described later in connection with Figure 7.
The capacitors including electrodes 60 ancl 61 are connected in parallel as shown in Figure 9 and are connected between the anodes of thyristors 64a, 6 b, 64c and 64d and ~ates of control MOSFETS 76, 77, 78 and 79, respectively.
Thyris-tors 6~a, 64b, 64c and 64d are in parallel and have common cathodes ancl anodes, shown as cathode 50 and anode 51 in Figures 2 and 6.
Also provided in-tegrally with the chip of Figure 3 is a 100 K resistor 70 which is formed of polysilicon and is electrically connected between the cathodes and ~ates of each of thyristors 64a, 64b, 64c and 64d. The detailed structure of resistor 70 will be later described in connection with Fi~ure 8.
Additionally provided and formed integrally in the chip of Fi~ure 3 is a zener diode 71 which, as shown in Fi~ure 9, is connected in series with capacitors 60 and 61 between the anode and cathode terminals 51 and 50 of the thyristors shown. There is also shown in Figure 9 an in-herent distributed capacitance 75 in parallel with zener diode 71.
The zener diode 71 may be formed in the inactive P
re~ion 82 and can consist of the N+ re~ion 71a shown in Fi~ure 3. One zener terminal 71b may be formed directly atop the N~ re~ion 71a, and the other terminal may be formed of a metal contact 71c which is connec-ted to the cathode electrode.
A plurality of control MOSFETs 76, 77, 78 and 79, shown in Fi~ure 9, and which will be later described in '71'~3 ~2 ~ ures 3 and 4, are aLso contained on the chip and operate with thyristors 6~a, 6~b, 6~c and 6~d, respectively. Each control MOSF~T is clisposed immedlately adjacont its respec-tive main thyristor element so tha-t operational delay times are limited and circuit symmetry is assured.
The circuit of ~igure 9 is implemented in a novel way, as will now be described in connection with Figures 2 to 8. Note that, while the embodimen-t disclosed herein uses ~our parallel thyristor elements 6~a, ~4b, 64c and 64d, any desired number of elements could be used.
Referring to Figures 3 to 6, the entire integrated device is formecl in a relatively high resistance N(--) sub-strate 80 which can have a resistivity of about 20 ohm-centi-~neters.
A number of individual P type regions are formed in substrate 80 by any desired process. The first of these is the P+ type anode region 81 which corresponds to anode region 21 in Figure 1. As shown in Figures 3 and 4, anode region 81 has a main body section from which three parallel fingers 81a, 81b and 81c extend. Figures 81a and 81b are shown in more detail in Figures 4 and 6. ~ rectangular anode region frame havirlg legs 81d, 81e and 81f surrounds the periphery of -the chip as shown in F`igure 3. Legs 81d and 81e are seen in Figure 5.
The second P type region shown in F`igures 3 to 8 is "inactive" P type auxiliary region 82. Inactive region 82 has loop sections 82a, 82b, 82c and 82d (Figure 3), which enclose the bases of four respec-tive thyristors as will be later described and serve the purpose of auxiliary ring 23a of Fi~ure 1. Loop section 82b is shown in Figure 6.
Four equally spaced, elongated P type base regions 83a, 83b, 83c and 83d (Figures 3, 4 and 6) are also formed in re~ion 80. These base regions correspond to the base region 23 in Fi~ure 1. Base re~ion 83b is shown in enlarged detail In Fi~ure 4. Note -that the base regions 83a, 83b, ~ , . . .
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83c ancl ~3d are aLmost ~ul-Ly enclosed by auxiLiary ring loops 82a, 82b, 82c and 82cl, respective~ly.
~ ~urttler P -type region is Eormed, consisting of a iloating guard ring 84, shown in Eigures 3 to 6. Guard ring 84 Eollows a sinuous path and divides in hale the N(--~re~ion 8~ which reaches the device sur-eace in Figures 3 and 4.
Each of the -thyristor bases 83a, 83b, 83c and 83d receives two parallel N~ emit-ter regions 85a~85b, 86a-8~b, 87a-87b and 88a-88b, respectively (Figures 3, ~ and 6).
Emitter regions 86a and 8Gb are shown in enlarged detail in Fi~ure 4.
From the above, it will be seen thak the junction pattern in Fi~ure 3 iorms the basis for -the four thyristor elernents 64a, 64b, ~c and 64d o-E Figure 9 and makes possi-ble the parallel connection of the devices.
The thyristor element deEining thyristor 64b is shown in Figures ~ and 6 and is now described. The thyris-- tor base consists of active P region 83b containing parallel emitter regions 86a and 86b. The thyristor anode region is comprised o~` the anode region Eingers 81a and 81b which symmetrically enclose the base 83b. The thyristor body consists oE the N(--) re~ion 80. The base is also almost completely surrounded by auxiliary loo~ region 82b which has t~le benefit previously described of increasing collection efficiency~ The novel junction pattern also ma~es possible the parallel connection of the plural thyristors on the chi~.
In iormin~ the junction pattern shown, -the Iateral spacing between the conErontin~ edges oE base re~ions 83a, 83b, 83c and 83d and the respective adjacent anode Ein~ers 81a, 81b and 81c (and the outer anode legs 81d and 81e) was about 105 microns. The depth of each of the P type regions was about ~ Microns. Each oE base regions 83a, 83b, 83c and 83d had a length oi about 40 mils and a width Oe about 75 Ini c.rons .

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Durirlg the formation O:e the various P regions, a further ~ type guard -ring 90 (~'igures 2 and 5) is preferably formed around the periphery oE the chip. I~ing 90 is spaced from the outer periphery of the P~ anode 81e by about 38 microns.
Also during the formation of the various junctions, and as shown in Figures 3 and 4, N(t) source and drain regions 91a-9lb, 92a-92b, '33a-93b and 94a-94b are ~ormed for the con-trol MOSFETs 76, 77, 78 and 79, respectively, in Figure 0.
These are ~ormed in the enlarged inac-tive P type region 82.
As is shown in Figure 4 ~or the case oE con-trol MOSFET 77, a suitable gate oxide having a thickness of about 0.1 micron, and a polysilicon gate electrode (no-t shown) are arranged over the ga~ between regions 92a and 92b. An extremely thin oXide can be used for the control MOSFETs because the gate is at the ~otential of the node between capacitors 60 and 61 and caE)acitor 75. Thus, the potential difference between the control MOSFET gates and the cathode of the main thyris~
tors is very low. Therefore, transistors 76 to 79 can be very high gain transistors.
The source region 92a is connected to the inac-tive base, while drain region 92b is electrically connec-ted to the thyristor base region 83b through the conduc-tive strip 95 (Figures 4 and 6). Strip 95 is preferably metal. A
similar arran~ement is provided ~or each of the thyristor elernents with a conductive strip connecting bases 83a, 83b, 83c and 83d to control MOSFET source electrodes 91b, 92b, - 93b and 94b, respectively. The conductive strips are then all connec-ted to~ether as by a polysilicon connection strip, ~artly schematically shown in Figure 4 by dotted line 95a.
Capacitors 60 and 61 are also implemented in the inactive P region 82 as shown in Figure 7 for capacitor 60.
Thus, ca~acitor 60 is formed by depositing a metal layer atop an area of the P type base 82 which is isolated from the chip by causing a rectangular ring 96 having appropriately .

.15 rad.iused corne.rs ancl o:E the N(--) material 80 to reach the chip sur-l'ace. Note that the metal laye:r 60 overl:Les the:rmal oxide :Layer 97 to :Eor~ a ~:ield plate.
I'he resistor 70 is also :lmplemen-ted in inac-tive P type region 82 as shown in Figure 8. Thus, in Figure 8, a polysilicon strip 70a is deposited atop oxide layer 97 and is overcoated with a deposited silicon dioxide layer 98.
Therefore, resistor 70 is formecl of a resistive layer which is coll~pletely insulated from the chip body by insul.ation layer 97. The resistor is thus an ideal resistor which will be ~ree of parasitic interaction with other circuit compo-nents. Openings are then formed in layer 98 and resistor terminal connections 99 and 100 are made to the resistor.
These terminals are appropriately connected to the thryistor cathode and to the source electrodes o:E control MOSFE'rs 76, 77, 78 and 7~.
The up~er surface of the chip shown in Figures ~
and 6 is further processed -to have the desired metallizing.
~efore'metallizin~, an appropriate thermal oxide 110 exists . 20 in place, or is applied to the device surface to a thickness of about 1 micron. After conven-tional masking and etching steps, metals are applied in the necessary sequence. The upper surface is then covered with a deposited oxide coating 111 which may have any desired thickness.
Novel polysilicon field plates 112 and 113 are de-~osited on the thermal oxide 110. Note that all polysilicon strips or layers may be deposited in any desired sequence.
Field plate 112 is an elongated, sinuous plate which is disposed atop and follows the path of the junction between P(+) anode region 81 and N(--) region 80. Field plate 113 similarly is an elongated, sinuous plate which follows a path parallel to that of plate 112 and overlies the junction between auxiliary region 82 and the outwardly dis~osed N(--) re~lon 80.

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At the time ~:-ie1d plates 11~ ancl ll3 are~ de~osited, an outer equil~otentlal ring lL5 (~igllre 5) may also be dls-~osed al~ouncl -the ou-ter periphery Oe the chip. Ring 115 iæ
connected to substrate 80 in the usual manner.
Each of field plates 112 and 113 and ring 115 may have a width of about 20 microns. The guard ring region 8~
may have a width of about 8 microns and is centrally located between the opposing edges O:e pla-tes 112 and 113 which edges are about 4~ microns apart. Similarly, P type region 90 (Figure 5) is centrally located between plates 112 and 115, the edges of which are abou-t 44 microns apart.
The anode electrode 51 is then formed as shown and engages the P type anode region 81, as shown in Figures 2 and 6. Cathode electrode 50 is also formed as shown in Figures 2, 5 and 6.
The lateral thyristor of Figures 2 through 9 is turned on by radiation from LED 45 (Figures 6 and 9) which is arranged to illuminate the exposed surface of the chip.
Since the chip is extremely sensitive, the LED 45 is not critical in size, output or location.
The patterns described in Figures 2 through 8 will form the electrical circuit shown in Figure 9 and define one-half of the solid state relay which is later described.
Turn-on of the thyristor is clamped against ~iring by tran-sients when no light is present. Voltage division obtained between capacitors 60-61 and 75 defines the volta~e window at which turn-on is possible. Significantly, the capacitive voltage divider permi~ts a very low gate voltage for the control transistors and very low function leakage current.
The capacitors also provide shielding from input light or radiation.
The novel lateral thyristor shown in Figures 2 to 8 can be made by any desired process. The device provides a maximum effective current carrying area between the anode 3S region 81 and the base region 83 for a given chip area. The . .

; . .

17 ~23'~ ~o pat-tern conelgurlltion is also arrangecl-to reduce eo-rward voltage drop -to as large a degree as possible while main-taining high light sensitivity so tha-t the LED ~5 is not critical.
A signi~icant ~ea-ture of the novel geometry is the novel P type auxiliary regions 82a, 82b, 82c and 82d which loop around each base region 83a, 83b, 83c and 83d, respec---tively. This geometry makes it possible to connect together all N+ cathodes. Thus, regions 82a, 82h, 82c and 82d and main region 82 are constant potential re~ions in which all thyristor bases are embedded. By spreading out into region 82 at the ends of the bases, a large area is made available for rnetallizing to connect regions in parallel.
Pre~erably, a resistive connection is rnade ~rom the cathode 50 to the loops 82al 82b, 82c and 82d as by using spaced dot type connec-tions, schematically shown as connec-tion points 120 in Figure 4, extending along the length o~
the P type loop 82b. The connection can also be made by a short contact strip 121, shown in Figure 4. By using a resistive connection between the auxiliary loops and the cathode electrode 50, and as shown in Figures 4 and 6, car-riers which are injected -~rom -the anode regions 81a and 81b durin~ turn-on of the device will tend to move to the emitter re~ions 86a and 86b rather than being collected by the auxil-iarg re~ions 82a, 82b, 83c and 82d~ This increases the col-lection ef~iciency o~ the emit-ter and substantially decreases the forward volta~e drop of the device. By way o-f example, by makin~ the resistive connection between auxiliary loo~
re~ions and cathode 50, the ~orward voltage drop at 1.5 ampares forward current was reduced ~rom about 1.45 volts to about 1.15 volts. This results in a signi-ficant reduction of power dissipation during forward conduc-tion.
~uring processing of the device of Figures 3 to 6, the anode regioll 81 and all its segments are pre~erably heavily doped as compared to the doping oi P type regions 82, 83 ancl ~. By way o:E example, anode re~:ion ~:L can be doped to -the point where it has a re~s-l,s-ti.vity o:~ 60 ohms per s~luare as cornpared to 1600 ohms per square ~c~r rebrlons 82, 83 and 8~. This sets a hi~h gain and thus high li~ht sensi-tivi-ty for the inherent lateral transistor consisting o.~
re~ions 81, 80 and 83. Furthermore7 by more heavily dopi.ng the anode re~ion, the ~orward voltage drop of -the device ls reduced.
A further impor-tant Eeature of the invention lies in the control o:E the dopin~ o.~ the emitter regions, such as re~ions 8~ and 86b in ~igures 3 and 6, so that the ~ type concentration at the surface of the device is at an optimum value of 1 x 10 to 6 x 10 phosphorus ions/cc. This can be done as by diffusin~ phosphorus through a thin oxide durin~ the formation of the regions 86 or by control of the various ~as :Elows during the diffusion process. By reducing -the N type concentration at the surface of regions 86, the injection efficiency of the device is improved, thus further reducin~ -the ~orward volta~e drop and substantially increasing the sensitivity o-f the device to turn-on by photons from the source 45.
Referrin~ next to Figure 10, there is shown a cir-cuit dia~ram of the full a.c. relay of the present invention The relay of Fi~ure 10 employs two identical thyristors 210 and 211 connected in anti-parallel relationship with respect to one another between main a~c. power terminals 212 and 213, respectively. Schematically illustrated thyristors 210 and 211 are each of the type shown in Figures 1 to 9 and are provided with ~ate circuits schematically illustrated by the ~ates 216 and 217, respectively. Thyristor chip 210 has, on its upper surface, anode electrode pad 220 and cathode elec-trode pad 221, while chip 211 has an identical anode pad 222 .and cathode pad 223 (Figure 11).
Thyristors 210 and 211 are electrically connected togéther so that anode 220 of one is connected to cathode 19 :L2~'7.~

~23 o~ the other and so that anode 22~ of one is connec-t~d to ca-thode 22] of -the other. 'rhus, the devices are connected in the an-ti-parallel relationship shown in ~igure 10.
~ sin~le LEI) 225, which can be a conventional com-mercially available ~allium aluminum arsenide device havingterminals 226 and Z27 in Figure 10, is arranged as will be later described to flood the pho-tosensitive surfaces of chips 210 and 211 in order to permit -turn on of the chips if other circuit condi-tions are appropriate. Good electrical isolation is provided be-tween the input circuit connected to terminals 22~ and 227 and the a.c. power circuit connected to terminals 212 and 213.
Identical control circuits such as those described previously are provided for controlling the turn on of -thy-ristors 210 and 211 respectively and include respective MOSFET transistors 230 and 231, zener diodes 232 and 233, resistors 234 and 235 and capacitors 236 and 237. Capacitors 236 and 237, like capacitors 60 and 61 of ~i~ure 9, serve as one componen-t of respec-tive capacitive dividers. Tha second ~o component of the capacitive dividers consists of the distri-- - buted capacitance 238 and 239 of devices 230 and 231, respec-tively.
The circuit co~ponents 230-239 could be implemented as discrete components. Preferably, however, these circuit components are implemented integrally with the semiconductor chips deiinin~ thyristors 210 and 211, as described in con-nection ~,vith ~i~ures 1 to 9.
Transistors 230 and 231 are connec-ted to the gates 216 and 21f of thyristors 210 and 211, respectively. So long as transistors 230 and 231 conduct, or are on, the application of illumination to the surfaces of devices 210 an~ 211 from LED 22~ cannot turn on the device. Transistors 230 and 231 will turn on when their respective gates 240 and 241 are appro~riately charged to a suitable threshold voltage Vth~ -Thus, when the nodes 242 and 243 reach the threshold turn on . .

~o .~.2~3'7~

volta~e oE ~ransistors 230 and 231, respectively, and if suita~,le drain to source voltage i~s provided, -the devices will con-luct and clamu the respec-tive gates 216 and 2t7 oi' thyristors 210 and 21L.
The voltage at each of nodes 2~2,and 2~3, ter~ed V~, will be =VCCCp/(Cl-~Cp).
In the above, Vcc is the volta~e across terminals 212 and 213, Cp is the capacitance of distributed capaci-tors 238 and 239, respectively, and C1 is the capacitance o-f capacitors ~36 and 237, respectively.
From the above, it will be seen that the voltage V0 at nodes 242 or 243 will be greater than the threshold volta~e oE the transistors 230 and 231 when the instantaneous a.c. volta~e between terminals 212 and 213 is more positive,, or is more negative than some "window" value. ~ Consequently, transistors 230 and 231 clamp thyristors 210 and 211 when this window voltage is exceeded. This arrangement then per-mits a zero detection circuit wi-thout requiring a resistor ex-tendinO between the main terminals of the device.
The novel capacitive divider circuit is also useful , in sup~ressin~ the firin~ of devices 210 and 211 due to fast rising ~ulses such as transient noise or high dV/dt signals.
~uch hi~h transient pulses will apply a suitably high voltage across parasitic capacitances 23~ and 239 that the transistors 23U and 231 respectively turn on to clall~p its respective thy-ristor. Thus, the thyristor will not be fired in respon,se to fast risini transient pulses.
For relatively slow rising pulses, such as those produced by highly inductive loads connected to the relay terminals 212 and 213, these pulses will not be sufficiently iast to turn on the control transistors and unintentionally clamp the thyristors 210 and 211, thereby to avoid single ;;..........

~2~'7~
ptlaslrlg or chattering Oe tlle relay on highly indllctive loads.
Note also that -this is accomplished wlthout havin~ to reduce -the optical sensl-tivity of the device. Thus, the -thyristors 210 and 211 can be designed to have optimum optical sensiti-vity for firing without concerZl for false operation by rela-tively slow risin~ transients.
A further advantage of the circuit shown in Figure lU is in the design o-f resistors 234 and 235. Thus, the tem-perature coe~icient oE -the resistor is balanced against the sensitivity o~ its respective thyristor. That is, if the resistor has the usual ne~ative ternperature coefEicient, it is possible that the resistor would clamp its respective controlled rectifier when ho-t. However, by balancing the resistance temperature coefficient of resis-tors 234 and 235, this clampin~ action can be avoided.
There is next described in Fi~ures 11 to 14 a struc--ture for housinD the chips 210 and 211 and LED 225 of ~igure 10. Referring first to Figures 11 and 12, there is shown a ceramic substrate support 260 which can be of alu~ina but may - 20 be of any desired electrically insulative, thermally conductive material. By way of example, the alumina slab 260 can have a thic~ness of 0.025 inch, a length of about 0.9 inch and a width of about 0.25 inch. A plurality of conductive patterns is formed on one surface of substrate 2607 including patterns 261 to 267. Each of these patterns may be formed by gold platin~ onto the substrate where the gold plating has a thickness greater than about 150 microinchesY Each of thy-ristor chips 210 and 211 is then sllitably soldered or other-wise mounted down onto conductive pads 265 and 264~ respec-~0 tively, so as to be in ~ood thermal contact with the alumina body 2~0. Each of the chips 210 and 211 may have a size o~
approximately 82 X 116 mils for a typically sized device.
The LED chip 225 is mounted down on one end of conductive patter 262.

.

. . ...

22 ~ ~,,7~

Chips 2lO ancl 2lL a-re so mounte~d that their anode and catllode leads are general1y in Line with one anothcr and with one en~l Oe cond~lctive pQtternS 266 and 267. Conseq1lently, one single wire 270 is conveniently used to electrically con-nect conductive pads 223 oE thyristor 211 and 220 o~' thyristor 210 and the ends o~ conduc-tive pattern 267. This can be done in a stitch-bondin~ process o-f relatively simple nature which lends itself to high speed automated techniques. Thus, a bonding head is simply brought clown on-to the wire 270 to electrically attach the wire at the three spaced points cor-responding to the location o~ pads 223, 220 and the end of conductor 267. In a similar manner, a second parallel wire 271 is stitch-bonded to conductive pads 222, 221 and the end of conductive pattern 266. The s-titch-bonding of conduc-tor 271 is shown in Eigures 11 and 12. Each o~ conductive ~vires 270 and 271 may be o~ aluminum wire having a diameter of about 6 mils.
As a result of the above, the power -terminals 212 and 213 are connected to the thyristor devices 210 and 211 in Figure 11 in the manner shown in Figure lO with the thy-ristors in anti-parallel relationship with respect to vne another. Note tha-t, since the chips 210 and 211 also con-tain their respective control circuits, the control circuits are also connected in place wi-th this sin~le stitch-bonding o~eration.
The LED 225 is shown disposed atop one en~ o~ con-ductive pattern 262 which is connected to lead 226. The other electrode o:~ LED 225 is electrically connected to one end o~ conductive pattern 261 by the wire 280. Wire 280 which may be an extending lead of the LED 225 is bonded to the end o~ conductive pa-ttern 261 in any desired manner.
Conductive pattern 261 is then electrically connected to spaced conductive pattern 263 either by the direct shorting connection o~ ~vire 281 or by a resistor 282. The selection o:E the ~horting wire 281 or reslstor 2g2 dependo upon Ih~

.

23 ~ 3'7~

power avai:Lable a-t -ter-minals 226 ancl 227 and the character-istics oE -the L,E,L) ~25. Wires 2~0 and 2~l may be ~old wires having diameters O:e abou-t 1 mil~ Note -that the leads 212, 213, 2~ ancl 227 ex-tencl Erom the periphery oE substrate 260, to define a dual in-line pin type of package.
An optical cap or enclosure 291 is then placed a-top the LED 225 and thyristors 210 and 211 and encloses the area shown in dot-dash lines 290 in Figure 11. The cap is ehown in Fi~ures 13 and 14 as cap 291 and may be composed oE any desired reElective plastic material capable of withstanding the temperatures which are produced during device opera-tion.
A white colored plastic has been used. The plastic selected may be disulphone. The plastic pre~erably is whi-te so that light will reflect irom its interior surface. The cap can also consist oE a suitable silicone such as RTV having tita-nium oxide powder mixed therein. The titanium oxide powder uniquely remains in dispersion within the silicone. The mix-ture can be oven cured at about 115C. for about 15 minutes.
The cap 291 has a sloped side 292 above the location of the LEI) 225 with this sloped edge tending to re~lect light toward the region of the chips 210 and 211, as can be seen in Figure 13.
Cap 2~1 can be cemented in place, as shown in Figure 13 or if desired, can be arran~ed to overlap the substrate and snap over the substrate edge. A clear silicone is then loaded into the interior of cap 292 through the filling holes 2~3 and 2~4 of Figures 13 and 14 in order to completely en-capsulate all of chips 225, 210, 211 and their connecting leads while permitting illumination from LED 225 to reach the ~hotosensitive surfaces of thyristor chips 210 and 211.
After the cap 291 is secured in place and -Eilled with silicone, the entire substrate 260 along with the cap 2~1 can be Inounted within a lead Erame which provides the leads 212, 213, 226 and 227. The device may then be com-~5 pletely housed within a molded housing which could, Eor 2~ 3'7~7~

example, be eormecl by a -transeer molding process or the like.
Leads 212, 213, 22G and 227 will e~tend Erom the packa~e to de~ine a dual Ln-line pin package Oe relat:i.vely gmall size and volume. The devlce, however, will be capable O:e a con-tinuous current rating Oe 1-1/2 amperes or greater at volta~es of 240 volts a.c.
Although the present invention has been described in connection with a preeerred embodiment -thereoe, many variations and modieica-tions will now become apparen-t to those skilled in the art. It is preferred, there~ore, that the present invention be lirnited not by the speciFic disclo-sure herein, but only by the appended claims.

.

Claims

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A solid state a.c. relay comprising first and second thyristors each having respective anode and cathode electrodes and a respective gate circuit; characterized in that each of said thyristors is formed in separate respective first and second semiconductor chips and is of the lateral conductivity type, wherein said anode and cathode electrodes of each of said thyristors are on the same first surface of their said first and second chips respectively; said first surface of said first and second chips being optically sen-sitive, whereby said first and second chips can be switched to conduct current by illuminating said one surface; said solid state relay further comprising a light emitting diode arranged to illuminate said first surfaces upon its energi-zation; a pair of a.c. terminals; said anode and cathode electrodes of said first and second thyristors connected to said pair of a.c. terminals and in anti-parallel relation with one another; a pair of control terminals insulated from said a.c. terminals and connected to said light emitting diode; and first and second control circuits connected to said gate circuits of said first and second thyristors re-spectively for clamping said first and second gate circuits respectively to prevent firing of said first and second thy-ristors when the voltage between said pair of a.c. terminals exceeds a given value and for clamping said first and second gate circuits in response to transient pulses having a dV/dt greater than a given value.

2. The solid state relay of claim 1, wherein said first and second control circuits include first and second control transistors respectively, each having an output cir-cuit and a transistor control circuit operable to switch its respective control circuit between a conductive and a non-conductive condition; and further characterized in containing first and second capacitor dividers; said first and second tran-sistor output circuits connected between said gate circuit and said cathode electrode of its respective one of said first and second thyristors, whereby, when said first or second transistor output circuit is conductive, the respective one of said first or second thyristors cannot fire in response to illumination of its said first surface; said first and second capacitor dividers con-nected across said pair of a.c. terminals and having respective nodes between capacitors connected to said control circuit of the respective control transistor, whereby the voltage at said nodes renders its respective transistor conductive so long as the volt-age between said pair of a.c. terminals exceeds a given value to prevent turn on of the respective one of said thyristors when the a.c. voltage exceeds a given window voltage, and whereby fast rising transient pulses turn on said transistors for their dura-tion to prevent turn on of said thyristors by transient high dV/dt pulses.

3. The solid state relay of claim 2, wherein said first and second control circuits are further characterized in including first and second zener diodes respectively connected from said nodes of said first and second capacitor dividers respectively to the cathode electrode of said first and second thyristors, respectively.

4. The solid state relay of claim 2 or 3, which is further characterized in including first and second resistors connected between said gate circuit of said first and second thyristors, respectively to the cathode electrode of said first and second thyristors, respectively.

5. The solid state relay of claim 3, wherein said first and second transistors are metal oxide semi-conductor field effect transistors and wherein said transistor control circuits include the gate circuit of said transistors.

6. The solid state relay of claim 5, which is further characterized in that said second capacitor of each of said first and second capacitor dividers is the distributed capacitance of said first and second transistors, respectively.

7. The solid state relay of claim 1, 2 or 3, which further includes an electrically insulative but thermally conduc-tive ceramic substrate for mounting said first and second chips and said light emitting diode; said first and second chips and said light emitting diode being fixed to the same surface of said substrate and spaced from one another; said optically sensitive surfaces of said first and second chips facing away from said substrate; said light emitting diode being in a position which enables illumination of said first and second chips by reflection of its light output from reflecting surfaces.

8. The solid state relay of claim 1, which is further characterized in that said first surface of each chip constitutes a junction-receiving surface of one conductivity type; an anode region of the other conductivity type and a base region of said other conductivity type each formed into said surface and later-ally spaced from one another; an emitter region of said one con-ductivity type formed in and totally contained within said base region and extending therein from said surface; said anode and cathode electrodes connected to said anode and emitter regions, respectively; said anode being more heavily doped than said base region in order to reduce forward voltage drop and increase light sensitivity.

9. The solid state relay of claim 1, which is further characterized in that said first surface of each ship constitutes a junction-receiving surface of one conductivity type; an anode region of the other conductivity type and a base region of said other conductivity type each formed into said surface and later-ally spaced from one another; an emitter region of said one con-ductivity type formed in and totally contained within said base region and extending therein from said surface; said anode and cathode electrodes connected to said anode and emitter regions, respectively; said emitter region being relatively lightly doped at said surface to a level which would be obtained by diffusion through a thin oxide layer in order to increase the radiation sensitivity of said lateral thyristor to turn on by radiation from said radiation means.

10. The solid state relay of claim 8 or 9, which further includes a guard ring of said other conductivity type formed into said surface and disposed between and laterally spaced from said anode and base regions; said guard ring being out of contact with said cathode and anode electrodes and float-ing electrically with respect to said electrodes.

11. The solid state relay of claim 1, which is further characterized in that said first surface of each chip constitutes a junction-receiving surface of one conductivity type; an anode region of the other conductivity type and a base region of said other conductivity type each formed into said surface and later-ally spaced from one another; an emitter region of said one conductivity type formed in and totally contained with said base region and extending therein from said surface; said anode and cathode electrodes connected to said anode and emitter regions, respectively; and an auxiliary region of said other conductivity type formed in said surface and laterally spaced from and sur-rounding said base region.

12. The solid state relay of claim 8 or 9, which is further characterized in that said base region has an elongated shape terminating at said surface; said emitter region comprising at least one elongated rectangular shape contained within said base region; said anode region having a digitated pattern, the fingers of which envelope said base region.

13. The solid state relay of claim 11, which is fur-ther characterized in including means for resistively connected in permanent fashion said auxiliary region to said cathode elec-trode.