GB2174242A - Optically fired lateral thyristor structure - Google Patents

Abstract

An anode region (21) and a base region (23) of one conductivity type are formed on the surface of a chip (20) of the other conductivity type. An emitter region (24) is contained within the base region, (23) and an auxiliary region (23a) of the one conductivity type is laterally spaced from and surrounding the base region (23). Anode and cathode electrodes (41,40) are connected to the anode and emitter regions respectively, and a LED illuminates the surface to turn on the thyristor. <IMAGE>

Description

GB2174242A 1 SPECIFICATION imum temperature rise of about 1 100C., thus

limiting their current-handling capability. Finally, A.C. solid state relay circuit and thyristor solid state relays of the past have been rela structure tively expensive in view of the need for large 70 numbers of discrete components and large

BACKGROUND OF THE INVENTION housings.

This invention relates to a.c. solid state relays, Optically fired lateral thyristor devices which and to a novel thyristor which can be used in can be used alone or in such relays are also a solid state relay. known. Such devices, however, are expensive Solid state a.c. relays are well known. Such 75 and have a relatively high forward drop and relays, with optical isolation between input are relatively insensitive to input radiation. One and output, are also well known. In existing thyristor device of this type is shown, for devices, many discrete components are com- example, in U.S. Patent 4,355, 320, dated Oc monly required to complete the a.c. circuit. tober 19, 1982, entitiled LIGHT-CONTROLLED Thus, it may take thirty or more discrete thy- 80 TRANSISTOR.

ristors, transistors, resistors and capacitors to A first aspect of the present invention pro manufacture a single device. Attempts have vides a solid state a.c. relay comprising first been made to integrate the various parts of and second thyristors each having respective the entire solid state relay, but these have anode and cathode electrodes and a respec met only limited success due to the mix of 85 tive gate circuit, characterized in that each of high voltage and high power components. said thyristors is formed in separate respective Solid state relays made in the past have first and second semiconductor chips and is also employed zero voltage crossing circuits of the lateral conductivity type, wherein said to ensure turn on of the thyristor only when anode and cathode electrodes of each of said the a.c. voltage is within some small "win- 90 thyristors are on the same first surface of dow". These circuits have also been relatively their said first and second chips respectively; complex and difficult to integrate into the main said first surface of said first and second power chip. Thus, zero cross firing circuits chips being optically sensitive, whereby said have required the use of a discrete resistor first and second chips can be switched to connected across the power terminals. These 95 conduct current by illuminating said one sur resistors have not been easily integrated into face; said solid state relay further comprising a single chip because of the difficulty of form- a light emitting diode arranged to illuminate ing this resistor on the chip surface. said first surfaces upon its energization; a pair It has also been difficult to provide so-called of a.c. terminals; said anode and cathode "snubberless" operation for the relay under 100 electrodes of said first and second thyristors any inductive or resistive load. Thus, while connected to said pair of a. c. terminals and in solid state relays may operate well under re- anti-parallel relation with one another; a pair of sistive or slightly inductive loads, they may control terminals insulated from said a.c. ter tend to "half wave" or "chatter", which is a minals and connected to said light emitting condition wherein a relay turns on only for 105 diode; and first and second control circuits one-half of a cycle, under a highly inductive connected to said gate circuits of said first load. This has occurred in the past because and second thyristors respectively for clamp the relays are commonly provided with condi- ing said first and second gate circuits respec tioning circuits for suppressing fast turn on of tively to prevent firing of said first and second the circuit under some fast transient or high 110 thyristors when the voltage between said pair dV/dt condition. When the device is operated of a.c. terminals exceeds a given value and for under a very highly inductive load, however, clamping said first and second gate circuits in voltage transients are commonly generated re- response to transient pulses having a dV/dt petitively during device turn on. When the sig- greater than a given value.

nal conditioning circuit misinterprets this as a 115 A second aspect of the present invention transient signal, it shuts off the power output provides a lateral thyristor which is optically during a particular half phase of the operation. fired, comprising a chip of semiconductor ma The circuit will then appear to turn to normal terial having a junctionreceiving surface of one during the next half wave and the relay will conductivity type; an anode region of the turn on. This condition repeats so that the 120 other conductivity type and a base region of relay turns on only during one or another of said other conductivity type each formed into the half waves of the full cycle. To avoid this said surface and laterally spaced from one condition, relays of the past have been another; characterized by an emitter region of formed with reduced firing sensitivity and this said one conductivity type formed in and to has required reduction of sensitivity to optical 125 tally contained within said base region and ex firing. tending therein from said surface; anode and Since prior art relays have been relatively cathode electrodes connected to said anode complex, they have required substantial vol- and emitter regions respectively and radiation ume for their housings. Moreover, solid state means for illuminating at least a portion of relays of the past have been limited to a max- 130 said surface for turning on said thyristor; and 2 GB2174242A 2 an auxiliary region of said other conductivity minated. The capacitive divider is arranged so type formed in said surface and laterally that the control transistor is normally turned spaced from and surrounding said base re- on for all absolute voltages across the main gion. device greater than some relatively small win- A third aspect of the present invention pro- 70 dow value. Thus, the power thyristor cannot vides an optically triggered thyristor compris- turn on outside of this small window value or ing a semiconductor substrate of one of the zero cross value.

conductivity types, characterized in that said The novel capacitance divider, in combina substrate has at least first and second tion with the control transistor will now oper- spaced, parallel base regions of the other of 75 ate to suppress both fast transients and still the conductivity types extending into the sur- allow the device to function under its normal face of said substrate; respective emitter re- load condition. Thus, voltage transients which gions of said one of said conductivity types are generated repetitively during device turn extending into said surface of at least first and on under highly inductive load conditions will second parallel base regions and being com- 80 not be misinterpreted as a fast transient and pletely contained within their said respective the power thyristor chip will be permitted to base regions; respective- elongated anode re- turn on in its normal manner under even highly gions of said other of said conductivity types inductive loads.

extending into said substrate and disposed on The novel signal conditioner of the invention opposite elongated sides of and laterally 85 also allows for substantial improvement in op spaced from each of said parallel base regions tical sensitivity of the device without misfiring.

and extending at least coextensively with said Note that currently available optically isolated base regions; an anode contact connected to triac drivers and the like are always limited said anode regions; a cathode contact to said either in dV/dt capability or optical sensitivity emitter regions; and radiation generating 90 because of their inability to separate low level means genergizable to generate minority carri- command signals from transients.

ers in said substrate which act as a base A novel housing is provided for the two drive to turn on said thyristor when appropri- chip arrangement in which the two chips are ate bias voltages are applied to said anode easily and inexpensively connected in parallel and cathode contacts. 95 with one another and are protected from the outer environment. An alumina substrate or BRIEF DESCRIPTION OF THE INVENTION other suitable heat conductive but electrically

In accordance with the present invention, insulative substrate is provided with suitable two identical and novel thyristor power chips conductive patterns thereon for receiving the are provided for an a.c. relay wherein the 100 various chips of the switch and for connecting power chips are both of lateral construction the chip electrodes to suitable output leads.

with both cathode and anode electrodes at The two identical thyristor chips which are to one surface of each device and wherein each be connected in anti-parallel are symmetrically of the chips can be optically fired and has an secured to respective conductive pads on the optically sensitive upper surface which, when 105 substrate and are in alignment with one aother illuminated, will permit the device to become and with the terminal ends of two conductive conductive between its anode and cathode patterns on the substrate. Two continuous electrodes. wires are then stitch-bonded to the thyristor The gate circuit of each of the thyristors is pads and conductive leads in such a manner connected to a novel control circuit, formed 110 that one lead wire is electrically connected to either of discrete components or of compo- the anode pad of one chip, the cathode pad nents merged within the body of the semicon- of the second chip and one of the conductive ductor material forming the thyristor. The conpatterns which is connected to an input a.c.

trol circuit is operable to prevent turn on, lead. The other wire is similarly connected to even though the surface is illuminated, when 115 the other electrodes and conductive pattern to the voltage across the device exceeds a value conduct the thyristors; in anti-parallel.

greater than some predetermined window A small LED chip is also connected to the value, or when high dV/dt transients appear alumina substrate at the same time the power across the device. This control circuit includes chips are connected. The LED is connected a clamping transistor which can be turned on 120 appropriately to two input leads which are to clamp the gate of its respective thyristor well insulated from the a.c. output leads.

and a capacitive divider circuit connected A plastic cap covered by a white illumina across the main power electrodes. The capaci- tion reflecting material then is secured to the tive divider applies a control signal to the con- substrate and covers the region of the sub trol transistor. 125 strate containing the LED and the two power One of the capacitors of the capacitive di- chips. The cap may consist of a transparent vider includes the distributed capacitance of silicone which encloses and encapsulates the the control transistor. So long as the control surfaces of the chips and their inter-connect transistor is on, its respective power thyristor ing leads with a white silicone painted outer cannot turn on even though its surface is illu- 130 surface.

3 GB2174242A 3 If the control circuit for the power transistor obtained when using a surface concentration is carried out in discrete form, the discrete of 1 X 1020 to 6 X 1020 phosphorus ions/cc components may also be suitably connected at the emitter surface.

to this substrate. Preferably, however, these Finally, in making the surface contacts for components are integrated into the individual 70 the device, thin lines of relatively thick alumi power chips so that the entire solid state re- num are used to expose a maximum amount lay will consist of two power chips and their of silicon.

controls, the LED chip and the various support structures previously described. BRIEF DESCRIPTION OF THE DRA WINGS

Each thyristor of the relay has a novel struc- 75 Figure 1 is a crosssectional view of the ture and is formed in a single chip which has junction pattern of a single lateral thyristor a low forward voltage drop and a relatively which employs some features of the present high current capacity and is highly sensitive to invention.

input radiation so that a noncritical LED trig- Figure 2 is a plan view of the metallizing gering source can be provided to cause the 80 pattern on the surface of a single chip which thyristor to conduct. The relay circuit control employs the lateral thyristor of the present components including parallel connected con- invention.

trol MOSFETs, a resistor, zener diode and Figure 3 is a plan view of the silicon surface capacitor may also be provided in the single of the chip of Fig. 2 and shows the junction chip. The relay control components permit 85 patterns which come to the device surface.

thyristor turn-on only when the anode-to-cath- Figure 4 is an enlarged view of one of the ode voltage is less than a given value. More- parallel elements or loops of Fig. 3.

over, false turn-on due to a transient is pre- Figure 5 is a crosssectional view of Fig. 3 vented under all circuit conditions, if the LED taken across the section line 5-5 in Fig. 3.

is off. 90 Figure 6 is a cross-sectional view of Fig. 4 In accordance with the invention, a plurality taken across section line 6- 6 in Fig. 4.

of individual lateral thyristors, each of which Figure 7 is a crosssectional view of Fig. 3 may be optically fired, are connected in paraltaken across section line 7-7 in Fig. 3.

lel with one another within a single chip. Each Figure B is a crosssectional view of the lateral thyristor has a respective base with 95 polysilicon resistor which is shown in Fig. 3.

emitter elements formed in the base. A novel Figure 9 is a circuit diagram of the thyristor anode region consisting of a plurality of and its control circuit as produced by the spaced anode region fingers which envelope junction pattern and interconnections of the the end and two sides of each base make device of Figs. 2 through 8.

parallel connection of the elements easily pos- 100 Figure 10 is a circuit diagram of the novel sible. The thyristor base zone contains spaced a.c. relay of the present invention.

parallel emitter regions and the base zone is Figure 11 illustrates the two power thyristor surrounded by an auxiliary P region. An aux- chips of Fig. 10 and an LED mounted on a iliary region for a lateral optically triggered thy- ceramic substrate.

ristor is shown in US Patent 4355320. The 105 Figure 12 is a side view of Fig. 11.

novel auxiliary regions of the invention, how- Figure 13 is an elevation view of the as ever, loop around and fully enclose the indivi- sembly of Fig. 11 with an enclosing cap for dual base regions and are resistively con- enclosing the LED and power chips.

nected to a conductive polysilicon field plate Figure 14 is a top view of Fig. 13.

which is solidly connected to the metallic 110 cathode electrode. DETAILED DESCRIPTION OF THE DRAWINGS

The novel resistive connection may be ob- Referring first to Fig. 1, there is shown tained by making spaced connections from the therein in cross-section the junction pattern field plate to the auxiliary region. By using a and metallizing of a lateral thyristor chip which resistive connection in this manner, more car- 115 is manufactured in accordance with some of riers which are injected from the anode region the principles of the present invention. The and which travel laterally toward the emitter chip containing the lateral thyristor of Fig. 1 will reach the emitter. This improves the for- can have ' any desired size and configuration, ward drop of the device by a significant and is a chip of monocrystalline silicon.

amount (for example, from 1.45 volts to 1.15 120 The various junctions shown in Fig. 1 are volts) which significantly decreases power dis- formed in N(- -) layer 20. Layer 20 may sipation during the operation of the device. have a resistivity of about 20 ohm-centi In accordance with further features of the meters. Spaced P type regions 21, 22 and 23 invention, the anode region may be relatively are formed in the upper surface of chip 20 by heavily doped in comparison to the emitter 125 any desired process. A further P type region doping to further reduce the forward drop. 23a, which is inactive, may enclose the peri The emitter doping concentration at the emit- phery of region 23. Regions 21, 22, 23 and ter region surface is also controlled to a point 23a can be borondiffused regions of sufficient found to be optimum for improving injection concentration so that the sheet resistance of efficiency. In particular, very good operation is 130the P regions will be about 1,600 ohms per 4 GB2174242A 4 square at the chip surface. They may also be obtained by applying radiation to the upper formed, for example, by an ion implantation surface of the device which will generate carri and drive-diffusion process employing ers (holes) in the body 20. These holes drift 5X10+13 boron atoms per square centimeter to region 23 and are collected by-the emitter dose so that it is relatively lightly doped. Re70 junction between regions 23 and 24 to act as gion 21 is preferably more heavily doped than a base drive to turn the device on. A suitable the other P regions. Regions 21, 22, 23 and source of radiation can be the schematically 23a may have the same depth of approxi- illustrated LED 45 which is arranged to illumi mately 4 microns. P type region 23 contains nate the surface of the device.

an N(+) region 24 to complete the laterally 75 It has been found that a device employing spaced junctions of the lateral thyristor. the structure of Fig. 1 is capable of blocking The facing edges of regions 21 and 23 from 400 to 500 volts. During forward con should be as close together as possible while duction, the forward voltage drop was about still being able to block a selected voltage. In 1.15 Volts at about 1.5 amperes forward cur- the present application, the device preferably 80 rent.

blocks about 400 to 500 volts and a spacing The arrangement of the lateral thyristor of of 105 microns is used. Fig. 1 can be implemented in any number of Region 21 is the anode region, region 23 is desired geometries. A particularly efficient the gate or base region, region 24 is the emitgeometry is that disclosed in Figs. 2 to 9 ter or cathode region while the N(--) body 85 which are now described and show an ar is the main blocking region of the thyristor rangement in which a plurality of devices, shown in Fig. 1. Region 22 is a known type such as that of Fig. 1, are connected in paral of floating guard region which permits an in- lel.

crease in the blocking voltage between junc- Referring to Figs. 2 and 3, there is shown a tions 21 and 23 to as high as 400 to 500 90 plan view of a single chip containing a single volts without danger of breakdown at the sur- thyristor device and its control circuit compo face of the chip. nents. The chip of Figs. 2 and 3 is one of a The upper chip surface is covered by a thin large number of chips on a common wafer silicon dioxide layer 30 which can have a which are separated after common processing thickness, for example, of about 1 micron. Po- 95 is completed. The chip is shown in Fig. 2 lysilicon field plates 31 and 32 are formed after metallizing of the cathode and anode ter atop the oxide layer 30 as shown, using con- minal electrodes. The junction patterns on the ventional polysilicon deposition and masking chip surface are shown in Fig. 3. As will be techniques. The entire upper surface of chip, described in detail, a plurality of separate thy- including the polysilicon field plates, and the 100 ristor elements are connected in parallel, using oxide 30 is covered with a conventional novel junction patterns for the anode, base glassy, phosphorus doped silicon dioxide layer and emitter regions (Figs. 3 and 4) which ex 35. Spaced gaps 36 and 37 of known struc- tend along a path hereinafter designated either ture may be placed on either side of the float- a serpentine or interdigitated path, so that ing guard region 22 to prevent lateral polariza- 105 they will have the longest possible length, tion effects within the phosphorus doped ox- thus permitting a high current capacity for the ide layer 35 from interfering with the field dis- device.

tribution at the surface of region 20 adjacent In the embodiment of Figs. 2 and 3, the the floating guard region 22. chip may have a width of 82 mils, a length of Suitable openings are formed in the oxide 110 113 mils and will have a forward current-car layers 30 and 35 above emitter region 24 and rying rating of 1.5 amperes with a 1.15 volts anode region 21 to permit contact to the vari- forward voltage drop. The bisymmetrical ous regions and field plates. Thus, aluminum blocking voltage capability of the device is cathode electrode 40 and anode electrode 41 about 500 volts peak. Therefore, the thyristor are applied to emitter region 24 and anode 115 chip of the invention can be employed with an region 21, respectively, as shown. Other identical anti-parallel connected thyristor chip openings which are formed in the oxide layer and used in a solid state relay for controlling permit connection from the cathode 40 to an a.c. circuit which might have an RMS vol the field plate 31 and from the anode 41 to tage of up to 280 volts.

the field plate 32. Both cathode electrode 40 120 The basic metallizing pattern of Fig. 2 em and anode electrode 41 are relatively thin and ploys the cathode 50 and anode 51 confi can, for example, be about 4 microns in thick- gured as shown. A control circuit, not shown ness. in Fig. 2, is contained within the chip body.

Region 23a is preferably resistively con- The circuit is shown in Fig. 9. Metallized sec nected to the cathode 40. Thus, region 23a 125 tions 60 and 61 in Fig. 3 are electrodes of can be connected to cathode 40 only at two respective capacitors shown in Fig. 9.

spaced points along their peripheries. Capacitor 60 will be described later in connec The lateral thyristor of Fig. 1 is turned on tion with Fig. 7.

by injection of carriers from emitter region 24 The capacitors including electrodes 60 and into gate region 23. Suitable injection can be 130 61 are connected in parallel as shown in Fig.

GB2174242A 5 9 and are connected between the anodes of Inactive region 82 has loop sections 82a, thyristors; 64a, 64b, 64c and 64d and gates 82b, 82c and 82d (Fig. 3), which enclose the of control MOSFETS 76, 77, 78 and 79, re- bases of four respective thyristors; as will be spectively. Thyristors 64a, 64b, 64c and 64d later described and serve the purpose of aux are in parallel and have common cathodes and 70 iliary ring 23a of Fig. 1. Loop section 82b is anodes, shown as cathode 50 and anode 51 shown in Fig. 6.

in Figs. 2 and 6. Four equally spaced, elongated P type base Also provided integrally with the chip of Fig. regions 83a, 83b, 83c and 83d (Figs. 3, 4 3 is a 100 K resistor 70 which is formed of and 6) are also formed in region 80. These polysilicon and is electrically connected be- 75 base regions correspond to the base region tween the cathodes and gates of each of thy- 23 in Fig. 1. Base region 83b is shown in ristors 64a, 64b, 64c and 64d. The detailed enlarged detail in Fig. 4. Note that the base structure of resistor 70 will be later described regions 83a, 83b, 83c and 83d-are almost in connection with Fig. 8. fully enclosed by auxiliary ring loops 82a, 82b, Additionally provided and formed integrally 80 82c and 82d, respectively.

in the chip of Fig. 3 is a zener diode 71 A further P type region is formed, consist- which, as shown in Fig. 9, is connected in ing of a floating guard ring 84, shown in Figs.

series with capacitors 60 and 61 between the 3 to 6. Guard ring 84 follows a sinuous path anode and cathode terminals 51 and 50 of and divides in half the N(- -) region 80 which the thyristors shown. There is also shown in 85 reaches the device surface in Figs. 3 and 4.

Fig. 9 an inherent distributed capacitance 75 Each of the thyristor bases 83a, 83b, 83c in parallel with zener diode 71. and 83d receives two parallel N+ emitter re The zener diode 71 may be formed in the gions 85a-85b, 86a-86b, 87a-87b and inactive P region 82 and can consist of the 88a-88b, respectively (Figs. 3, 4 and 6).

N+ region 71a shown in Fig. 3. One zener 90 Emitter regions 86a and 86b are shown in terminal 71b may be formed directly atop the enlarged detail in Fig. 4.

N+ region 71a, and the other terminal may From the above, it will be seen that the be formed of a metal contact 7 1 c which is junction pattern in Fig. 3 forms the basis for connected to the cathode electrode. the four thyristor elements 64a, 64b, 64c and A plurality of control MOSFETs 76, 77, 78 95 64d of Fig. 9 and makes possible the parallel and 79, shown in Fig. 9, and which will be connection of the devices.

later described in Figs. 3 and 4, are also con- The thyristor element defining thyristor 64b tained on the chip and operate with thyristors; is shown in Figs. 4 and 6 and is now de 64a, 64b, 64c and 64d, respectively. Each scribed. The thyristor base consists of active control MOSFET is disposed immediately adja- 100 P region 83b containing parallel emitter re cent its respective main thyristor element so gions 86a and 86b. The thyristor anode re that operational delay times are limited and gion is comprised of the anode region fingers circuit symmetry is assured. 81a and 81b which symmetrically enclose the The circuit of Fig. 9 is implemented in a base 83b. The thyristor body consists of the novel way, as will now be described in con- 105 N(--) region 80. The base is also almost nection with Figs. 2 to 8. Note that, while the completely surrounded by auxiliary loop region embodiment disclosed herein uses four parallel 82b which has the benefit previously de thyristor elements 64a, 64b, 64c and 64d, scribed of increasing collection efficiency. The any desired number of elements could be novel junction pattern also makes possible the used. 110 parallel connection of the plural thyristors on Referring to Figs. 3 to 6, the entire inte- the chip.

grated device is formed in a relatively high In forming the junction pattern shown, the resistance N(--) substrate 80 which can lateral spacing between the confronting edges have a resistivity of about 20 ohm-centi- of base regions 83a, 83b, 83c and 83d and meters. 115 the respective adjacent anode fingers 81a, A number of individual P type regions are 8 1 b and 8 1 c (and the outer anode legs 8 1 d formed in substrate 80 by any desired pro- and 8 1 e) was about 105 microns. The depth cess. The first of these is the P+ type anode of each of the P type regions was about 4 region 81 which corresponds to anode region microns. Each of base regions 83a, 83b, 83c 21 in Fig. 1. As shown in Figs. 3 and 4, 120 and 83d had a length of about 40 mils and a anode region 81 has a main body section width of about 75 microns.

from which three parallel fingers 81a, 81b and During the formation of the various P re 8 1 c extend. Figs. 8 1 a and 81 b are shown in gions, a further P type guard ring- 90 (Figs. 2 more detail in Figs. 4 and 6. A rectangular and 5) is preferably formed around the peri anode region frame having legs 81d, 81e and 125 phery of the chip. Ring 90 is spaced from the 81f surrounds the periphery of the chip as outer periphery of the P+ anode 81e by shown in Fig. 3. Legs 8 1 d and 8 1 e are seen about 38 microns.

in Fig. 5. Also during the formation of the various The second P type region shown in Figs. 3 junctions, and as shown in Figs. 3 and 4, to 8 is "inactive" P type auxiliary region 82. 130 N(+) source and drain regions 9la-91b, 6 GB2174242A 6 92a-92b, 93a-93b and 94a-94b are formed 111 which may have any desired thickness.

for the control MOSFETs 76, 77, 78 and 79, Novel polysilicon field plates 112 and 113 respectively, in Fig. 9. These are formed in are deposited on the thermal oxide 110. Note the enlarged inactive P type region 82. As isthat all polysilicon strips or layers may be de shown in Fig. 4 for the case of control MOS- 70 posited in any desired sequence.

FET 77, a suitable gate oxide having a thick- Field plate 112 is an elongated, sinuous ness of about 0. 1 micron, and a polysilicon plate which is disposed atop and follows the gate electrode (not shown) are arranged over path of the junction between P(+) anode re the gap between regions 92a and 92b. An gion 81 and N(--) region 80. Field plate 113 extremely thin oxide can be used for the con- 75 similarly is an elongated, sinuous plate which trol MOSFETs because the gate is at the pofollows a path parallel to that of plate 112 tential of the node between capacitors 60 and and overlies the junction between auxiliary re 61 and capacitor 75. Thus, the potential dif- gion 82 and the outwardly disposed N(--) ference between the control MOSFET gates region 80.

and the cathode of the main thyristors is very 80 At the time field plates 112 and 113 are low. Therefore, transistors 76 to 79 can be deposited, an outer equipotential ring 115 very high gain transistors. (Fig. 5) may also be disposed around the The source region 92a is connected to the outer periphery of the chip. Ring 115 is con inactive base, while drain region 92b is electri- nected to substrate 80 in the usual manner.

cally connected to the thyristor base region 85 Each of field plates 112 and 113 and ring

83b through the conductive strip 95 (Figs. 4 115 may have a width of about 20 microns.

and 6). Strip 95 is preferably metal. A similar The guard ring region 84 may have a width of arrangement is provided for each of the thyris- about 8 microns and is centrally located be tor elements with a conductive strip connect- tween the opposing edges of plates 112 and ing bases 83a, 83b, 83c and 83d to control 90 113 which edges are about 44 microns apart.

MOSFET source electrodes 91b, 92b, 93b Similarly, P type region 90 (Fig. 5) is centrally and 94b, respectively. The conductive strips located between plates 112 and 115, the are then all connected together as by a poly- edges of which are about 44 microns apart.

silicon connection strip, partly schematically The anode electrode 51 is then formed as shown in Fig. 4 by dotted line 95a. 95 shown and engages the P type anode region Capacitors 60 and 61 are also implemented 81, as shown in Figs. 2 and 6. Cathode elec in the inactive P region 82 as shown in Fig. 7 trode 50 is also formed as shown in Figs. 2, for capacitor 60. Thus, capacitor 60 is formed 5 and 6.

by depositing a metal layer atop an area of The lateral thyristor of Figs. 2 through 9 is the P type base 82 which is isolated from the 100 turned on by radiation from LED 45 (Figs. 6 chip by causing a rectangular ring 96 having and 9) which is arranged to illuminate the ex appropriately radiused corners and of the posed surface of the chip. Since the chip is N(--) material 80 to reach the chip surface. extremely sensitive, the LED 45 is not critical Note that the metal layer 60 overlies thermal in size, output or location.

oxide layer 97 to form a field plate. 105 The patterns described in Figs. 2 through 8

The resistor 70 is also implemented in inac- will form the electrical circuit shown in Fig. 9 tive P type region 82 as shown in Fig. 8. and define one-half of the solid state relay Thus, in Fig. 8, a polysilicon strip 70a is de- which is later described. Turn-on of the thyris posited atop oxide layer 97 and is overcoated tor is clamped against firing by transients with a deposited silicon dioxide layer 98. 110 when no light is present. Voltage division ob Therefore, resistor 70 is formed of a resistive tained between capacitors 60-61 and 75 de layer which is completely insulated from the fines the voltage window at which turn-on is chip body by insulation layer 97. The resistor possible. Significantly, the capacitive voltage is thus an ideal resistor which will be free of divider permits a very low gate voltage for the parasitic interaction with other circuit compo- 115 control transistors and very low function leak nents. Openings are then formed in layer 98 age current. The capacitors also provide shi and resistor terminal connections 99 and 100 elding from input light or radiation.

are made to the resistor. These terminals are The novel lateral thyristor shown in Figs. 2 appropriately connected to the thryistor cath- to 8 can be made by any desired process.

ode and to the source electrodes of control 120 The device provides a maximum effective cur MOSFETs 76, 77, 78 and 79. rent carrying area between the anode region The upper surface of the chip shown in 81 and the base region 83 for a given chip Figs. 5 and 6 is further processed to have the area. The pattern configuration is also ar desired- metallizing. Before metallizing, an ap- ranged to reduce forward voltage drop to as propriate thermal oxide 110 exists in place, or 125 large a degree as possible while maintaining is applied to the device surface to a thickness high light sensitivity so that the LED 45 is not of about 1 micron. After conventional masking critical.

and etching steps, metals are applied in the A significant feature of the novel geometry necessary sequence. The upper surface is is the novel P type auxiliary regions 82a, 82b, then covered with a deposited oxide coating 130 82c and 82d which loop around each base 7 GB2174242A 7 region 83a, 83b, 83c and 83d, respectively. Referring next to Fig. 10, there is shown a This geometry makes it possible to connect circuit diagram of the full a. c. relay of the together all N+ cathodes. Thus, regions 82a, present invention. The relay of Fig. 10 em 82b, 82c and 82d and main region 82 are ploys two identical thyristors 210 and 211 constant potential regions in which all thyristor 70 connected in anti- parallel relationship with re- bases are embedded. By spreading out into spect to one another between main a.c.

region 82 at the ends of the bases, a large power terminals 212 and 213, respectively.

area is made available for metallizing to con- Schematically illustrated thyristors 210 and nect regions in parallel. 211 are each of the type shown in Figs. 1 to Preferably, a resistive connection is made 75 9 and are provided with gate circuits schema from the cathode 50 to the loops 82a, 82b, tically illustrated by the gates 216 and 217, 82c and 82d as by using spaced dot type respectively. Thyristor chip 210 has, on its connections, schematically shown as connec- upper surface, anode electrode pad 220 and tion points 120 in Fig. 4, extending along the cathode electrode pad 221, while chip 211 length of the P type loop 82b. The connection 80 has an identical anode pad 222 and cathode can also be made by a short contact strip pad 223 (Fig. 11).

121, shown in Fig. 4. By using a resistive Thyristors 210 and 211 are electrically con connection between the auxiliary loops and nected together so that anode 220 of one is the cathode electrode 50, and as shown in connected to cathode 223 of the other and Figs. 4 and 6, carriers which are injected from 85 so that anode 222 of one is connected to the anode regions 81a and 81b during turn-on cathode 221 of the other. Thus, the devices of the device will tend to move to the emitter are connected in the anti- parallel relationship regions 86a and 86b rather than being col- shown in Fig. 10.

lected by the auxiliary regions 82a, 82b, 83c A single LED 225, which can be a conven- and 82d. This increases the collection effici- 90 tional commercially available gallium aluminum ency of the emitter and substantially de- arsenide device having terminals 226 and 227 creases the forward voltage drop of the de- in Fig. 10, is arranged as will be later de vice. By way of example, by making the resis- scribed to flood the photosensitive surfaces of tive connection between auxiliary loop regions chips 210 and 211 in order to permit turn on and cathode 50, the forward voltage drop at 95 of the chips if other circuit conditions are ap 1.5 amperes forward current was reduced propriate. Good electrical isolation is provided from about 1.45 volts to about 1.15 volts. between the input circuit connected to termi This results in a significant reduction of power nals 226 and 227 and the a.c. power circuit dissipation during forward conduction. connected to terminals 212 and 213.

During processing of the device of Figs. 3 100 Identical control circuits such as those de to 6, the anode region 81 and all its seg- scribed previously are provided for controlling ments are preferably heavily doped as com- the turn on of thyristors 2 10 and 211 respec pared to the doping of P type regions 82, 83 tively and include respective MOSFET transis and 84. By way of example, anode region 81 tors 230 and 231, zener diodes 232 and can be doped to the point where it has a 105 233, resistors 234 and 235 and capacitors resistivity of 50 ohms per square as com- 236 and 237. Capacitors 236 and 237, like pared to 1600 ohms per square for regions capacitors 60 and 61 of Fig. 9, serve as one 82, 83 and 84. This sets a high gain and thus component of respective capacitive dividers.

high light sensitivity for the inherent lateral The second component of the capacitive di transistor consisting of regions 81, 80 and 110 viders consists of the distributed capacitance 83. Furthermore, by more heavily doping the 238 and 239 of devices 230 and 231, re anode region, the forward voltage drop of the spectively. - device is reduced. The circuit components 230-239 could be A further important feature of the invention implemented as discrete components. Prefera- lies in the control of the doping of the emitter 115 bly, however, these circuit components are regions, such as regions 86 and 86b in Figs. implemented integrally with the semiconductor 3 and 6, so that the N type concentration at chips defining thyristors 2 10 and 211, as de the surface of the device is at an optimum scribed in connection with Figs. 1 to 9.

value of 1 X 1020 to 6X 102 phosphorus Transistors 230 and 231 are connected to ions/cc. This can be done as by diffusing 120 the gates 216 and 217 of thyristors 210 and phosphorus through a thin oxide during the 211, respectively. So long as transistors 230.

I Mrmation of the regions 86 or by control of and 231 conduct, or are on, the application of the various gas flows during the diffusion proillumination to the surfaces of devices 210 cess. By reducing the N type concentration at and 211 from LED 225 cannot turn on the the surface of regions 86, the injection effici- 125 device. Transistors 230 and 231 will turn on ency of the device is improved, thus further when their respective gates 240 and 241 are reducing the forward voltage drop and subappropriately charged to a suitable threshold stantially increasing the sensitivity of the de- voltage V, Thus, when the nodes 242 and vice to turn-on by photons from the source 243 reach the threshold turn on voltage of 45. 130 transistors 230 and 231, respectively, and if 8 GB2174242A 8 suitable drain to source voltage is provided, and LED 225 of Fig. 10. Referring first to the devices will conduct and clamp the re- Figs. 11 and 12, there is shown a ceramic spective gates 216 and 217 of thyristors 210 substrate support 260 which can be of alu and 211. mina but may be of any desired electrically The voltage at each of nodes 242 and 243, 70 insulative, thermally conductive material. By termed VO, will be way of example, the alumina slab 260 can have a thickness of 0.025 inch, a length of VO=V CP/(C,+C,). about 0.9 inch and a width of about 0.25 inch. A plurality of conductive patterns is In the above, 75 formed on one surface of substrate 260, in V., is the voltage across terminals 212 and cluding patterns 261 to 267. Each of these 213, patterns may be formed by gold plating onto CP is the capacitance of distributed capaci- the substrate where the gold plating has a tors 238 and 239, respectively, and thickness greater than about 150 microinches.

C, is the capacitance of capacitors 236 and 80 Each of thyristor chips 210 and 211 is then 237, respectively. suitably soldered or otherwise mounted down From the above, it will be seen that the onto conductive pads 265 and 264, respec voltage VO at nodes 242 or 243 will be tively, so as to be in good thermal contact greater than the threshold voltage of the tran- with the alumina body 260. Each of the chips sistors; 230 and 231 when the instantaneous 85 210 and 211 may have a size of approxi a.c. voltage between terminals 212 and 213 mately 82X 116 mils for a typically sized de is more positive, or is more negative than vice. The LED chip 225 is mounted down on some "window" value. Consequently, transis- one end of conductive pattern 262.

tors 230 and 231 clamp thyristors 210 and Chips 210 and 211 are so mounted that 211 when this window voltage is exceeded. 90 their anode and cathode leads are generally in This arrangement then permits a zero detec- line with one another and with one end of tion circuit without requiring a resistor extend- conductive patterns 266 and 267. Conse ing between the main terminals of the device. quently, one single wire 270 is conveniently The novel capacitive divider circuit is also used to electrically connect conductive pads useful in suppressing the firing of devices 210 95 223 of thyristor 211 and 220 of thyristor 210 and 211 due to fast rising pulses such as and the ends of conductive pattern 267. This transient noise or high dV/dt signals. Such can be done in a stitch- bonding process of high transient pulses will apply a suitably high relatively simple nature which lends itself to voltage across parasitic capacitances 238 and high speed automated techniques. Thus, a 239 that the transistors 230 and 231 respec100 bonding head is simply brought down onto tively turn on to clamp its respective thyristor. the wire 270 to electrically attach the wire at Thus, the thyristor will not be fired in re- the three spaced points corresponding to the sponse to fast rising transient pulses. location of pads 223, 220 and the end of For relatively slow rising pulses, such as conductor 267. In a similar manner, a second those produced by highly inductive loads con- 105 parallel wire 271 is stitch-bonded to conduc nected to the relay terminals 212 and 213, tive pads 222, 221 and the end of conductive these pulses will not be sufficiently fast to pattern 266. The stitch- bonding of conductor turn on the control transistors and unintention- 271 is shown in Figs. 11 and 12. Each of ally clamp the thyristors 2 10 and 211, conductive wires 270 and 271 may be of aluthereby to avoid single phasing or chattering 110 minum wire having a diameter of about 6 of the relay on highly inductive loads. Note mils.

also that this is accomplished without having As a result of the above, the power termi to reduce the optical sensitivity of the device. nals 212 and 213 are connected to the thyris Thus, the thyristors; 210 and 211 can be de- tor devices 2 10 and 211 in Fig. 11 in the signed to have optimum optical sensitivity for 115 manner shown in Fig. 10 with the thyristors; in firing without concern for false operation by anti-parallel relationship with respect to one relatively slow rising transients. another. Note that, since the chips 210 and A further advantage of the circuit shown in 211 also contain their respective control circu Fig. 10 is in the design of resistors 234 and its, the control circuits are also connected in 235. Thus, the temperature coefficient of the 120 place with this single stitch-bonding operation.

resistor is balanced against the sensitivity of The LED 225 is shown disposed atop one its respective thyristor. That is, if the resistor end of conductive pattern 262 which is con has the usual negative temperature coefficient, nected to lead 226. The other electrode of it is possible that the resistor would clamp its LED 225 is electrically connected to one end respective controlled rectifier when hot. How- 125 of conductive pattern 261 by the wire 280.

ever, by balancing the resistance temperature Wire 280 which may be an extending lead of coefficient of resistors 234 and 235, this the LED 225 is bonded to the end of conduc clamping action can be avoided. tive pattern 261 in any desired manner.

There is next described in Figs. 11 to 14 a Conductive pattern 261 is then electrically structure for housing the chips 210 and 211 130 connected to spaced conductive pattern 263 9 GB2174242A 9 either by the direct shorting connection of pended claims.

wire 281 or by a resistor 282. The selection

Claims (1)

1. of the shorting wire 281 or resistor 282 de- CLAIMS pends upon the power

   available at terminals /, 1. A lateral thyristor which is optically 226 and 227 and the characteristics of the 70 fired, comprising a chip of semiconductor ma LED 225. Wires 280 and 281 may be gold terial having a junction-receiving surface of one wires having diameters of about 1 mil. Note conductivity type; an anode region of the that the leads 212, 213, 226 and 227 extend other conductivity type and a base region of from the periphery of substrate 260, to define said other conductivity type each formed into a dual in-line pin type of package. 75 said surface and laterally spaced from one An optical cap or enclosure 291 is then another; characterized by an emitter region of placed atop the LED 225 and thyristors 210 said one conductivity type formed in and to and 211 and encloses the area shown in dot- tally contained within said base region and ex dash lines 290 in Fig. 11. The cap is shown tending therein from said surface; anode and in Figs. 13 and 14 as cap 291 and may be 80 cathode electrodes connected to said anode composed of any desired reflective plastic ma- and emitter regions respectively and radiation terial capable of withstanding the temperatures means for illuminating at least a portion of which are produced during device operation. A said surface for turning on said thyristor; and white colored plastic has been used. The plas- an auxiliary region of said other conductivity tic selected may be disulphone. The plastic 85 type formed in said surface and laterally preferably is white so that light will reflect spaced from and surrounding said base re from its interior surface. The cap can also gion.

   consist of a suitable silicone such as RTV 2. The thyristor of claim 1, which is further having titanium oxide powder mixed therein. characterized in that said anode region is more The titanium oxide powder uniquely remains in 90 heavily doped than said base region in order dispersion within the silicone. The mixture can to reduce the forward voltage drop and in be oven cured at about 1150C. for about 15 crease light sensitivity.

   minutes. 3. The thyristor of claim 1 or 2 which is The cap 291 has a sloped side 292 above further characterized in that said emitter region the location of the LED 225 with this sloped 95 is relatively lightly doped at said surface and edge tending to reflect light toward the region has a surface concentration which would be of the chips 2 10 and 211, as can be seen in obtained by diffusion through a thin oxide Fig. 13. layer.

   Cap 291 can be cemented in place, as 4. The thyristor of claims 1, 2 or 3 which shown in Fig. 13 or if desired, can be ar- 100 is further characterized in that a guard ring of ranged to overlap the substrate and snap over said other conductivity type is formed into the substrate edge. A clear silicone is then said surface and disposed between and ioaded into the interior of cap 292 through laterally spaced from said anode and base re the filling holes 293 and 294 of Figs. 13 and gions; said guard ring being out of contact 14 in order to completely encapsulate all of 105 with said cathode and anode electrodes and chips 225, 210, 211 and their connecting floating electrically with respect to said elec leads while permitting illumination from LED trodes.

   225 to reach the photosensitive surfaces of 5. The lateral thyristor of claim 4, which is thyristor chips 2 10 and 2 11. further characterized in that said emitter re After the cap 291 is secured in place and 110 gion, said base region and said guard ring are filled with silicone, the entire substrate 260 relatively thin regions having coextensive por along with the cap 291 can be mounted tions.

   within a lead frame which provides the leads 6. The thyristor of any of claims 1 to 5 212, 213, 226 and 227. The device may then which is further characterized in including be completely housed within a molded housmeans for resistively connecting said auxiliary ing which could, for example, be formed by a region to said cathode electrode.

   transfer molding process or the like. Leads 7. An optically triggered thyristor compris 212, 213, 226 and 227 will extend from the ing a semiconductor substrate of one of the package to define a dual in-line pin package of conductivity types, characterized in that said relatively small size and volume. The device, 120 substrate has at least first and second however, will be capable of a continuous cur- spaced, parallel base regions of the other of rent rating of 1-1/2 amperes or greater at the conductivity types extending into the sur voltages of 240 volts a.c. face of said substrate; respective emitter re Although the present invention has been de- gions of said one of said conductivity types scribed in connection with a preferred embodi- 125 extending into said surface of at least first and ment thereof, many variations and modifica- second parallel base regions and being com tions will now become apparent to those pletely contained within their said respective skilled in the art. It is preferred, therefore, that base regions; respective elongated anode re the present invention be limited not by the gions of said other of said conductivity types specific disclosure herein, but only by the apextending into said substrate and disposed on GB2174242A 10 opposite elongated sides of and laterally cathode contact; respective gate insulation spaced from each of said parallel base regions layers overlying said substrate in the space and extending at least coextensively with said between said source and drain regions of each base regions; an anode contact connected to of said control transistors; and gate electrode said anode regions; a cathode contact con- 70 means atop each of said gate insulation nected to said emitter regions; and radiation layers.

   generating means energizable to generate mi- 15. The thyristor of claim 14 which is nority carriers in said substrate which act as a characterized in further including first and sec base drive to turn on said thyristor when ap- ond capacitors formed on said substrate and propriate bias voltages are applied to said an- 75 connected in series between said anode and ode and cathode contacts. cathode contacts and defining a capacitive di 8. The thyristor of claim 7, which is further vider; said gate electrode means of said con characterized in that said anode regions con- trol transistors 6onnected to the node be sist of parallel elongated fingers extending tween said first and second capacitors; said from an enlarged area of said other of said 80 first and second capacitors being sized to ap conductivity types which extends into said ply only a small fraction of the voltage be substrate surface and which is disposed adja- tween said anode and cathode contacts be cent one of the ends of said base regions. tween said gate electrode means and said 9. The thyristor of claim 7 or 8 which is substrate, whereby said gate insulation layer further characterized in including a plurality of 85 can be very thin and of the order of 0. 1 mi auxiliary regions of said other of said conduc- cron.

   tivity types which extend into said substrate 16. The thyristor of claim 15 which is fur surface and which loop around and are - ther characterized in that said first capacitor is laterally spaced from the elongated sides and a distributed capacitance and said second one end of respective ones of said base re- 90 capacitor consists of a capacitor junction in gions and being disposed between their re- said substrate and a capacitor electrode atop spective bases and said elongated anode re- said capacitor junction; said capacitor elec gions associated therewith. trode connected to said anode contact.

   10. The thyristor of claim 9, which is fur- 17. The thyristor of claim 16 which is fur ther characterized in that said plurality of aux- 95 ther characterized in including zener diode Mary regions extend from an enlarged region means formed in said substrate and connected of said other of said conductivity types which between said node between said first and is disposed adjacent one end of said base second capacitors and said cathode electrode.

   regions. 18. The thyristor of any of claims 7 to 13 11. The thyristor of claim 7 which is fur- 100 which is further characterized in including inte ther characterized in that said elongated anode gral resistor means connected across said regions and said plurality of base regions are source and drain regions of each of said con separated from one another by a continuous, trol transistors; said resistor means including a elongated, serpentine strip of said material of strip of polysilicon deposited atop a given re- said one of the conductivity types. 105 gion of said substrate; a layer of silicon diox 12. The thyristor of claim 11 which is fur- ide disposed between said given region of ther characterized in including a guard ring of said substrate and said strip of polysilicon, said other of the conductivity types which is whereby said resistor is electrically isolated disposed centrally of and is coextensive with from parasitic currents in said substrate; and said elongated serpentine strip and which ex- 110 first and second terminals extending from tends into said substrate surface. spaced points on said polysilicon strip; said 13. The thyristor of claim 11 or 12 which first terminal connected to each of said con is further characterized in including first and tact means which are connected to said second field plates which are spaced from one bases; said second terminal connected to said another and are disposed above and are coex- 115 cathode contact respectively.

   tensive with the opposite edges of said elon- 19. An optically triggerable lateral thyristor gated serpentine strip. substantially as hereinbefore described with 14. The thyristor of any of claims 7 to 13 reference to Fig. 1 of the accompanying draw which is ther characterized in including a re- ings.

   spective control transistor for each of said at 120 20. An optically triggerable lateral thyristor least first and second base regions; each of subtantially as hereinbefore described with ref said control transistors comprising spaced erence to Figs. 2 to 9 of the accompanying source and drain region s extending into said drawings.

   surface of said substrate and laterally spaced 21. A solid state a.c. relay comprising first from their respective said base regions; and 125 and second thyristors each having respective contact means supported on said substrate anode and cathode electrodes and a respec and electrically connecting each of said base tive gate circuit, characterized in that each of regions to said drain region of their respective said thyristors is formed in separate respective control transistor; said drain regions of each first and second semiconductor chips and is of said control transistors connected to said 130 of the lateral conductivity type, wherein said GB2174242A 11 anode and cathode electrodes of each of said 24. The solid state relay of claim 22 or thyristors are on the same first surface of 23, which is further characterized in including their said first and second chips respectively; first and second resistors connected between said first surface of said first and second said gate circuit of said first and second thy chips being optically sensitive, whereby said 70 ristors respectively to the anode electrode of first and second chips can be switched to said first and second thyristors respectively.

   conduct current by illuminating said one sur- 25. The solid state relay of claim 22,23 or face; said solid state relay further comprising 24 wherein said first and second transistors a light emitting diode arranged to illuminate are metal oxide semiconductor field effect said first surfaces upon its energization; a pair 75 transistors and wherein said transistor control of a.c. terminals; said anode and cathode circuits include the gate circuit of said transis electrodes of said first and second thyristors tors.

   connected to said pair of a.c. terminals and in 26. The solid state relay of claim 25, anti-parallel relation with one another; a pair of which is further characterized in that said sec control terminals insulated from said a.c. ter- 80 ond capacitor of each of said first and second minals and connected to said light emitting capacitor dividers is the distributed capaci diode; and first and second control circuits tance of said first and second transistors re connected to said gate circuits of said first spectively.

   and second thyristors respectively for clamp- 27. The solid state relay of claims 21 to ing said first and second gate circuits respec- 85 26, which further includes an electrically insu tively to prevent firing of said first and second lative but thermally conductive ceramic sub thyristors when the voltage between said pair strate for mounting said first and second chips of a.c. terminals exceeds a given value and for and said light emitting diode; said first and clamping said first and second gate circuits in second chips and said light emitting diode be response to transient pulses having a dV/dt 90 ing fixed to the same surface of said substrate greater than a given value, and spaced from one another; said optically 22. The solid state relay of claim 2 1, sensitive surfaces of said first and second wherein said first and second control circuits chips facing away from said substrate; said include first and second control transistors re- light emitting diode being in a position which spectively, each having an output circuit and a 95 enables illumination of said first and second transistor control circuit operable to switch its chips by reflection of its light output from respective control circuit between a conduc- reflecting surfaces.

   tive and a non-conductive condition; and fur- 28. The solid state relay of any of claims ther comprising first and second capacitor di- 21 to 27 which is further characterized in that viders; said first and second transistor output 100 said first surface of each chip constitutes a circuits connected between said gate circuit junction-receiving surface of one conductivity and said anode electrode of its respective one type; an anode region of the other conductiv of said first and second thyristors, whereby, ity type and a base region of said other con when said first or second transistor output ductivity type each formed into said surface circuit is conductive, the respective one of 105 and laterally spaced from one another; an said first or second thyristors cannot fire in emitter region of said one conductivity type response to illumination of its said first sur- formed in and totally contained within said face; said first and second capacitor dividers base region anq extending therein from said connected across said pair of a.c. terminals surface; said anode and cathode electrodes and having respective nodes between capack 110 connected to said anode and emitter regions tors connected to said control circuit of the respectively; said anode region being more respective control transistor, whereby the vol- heavily doped than said base region in order tage at said nodes renders its respective tran- to reduce forward voltage drop and increase sistor conductive so long as the voltage belight sensitivity.

   tween said pair of a.c. terminals exceeds a 115 29. The solid state relay of any of claims given value to prevent turn on of the respec- 21 to 27 which is further characterized in that tive one of said thyristors when the a.c. vol- said first surface of each chip constitutes a tage exceeds a given window voltage, and junction-receiving surface of one conductivity whereby fast rising transient pulses turn on type; an anode region of the other conductiv- said transistors for their duration to prevent 120 ity type and a base region of said other con turn on of said thyristors by transient high ductivity type each formed into said surface dV/dt pulses. and laterally spaced from one another; an 23. The solid state relay of claim 22, emitter region of said one conductivity type wherein said first and second control circuits formed in and totally contained within said are further characterized in including first and 125 base region and extending therein from said second zener diodes respectively connected surface; said anode and cathode electrodes from said nodes of said first and second connected to said anode and emitter regions capacitor dividers respectively to the anode respectively; said emitter region being rela electrodes of said first and second th-r:,;tors tively lightly doped at said surface to a level respectively. 130 which would be obtained by diffusion through 12 GB2174242A 12 a thin oxide layer in order to increase the radiation sensitivity of said lateral thyristor to turn on by radiation from said radiation means.

   30. The solid state relay of claim 28 or 29 which further includes a guard ring of said other conductivity type formed into said sur face and disposed between and laterally spaced from said anode and base regions; said guard ring being out of contact with said cathode and anode electrodes and floating electrically with respect to said electrodes.

   3 1. The solid state relay of any of claims 21 to 27 which is further characterized in that said first surface of each chip constitutes a junction-receiving surface of one conductivity type; an anode region of the other conductivity type and a base region of said other conductivity type each formed into said surface and laterally spaced from one another; an emitter region of said one conductivity type formed in and totally contained within said base region and extending therein from said surface; said anode and cathode electrodes connected to said anode and emitter regions respectively; and an auxiliary region of said other conductivity type formed in said surface and laterally spaced from and surrounding said base region.

   32. The solid state relay of any of claims 28 to 31 which is further characterized in that said base region has an elongated shape terminating at said surface; said emitter region comprising at least one elongated rectangular shape contained within said base region; said anode region having a digitated pattern, the fingers of which envelope said base region.

   33. The solid state relay of claim 31 which is further characterized in including means for resistively connecting said auxiliary region to said cathode electrode.

   Printed in the United Kingdom for Her Majesty's Stationery Office, Did 8818935. 1986, 4235 Published at The Patent Office, 25 Southampton Buildings. London, WC2A lAY, from which copies may be obtained.