KR900004197B1 - A.c. solid state relay circuit and structure - Google Patents

Abstract

The optically triggered lateral thyristor consists of a number of individual lateral thyristor elements connected in parallel. Each element has an active base region which contains a respective cathode region. Each of the base regions is carried in a common conductivity type body. Extending fingers of a continuous anode electrode partly enclose each individual base region to enable the parallel connection of the individual devices. The thyristor base and emitter zones are surrounded by an auxiliary P region which is resistively connected to a fieled plate and the cathode electrode to improve emitter collection efficiency. The cathode electrode is connected to spaced, parallel, generally rectangular emitter regions which are disposed in respective bases between loops of the cathod electrode.

Description

AC solid state relay circuit and thyristor structure

1 is a cross-sectional view of a single transverse thyristor junction pattern utilizing the characteristics of the present invention.

2 is a plan view of a metallization pattern on the surface of a single chip using the transverse thyristor of the present invention.

3 is a plan view of the silicon surface of the chip of FIG. 2 showing the bonding pattern serving as the device surface.

4 is an enlarged view showing one of parallel elements or loops of FIG.

5 is a cross-sectional view taken along line 5-5 of FIG.

6 is a cross-sectional view taken along line 6-6 of FIG.

7 is a cross-sectional view taken along line 7-7 of FIG.

8 is a cross-sectional view of the polysilicon resistor shown in FIG.

9 is a circuit diagram of a thyristors and control circuits thereof manufactured by joining patterns and internal connections of the apparatus of FIGS.

10 is a circuit diagram of a novel AC relay of the present invention.

FIG. 11 is a diagram showing an LED mounted on a ceramic substrate and a two-power thyristor chip of FIG. 10;

12 is a side view of FIG. .

FIG. 13 is a front view showing the assembly of FIG. 11 with an enclosing cap to surround the LED and the power chip. FIG.

14 is a top view of FIG. 13;

* Real names of symbols on the main parts of the drawings

20: N (-) layer 21, 22, 23: P-type region

24: N ⁺ region 30: oxide layer

31,32 polysilicon field board 35 silicon dioxide layer

40: cathode electrode 41: anode electrode

64a, 64b, 64c, 64d: Dyistor 71: Zener diode

76,77,78,79: MOSFET 80: substrate

81: P type anode area 82: P type auxiliary area

84,90: floating guard ring 95: strip

96: rectangle

The present invention relates to a novel thyristors that can be used for alternating solid and solid relays.

Solid flow relays are known. Relays with optical separation between the input and output are also known. In existing devices many separate components are typically required to have an alternating current circuit. As a result, more than 30 separate thyristors, transistors, resistors, and capacitors are required to manufacture a single device. Attempts have been made to integrate various components of the entire solid state relay, but with very limited success due to high voltage and high power components. Solid-state relays made in the past employ zero voltage crossing circuits to turn on the thyristor only when it is in a "window" where the AC voltage is somewhat small. These circuits were also relatively complex, making it difficult to integrate into main power chips. Thus, the zero cross firing circuit has demanded the use of a separate resistor connected via a power terminal. These resistors were not easily integrated into a single chip because it was difficult to form these resistors on the chip surface. It was also difficult to provide the so-called "Snubberless" action on the relay at any inductive or resistive load. As a result, solid-state relays tend to operate well under resistive or slightly inductive loads, while at high inductive loads they tend to be "half wave" or "chatter", which turn on the relay for half a cycle. This has occurred conventionally because relays were provided in the signal conditioning circuit to suppress the fast turn-on of the circuit under rather fast transients or high dV / dt conditions. However, when the device is operated at very high inductive loads, voltage transients usually occur repeatedly while the device is turned on. When a conditioning circuit misinterprets this as a transient signal, it shuts down the power output for more than half of its operation during operation. The circuit will change normally during the next half wave and the relay will turn on. This state is repeated so that the relay can turn on only between one or the other half waves of the radio wave. In order to avoid this condition, conventional relays have been formed with reduced firing sensitivity, which requires a reduction in optical firing sensitivity.

Since conventional relays are relatively complex, sufficient volume is needed for the housing. Furthermore, the solid state relays of the past have limited the maximum temperature rise to about 100 ° C, which limits their current handling capability. As a result, conventional solid-state relays are relatively expensive in that they require a large number of separate components and large housings. Optically fired transverse thyristors that can be used alone or in such relays are also known. However, these devices are expensive, have a relatively high forward drop, and are relatively insensitive to input radiation. One type of thyristor WKD value is, for example, U.S.P. 19 October 1982. 4,335,320 (name: light control transistor).

According to the present invention, two identical new thyristor power chips are provided for the AC relay, each power chip having a side structure with both cathode and anode electrodes on one surface of each device and each chip. They can be optically fired and have an optically sensitive top surface so that when illuminated the device is conductive between its anode and the cathode electrode. The gate circuit of each thyristors is connected to a novel control circuit and forms one of the discrete components or one of the components employed in the body of semiconductor material forming the thyristors. The control circuit can be operated by preventing the turn-on even if the surface is illuminated when the voltage across the device exceeds a certain window value or when a high dV / dt transient is present in the device. This control circuit includes a clamp transistor that can be turned on to clamp the gate of each respective thyristor and a capacitive component circuit connected across the main power electrode. The capacitive component separator applies a control signal to the control transistor. One of the capacitors of the capacitive divider includes the distributed capacity of the control transistor. As long as the control transistor is ON, each of its power thyristors cannot be turned on even if its surface is illuminated. The capacitive divider is arranged such that the control transistor can typically be turned on for all absolute voltages present in the main unit larger than any relatively small window. As a result, the power thyristor cannot turn on the side of this small window value or zero cross value. The novel capacitive divider, combined with the control transistor, works by suppressing two fast transients and also allows the device to operate under normal load. This ensures that voltage transients that occur repeatedly while the device is turned on under high inductive loads will not be misinterpreted as fast transients and that the power thyristor chip can turn on at high inductive loads.

The novel signal conditioner of the present invention can be expected to improve the optical sensitivity of the device without opposing. Commercially available optically isolated dry liquid drivers and the like have always been limited in their dV / dt capability or optical sensitivity because of their inability to separate low level command signals from transients. The novel housing is provided with two chip arrangements, which are easily and inexpensively connected in parallel with the other and protected from the external environment. Aluminum substrates or other suitable thermally conductive or electrically insulating substrates are provided with suitable conductive patterns on the substrate to embed several chips of the switch and connect the chip electrodes to the appropriate output leads. Two identical thyristor chips to be connected antiparallel to each other are symmetrically fixed to each conductive pad on the substrate and are in line with the other and the end of the two conductive patterns on the substrate.

The two consecutive wires are stitch bonded to the conductive leads with the diester pad and the lid wire electrically connected to one of the anode pads of one chip, the cathode pad of the second chip, and the conductive patterns connected to the input alternating leads. -bonded). The other wire becomes similar to the conductive pattern and the other electrodes to connect the thyristors antiparallel to each other. The small LED chip is connected to the alumina substrate at the same time that the power chip is connected. The LEDs are properly connected to two input leads that are reliably isolated from the AC output leads.

A plastic cap covered with a white dimming reflective material is then secured to the substrate and covers the area of the substrate containing the LEDs and the two power chips. The cap may consist of its inner connection leads with an outer surface painted with transparent silicon and white silicon surrounding or enclosing the surface of the chip. If the control circuit for the power transistor is performed in a separate form, the separate components can be properly connected to this substrate. Preferably, however, these components are integrated in separate power chips so that the all-solid-state relay consists of two power chips and their control devices, LED chips and the various supporting structures described above.

Each diester of the relay is a novel structure, formed on a single chip with low forward voltage drop and relatively high current capability, and the non-critical LED triggering source is highly sensitive to input radiation so that it can be provided to energize the diester. Do. Relay circuit control components, including control MOSFETs, resistors, control diodes, and capacitors connected in parallel, may be provided in a single chip. The relay control component turns on the thyristors only when the anode-to-cathode voltage is below a predetermined value. Moreover, when the LED is off, false turn-on due to transients is prevented under all current conditions.

According to the invention, a number of individual transverse thyristors, each of which can be optically fired, are connected in parallel with the other in a single chip. Each transverse thyristor has a respective base with emitter elements formed in the base. The novel anode region, which consists of multiple spaced anode region fingers wrapping the two sides and ends of each base, facilitates parallel connection of the devices. The thyristor base region includes a distanced parallel emitter region, which base region is surrounded by the auxiliary P region. Auxiliary areas for laterally optically triggered thyristors are shown in US Pat. No. 4,355,320. However, the novel auxiliary region of the present invention is rounded and resistively connects to a conductive polysilicon field plate that surrounds all of the individual base regions and is tightly connected to the metal cathode electrode. The novel resistive connection can be obtained by connecting at a distance from the field plate to the auxiliary region. By using a resistive connection in this way, more carriers will arrive at the emitter that are injected from the anode region and laterally moved towards the emitter. This improves the forward voltage drop of the device by an important amount (e.g., 1.45 V to 1.15 V) which significantly reduces power loss during operation of the device.

According to another feature of the invention the anode region may be doped at a relatively high density compared to emitter doping which again reduces the forward drop. The emitter doping concentration on the emitter area surface is controlled to an optimal level to improve implantation capability. Particularly good behavior is obtained when using surface concentrations of ions / cc of l × 10 ^{2 °} to 6 × 10 ^{2 °} on the emitter surface. As a result, when making surface contacts for the device, thin lines of relatively thick aluminum are used to indicate the maximum amount of silicon. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. 1 shows a cross-sectional view of a bonding pattern when metallizing a transverse thyristor chip made in accordance with the present invention. A chip comprising the transverse thyristor of FIG. 1 can have any desired size and shape, which is a chip of single crystal silicon.

Various junctions shown in FIG. 1 are formed in the N (−) layer 20. Layer 20 may have a resistance of about 20Ω-cm. The spaced P-type regions 21, 22 and 23 are formed on the upper surface of the chip 20 by any desired process. Another inactive P-type region 23a may surround the region 23. The regions 21, 22, 23, and 23a may be boron diffusion regions of sufficient concentration so that the sheet resistance of the P region is about 1600 Ω / cm ² on the chip surface. They may be formed, for example, by a drive-diffusion process and ion implantation employing 5 × 10 ^{+ l 3} boron atoms per cm ² so that it can be doped relatively shallowly. Region 2l is preferably more heavily doped than other P regions. Regions 21, 22, 23 and 23a may all have a depth of approximately 4μ. P-type region 23 includes N (+) region 24 to complete the laterally spaced joints of the transverse thyristor.

Opposite edges of regions 21 and 23 should be as close as possible to each other as long as possible to block the selected voltage. In the present application, the device blocks about 400 to 500 V, with a distance of 105 μ. Region 21 is an anode region, region 23 is a gate or base region and region 24 is an emitter or cascade region, while N (-) body 20 is shown in FIG. Main blocking area of the thyristor. The region 22 is a floating guide region of a known type so that a high voltage of 400 to 500 V is increased between the junctions 21 and 23 without a risk of dielectric breakdown on the surface of the chip.

The upper chip surface is covered with a thin film silicon dioxide layer 30 having, for example, a thickness of about 1 mu. Polysilicon field plates 31 and 32 are formed on the oxide layer 30 as shown using conventional polysilicon deposition and masking techniques. The top surface of the chip and the oxide layer 30, including the polysilicon field plate, are covered with a conventional silicon dioxide layer 35 doped with glassy and phosphorous. The spaced gaps 36 and 37 of known structures prevent the electric field distribution at the surface of the region 20 adjacent to the floating guard region 22 due to the polarization of the side in the oxide layer 35 doped with phosphorus. It may be located at each end of the floating guard region 22 so as not to.

Appropriate openings are formed in the oxide layers 30 and 35 to allow the emitter region 24 and the anode region 21 to contact various regions and the field plate. Accordingly, the aluminum cathode electrode 40 and the anode electrode 41 are coupled to the emitter region 24 and the anode region 21, respectively, as shown. Other openings formed in the oxide layer 35 make it possible to connect from the cathode 40 to the field plate 31 and from the anode 41 to the field plate 32. Both cathode electrode 40 and anode electrode 41 are relatively thin and can be, for example, approximately 4 mu thick. Region 23a is preferably resistively connected to cathode 40. Accordingly, regions 23a may be connected to cathode 40 only at points spaced along their periphery. The transverse thyristor of FIG. 1 is turned on by injection of a carrier from the emitter region 24 into the gate region 23. Appropriate infusion is in the body 20 carrier. It can be obtained by applying radiation to the upper surface of the device to generate (holes). These holes are collected by emitter bonding between regions 23 and 24 to act as a base drive to move to region 23 and turn on the device. A suitable radiation source can be a schematic LED 45 arranged to illuminate the surface of the device. The device employing the structure of FIG. 1 can block 400 to 500V. During forward conduction, the forward voltage drop is about 1.15 volts at approximately 1.5 amps forward current.

The arrangement of the transverse thyristors of FIG. 1 can be met in any number of preferred geometric aspects. Particularly effective geometries are shown in FIGS. 2-9 which are now described and show an arrangement in which a number of devices are connected in parallel, as in FIG. 2 and 3, a plan view of a single chip including a single thyristor device and its control circuit components is shown. The second and third degree chips are one of many chips on a normal wafer that are separated after the normal process is completed. The chip is shown in FIG. 2 and after metallization of the cathode and anode terminal electrodes. The bonding pattern of the chip surface is shown in FIG. A number of separate thyristors are novel patterns for the anode, base, and emitter regions that extend along the passages shown later, as serpentine or hand-shaped passages (FIGS. 3 and 4). Are connected in parallel, whereby they have the longest possible length so that the device has a high current capacity. In the embodiments of FIGS. 2 and 3, the chip has a width of 82 mm and a length of 113 mm and a forward current transfer rate of 1.5 A with a forward voltage drop of 1.15 V. FIG. The device's bisymmetrical blocking capability is approximately 500 V peak. Therefore, the thyristor chip of the present invention can be employed together with the anti-parallel connected same thyristor chip and is used in a solid state relay for controlling an AC circuit having an effective voltage of up to 280V. The basic metallization pattern of FIG. 2 employs a cathode 50 and an anode 51 in the shape as shown. Although not shown in FIG. 2, the control circuit is embedded in the chip body. The circuit is shown in FIG. The metallization regions 60 and 61 of FIG. 3 are the electrodes of the two capacitors shown in FIG.

Capacitor 60 will be described later with reference to FIG. Capacitors comprising electrodes 60, 61 are connected in parallel as shown in FIG. 9, and the anodes of the thyristors 64a, 64b, 64c and 64d and the control MOSFETs 76, 77, 78 and 79 Are connected between the gates. The thyristors 64a, 64b, 64c, 64d are in parallel and have a common cathode and anode shown as cathode 50 and anode 51 in FIGS. 2 and 6. A 100KΩ resistor 70 formed of polysilicon and electrically connected between the cathode and the jade of each of the thyristors 64a, 64b, 64c, 64d is packed with a chip of FIG. The detailed configuration of the resistor 70 will be described later in connection with the eighth degree. In addition, as shown in FIG. 9, a zener diode 71 is integrally formed on the chip of FIG. 3, and capacitors 60 and 61 are formed between the anode and the cathode terminals 50 and 51 of the illustrated thyristor. It is connected in series with. Also shown in FIG. 9 is an intrinsic distribution capacitor 75 in parallel with the zener diode 71. The zener diode 71 may be formed in the inert P region 82 and may be composed of the N ⁺ region 71a shown in FIG. The zener terminal 71b may be formed directly on the N ⁺ region 71a, and the other terminal may be formed by the metal contact 71c connected to the cathode electrode. The plurality of control MOSFETs 76,77,78,79 shown in FIG. 9, which will be described above on FIGS. 3 and 4, are embedded on a chip and operate with thyristors 64a, 64b, 64c and 64d, respectively. . Each control MOSFET is arranged in close proximity to its respective main diester member so that operation delay time is limited and circuit symmetry can be guaranteed.

The circuit of FIG. 9, which will now be described in connection with FIGS. 2-8, is performed in a novel way. The embodiment described here uses four parallel thyristors 64a, 64b, 64c, 64d and no number of elements can be used. 3-6, the entire integrated device is formed on a relatively high resistive N (−) substrate 80 which may have a resistivity of about 20Ω-cm. Many individual P-type regions are formed in the substrate 80 by any desired process. The first of these is the P ⁺ type anode region 81 corresponding to the anode region 21 of FIG. As shown in Figs. 3 and 4, the anode region 81 has a main body portion in which three parallel fingers 81a, 81b, 81c extend. 81a and 81b are shown in more detail in FIGS. 4 and 6. A rectangular anode area frame with legs 81a, 81e and 81f surrounds the chip as shown in FIG. Legs 81d and 81e are shown in FIG.

The second P-type region shown in FIGS. 3-8 is an "inactive" P-type auxiliary region 82. The inactive region 82 has loop portions 82a, 82b, 82c and 82d (FIG. 3), and the auxiliary ring 23a of FIG. 1 serves to surround the base of the four respective thyristors described later. Perform. The loop portion 82b is shown in FIG. Elongated P-type base regions 83a, 83b, 83c, and 83d (3rd, 4th and 6th degrees) separated by four equal distances are formed in the region 80. The base areas correspond to the base area 23 of FIG. Base area 83b is shown in detail in FIG. It should be noted that the base regions 83a, 83b, 83c and 83d are almost entirely surrounded by the auxiliary ring loops 82a, 82b, 82c and 82d.

Another P-type region consisting of floating guard ring 84 has been formed, which is shown in FIGS. The guard ring 84 extends in a wavy path and divides the N (-) region 80 which reaches the surface of the apparatus of FIGS. 3 and 4 in half.

Each of the thyristor bases 83a, 83b, 83c and 83d contains two parallel N ⁺ emitter regions 85a-85b, 86a-86b, 87a-87b and 88a-88b, respectively (third, fourth, and fourth). And 6 degrees).

Emitter regions 86a and 86b are shown in greater detail in FIG. It can be seen from the above that the junction pattern of FIG. 3 forms the basis for the four thyristor elements 84a, 84b, 84c and 84d of FIG. 9 and is capable of parallel connection of the devices. The thyristor element defining the thyristor 64b is shown in FIGS. 4 and 6 and will now be described. The thyristor base is made up of an active P region 83b including bulging emitter regions 86a and 86b. The thyristor anode region is composed of anode region fingers 8la and 81b symmetrically surrounding the base 83b. The thyristor body consists of an N (-) region 80. The base is also almost completely surrounded by secondary loop area 82b with the above advantage of increasing integration capacity. The novel bonding pattern also allows parallel connection of multiple thyristors on a chip. The junction patterns shown in forming, on the sides, between the base regions 83a, 83b, 83c and 83d and their respective adjacent anode fingers 81a, 81b and 81c (and outer shaft anode legs 81d and 81e). The distance is about 105 microns. Each depth of the P-type regions is about 4 microns. Each base region 83a, 83b, 83c and 83d has a length of about 40 millimeters and a width of about 75 microns. Another P-type guard ring 90 (FIGS. 5 and 5) is preferably formed around the periphery of the chip during the formation of the various P regions. The ring 90 is about 38 microns away from the perimeter of the P ⁺ anode 8181. Also, as shown in FIGS. 3 and 4, the N (+) source and drain regions 91a-91b, 92a-92b, 93a-93b and 94a-94b are controlled in FIG. 9 during the formation of the various junctions. For MOSFETs 76, 77, 78, and 79, respectively. These are formed in the enlarged inert P-type region 82.

As shown in FIG. 4 for the case of control MOSFET 77, a suitable gate oxide and polysilicon gate electrode (not shown) having a thickness of about 0.1 micron is disposed over the gap between regions 92a and 92b.

Locally thin oxides can be used for control MOSFETs because the gate is at the potential of the nod between capacitors 60 and 61 and capacitor 75.

Accordingly, the potential difference between the control MOSFET gates and the cathode of the main thyristors is very low. Thus, the transistors 76 to 79 can be very high gain transistors.

The source region 92a is connected to the inert base, while the drain region 92b is electrically connected to the thyristor base region 83b via the conductive strip 95 (FIGS. 4 and 6). Strip 95 is preferably metal.

Similar arrangements are provided such that each thyristor element with conductive strips connecting the bases 83a, 83b, 83c, 83d controls the control MOSFET source electrodes 91a, 92b, 93c, 94d, respectively. The conductive strips are then all connected together by polysilicon connecting strips, shown schematically in FIG. 4 by dashed lines 95a.

Capacitors 60 and 61 are provided in the inactive P region 82 as shown in FIG. 7 with respect to the capacitor 60. The capacitor 60 is thus placed on the area of the N (-) material 80 to reach the p-shaped base 82 and needle surface separated from the chip by having the rectangular ring 96 have an appropriate radial co-owner. It is formed by depositing a metal layer.

Note that the metal layer 60 is over the thermal oxide layer 97 to form the field plate.

In addition, the resistor 70 is provided in the inactive P-type region 82 as shown in FIG. Accordingly, in FIG. 8 the polysilicon strip 70a is deposited on the oxide layer 97 and covered with the attached silicon dioxide layer 98. Therefore, the resistor 70 is formed of a resistive layer completely insulated from the chip powder by the insulating layer 97.

The resistor 70 thus becomes an ideal resistor without parasitic interference with other circuit components.

The following openings are formed in layer 98 and resistor terminal connections 99 and 100 are made of resistors. These terminals are suitably connected to source electrodes of the thyristor cathode and the control MOSFETs 76, 77, 78 and 79.

The upper surface of the chip shown in FIGS. 5 and 6 is processed to give a predetermined metallization. Before metallization, a suitable thermal oxide 110 is present in place or applied to the device surface to a thickness of approximately 1 micron. After conventional masking and etching steps the metals are applied in the required order. The top surface is then covered with an attached oxide coating that can have any desired thickness.

The novel polysilicon field plates 112 and 113 are deposited on the thermal oxide 110. It should be noted that all polysilicon strips or layers may be attached in any order. The electric field plate 112 is an elongated and serpentine plate disposed on the upper portion, and flows through the junction path between the P (+)-anode region 81 and the N (-) region 80. Similarly, field plate 113 is an elongated, serpentine plate that connects a path parallel to that of plate 112 and is carried out on the junction between auxiliary region 82 and an outwardly disposed N (-) region 80. .

When the electric field plates 112 and 113 are attached, the outer light ring 115 (FIG. 5) can also be arranged around the outer periphery of the chip. Ring 115 is connected to substrate 80 in a normal manner.

Field plates 112, 113 and ring 115 are each about 20 microns wide. The protective ring region 84 has a width of about 8 microns and is positioned midway between the opposite sides of the plates 112 and 113 with a distance of about 44 microns between them. Similarly, the P-type region 90 (FIG. 5) is located midway between the plate 112 and the plate 115, both sides of which are spaced 44 microns apart.

An anode 51 is then formed as shown and connected to the P-type anode 81 as shown in FIGS. 2 and 6. In addition, as shown in FIGS. 2, 5, and 6, the cathode 50 is formed.

The transverse thyristors of FIGS. 2-9 are conducted by radiation from LEDs 45 (FIGS. 6 and 9) arranged to illuminate the exposed surface of the chip.

Since the chip is extremely sensitive, the size, output or position of the LED 45 is not particularly important.

The patterns shown in FIGS. 2-8 make up the electrical circuit shown in FIG. 9, thus determining half of the solid state relay, which will be described later. When there is no illumination light, the thyristor is suppressed from conducting so as not to be ignited by a transient signal. The voltage distribution between the capacitors 60-61, 75 determines the voltage window that can be conducted. It is important to note that a capacitive voltage splitter can put a very low gate voltage on the control transistor and a very low functional leakage current. Capacitors also block irradiated light or radiation.

The novel type thyristor shown in FIGS. 2 to 8 can be made in any way desired. This device provides a maximum effective current carrying area between anode area 81 and base area 84 for a given chip area. The shape of the padan is also arranged to adequately forward forward the voltage drop as much as possible so that the LED 45 is not dangerous while maintaining high photosensitivity.

The main features of the new shape are the novel P-type auxiliary regions 82a, 82b, 82c and 82d surrounding the respective base permanentities 83a, 83b, 83c and 83d, respectively. With this geometry all N + cathodes can be connected together. Thus, the regions 82a, 82b, 82c and 82d and the main region 82 are constant potential regions in which all thyristor bases are buried. By extending into the region 82 at the end of the base, a large area can be used for metallization to connect the regions in parallel.

Resistor from cathode 50 to loops 82a, 82b, 82c and 82d, as shown by the connection point l20 in FIG. 4, using a gap-point connection extending along the length of the P-type loop 82b. It is preferable to connect as a matter of course. It may also be connected by a short contact 121 as shown in FIG. By using a resistive connection between the auxiliary loops and the cathode 50 as shown in FIGS. 4 and 6, carriers injected in the anode areas 81a and 81b are transferred to the auxiliary areas 82a and 82b while the device is conducting. Rather than being collected at 82c and 82d, they tend to move to emitter regions 86a and 86b. This increases the collecting efficiency of the emitter and greatly reduces the forward voltage drop of the device. For example, by making a resistive connection between the secondary loop type reverse and the cathode 50, the forward voltage drop at 1.4 amps was reduced from about 1.45 volts to about 1.15 volts. As a result, power consumption can be greatly reduced in the forward challenge.

When making the device of FIGS. 3 to 6, it is desirable to dope the anode region 81 and all of its components more heavily than the doping of the P-type regions 82, 83, 84. For example, the anode region 81 is doped to a point where it has a resistivity of 50 Ω per square compared to 1600 Ω per square of the regions 82, 83, 84. This increases the gain, thereby making it possible to reliably increase the photosensitivity of the inherent lateral transistors composed of regions 81, 80, and 83. Moreover, by further doping the anode region, it is possible to lower the forward voltage drop of the device.

Another important feature of the invention is an emitter region for example third help Figure 6 the optimal value N type concentration in the surface of the device by controlling the doping of the region (86,86b) at 1 × 10 ²⁰ to 6 × 10 ² It can be made to be the phosphorus ion / cc. This is done by diffusing phosphorus into the thin oxide layer when forming region 86 or by controlling various gas flows by diffusion process. By lowering the N-type concentration at the surface of the region 86, the emission efficiency of the device can be improved and thus the forward voltage drop can be further lowered and the sensitivity of the device conducting by photons from the light source 45 can be significantly increased. have.

Next, in FIG. 10, a circuit diagram of the complete a, c relay of the present invention is shown. The relay shown in FIG. 10 uses two identical die Listers 210 and 211, which are connected in anti-parallel relations between the main a and c power terminals 212 and 213, respectively. The amblyed thyristors 210 and 211 have respective shapes shown in Figs. 1 to 9, and a gate circuit amblyted by the gates 216 and 217 is provided. The thyristor chip 210 has a positive pad 220 and a negative pad 221 on its top surface, while the chip 211 has the same positive pad 222 and a negative pad 223 (FIG. 11). .

The thyristors 210 and 211 are electrically connected to each other so that one anode 220 is connected to the other cathode 223 and the other anode 222 is connected to the other cathode 221. The devices are thus connected in antiparallel relationship as shown in FIG.

A single LED 225, which may be a commercially available potassium aluminum arsenide with terminals 226 and 227 in FIG. 10, is designed to sufficiently illuminate the reduction of the chips 210 and 211 to allow conduction when other circuit conditions are suitable. Posted as if blinded later. The circuit is electrically insulated between the input circuit connected to the terminals 226 and 227 and the a and c power circuits connected to the terminals 212 and 213.

The same control circuits as described above are provided to control the conduction of the thyristors 210 and 211, respectively, which include MOSFET transistors 230 and 231, zener diodes 232 and 233, resistors 234 and 235 and capacitors 236 and 237, respectively. . The condensers 236 and 237 serve as one component of each capacitive divider, like the condensers 60 and 61 of FIG. The second component of the capacitive component split consists of the distribution capacities (238,239) of the stationary (230,231), respectively.

Circuit components 230-239 can be treated as individual components. However, as shown in FIGS. 1 to 9, it is more preferable that these circuit components are integrally processed with the semiconductor including the thyristors 210 and 211.

Transistors 230 and 231 are connected to gates 216 and 217 of the thyristors 210 and 21l, respectively. As long as the transistors 230 and 231 are turned on, even if the surfaces of the devices 210 and 211 are illuminated from the LEDs 225, the devices cannot be turned on. Transistors 230 and 231 conduct when their respective gates 240 and 241 are adequately charged to an appropriate threshold voltage (V _th ). Thus, if the nodes 242 and 243 reach the critical conduction voltages of the transistors 230 and 231, respectively, and a suitable drain is provided up to the source voltage, the devices will conduct and clamp each gate 216 and 217 of the diester 2101,211.

If the voltage of each nord 242, 243 is V _o ;

V _o =: VccCp / (Cl + Cp)

Where V _cc is the static pressure between the terminals 212 and 213, C _p is the capacitance of the distribution capacitors 238 and 239 and C ₁ is the capacitance of the capacitors 236 and 237 respectively.

From the above, the suppression at nod 242 or 243 when the instantaneous a, c voltage between terminal 212 and 213 is more positive or negative than any " window " It can be seen that V _o will be greater than the threshold voltages of transistors 230 and 231. Therefore, when the window voltage is exceeded, the transistors 230 and 231 clap the thyristors 210 and 211. In this arrangement a zero detection circuit can be provided without the need to insert a resistor between the main terminals of the device.

The novel capacitive splitting circuit is also useful for suppressing ignition of devices 210 and 211 due to surge pulses, such as transient noise or high dV / dt signals. Such high transient pulses apply a voltage between the parasitic capacitors 236 and 239 that is high enough to cause the transistors 230 and 231 to conduct and clamp their respective thyristors, respectively. Thus, the thyristor will not ignite in response to the surge transient pulse.

In the case of pulses generated by high inductive loads connected to the relay terminals 212 and 213 and rising relatively slowly, these pulses will not be fast enough to allow the control transistors to conduct and clamp the die Listers 210 and 211 by themselves. Relays can avoid single phase or chattering at high inductive loads. It will also be noted that this is done without lowering the optimum sensitivity of the device. Thus, the thyristors 210 and 211 can be designed to have an optimal light sensitivity for ignition without fear of malfunction due to a relatively slow rising transient pulse.

Another advantage shown in FIG. 10 is the design of resistors 234 and 235. That is, the temperature coefficient of resistance is parallel to each thyristor sensitivity. That is, if the resistance has a negative temperature coefficient that is common, it may be possible for the resistance to clamp each controlled rectifier at high temperatures. However, the clamping action can be avoided by parallelizing the resistance temperature coefficients of the resistors 234 and 235.

Next, a structure in which the chips 210 and 211 and the LEDs 25 of FIG. 10 are inserted in FIGS. 11 to 14 will be described. First, in FIGS. 11 and 12, a ceramic body support 200 is shown which may be made of alumina but may be any desired electrically insulating, inevitable material. By way of example, the alumina slab 260 may have a thickness of 0.025 inches and a length of about 0.9 inches and about 0.25 inches.

A plurality of conductive patterns, including patterns 261 and 267, are formed on one surface of the substrate 260. Each pattern is formed on a substrate by gold plating, the thickness of which is greater than about 150 microinches. Each of the thyristors chips 210 and 211 is then soldered or otherwise attached to the conductive pads 265 and 264, respectively, in good thermal contact with the alumina body 260. For typical sized devices, chips 210 and 211 are each about 82 x 116 mils in size.

The LED chip 225 is mounted on one unit of the conductive pattern 262. The chirps 210 and 211 are generally mounted such that their positive and negative leads are in line with one another of the conductive patterns 266 and 267. Therefore, it will be convenient to electrically connect the ends of the conductive pads 223 of the thyristor 211, the diesters 210 and 220, and the conductive pattern 207 using the single wire 270. This can be done by a relatively simple stitch bonding process suitable for high speed automatic technology.

In other words, the bonding head is lowered up to the wire 270 and the wire is electrically attached to two spaced apart points corresponding to the positions of the pads 223 and 220 and one end of the conductor 267. In the same manner, the second parallel wires 271 are stitch bonded to the ends of the conductive pads 222 and 221 and the conductive pattern 226. The stitch bonding of the conductor 27 is shown in FIGS. 11 and 12. Each conductive wire 270, 271 would be an aluminum wire with a diameter of about 6 mils.

As a result of the above, the power supply terminals 212 and 213 are connected to the thyristors 210 and 211 of FIG.

Since the chips 210 and 211 also contain their respective control circuits, the control circuits may also be connected on the spot by the single stitch bonding method as described above.

It can be seen that the LED 225 is disposed above one end of the conductive pattern 262 connected to the lead 226. The other pole of the LED 225 is electrically connected to one end of the conductive pattern 261 by a wire 280.

Wire 280 may be an extension of LED 225 which is bonded to one end of conductive pattern 261 in any desired manner. The conductive pattern 261 is then connected to a conductive pattern 263 spaced apart by a direct short circuit connection of the wire 281 or by a resistor 282.

The shorting wire 281 or the resistor 282 is appropriately selected depending on the power of the terminals 226 and 227 and the characteristics of the LED 225. The wires 280 and 281 may be gold wires having a diameter of about 1 mil. The leads 212, 213, 226, and 227 extend from the periphery of the substrate 260 to form a double in-line pin package. An optical cap or cover 291 is then placed over the LED 225 and the thyristors 210 and 211 to surround the area indicated by dashed line 290 in FIG.

This cap is shown as cap 291 in FIGS. 13 and 14 and can be made from any desired reflector plastic material that can withstand the heat generated during operation of the device.

I actually used white plastic. Plastic may be made of disulfone. The plastic is preferably white so that it can reflect off its inner surface. The cap can also be made of suitable silicon, such as RTV mixed with titanium oxide powder.

Titanium oxide powder remains dispersed in silicon. This mixture can be cured in an oven at about 115 ° C. for about 15 minutes. The cap 291 has an inclined surface 292 over the location of the LED 225, which can reflect light toward portions of the chips 210 and 211 as shown in FIG.

Cap 291 may be secured in place, as shown in FIG. 13, or may be disposed so as to overlap over the substrate and snap over the edge of the substrate as required.

Next, the transparent silicon is filled in the cap 292 through the filling holes 294 and 294 in FIGS. 13 and 14 to completely encapsulate all the chips 225, 210 and 211 and the leads connected thereto. Irradiation light from) reaches the photosensitive surfaces of the coil thruster chips 210 and 211.

After the cap 291 is fixed in position and filled with silicon, the entire substrate 260 to which the cap 291 is attached can be mounted in a lead frame with leads 212, 213, 226 and 227. The assembled device is then fully loaded into a housing made, for example, by a transfer molding method. The leads 212, 213, 226 and 227 extend from this package and a dual, inline pin package is obtained which is relatively small in size and bulky. However, this hatch can withstand 1 to 1/2 amps of continuous current rating at 240 volts a, c.

While the invention has been described in terms of its preferred embodiments, many variations and modifications will be readily apparent to those skilled in the art. Therefore, the present invention should not be limited to the specific details described herein but only by the scope of the appended claims.

Claims (31)

An alternating-current solid state relay circuit comprising an anode and a cathode electrode and a first and a second thyristors, each having a gate circuit, wherein each of the thyristors is formed on separate first and second semiconductor chips, respectively. And transversely conductive, wherein the anode and cathode electrodes of each of the thyristors are located on the same first surface of the first and second chips, respectively, and the first surfaces of the first and second chips are optically Sensitive to the first and second chips can be switched to conduct current by dimming the one surface, the solid state relay further comprising a light emitting diode arranged to illuminate the first surface upon excitation. LED), a pair of AC terminals, insulated from the anode and cathode electrodes of the first and second thyristors connected to the AC terminal pairs in parallel with each other, and the AC terminal. And a pair of control terminals connected to the light emitting diodes, and the gate circuits of the first and second diistors, respectively, so that when the voltage between the AC terminal pair exceeds a predetermined value, First and second clamping of the first and second gate circuits respectively to prevent firing of the first and second clamping circuits of the first and second gate circuits in response to a transient pulse having a dv / dt greater than a predetermined value. AC solid state relay further comprising a control circuit. 2. The transistor control circuit of claim 1, wherein the first and second control circuits comprise first and second control transistors, respectively, and are operable to switch output circuits and respective control circuits in conductive and non-conductive states, respectively. And a first and second capacitor divider, wherein the first and second transistor output circuits each include one of the gate circuit and the anode of one of the first and second diodes. Connected between the electrodes, whereby one of the first or second dielisters is not fired in response to dimming of the first surface when the first or second transistor output circuit is in a conductive state, respectively. A two capacitor divider is connected across the AC terminal pair and has each node between capacitors connected to the control circuit of each control transistor so that the AC voltage When the voltage of the node exceeds a predetermined window voltage, each transistor is turned on while the voltage between the AC terminal pairs exceeds a predetermined value that can prevent one of the die thrusters from turning on, respectively. And a transient pulse turns on the transistor during this period to prevent the thyristors from turning on by a high transient dv / dt pulse. 3. The apparatus of claim 2, wherein the first and second control circuits are further connected from the first and second capacitor distributors and the respective nodes to respective anode electrodes of the first and second thyristors, respectively. And a first zener diode. 4. The first and second resistors of claim 2 or 3, further comprising first and second resistors connected to the anode electrodes of the first and second diesters, respectively, between the gate circuits of the first and second diesters, respectively. Solid relay, characterized in that. 4. The solid state relay of claim 2 or 3 wherein the first and second transistors are MOSFETs and the transistor control circuitry comprises a gate circuit of the transistor. 6. The solid state relay according to claim 5, wherein said second capacitor of each of said first and second capacitor dividers is respectively a distribution capacitor of said first and second transistors. The method of claim 1, further comprising an electrically insulating or thermally conductive ceramic substrate for mounting the first or second chip and the light emitting diode, wherein the first and second chip and the light emitting diode are the substrate. The optically sensitive surfaces of the first and second chips are spaced apart from the substrate, the light emitting diodes being reflected by the reflection of light output from the reflective surface. A solid state relay, characterized in that it is in a position to enable dimming of the first and second chips. The method of claim 1, wherein the first surface of each chip is a junction-receiving surface of one conductivity type, the other conductivity type anode area and the other conductivity, each of which is formed spaced apart from each other in the axial direction in the surface. A base region of the die type, and an emitter region of the one conductivity type which is entirely contained within the base region and extends from the surface, wherein the anode and cathode electrodes are the anode and emitter, respectively. And the anode region is doped more densely than the base region to reduce forward voltage drop and increase light sensitivity. The method of claim 1, wherein the first surface of each chip is a junction-receiving surface of one conductivity type, the other conductivity type anode area and the other conductivity, each of which is formed in the surface at intervals from each other in the axial direction. A base region of the die type, and an emitter region of the one conductivity type all contained within and extending from the surface, wherein the anode and cathode electrodes are respectively the anode and emitter regions. In contact with the surface of the at least one level obtained by diffusion through a thin oxide layer to increase the radiation sensitivity of the transverse thyristor turned on by radiation from the radiating means. Solid relay, characterized in that. 10. The method of claim 8 or 9, further comprising a guard ring of another conductivity type formed in the surface and spaced laterally between the anode and the base region, wherein the guard ring comprises: the cathode and the anode electrode; And relay electrically with respect to said electrodes. 2. The semiconductor device of claim 1, wherein the first surface of each chip comprises a junction-integrated surface of one conductivity type, an anode region of another conductivity type and a base region of the other conductivity type, each formed in the surface at a distance laterally from the other; An electrically conductive emitter permanently formed in the base region and extending therefrom, the anode and cathode electrodes connected to the anode and emitter regions, respectively, and formed on the surface. And an auxiliary region of another conductivity type surrounding the base region and spaced laterally. 9. The method of claim 8, wherein the base region has an extended shape that is terminally connected to the surface, the emitter region includes at least one rectangular shape included in the base region, the anode region is finger-shaped And wherein the fingers have a pattern surrounding the base region. 12. The solid state relay according to claim 11, wherein said auxiliary area is connected to said cascade electrode with resistance. An optically fired transverse cross section consisting of a chip of a semiconductor material having a junction-integrating surface of one conductivity type, and having an anode area of the other conductivity type and a base area of the other conductivity type each formed laterally at a distance from each other in the surface. In the thyristor, the conductive type emitter region extends therefrom and is entirely contained within the base region, and an anode and a cathode electrode are formed with the anode region and the emitter region, respectively. A die type thyristor characterized in that it is connected to radiating means for dimming at least a portion of the surface for conducting the die thyristor, and the auxiliary area of the other conductivity type is formed on the surface and is laterally dropped from and enclosed from the base area. . 15. The thyristor of claim 14, wherein the anode region is doped more densely than the base region to reduce forward voltage drop and increase light sensitivity. 16. The thyristors according to claim 14 or 15, wherein the emitter region is doped to the surface at a relatively low density and has a surface concentration obtained by diffusion through a thin film oxide layer. 15. The method of claim 14, wherein the other conductivity type guard ring is formed in the surface and is disposed between and spaced apart from the anode and the base region, wherein the guard ring is the cathode and anode electrode. And is electrically floating with respect to the electrodes. 18. The transverse thyristor according to claim 17, wherein the emitter region, the base region and the guide ring are relatively thin regions having portions extending together. The thyristor according to claim 14, wherein said auxiliary region is included as a means for making a resistive connection to said cathode electrode. In an optically triggered thyristors composed of one conductive semiconductor substrate, the substrate has parallel conducting base regions of another conductivity type extending into at least a surface of the first and second substrates. Respective emitter regions extending into the surface of at least the first and second parallel base regions and completely contained within their respective base regions, each pen-based extended anode region of the other conductivity type into the substrate. Extends and is laterally separated from each of the parallel base regions and is disposed at oppositely extending sides thereof and extends at least together with the base region, an anode contact is connected to the anode region, and a cathode contact is the emitter region And the means for generating radiation has an appropriate bias voltage When applied to the contacts for turning on the thyristor, characterized in that the optical that may be enabled to generate the minority carriers in the substrate acting as a base drive trigger thyristors. 21. The die of claim 20, wherein the anode region consists of parallel and elongated fingers extending into the substrate surface and extending from the other conductivity type enlargement region disposed at an adjacent end of the base region. Lister. 22. The apparatus of claim 20 or 21, comprising a plurality of auxiliary regions of said other conductivity type extending into said substrate, surrounding said space, and laterally spaced apart from one end of each side of said base region. And a base disposed between the bases and the elongated anode area associated therewith. 23. The thyristor of claim 22, wherein the plurality of auxiliary regions extend from the other conductivity type enlargement region disposed at an adjacent end of the base region. 21. The thyristor of claim 20, wherein the elongated anode region and the plurality of base regions are separated from each other by successively elongated sinuous springs of the one conductivity type material. 25. The die Lister of claim 24, comprising the other conductive guide ring extending with and extending in the center of the elongated sinuous strip and extending into the tracheal surface. 26. The thyristor of claim 24 or 25, comprising first and second field plates spaced from each other and extending with opposite ends of the elongate sinuous strip. 21. The apparatus of claim 20, comprising respective control transistors for said at least first and second base regions, each said control transistor comprised of source and drain regions spaced apart into the surface of said engine, respectively. Spaced apart laterally from the base region of the contact means, a contact means is supported on the substrate to electrically connect the base region to the drain region of each control transistor, the drain region of each control transistor being the cathode. Connected to a contact, each gate insulating layer is covered on the substrate in a space between the source and drain regions of the respective control transistor, and a gate electrode means is on each of the gate insulator layers. Lister. 28. The device of claim 27, further comprising: first and second capacitors formed on the substrate and connected in series between the anode and the cathode contact and defining a capacitive divider, wherein the gate electrode means of the control transistor comprises: A first capacitor connected to the nod between the first and second capacitors, the first and second capacitors being sized to apply only a very small voltage between the anode and the cathode contact between the gate electrode means and the substrate; Thereby the gate insulating layer can be very thin, approximately 0.1 micron. 29. The method of claim 28, wherein the first capacitor is a distributed capacitance and the second capacitor is comprised of a capacitor junction on the substrate and a capacitor electrode on the capacitor junction, and the capacitor is connected to the anode contact. The thyristor. 30. The thyristor of claim 29, wherein a zener diode means is formed on the substrate and connected between the first and second capacitors and the Nord between the cathode electrode. 28. The silicon dioxide layer of claim 27 wherein integrated resistor means are connected across source and drain regions of each control transistor, the resistor means comprising a strip of polysilicon attached over a predetermined region of the substrate, the silicon dioxide layer Disposed between the predetermined area of the substrate and the strip of polysilicon such that the resistor is electrically isolated from the parasitic currents in the substrate, the first and second terminals extending from the spaced chips on the polysilicon strip; And the first terminal is connected to each of the contact means connected to the base, and the second terminal is connected to the cathode contact, respectively.

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