BR9915383A - Processo de tratamento de sinais de tarefa em um sistema de processamento, sistema de processamento possuindo múltiplas unidades de processamento para o processamento de sinais de tarefa, e, fila de sinal de tarefa em um sistema de processamento - Google Patents

Processo de tratamento de sinais de tarefa em um sistema de processamento, sistema de processamento possuindo múltiplas unidades de processamento para o processamento de sinais de tarefa, e, fila de sinal de tarefa em um sistema de processamento

Info

Publication number
BR9915383A
BR9915383A BR9915383-1A BR9915383A BR9915383A BR 9915383 A BR9915383 A BR 9915383A BR 9915383 A BR9915383 A BR 9915383A BR 9915383 A BR9915383 A BR 9915383A
Authority
BR
Brazil
Prior art keywords
processing
task
processing system
signals
processing units
Prior art date
Application number
BR9915383-1A
Other languages
English (en)
Portuguese (pt)
Inventor
Per Anders Holmberg
Nils Ola Linnermark
Karl Oscar Joachim St Mbergson
Terje Egeland
Magnus Carlsson
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from SE9803901A external-priority patent/SE9803901D0/xx
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Publication of BR9915383A publication Critical patent/BR9915383A/pt

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/50Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842Speculative instruction execution
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Hardware Redundancy (AREA)
BR9915383-1A 1998-11-16 1999-11-12 Processo de tratamento de sinais de tarefa em um sistema de processamento, sistema de processamento possuindo múltiplas unidades de processamento para o processamento de sinais de tarefa, e, fila de sinal de tarefa em um sistema de processamento BR9915383A (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
SE9803901A SE9803901D0 (sv) 1998-11-16 1998-11-16 a device for a service network
SE9901145A SE9901145D0 (sv) 1998-11-16 1999-03-29 A processing system and method
PCT/SE1999/002061 WO2000029940A1 (en) 1998-11-16 1999-11-12 Multiple job signals per processing unit in a multiprocessing system

Publications (1)

Publication Number Publication Date
BR9915383A true BR9915383A (pt) 2001-08-07

Family

ID=26663434

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9915383-1A BR9915383A (pt) 1998-11-16 1999-11-12 Processo de tratamento de sinais de tarefa em um sistema de processamento, sistema de processamento possuindo múltiplas unidades de processamento para o processamento de sinais de tarefa, e, fila de sinal de tarefa em um sistema de processamento

Country Status (9)

Country Link
US (1) US6714961B1 (https=)
EP (1) EP1131701B1 (https=)
JP (1) JP4608099B2 (https=)
AU (1) AU1437000A (https=)
BR (1) BR9915383A (https=)
CA (1) CA2350924C (https=)
DE (1) DE69941998D1 (https=)
SE (1) SE9901145D0 (https=)
WO (1) WO2000029940A1 (https=)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7152232B2 (en) * 2001-07-16 2006-12-19 Sun Microsystems, Inc. Hardware message buffer for supporting inter-processor communication
US8015303B2 (en) * 2002-08-02 2011-09-06 Astute Networks Inc. High data rate stateful protocol processing
US7814218B1 (en) 2002-10-17 2010-10-12 Astute Networks, Inc. Multi-protocol and multi-format stateful processing
US7596621B1 (en) * 2002-10-17 2009-09-29 Astute Networks, Inc. System and method for managing shared state using multiple programmed processors
US8151278B1 (en) 2002-10-17 2012-04-03 Astute Networks, Inc. System and method for timer management in a stateful protocol processing system
DE102006006582B4 (de) * 2006-02-13 2009-06-10 Jenoptik Laser, Optik, Systeme Gmbh Laser und Verfahren zur Erzeugung gepulster Laserstrahlung
US8156493B2 (en) * 2006-04-12 2012-04-10 The Mathworks, Inc. Exception handling in a concurrent computing process
KR20120017294A (ko) 2010-08-18 2012-02-28 삼성전자주식회사 어플리케이션을 효율적으로 처리하는 스케쥴링 시스템 및 스케쥴링 방법
US9329915B1 (en) * 2012-05-08 2016-05-03 Amazon Technologies, Inc. System and method for testing in a production environment
KR101476789B1 (ko) * 2013-05-06 2014-12-26 (주)넥셀 프로세싱 장치 및 방법
US9455887B1 (en) 2013-08-14 2016-09-27 Amazon Technologies, Inc. Distributed performance evaluation framework
CN104516773B (zh) * 2013-09-29 2018-04-20 国际商业机器公司 用于物理机的数据分配方法和数据分配装置
US9465653B2 (en) * 2013-12-11 2016-10-11 Dropbox, Inc. Automated invalidation of job output data in a job-processing system
US10372492B2 (en) 2013-12-11 2019-08-06 Dropbox, Inc. Job-processing systems and methods with inferred dependencies between jobs
US10133771B2 (en) 2015-05-13 2018-11-20 International Business Machines Corporation Opportunistic wait-triggered elastic commit

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4466061A (en) 1982-06-08 1984-08-14 Burroughs Corporation Concurrent processing elements for using dependency free code
EP0230721A3 (en) 1986-01-22 1988-04-27 Mts Systems Corporation Multiprocessor control system
SE454921B (sv) 1986-10-03 1988-06-06 Ellemtel Utvecklings Ab Sett och anordning for att i en pa forhand avgjord ordningsfoljd exekvera tva instuktionssekvenser
US5781753A (en) 1989-02-24 1998-07-14 Advanced Micro Devices, Inc. Semi-autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for speculative and out-of-order execution of complex instructions
US5072364A (en) * 1989-05-24 1991-12-10 Tandem Computers Incorporated Method and apparatus for recovering from an incorrect branch prediction in a processor that executes a family of instructions in parallel
US5487156A (en) * 1989-12-15 1996-01-23 Popescu; Valeri Processor architecture having independently fetching issuing and updating operations of instructions which are sequentially assigned and stored in order fetched
JPH03263164A (ja) 1990-03-13 1991-11-22 Kawasaki Steel Corp データ並列処理方式
JP2957223B2 (ja) 1990-03-20 1999-10-04 富士通株式会社 コールプロセッサの負荷分散制御方式
JPH04100449A (ja) 1990-08-20 1992-04-02 Toshiba Corp Atm通信システム
US5287467A (en) 1991-04-18 1994-02-15 International Business Machines Corporation Pipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unit
US5430850A (en) 1991-07-22 1995-07-04 Massachusetts Institute Of Technology Data processing system with synchronization coprocessor for multiple threads
US5511172A (en) 1991-11-15 1996-04-23 Matsushita Electric Co. Ind, Ltd. Speculative execution processor
US5195181A (en) 1992-01-10 1993-03-16 Digital Equipment Corporation Message processing system having separate message receiving and transmitting processors with message processing being distributed between the separate processors
JP3263164B2 (ja) 1992-01-24 2002-03-04 三井武田ケミカル株式会社 塗装性に優れた自動車外装部品の成形品用不飽和ポリエステル樹脂組成物及び成形材料、並びに塗装性に優れた自動車外装部品の成形品
JPH05274279A (ja) 1992-03-30 1993-10-22 Hitachi Ltd 並列処理装置及び方法
US5379428A (en) 1993-02-01 1995-01-03 Belobox Systems, Inc. Hardware process scheduler and processor interrupter for parallel processing computer systems
JP2655466B2 (ja) 1993-03-18 1997-09-17 日本電気株式会社 パケット交換装置
US5740393A (en) 1993-10-15 1998-04-14 Intel Corporation Instruction pointer limits in processor that performs speculative out-of-order instruction execution
US5787300A (en) 1993-11-10 1998-07-28 Oracle Corporation Method and apparatus for interprocess communications in a database environment
SG52391A1 (en) * 1994-01-03 1998-09-28 Intel Corp Method and apparatus for implementing a four stage branch resolution system in a computer processor
US5832262A (en) 1995-09-14 1998-11-03 Lockheed Martin Corporation Realtime hardware scheduler utilizing processor message passing and queue management cells
US5848257A (en) * 1996-09-20 1998-12-08 Bay Networks, Inc. Method and apparatus for multitasking in a computer system
JPH10143382A (ja) 1996-11-08 1998-05-29 Hitachi Ltd 共有メモリ型マルチプロセッサシステムの資源管理方法
US5875326A (en) 1997-04-25 1999-02-23 International Business Machines Corporation Data processing system and method for completing out-of-order instructions
US5870597A (en) 1997-06-25 1999-02-09 Sun Microsystems, Inc. Method for speculative calculation of physical register addresses in an out of order processor
US6240509B1 (en) * 1997-12-16 2001-05-29 Intel Corporation Out-of-pipeline trace buffer for holding instructions that may be re-executed following misspeculation

Also Published As

Publication number Publication date
DE69941998D1 (de) 2010-04-01
CA2350924A1 (en) 2000-05-25
WO2000029940A1 (en) 2000-05-25
AU1437000A (en) 2000-06-05
CA2350924C (en) 2011-05-10
JP4608099B2 (ja) 2011-01-05
JP2002530735A (ja) 2002-09-17
US6714961B1 (en) 2004-03-30
EP1131701B1 (en) 2010-02-03
EP1131701A1 (en) 2001-09-12
SE9901145D0 (sv) 1999-03-29

Similar Documents

Publication Publication Date Title
BR9915383A (pt) Processo de tratamento de sinais de tarefa em um sistema de processamento, sistema de processamento possuindo múltiplas unidades de processamento para o processamento de sinais de tarefa, e, fila de sinal de tarefa em um sistema de processamento
BR9403516A (pt) Sistema e método de despacho de unidades de execução múltiplas com dependência de instruções
EP0330836A3 (en) Method for multiprocessor system having self-allocating processors
EP1391820A3 (en) Concurrent task execution in a multi-processor, single operating system environment
US5987587A (en) Single chip multiprocessor with shared execution units
BRPI0506384A (pt) aparelho de processamento de informação, e, método de controle de processo e programa de computador para processar dados
KR900012155A (ko) 데이타 처리 시스템
KR20050084661A (ko) 순차 멀티스레딩 프로세서, 순차 멀티스레딩 프로세서의처리량 향상 방법 및 컴퓨터 프로그램 제품
EP0911724A3 (en) Process and method for utilizing register file resources
JPH0335322A (ja) デコーダ
AR246809A1 (es) Una disposicion de procesamiento de datos mejorada.
AU7097900A (en) Branch instructions in a multithreaded parallel processing system
DE69031139D1 (de) Verfahren und Vorrichtung zum Ordnen und in Warteschlangesetzen mehrerer Speicherzugriffsanforderungen
YU45743B (sh) Multiprocesorski podeljena razvedena keš memorija
BR9002303A (pt) Sistema de processamento de dados com gerenciamento de recurso de sistema para ele proprio e para um processador estranho associado
TW200506611A (en) Apparatus and method for virtualizing interrupts in a logically partitioned computer system
DE68926094D1 (de) Hochgeschwindigkeits-Verarbeitungssystem für Rechnergraphik
GB2317466B (en) Data processing condition code flags
BR9906563A (pt) Sistema de processamento de informações e processo de habilitar o controle do mesmo
TW377409B (en) Data processing system and method for implementing an efficient out-of-order issue mechanism
BR8701106A (pt) Processo para a operacao de uma unidade de comando central-multiprocessador com alta disponibilidade e com seguranca contra falhas,pertencente a um sistema de comutacao
CA2320913A1 (en) Zero overhead computer interrupts with task switching
TW200622908A (en) System and method for sharing resources between real-time and virtualizing operating systems
BR9915385A (pt) Processador para uma rede de serviço, e, sistema de processamento para uma rede de serviço
AU5487090A (en) Method and apparatus for the direct transfer of information between application programs running on distinct processors without utilizing the services of one or both operating systems

Legal Events

Date Code Title Description
B11A Dismissal acc. art.33 of ipl - examination not requested within 36 months of filing
B11Y Definitive dismissal - extension of time limit for request of examination expired [chapter 11.1.1 patent gazette]