AU1437000A - Multiple job signals per processing unit in a multiprocessing system - Google Patents

Multiple job signals per processing unit in a multiprocessing system

Info

Publication number
AU1437000A
AU1437000A AU14370/00A AU1437000A AU1437000A AU 1437000 A AU1437000 A AU 1437000A AU 14370/00 A AU14370/00 A AU 14370/00A AU 1437000 A AU1437000 A AU 1437000A AU 1437000 A AU1437000 A AU 1437000A
Authority
AU
Australia
Prior art keywords
processing unit
signals per
multiprocessing system
per processing
multiple job
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU14370/00A
Other languages
English (en)
Inventor
Magnus Carlsson
Terje Egeland
Per Anders Holmberg
Nils Ola Linnermark
Karl Oscar Joachim Strombergson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefonaktiebolaget LM Ericsson AB
Original Assignee
Telefonaktiebolaget LM Ericsson AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from SE9803901A external-priority patent/SE9803901D0/xx
Application filed by Telefonaktiebolaget LM Ericsson AB filed Critical Telefonaktiebolaget LM Ericsson AB
Publication of AU1437000A publication Critical patent/AU1437000A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Hardware Redundancy (AREA)
AU14370/00A 1998-11-16 1999-11-12 Multiple job signals per processing unit in a multiprocessing system Abandoned AU1437000A (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
SE9803901A SE9803901D0 (sv) 1998-11-16 1998-11-16 a device for a service network
SE9803901 1998-11-16
SE9901145 1999-03-29
SE9901145A SE9901145D0 (sv) 1998-11-16 1999-03-29 A processing system and method
PCT/SE1999/002061 WO2000029940A1 (en) 1998-11-16 1999-11-12 Multiple job signals per processing unit in a multiprocessing system

Publications (1)

Publication Number Publication Date
AU1437000A true AU1437000A (en) 2000-06-05

Family

ID=26663434

Family Applications (1)

Application Number Title Priority Date Filing Date
AU14370/00A Abandoned AU1437000A (en) 1998-11-16 1999-11-12 Multiple job signals per processing unit in a multiprocessing system

Country Status (9)

Country Link
US (1) US6714961B1 (https=)
EP (1) EP1131701B1 (https=)
JP (1) JP4608099B2 (https=)
AU (1) AU1437000A (https=)
BR (1) BR9915383A (https=)
CA (1) CA2350924C (https=)
DE (1) DE69941998D1 (https=)
SE (1) SE9901145D0 (https=)
WO (1) WO2000029940A1 (https=)

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US7152232B2 (en) * 2001-07-16 2006-12-19 Sun Microsystems, Inc. Hardware message buffer for supporting inter-processor communication
US8015303B2 (en) * 2002-08-02 2011-09-06 Astute Networks Inc. High data rate stateful protocol processing
US7814218B1 (en) 2002-10-17 2010-10-12 Astute Networks, Inc. Multi-protocol and multi-format stateful processing
US7596621B1 (en) * 2002-10-17 2009-09-29 Astute Networks, Inc. System and method for managing shared state using multiple programmed processors
US8151278B1 (en) 2002-10-17 2012-04-03 Astute Networks, Inc. System and method for timer management in a stateful protocol processing system
DE102006006582B4 (de) * 2006-02-13 2009-06-10 Jenoptik Laser, Optik, Systeme Gmbh Laser und Verfahren zur Erzeugung gepulster Laserstrahlung
US8156493B2 (en) * 2006-04-12 2012-04-10 The Mathworks, Inc. Exception handling in a concurrent computing process
KR20120017294A (ko) 2010-08-18 2012-02-28 삼성전자주식회사 어플리케이션을 효율적으로 처리하는 스케쥴링 시스템 및 스케쥴링 방법
US9329915B1 (en) * 2012-05-08 2016-05-03 Amazon Technologies, Inc. System and method for testing in a production environment
KR101476789B1 (ko) * 2013-05-06 2014-12-26 (주)넥셀 프로세싱 장치 및 방법
US9455887B1 (en) 2013-08-14 2016-09-27 Amazon Technologies, Inc. Distributed performance evaluation framework
CN104516773B (zh) * 2013-09-29 2018-04-20 国际商业机器公司 用于物理机的数据分配方法和数据分配装置
US9465653B2 (en) * 2013-12-11 2016-10-11 Dropbox, Inc. Automated invalidation of job output data in a job-processing system
US10372492B2 (en) 2013-12-11 2019-08-06 Dropbox, Inc. Job-processing systems and methods with inferred dependencies between jobs
US10133771B2 (en) 2015-05-13 2018-11-20 International Business Machines Corporation Opportunistic wait-triggered elastic commit

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US4466061A (en) 1982-06-08 1984-08-14 Burroughs Corporation Concurrent processing elements for using dependency free code
EP0230721A3 (en) 1986-01-22 1988-04-27 Mts Systems Corporation Multiprocessor control system
SE454921B (sv) 1986-10-03 1988-06-06 Ellemtel Utvecklings Ab Sett och anordning for att i en pa forhand avgjord ordningsfoljd exekvera tva instuktionssekvenser
US5781753A (en) 1989-02-24 1998-07-14 Advanced Micro Devices, Inc. Semi-autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for speculative and out-of-order execution of complex instructions
US5072364A (en) * 1989-05-24 1991-12-10 Tandem Computers Incorporated Method and apparatus for recovering from an incorrect branch prediction in a processor that executes a family of instructions in parallel
US5487156A (en) * 1989-12-15 1996-01-23 Popescu; Valeri Processor architecture having independently fetching issuing and updating operations of instructions which are sequentially assigned and stored in order fetched
JPH03263164A (ja) 1990-03-13 1991-11-22 Kawasaki Steel Corp データ並列処理方式
JP2957223B2 (ja) 1990-03-20 1999-10-04 富士通株式会社 コールプロセッサの負荷分散制御方式
JPH04100449A (ja) 1990-08-20 1992-04-02 Toshiba Corp Ａｔｍ通信システム
US5287467A (en) 1991-04-18 1994-02-15 International Business Machines Corporation Pipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unit
US5430850A (en) 1991-07-22 1995-07-04 Massachusetts Institute Of Technology Data processing system with synchronization coprocessor for multiple threads
US5511172A (en) 1991-11-15 1996-04-23 Matsushita Electric Co. Ind, Ltd. Speculative execution processor
US5195181A (en) 1992-01-10 1993-03-16 Digital Equipment Corporation Message processing system having separate message receiving and transmitting processors with message processing being distributed between the separate processors
JP3263164B2 (ja) 1992-01-24 2002-03-04 三井武田ケミカル株式会社 塗装性に優れた自動車外装部品の成形品用不飽和ポリエステル樹脂組成物及び成形材料、並びに塗装性に優れた自動車外装部品の成形品
JPH05274279A (ja) 1992-03-30 1993-10-22 Hitachi Ltd 並列処理装置及び方法
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JP2655466B2 (ja) 1993-03-18 1997-09-17 日本電気株式会社 パケット交換装置
US5740393A (en) 1993-10-15 1998-04-14 Intel Corporation Instruction pointer limits in processor that performs speculative out-of-order instruction execution
US5787300A (en) 1993-11-10 1998-07-28 Oracle Corporation Method and apparatus for interprocess communications in a database environment
SG52391A1 (en) * 1994-01-03 1998-09-28 Intel Corp Method and apparatus for implementing a four stage branch resolution system in a computer processor
US5832262A (en) 1995-09-14 1998-11-03 Lockheed Martin Corporation Realtime hardware scheduler utilizing processor message passing and queue management cells
US5848257A (en) * 1996-09-20 1998-12-08 Bay Networks, Inc. Method and apparatus for multitasking in a computer system
JPH10143382A (ja) 1996-11-08 1998-05-29 Hitachi Ltd 共有メモリ型マルチプロセッサシステムの資源管理方法
US5875326A (en) 1997-04-25 1999-02-23 International Business Machines Corporation Data processing system and method for completing out-of-order instructions
US5870597A (en) 1997-06-25 1999-02-09 Sun Microsystems, Inc. Method for speculative calculation of physical register addresses in an out of order processor
US6240509B1 (en) * 1997-12-16 2001-05-29 Intel Corporation Out-of-pipeline trace buffer for holding instructions that may be re-executed following misspeculation

Also Published As

Publication number Publication date
DE69941998D1 (de) 2010-04-01
CA2350924A1 (en) 2000-05-25
WO2000029940A1 (en) 2000-05-25
CA2350924C (en) 2011-05-10
JP4608099B2 (ja) 2011-01-05
JP2002530735A (ja) 2002-09-17
US6714961B1 (en) 2004-03-30
BR9915383A (pt) 2001-08-07
EP1131701B1 (en) 2010-02-03
EP1131701A1 (en) 2001-09-12
SE9901145D0 (sv) 1999-03-29

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase