GB9916289D0 - A multi-processor computer system - Google Patents
A multi-processor computer systemInfo
- Publication number
- GB9916289D0 GB9916289D0 GBGB9916289.3A GB9916289A GB9916289D0 GB 9916289 D0 GB9916289 D0 GB 9916289D0 GB 9916289 A GB9916289 A GB 9916289A GB 9916289 D0 GB9916289 D0 GB 9916289D0
- Authority
- GB
- United Kingdom
- Prior art keywords
- computer system
- processor computer
- processor
- computer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/404—Coupling between buses using bus bridges with address mapping
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Multi Processors (AREA)
- Bus Control (AREA)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9916289A GB2352064A (en) | 1999-07-13 | 1999-07-13 | Multi-processor system with PCI backplane |
CA 2313810 CA2313810A1 (en) | 1999-07-13 | 2000-07-12 | A multi-processor computer system |
FR0009242A FR2796478A1 (en) | 1999-07-13 | 2000-07-13 | MULTIPROCESSOR COMPUTER SYSTEM |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9916289A GB2352064A (en) | 1999-07-13 | 1999-07-13 | Multi-processor system with PCI backplane |
Publications (2)
Publication Number | Publication Date |
---|---|
GB9916289D0 true GB9916289D0 (en) | 1999-09-15 |
GB2352064A GB2352064A (en) | 2001-01-17 |
Family
ID=10857082
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB9916289A Withdrawn GB2352064A (en) | 1999-07-13 | 1999-07-13 | Multi-processor system with PCI backplane |
Country Status (3)
Country | Link |
---|---|
CA (1) | CA2313810A1 (en) |
FR (1) | FR2796478A1 (en) |
GB (1) | GB2352064A (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6925052B1 (en) | 1999-10-01 | 2005-08-02 | Agilent Technologies, Inc. | Multi-channel network monitoring apparatus, signal replicating device, and systems including such apparatus and devices, and enclosure for multi-processor equipment |
US6452789B1 (en) * | 2000-04-29 | 2002-09-17 | Hewlett-Packard Company | Packaging architecture for 32 processor server |
WO2005084040A1 (en) * | 2004-02-27 | 2005-09-09 | Utstarcom (China) Co., Ltd. | A method and a system of double engines sharing memory |
GB0509738D0 (en) | 2005-05-12 | 2005-06-22 | Cambridge Consultants | Processor and interface |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5729767A (en) * | 1994-10-07 | 1998-03-17 | Dell Usa, L.P. | System and method for accessing peripheral devices on a non-functional controller |
US5594882A (en) * | 1995-01-04 | 1997-01-14 | Intel Corporation | PCI split transactions utilizing dual address cycle |
RU2157000C2 (en) * | 1995-06-15 | 2000-09-27 | Интел Корпорейшн | Architecture of input-output processor, which connects inter-bridge of primary components |
US5848249A (en) * | 1995-06-15 | 1998-12-08 | Intel Corporation | Method and apparatus for enabling intelligent I/O subsystems using PCI I/O devices |
US5872998A (en) * | 1995-11-21 | 1999-02-16 | Seiko Epson Corporation | System using a primary bridge to recapture shared portion of a peripheral memory of a peripheral device to provide plug and play capability |
US5898888A (en) * | 1996-12-13 | 1999-04-27 | International Business Machines Corporation | Method and system for translating peripheral component interconnect (PCI) peer-to-peer access across multiple PCI host bridges within a computer system |
GB2329984B (en) * | 1997-10-01 | 2002-07-17 | Thomson Training & Simulation | A Multi-Processor Computer System |
-
1999
- 1999-07-13 GB GB9916289A patent/GB2352064A/en not_active Withdrawn
-
2000
- 2000-07-12 CA CA 2313810 patent/CA2313810A1/en not_active Abandoned
- 2000-07-13 FR FR0009242A patent/FR2796478A1/en active Pending
Also Published As
Publication number | Publication date |
---|---|
GB2352064A (en) | 2001-01-17 |
FR2796478A1 (en) | 2001-01-19 |
CA2313810A1 (en) | 2001-01-13 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |