BR9915383A - Processo de tratamento de sinais de tarefa em um sistema de processamento, sistema de processamento possuindo múltiplas unidades de processamento para o processamento de sinais de tarefa, e, fila de sinal de tarefa em um sistema de processamento - Google Patents

Processo de tratamento de sinais de tarefa em um sistema de processamento, sistema de processamento possuindo múltiplas unidades de processamento para o processamento de sinais de tarefa, e, fila de sinal de tarefa em um sistema de processamento

Info

Publication number
BR9915383A
BR9915383A BR9915383-1A BR9915383A BR9915383A BR 9915383 A BR9915383 A BR 9915383A BR 9915383 A BR9915383 A BR 9915383A BR 9915383 A BR9915383 A BR 9915383A
Authority
BR
Brazil
Prior art keywords
processing
task
processing system
signals
processing units
Prior art date
Application number
BR9915383-1A
Other languages
English (en)
Inventor
Per Anders Holmberg
Nils Ola Linnermark
Karl Oscar Joachim St Mbergson
Terje Egeland
Magnus Carlsson
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from SE9803901A external-priority patent/SE9803901D0/xx
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Publication of BR9915383A publication Critical patent/BR9915383A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Hardware Redundancy (AREA)

Abstract

"PROCESSO DE TRATAMENTO DE SINAIS DE TAREFA EM UM SISTEMA DE PROCESSAMENTO, SISTEMA DE PROCESSAMENTO POSSUINDO MúLTIPLAS UNIDADES DE PROCESSAMENTO PARA O PROCESSAMENTO DE SINAIS DE TAREFA, E, FILA DE SINAL DE TAREFA EM UM SISTEMA DE PROCESSAMENTO". A invenção é direcionada no sentido de um sistema de multiprocessamento (10) possuindo várias unidades de processamento (34A-D). De acordo com a invenção, para pelo menos uma das unidades de processamento no sistema de multiprocessamento, um primeiro sinal de tarefa é designado para a unidade de processamento para execução especulativa de uma primeira tarefa correspondente, e um sinal de tarefa adicional é designado para a unidade de processamento para execução especulativa de uma tarefa correspondente adicional. A execução especulativa da dita tarefa adicional é iniciada quando a unidade de processamento completou a execução da primeira tarefa. Se desejável, mais sinais de tarefa podem ser designados para a unidade de processamento para execução especulativa. Dessa forma, vários sinais de tarefa são designados para as unidades de processamento (34A-D) do sistema de processamento, e as unidades de processamento podem executar uma pluralidade de tarefas de forma especulativa enquanto esperam pela prioridade. Designando-se vários sinais de tarefa para execução especulativa por uma ou mais das unidades de processamento, os efeitos das variações no tempo de execução entre as tarefas são neutralizados, e o desempenho geral do sistema de processamento é substancialmente aperfeiçoado.
BR9915383-1A 1998-11-16 1999-11-12 Processo de tratamento de sinais de tarefa em um sistema de processamento, sistema de processamento possuindo múltiplas unidades de processamento para o processamento de sinais de tarefa, e, fila de sinal de tarefa em um sistema de processamento BR9915383A (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
SE9803901A SE9803901D0 (sv) 1998-11-16 1998-11-16 a device for a service network
SE9901145A SE9901145D0 (sv) 1998-11-16 1999-03-29 A processing system and method
PCT/SE1999/002061 WO2000029940A1 (en) 1998-11-16 1999-11-12 Multiple job signals per processing unit in a multiprocessing system

Publications (1)

Publication Number Publication Date
BR9915383A true BR9915383A (pt) 2001-08-07

Family

ID=26663434

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9915383-1A BR9915383A (pt) 1998-11-16 1999-11-12 Processo de tratamento de sinais de tarefa em um sistema de processamento, sistema de processamento possuindo múltiplas unidades de processamento para o processamento de sinais de tarefa, e, fila de sinal de tarefa em um sistema de processamento

Country Status (9)

Country Link
US (1) US6714961B1 (pt)
EP (1) EP1131701B1 (pt)
JP (1) JP4608099B2 (pt)
AU (1) AU1437000A (pt)
BR (1) BR9915383A (pt)
CA (1) CA2350924C (pt)
DE (1) DE69941998D1 (pt)
SE (1) SE9901145D0 (pt)
WO (1) WO2000029940A1 (pt)

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US8151278B1 (en) 2002-10-17 2012-04-03 Astute Networks, Inc. System and method for timer management in a stateful protocol processing system
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Also Published As

Publication number Publication date
JP4608099B2 (ja) 2011-01-05
DE69941998D1 (de) 2010-04-01
WO2000029940A1 (en) 2000-05-25
EP1131701B1 (en) 2010-02-03
AU1437000A (en) 2000-06-05
CA2350924C (en) 2011-05-10
US6714961B1 (en) 2004-03-30
CA2350924A1 (en) 2000-05-25
EP1131701A1 (en) 2001-09-12
JP2002530735A (ja) 2002-09-17
SE9901145D0 (sv) 1999-03-29

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Legal Events

Date Code Title Description
B11A Dismissal acc. art.33 of ipl - examination not requested within 36 months of filing
B11Y Definitive dismissal - extension of time limit for request of examination expired [chapter 11.1.1 patent gazette]