BR9912989A - Memória deintercaladora repartida para decodificador map - Google Patents

Memória deintercaladora repartida para decodificador map

Info

Publication number
BR9912989A
BR9912989A BR9912989-2A BR9912989A BR9912989A BR 9912989 A BR9912989 A BR 9912989A BR 9912989 A BR9912989 A BR 9912989A BR 9912989 A BR9912989 A BR 9912989A
Authority
BR
Brazil
Prior art keywords
map decoder
portions
split
block
substantially simultaneously
Prior art date
Application number
BR9912989-2A
Other languages
English (en)
Inventor
Inyup Kang
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR9912989A publication Critical patent/BR9912989A/pt

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2771—Internal interleaver for turbo codes
    • H03M13/2775—Contention or collision free turbo code internal interleaver
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/3972—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using sliding window techniques or parallel windows

Landscapes

  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)

Abstract

"MEMóRIA DEINTERCALADORA REPARTIDA PARA DECODIFICADOR MAP". A presente invenção consiste de uma nova e aperfeiçoada técnica de decodificação com particular aplicação a técnicas de codificação turbo, ou iterativas. De acordo com uma modalidade da invenção, um sistema para decodificação inclui uma RAM deintercaladora de canal para armazenar um bloco de estimativas de símbolos e para ler pelo menos três diferentes porções do bloco de forma substancialmente simultânea. Um conjunto de 3 calculadores de medida de estado recebe as três porções de uma forma substancialmente simultânea e gera conjuntos correspondentes de cálculos de medida de estado a partir das três porções do bloco deintercalador de canal.
BR9912989-2A 1998-08-14 1999-08-13 Memória deintercaladora repartida para decodificador map BR9912989A (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US9648998P 1998-08-14 1998-08-14
US09/259,665 US6381728B1 (en) 1998-08-14 1999-02-26 Partitioned interleaver memory for map decoder
PCT/US1999/018551 WO2000010255A1 (en) 1998-08-14 1999-08-13 Partitioned deinterleaver memory for map decoder

Publications (1)

Publication Number Publication Date
BR9912989A true BR9912989A (pt) 2003-01-07

Family

ID=26791750

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9912989-2A BR9912989A (pt) 1998-08-14 1999-08-13 Memória deintercaladora repartida para decodificador map

Country Status (10)

Country Link
US (1) US6381728B1 (pt)
EP (1) EP1108289A1 (pt)
JP (1) JP4298170B2 (pt)
KR (2) KR20010072498A (pt)
CN (1) CN1168221C (pt)
AU (1) AU759044B2 (pt)
BR (1) BR9912989A (pt)
CA (1) CA2340364A1 (pt)
ID (1) ID29610A (pt)
WO (1) WO2000010255A1 (pt)

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KR100532325B1 (ko) * 2002-11-23 2005-11-29 삼성전자주식회사 터보 복호기의 입력 제어 방법 및 장치
US7440392B2 (en) * 2003-02-19 2008-10-21 Advanced Micro Devices, Inc. Wireless receiver deinterleaver having partitioned memory
US7010453B2 (en) * 2003-10-14 2006-03-07 Agilent Technologies, Inc. Methods and apparatus for optimizing lists of waveforms
US6944558B2 (en) 2003-10-14 2005-09-13 Agilent Technologies, Inc. Methods and apparatus for optimizing the masking of waveforms to reduce the number of waveforms in a list of waveforms
KR100520934B1 (ko) * 2003-12-30 2005-10-17 삼성전자주식회사 디인터리버 메모리의 크기가 절감된 디지털 방송 수신기의디인터리빙장치 및 그의 디인터리빙방법
US7702968B2 (en) * 2004-02-27 2010-04-20 Qualcomm Incorporated Efficient multi-symbol deinterleaver
KR100744367B1 (ko) * 2004-05-24 2007-07-30 삼성전자주식회사 가변 윈도우가 적용된 터보 복호화 장치 및 방법
EP1832028B1 (en) 2004-10-12 2018-01-31 TQ Delta, LLC Resource sharing in a dsl transceiver
KR100736606B1 (ko) * 2005-03-23 2007-07-09 엘지전자 주식회사 비트 역인터리버용 메모리 및 그 제어방법
US20090022079A1 (en) * 2005-05-04 2009-01-22 Fei Frank Zhou Method and apparatus for providing enhanced channel interleaving
TW200723709A (en) * 2005-07-21 2007-06-16 Wionics Research Deinterleaver and dual-viterbi decoder architecture
US7409606B2 (en) * 2005-08-31 2008-08-05 Motorola, Inc. Method and system for interleaving in a parallel turbo decoder
FR2890804B1 (fr) * 2005-09-12 2008-04-04 St Microelectronics Sa Traitement de blocs dans un dispositif de decodage par blocs
US7810015B2 (en) * 2005-11-28 2010-10-05 Stmicroelectronics Sa Decoding with a concatenated error correcting code
KR100651035B1 (ko) * 2005-12-01 2006-11-30 한국전자통신연구원 차세대 무선 랜 시스템의 블록 디인터리버 장치 및 그 방법
US8139612B2 (en) * 2006-04-04 2012-03-20 Qualcomm Incorporated Methods and apparatus for dynamic packet mapping
US8213548B2 (en) * 2006-04-04 2012-07-03 Qualcomm Incorporated Methods and apparatus for dynamic packet reordering
KR101952812B1 (ko) 2006-04-12 2019-02-27 티큐 델타, 엘엘씨 패킷 재전송 및 메모리 공유
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JP2010508790A (ja) * 2006-11-01 2010-03-18 クゥアルコム・インコーポレイテッド 高データレートのためのターボインターリーバ
US20130170842A1 (en) * 2012-01-04 2013-07-04 Toshiaki Koike-Akino Method and System for Equalization and Decoding Received Signals Based on High-Order Statistics in Optical Communication Networks
KR102478169B1 (ko) * 2020-04-03 2022-12-16 한국전자통신연구원 디인터리빙 방법 및 이를 수행하는 디인터리빙 시스템
CN112233613B (zh) * 2020-10-29 2021-08-06 中国航发南方工业有限公司 显示板组件、燃气涡轮发电机组的显示及操作装置
CN112289257B (zh) * 2020-10-29 2021-08-06 中国航发南方工业有限公司 燃气涡轮发电机组的显示及操作装置

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Also Published As

Publication number Publication date
AU759044B2 (en) 2003-04-03
KR100671075B1 (ko) 2007-01-17
CN1168221C (zh) 2004-09-22
CA2340364A1 (en) 2000-02-24
KR20010072501A (ko) 2001-07-31
US6381728B1 (en) 2002-04-30
ID29610A (id) 2001-09-06
EP1108289A1 (en) 2001-06-20
JP2003528477A (ja) 2003-09-24
AU5486799A (en) 2000-03-06
KR20010072498A (ko) 2001-07-31
WO2000010255A1 (en) 2000-02-24
CN1344438A (zh) 2002-04-10
JP4298170B2 (ja) 2009-07-15

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Legal Events

Date Code Title Description
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE A 7A, 8A E 9A ANUIDADES.

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: REFERENTE AO DESPACHO PUBLICADO NA RPI 1962 DE 12/08/2008.