DE69941553D1 - Faltungsdekodierer mit geänderter Metrik - Google Patents
Faltungsdekodierer mit geänderter MetrikInfo
- Publication number
- DE69941553D1 DE69941553D1 DE69941553T DE69941553T DE69941553D1 DE 69941553 D1 DE69941553 D1 DE 69941553D1 DE 69941553 T DE69941553 T DE 69941553T DE 69941553 T DE69941553 T DE 69941553T DE 69941553 D1 DE69941553 D1 DE 69941553D1
- Authority
- DE
- Germany
- Prior art keywords
- convolutional decoder
- modified metric
- metric
- modified
- convolutional
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6563—Implementations using multi-port memories
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/3961—Arrangements of methods for branch or transition metric calculation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
- H03M13/4107—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing add, compare, select [ACS] operations
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
- H03M13/4161—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management
- H03M13/4169—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management using traceback
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6577—Representation or format of variables, register sizes or word-lengths and quantization
Landscapes
- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Error Detection And Correction (AREA)
- Detection And Correction Of Errors (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/105,759 US6477680B2 (en) | 1998-06-26 | 1998-06-26 | Area-efficient convolutional decoder |
Publications (1)
Publication Number | Publication Date |
---|---|
DE69941553D1 true DE69941553D1 (de) | 2009-12-03 |
Family
ID=22307632
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69941553T Expired - Lifetime DE69941553D1 (de) | 1998-06-26 | 1999-06-15 | Faltungsdekodierer mit geänderter Metrik |
Country Status (4)
Country | Link |
---|---|
US (1) | US6477680B2 (de) |
EP (1) | EP0967730B1 (de) |
JP (2) | JP3604955B2 (de) |
DE (1) | DE69941553D1 (de) |
Families Citing this family (40)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7031407B1 (en) * | 1998-09-28 | 2006-04-18 | Ceva D.S.P. Ltd. | Apparatus and method for decoding and trace back of convolution codes using the viterbi decoding algorithm |
US6690750B1 (en) * | 1999-12-23 | 2004-02-10 | Texas Instruments Incorporated | Flexible Viterbi decoder for wireless applications |
US6741664B1 (en) * | 1999-02-05 | 2004-05-25 | Broadcom Corporation | Low-latency high-speed trellis decoder |
US6587519B1 (en) * | 1999-05-28 | 2003-07-01 | Koninklijke Philips Electronics N.V. | Efficient apparatus and method for generating a trellis code from a shared state counter |
US6542492B1 (en) * | 1999-05-28 | 2003-04-01 | Koninklijke Philips Electronics N.V. | Method and system of initializing state metrics for traffic, paging, and sync channels to enhance Viterbi decoder performance |
US6654929B1 (en) * | 1999-10-01 | 2003-11-25 | Matsushita Electric Industrial Co., Ltd. | Viterbi decoder and Viterbi decoding method |
US7225393B2 (en) | 1999-10-01 | 2007-05-29 | Matsushita Electric Industrial Co., Ltd. | Viterbi decoder and Viterbi decoding method |
US6901118B2 (en) * | 1999-12-23 | 2005-05-31 | Texas Instruments Incorporated | Enhanced viterbi decoder for wireless applications |
FI112711B (fi) | 2000-03-17 | 2003-12-31 | Nokia Corp | Menetelmä ja laite muistinhallintaan digitaalisessa tiedonsiirrossa |
FI109162B (fi) | 2000-06-30 | 2002-05-31 | Nokia Corp | Menetelmä ja järjestely konvoluutiokoodatun koodisanan dekoodaamiseksi |
US6865710B2 (en) * | 2000-09-18 | 2005-03-08 | Lucent Technologies Inc. | Butterfly processor for telecommunications |
JP3876662B2 (ja) * | 2001-08-03 | 2007-02-07 | 三菱電機株式会社 | 積符号の復号方法および積符号の復号装置 |
US7191387B1 (en) * | 2002-01-15 | 2007-03-13 | Ikanos Communication Inc. | Method and apparatus for forward error correction |
US6810093B1 (en) * | 2002-05-03 | 2004-10-26 | Atheros Communications, Inc. | Sequence detection |
US7173985B1 (en) * | 2002-08-05 | 2007-02-06 | Altera Corporation | Method and apparatus for implementing a Viterbi decoder |
FR2854747A1 (fr) * | 2003-05-09 | 2004-11-12 | St Microelectronics Sa | Dispositif et procede d'addition-comparaison-selection- ajustement dans un decodeur |
US20040255230A1 (en) * | 2003-06-10 | 2004-12-16 | Inching Chen | Configurable decoder |
US7877670B2 (en) * | 2005-12-06 | 2011-01-25 | Ternarylogic Llc | Error correcting decoding for convolutional and recursive systematic convolutional encoded sequences |
US8577026B2 (en) | 2010-12-29 | 2013-11-05 | Ternarylogic Llc | Methods and apparatus in alternate finite field based coders and decoders |
JP2007529974A (ja) * | 2004-03-22 | 2007-10-25 | 松下電器産業株式会社 | ローカルイレージャmap復号器 |
US7231586B2 (en) * | 2004-07-21 | 2007-06-12 | Freescale Semiconductor, Inc. | Multi-rate viterbi decoder |
US7275204B2 (en) * | 2004-09-30 | 2007-09-25 | Marvell International Ltd. | Distributed ring control circuits for Viterbi traceback |
US20060068911A1 (en) * | 2004-09-30 | 2006-03-30 | Microsoft Corporation | Game console communication with a computer |
US7797618B2 (en) * | 2004-12-30 | 2010-09-14 | Freescale Semiconductor, Inc. | Parallel decoder for ultrawide bandwidth receiver |
US7458008B2 (en) * | 2004-12-30 | 2008-11-25 | Freescale Semiconductor, Inc. | Decision voting in a parallel decoder |
JP4432781B2 (ja) * | 2005-01-17 | 2010-03-17 | 株式会社日立製作所 | 誤り訂正復号器 |
US7404139B2 (en) * | 2005-01-21 | 2008-07-22 | Freescale Semiconductor, Inc. | Decoder with M-AT-A-Time Traceback |
US20070006058A1 (en) * | 2005-06-30 | 2007-01-04 | Seagate Technology Llc | Path metric computation unit for use in a data detector |
US7797615B2 (en) * | 2005-07-07 | 2010-09-14 | Acer Incorporated | Utilizing variable-length inputs in an inter-sequence permutation turbo code system |
US20070011557A1 (en) * | 2005-07-07 | 2007-01-11 | Highdimension Ltd. | Inter-sequence permutation turbo code system and operation methods thereof |
US7856579B2 (en) * | 2006-04-28 | 2010-12-21 | Industrial Technology Research Institute | Network for permutation or de-permutation utilized by channel coding algorithm |
US20070150332A1 (en) * | 2005-12-22 | 2007-06-28 | Caterpillar Inc. | Heuristic supply chain modeling method and system |
US20080152044A1 (en) * | 2006-12-20 | 2008-06-26 | Media Tek Inc. | Veterbi decoding method for convolutionally encoded signal |
EP2232378A1 (de) * | 2007-12-10 | 2010-09-29 | Sandbridge Technologies, Inc. | Sich beschleunigende Rückverfolgung auf einem SIGNALPROzESSOR |
US8856630B2 (en) * | 2008-06-10 | 2014-10-07 | Telefonaktiebolaget L M Ericsson (Publ) | Continuous parallel Viterbi decoder |
US8179999B2 (en) * | 2008-08-08 | 2012-05-15 | Nokia Corporation | Decoding of blocks in radio communications |
US20100299579A1 (en) * | 2009-05-21 | 2010-11-25 | Ternarylogic Llc | Methods and Systems for Error-Correction in Convolutional and Systematic Convolutional Decoders in Galois Configuration |
FR2946480B1 (fr) * | 2009-06-09 | 2011-06-17 | Thales Sa | Recepteur equipe d'un decodeur de viterbi a treillis |
US8644432B2 (en) * | 2012-04-05 | 2014-02-04 | Freescale Semiconductor, Inc. | Viterbi decoder for decoding convolutionally encoded data stream |
US9419656B2 (en) * | 2014-07-29 | 2016-08-16 | Intel IP Corporation | Decoder and method for decoding an encoded sequence of bits |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4346473A (en) * | 1980-02-26 | 1982-08-24 | Harris Corporation | Error correction coding method and apparatus for multilevel signaling |
US4583078A (en) * | 1984-11-13 | 1986-04-15 | Communications Satellite Corporation | Serial Viterbi decoder |
US5027374A (en) * | 1990-03-26 | 1991-06-25 | Motorola, Inc. | Bit serial Viterbi decoder add/compare/select array |
DE4038251A1 (de) | 1990-11-30 | 1992-06-04 | Philips Patentverwaltung | Entzerrer fuer ein digitales uebertragungssystem |
KR930004862B1 (ko) * | 1990-12-17 | 1993-06-09 | 삼성전자 주식회사 | 상태 평가량 기억장치 |
US5418795A (en) * | 1991-09-13 | 1995-05-23 | Sony Corporation | Viterbi decoder with path metric comparisons for increased decoding rate and with normalization timing calculation |
KR940010435B1 (ko) * | 1992-08-31 | 1994-10-22 | 삼성전자 주식회사 | 비터비 복호기의 경로기억장치 |
JPH06338808A (ja) * | 1993-05-28 | 1994-12-06 | Matsushita Electric Ind Co Ltd | 加算比較選択装置 |
US5550870A (en) * | 1994-03-02 | 1996-08-27 | Lucent Technologies Inc. | Viterbi processor |
US5471500A (en) * | 1994-03-08 | 1995-11-28 | At&T Ipm Corp. | Soft symbol decoding |
US5822341A (en) * | 1995-04-06 | 1998-10-13 | Advanced Hardware Architectures, Inc. | Multiport RAM for use within a viterbi decoder |
DE59509663D1 (de) * | 1995-10-21 | 2001-11-08 | Micronas Gmbh | Logischer Block für einen Viterbi-Decoder |
JPH09232973A (ja) * | 1996-02-28 | 1997-09-05 | Sony Corp | ビタビ復号器 |
US5987638A (en) * | 1997-04-22 | 1999-11-16 | Lsi Logic Corporation | Apparatus and method for computing the result of a viterbi equation in a single cycle |
-
1998
- 1998-06-26 US US09/105,759 patent/US6477680B2/en not_active Expired - Lifetime
-
1999
- 1999-06-15 DE DE69941553T patent/DE69941553D1/de not_active Expired - Lifetime
- 1999-06-15 EP EP99304665A patent/EP0967730B1/de not_active Expired - Lifetime
- 1999-06-16 JP JP17027799A patent/JP3604955B2/ja not_active Expired - Fee Related
-
2002
- 2002-06-27 JP JP2002187012A patent/JP3677257B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20020010895A1 (en) | 2002-01-24 |
EP0967730B1 (de) | 2009-10-21 |
EP0967730A1 (de) | 1999-12-29 |
JP3677257B2 (ja) | 2005-07-27 |
JP3604955B2 (ja) | 2004-12-22 |
US6477680B2 (en) | 2002-11-05 |
JP2000031836A (ja) | 2000-01-28 |
JP2003092536A (ja) | 2003-03-28 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |