FR2890804B1 - Traitement de blocs dans un dispositif de decodage par blocs - Google Patents

Traitement de blocs dans un dispositif de decodage par blocs

Info

Publication number
FR2890804B1
FR2890804B1 FR0509284A FR0509284A FR2890804B1 FR 2890804 B1 FR2890804 B1 FR 2890804B1 FR 0509284 A FR0509284 A FR 0509284A FR 0509284 A FR0509284 A FR 0509284A FR 2890804 B1 FR2890804 B1 FR 2890804B1
Authority
FR
France
Prior art keywords
block
decoding device
processing
block processing
block decoding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0509284A
Other languages
English (en)
Other versions
FR2890804A1 (fr
Inventor
Laurent Paumier
Vincent Heinrich
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to FR0509284A priority Critical patent/FR2890804B1/fr
Priority to US11/470,982 priority patent/US7640482B2/en
Publication of FR2890804A1 publication Critical patent/FR2890804A1/fr
Application granted granted Critical
Publication of FR2890804B1 publication Critical patent/FR2890804B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13Linear codes
    • H03M13/15Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/152Bose-Chaudhuri-Hocquenghem [BCH] codes
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105Decoding
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105Decoding
    • H03M13/1131Scheduling of bit node or check node processing
    • H03M13/1137Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13Linear codes
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957Turbo codes and decoding
    • H03M13/296Particular turbo code structure
    • H03M13/2963Turbo-block codes, i.e. turbo codes based on block codes, e.g. turbo decoding of product codes
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65Purpose and implementation aspects
    • H03M13/6508Flexibility, adaptability, parametrability and configurability of the implementation
    • H03M13/6516Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65Purpose and implementation aspects
    • H03M13/6566Implementations concerning memory access contentions

Landscapes

  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Algebra (AREA)
  • General Physics & Mathematics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Error Detection And Correction (AREA)
FR0509284A 2005-09-12 2005-09-12 Traitement de blocs dans un dispositif de decodage par blocs Expired - Fee Related FR2890804B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR0509284A FR2890804B1 (fr) 2005-09-12 2005-09-12 Traitement de blocs dans un dispositif de decodage par blocs
US11/470,982 US7640482B2 (en) 2005-09-12 2006-09-07 Block processing in a block decoding device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0509284A FR2890804B1 (fr) 2005-09-12 2005-09-12 Traitement de blocs dans un dispositif de decodage par blocs

Publications (2)

Publication Number Publication Date
FR2890804A1 FR2890804A1 (fr) 2007-03-16
FR2890804B1 true FR2890804B1 (fr) 2008-04-04

Family

ID=36215489

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0509284A Expired - Fee Related FR2890804B1 (fr) 2005-09-12 2005-09-12 Traitement de blocs dans un dispositif de decodage par blocs

Country Status (2)

Country Link
US (1) US7640482B2 (fr)
FR (1) FR2890804B1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7505478B2 (en) * 2002-10-02 2009-03-17 Marvell International Ltd. Method and apparatus of de-multiplexing data
JP2009009545A (ja) * 2007-01-31 2009-01-15 Hewlett-Packard Development Co Lp データ処理システム及び方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6252917B1 (en) 1998-07-17 2001-06-26 Nortel Networks Limited Statistically multiplexed turbo code decoder
US6381728B1 (en) * 1998-08-14 2002-04-30 Qualcomm Incorporated Partitioned interleaver memory for map decoder
US6624767B1 (en) * 2000-09-06 2003-09-23 Qualcomm, Incorporated Data buffer structure for asynchronously received physical channels in a CDMA system
DE10214393A1 (de) * 2001-03-27 2003-02-06 Univ Dresden Tech Verfahren zur iterativen Decodierung von verketteten Codes
JP4224777B2 (ja) 2003-05-13 2009-02-18 ソニー株式会社 復号方法および復号装置、並びにプログラム
FR2859332B1 (fr) 2003-08-28 2005-12-02 Agence Spatiale Europeenne Architecture pour un decodeur iteratif

Also Published As

Publication number Publication date
FR2890804A1 (fr) 2007-03-16
US7640482B2 (en) 2009-12-29
US20070089020A1 (en) 2007-04-19

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Legal Events

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ST Notification of lapse

Effective date: 20130531